drm/fsl-dcu: enable TCON bypass mode by default
Subsystems (3)
Stefan Agner
maintainerPATCH 1/3 drm/fsl-dcu: enable TCON bypass mode by default
Do not use encoder disable/enable callbacks to control bypass mode as this seems to mess with the signals not liked by displays. This also makes more sense since the encoder is already defined to be parallel RGB/LVDS at creation time.
Signed-off-by Stefan Agner <[email protected]>
---
I tested that on Vybrid. Meng, since LS1021a does not use TCON this should not affect LS1021a, so I think we are fine.
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c | 24 ++++-------------------- 1 file changed, 4 insertions(+), 20 deletions(-)
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c +4 -20
@@ -28,28 +28,8 @@ fsl_dcu_drm_encoder_atomic_check(struct drm_encoder *encoder,return 0 ; } -static void fsl_dcu_drm_encoder_disable (struct drm_encoder *encoder) -{ -struct drm_device *dev = encoder->dev; -struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; - -if (fsl_dev->tcon) -fsl_tcon_bypass_disable (fsl_dev->tcon); -} - -static void fsl_dcu_drm_encoder_enable (struct drm_encoder *encoder) -{ -struct drm_device *dev = encoder->dev; -struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; - -if (fsl_dev->tcon) -fsl_tcon_bypass_enable (fsl_dev->tcon); -} -static const struct drm_encoder_helper_funcs encoder_helper_funcs = { .atomic_check = fsl_dcu_drm_encoder_atomic_check, - .disable = fsl_dcu_drm_encoder_disable, - .enable = fsl_dcu_drm_encoder_enable, };static void fsl_dcu_drm_encoder_destroy (struct drm_encoder *encoder)
@@ -68,6 +48,10 @@ int fsl_dcu_drm_encoder_create(struct fsl_dcu_drm_device *fsl_dev,int ret; encoder->possible_crtcs =1 ; + +/* Use bypass mode for parallel RGB/LVDS encoder */ +fsl_tcon_bypass_enable (fsl_dev->tcon); + ret =drm_encoder_init (fsl_dev->drm, encoder, &encoder_funcs,DRM_MODE_ENCODER_LVDS ,NULL );if (ret <0 )
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Stefan Agner
maintainerPATCH 2/3 drm/fsl-dcu: do not explicitly transfer registers on plane init
There is no need to explicitly initiate a register transfer and turn off the DCU after initializing the plane registers. In fact, this is harmful and leads to unnecessary flickers if the DCU has been left on by the bootloader.
Signed-off-by Stefan Agner <[email protected]>
---
If you could give this and 3/3 a try on LS1021a I would be glad. Since those are fixes I would like to send them for v4.9...
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c | 5 ----- 1 file changed, 5 deletions(-)
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c +0 -5
@@ -211,11 +211,6 @@ void fsl_dcu_drm_init_planes(struct drm_device *dev)for (j =1 ; j <= fsl_dev->soc->layer_regs; j++)regmap_write (fsl_dev->regmap,DCU_CTRLDESCLN (i, j),0 ); } -regmap_update_bits (fsl_dev->regmap,DCU_DCU_MODE , -DCU_MODE_DCU_MODE_MASK , -DCU_MODE_DCU_MODE (DCU_MODE_OFF )); -regmap_write (fsl_dev->regmap,DCU_UPDATE_MODE , -DCU_UPDATE_MODE_READREG ); }struct drm_plane *fsl_dcu_drm_primary_create_plane (struct drm_device *dev)
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Stefan Agner
maintainerPATCH 3/3 drm/fsl-dcu: enable pixel clock when enabling CRTC
In reply to Stefan AgnerThe pixel clock should not be on if the CRTC is not in use, hence move clock enable/disable calls into CRTC callbacks.
Signed-off-by Stefan Agner <[email protected]>
--- drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 7 +++++++ drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 16 +--------------- 2 files changed, 8 insertions(+), 15 deletions(-)
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c +7 -0
@@ -51,13 +51,20 @@ static void fsl_dcu_drm_disable_crtc(struct drm_crtc *crtc) DCU_MODE_DCU_MODE(DCU_MODE_OFF));regmap_write (fsl_dev->regmap,DCU_UPDATE_MODE ,DCU_UPDATE_MODE_READREG ); +clk_disable_unprepare (fsl_dev->pix_clk); }static void fsl_dcu_drm_crtc_enable (struct drm_crtc *crtc) {struct drm_device *dev = crtc->dev;struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; +int ret; + ret =clk_prepare_enable (fsl_dev->pix_clk); +if (ret <0 ) { +dev_err (fsl_dev->dev,"failed to enable pix clk\n" ); +return ; + }regmap_update_bits (fsl_dev->regmap,DCU_DCU_MODE ,DCU_MODE_DCU_MODE_MASK ,DCU_MODE_DCU_MODE (DCU_MODE_NORMAL ));
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c +1 -15
@@ -267,12 +267,6 @@ static int fsl_dcu_drm_pm_resume(struct device *dev)return ret; } - ret =clk_prepare_enable (fsl_dev->pix_clk); -if (ret <0 ) { -dev_err (dev,"failed to enable pix clk\n" ); - goto disable_dcu_clk; - } -fsl_dcu_drm_init_planes (fsl_dev->drm);drm_atomic_helper_resume (fsl_dev->drm, fsl_dev->state);
@@ -401,18 +395,12 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev) goto disable_clk; } - ret =clk_prepare_enable (fsl_dev->pix_clk); -if (ret <0 ) { -dev_err (dev,"failed to enable pix clk\n" ); - goto unregister_pix_clk; - } - fsl_dev->tcon =fsl_tcon_init (dev); drm =drm_dev_alloc (driver, dev);if (IS_ERR (drm)) { ret =PTR_ERR (drm); - goto disable_pix_clk; + goto unregister_pix_clk; } fsl_dev->dev = dev;
@@ -433,8 +421,6 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev) unref:drm_dev_unref (drm); -disable_pix_clk: -clk_disable_unprepare (fsl_dev->pix_clk); unregister_pix_clk:clk_unregister (fsl_dev->pix_clk); disable_clk:
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