Add R8A7743/SK-RZG1M board support
Subsystems (5)
v3 cover Add R8A7743/SK-RZG1M board support
Hello.
Here's the set of 11 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20161003-v4.8' tag. I'm adding the device tree support for the R8A7743-based SK-RZG1M board. The SoC is close to R8A7791 and the board seems identical to the R8A7791/Porter board. The device tree patches depend on the R8A7743 CPG/MSSR driver series just posted in order to compile and work.
[01/12] ARM: shmobile: r8a7743: add power domain index macros [02/12] soc: renesas: rcar-sysc: add R8A7743 support [03/12] ARM: shmobile: r8a7743: basic SoC support [04/12] ARM: dts: r8a7743: initial SoC device tree [05/12] ARM: dts: r8a7743: add SYS-DMAC support [06/12] ARM: dts: r8a7743: add [H]SCIF{A|B} support [07/12] ARM: dts: r8a7743: add Ether support [08/12] ARM: dts: r8a7743: add IRQC support
[09/12] DT: arm: shmobile: document SK-RZG1M board [10/12] ARM: dts: sk-rzg1m: initial device tree [11/12] ARM: dts: sk-rzg1m: add Ether support
WBR, Sergei
PATCH v3 1/11 ARM: shmobile: r8a7743: add power domain index macros
Add macros usable by the device tree sources to reference R8A7743 SYSC power domains by index.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
---
Changes in version 2:
- added Geert's tag.
include/dt-bindings/power/r8a7743-sysc.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+)
include/dt-bindings/power/r8a7743-sysc.h new file +25 -0
@@ -0,0 +1,25 @@ +/* +* Copyright (C) 2016 Cogent Embedded Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +*/ +#ifndef __DT_BINDINGS_POWER_R8A7743_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7743_SYSC_H__ + +/* +* These power domain indices match the numbers of the interrupt bits +* representing the power areas in the various Interrupt Registers +* (e.g. SYSCISR, Interrupt Status Register) +*/ + +#define R8A7743_PD_CA15_CPU0 0 +#define R8A7743_PD_CA15_CPU1 1 +#define R8A7743_PD_CA15_SCU 12 +#define R8A7743_PD_SGX 20 + +/* Always-on power area */ +#define R8A7743_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7743_SYSC_H__ */
Re: [PATCH v3 01/11] ARM: shmobile: r8a7743: add power domain index macros
Quoted 9 lines · Sergei Shtylyov
Add macros usable by the device tree sources to reference R8A7743 SYSC power domains by index.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
Signed-off-by Sergei Shtylyov <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>
Quoted 6 lines
---
Changes in version 2:
- added Geert's tag.include/dt-bindings/power/r8a7743-sysc.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+)
Thanks, I have queued this up.
PATCH v3 2/11 soc: renesas: rcar-sysc: add R8A7743 support
In reply to Sergei ShtylyovAdd support for RZ/G1M (R8A7743) SoC power areas to the R-Car SYSC driver.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
---
Changes in version 2:
- documented the R8A7743 SYSC device tree binding;
- added "R-Car" to the patch description;
- added Geert's tag.
Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt | 7 +- drivers/soc/renesas/Makefile | 1 drivers/soc/renesas/r8a7743-sysc.c | 32 ++++++++++ drivers/soc/renesas/rcar-sysc.c | 3 drivers/soc/renesas/rcar-sysc.h | 1 5 files changed, 41 insertions(+), 3 deletions(-)
Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt +4 -3
@@ -1,12 +1,13 @@ -DT bindings for the Renesas R-Car System Controller +DT bindings for the Renesas R-Car (RZ/G) System Controller == System Controller Node == -The R-Car System Controller provides power management for the CPU cores and -various coprocessors. +The R-Car (RZ/G) System Controller provides power management for the CPU cores +and various coprocessors. Required properties: - compatible: Must contain exactly one of the following: + - "renesas,r8a7743-sysc" (RZ/G1M) - "renesas,r8a7779-sysc" (R-Car H1) - "renesas,r8a7790-sysc" (R-Car H2) - "renesas,r8a7791-sysc" (R-Car M2-W)
drivers/soc/renesas/Makefile +1 -0
@@ -1,3 +1,4 @@ +obj-$(CONFIG_ARCH_R8A7743) += rcar-sysc.o r8a7743-sysc.o obj-$(CONFIG_ARCH_R8A7779) += rcar-sysc.o r8a7779-sysc.o obj-$(CONFIG_ARCH_R8A7790) += rcar-sysc.o r8a7790-sysc.o obj-$(CONFIG_ARCH_R8A7791) += rcar-sysc.o r8a7791-sysc.o
drivers/soc/renesas/r8a7743-sysc.c new file +32 -0
@@ -0,0 +1,32 @@ +/* +* Renesas RZ/G1M System Controller +* +* Copyright (C) 2016 Cogent Embedded Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation; of the License. +*/ + +#include <linux/bug.h> +#include <linux/kernel.h> + +#include <dt-bindings/power/r8a7743-sysc.h> + +#include "rcar-sysc.h" + +static const struct rcar_sysc_area r8a7743_areas[]__initconst = { + {"always-on" ,0 ,0 ,R8A7743_PD_ALWAYS_ON ,-1 ,PD_ALWAYS_ON }, + {"ca15-scu" ,0x180 ,0 ,R8A7743_PD_CA15_SCU ,R8A7743_PD_ALWAYS_ON , +PD_SCU }, + {"ca15-cpu0" ,0x40 ,0 ,R8A7743_PD_CA15_CPU0 ,R8A7743_PD_CA15_SCU , +PD_CPU_NOCR }, + {"ca15-cpu1" ,0x40 ,1 ,R8A7743_PD_CA15_CPU1 ,R8A7743_PD_CA15_SCU , +PD_CPU_NOCR }, + {"sgx" ,0xc0 ,0 ,R8A7743_PD_SGX ,R8A7743_PD_ALWAYS_ON }, +}; + +const struct rcar_sysc_info r8a7743_sysc_info__initconst = { + .areas = r8a7743_areas, + .num_areas =ARRAY_SIZE (r8a7743_areas), +};
drivers/soc/renesas/rcar-sysc.c +3 -0
@@ -275,6 +275,9 @@ finalize: }static const struct of_device_id rcar_sysc_matches[] = { +#ifdef CONFIG_ARCH_R8A7743 + { .compatible ="renesas,r8a7743-sysc" , .data = &r8a7743_sysc_info }, +#endif #ifdef CONFIG_ARCH_R8A7779 { .compatible ="renesas,r8a7779-sysc" , .data = &r8a7779_sysc_info }, #endif
drivers/soc/renesas/rcar-sysc.h +1 -0
@@ -50,6 +50,7 @@ struct rcar_sysc_info {unsigned int num_areas; }; +extern const struct rcar_sysc_info r8a7743_sysc_info;extern const struct rcar_sysc_info r8a7779_sysc_info;extern const struct rcar_sysc_info r8a7790_sysc_info;extern const struct rcar_sysc_info r8a7791_sysc_info;
A message that is not in the archive (sent off-list or not yet received): 1691511.DcOcZO89eZ-gHKXc3Y1Z8zGSmamagVegGFoWSdPRAKMAL8bYrjMMd8@public.gmane.org
Re: [PATCH v3 02/11] soc: renesas: rcar-sysc: add R8A7743 support
Quoted 7 lines · Sergei Shtylyov
Add support for RZ/G1M (R8A7743) SoC power areas to the R-Car SYSC driver.
Based on the original (and large) patch by Dmitry Shifrin <dmitry.shifrin-M4DtvfQ/[email protected]>.
Reviewed-by Geert Uytterhoeven <[email protected]>
Thanks, I have queued this up.
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PATCH v3 3/11 ARM: shmobile: r8a7743: basic SoC support
In reply to Sergei ShtylyovAdd minimal support for the RZ/G1M (R8A7743) SoC.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
---
Changes in version 2:
- removed "select I2C" from the R8A7743 Kconfig entry;
- documented the R8A7743 device tree binding;
- added Geert's tag.
Documentation/devicetree/bindings/arm/shmobile.txt | 2 + arch/arm/mach-shmobile/Kconfig | 4 ++ arch/arm/mach-shmobile/Makefile | 1 arch/arm/mach-shmobile/setup-r8a7743.c | 34 +++++++++++++++++++++ 4 files changed, 41 insertions(+)
Documentation/devicetree/bindings/arm/shmobile.txt +2 -0
@@ -13,6 +13,8 @@ SoCs: compatible = "renesas,r8a73a4" - R-Mobile A1 (R8A77400) compatible = "renesas,r8a7740" + - RZ/G1M (R8A77430) + compatible = "renesas,r8a7743" - R-Car M1A (R8A77781) compatible = "renesas,r8a7778" - R-Car H1 (R8A77790)
arch/arm/mach-shmobile/Kconfig +4 -0
@@ -68,6 +68,10 @@ config ARCH_R8A7740 select ARCH_RMOBILE select RENESAS_INTC_IRQPIN +config ARCH_R8A7743 + bool "RZ/G1M (R8A77430)" + select ARCH_RCAR_GEN2 + config ARCH_R8A7778 bool "R-Car M1A (R8A77781)" select ARCH_RCAR_GEN1
arch/arm/mach-shmobile/Makefile +1 -0
@@ -9,6 +9,7 @@ obj-y := timer.o obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o +obj-$(CONFIG_ARCH_R8A7743) += setup-r8a7743.o obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o pm-r8a7779.o obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o
arch/arm/mach-shmobile/setup-r8a7743.c new file +34 -0
@@ -0,0 +1,34 @@ +/* +* r8a7743 processor support +* +* Copyright (C) 2016 Cogent Embedded, Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation; of the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#include <linux/init.h> + +#include <asm/mach/arch.h> + +#include "common.h" +#include "rcar-gen2.h" + +static const char *const r8a7743_boards_compat_dt[]__initconst = { +"renesas,r8a7743" , +NULL , +}; + +DT_MACHINE_START (R8A7743_DT ,"Generic R8A7743 (Flattened Device Tree)" ) + .init_early = shmobile_init_delay, + .init_time = rcar_gen2_timer_init, + .init_late = shmobile_init_late, + .reserve = rcar_gen2_reserve, + .dt_compat = r8a7743_boards_compat_dt, +MACHINE_END
PATCH v3 3/11 ARM: shmobile: r8a7743: basic SoC support
Quoted 7 lines · Sergei Shtylyov
Add minimal support for the RZ/G1M (R8A7743) SoC.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
Signed-off-by Sergei Shtylyov <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>
Thanks, I have queued this up.
PATCH v3 3/11 ARM: shmobile: r8a7743: basic SoC support
Hi Simon,
Quoted 10 lines · On Friday 07 Oct 2016 12:15:37 Simon Horman wrote:
Quoted 7 lines · Sergei Shtylyov
Add minimal support for the RZ/G1M (R8A7743) SoC.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
Signed-off-by Sergei Shtylyov <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>Thanks, I have queued this up.
I'd like to see this patch rebased on top of "[PATCH] ARM: shmobile:
Consolidate R8A779[234] machine definitions".
Signature · 3 lines
Regards, Laurent Pinchart
PATCH v3 3/11 ARM: shmobile: r8a7743: basic SoC support
Hello.
Quoted 5 lines · Laurent Pinchart
Quoted 5 lines
Quoted 5 lines
Add minimal support for the RZ/G1M (R8A7743) SoC.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
Quoted 7 lines
Quoted 4 lines
Quoted 2 lines
Signed-off-by Sergei Shtylyov <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>Thanks, I have queued this up.
I'd like to see this patch rebased on top of "[PATCH] ARM: shmobile:
Consolidate R8A779[234] machine definitions".
R87743 is analogous to R8A7791, not R8A779[234], not sure how it is
connected to your patch.
MBR, Sergei
PATCH v3 3/11 ARM: shmobile: r8a7743: basic SoC support
Hi Sergei,
Quoted 12 lines · Sergei Shtylyov
Quoted 11 lines · Laurent Pinchart
Quoted 9 lines
Quoted 6 lines
Add minimal support for the RZ/G1M (R8A7743) SoC. Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
Signed-off-by Sergei Shtylyov <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>Thanks, I have queued this up.
Quoted 6 lines
Quoted 2 lines
I'd like to see this patch rebased on top of "[PATCH] ARM: shmobile:
Consolidate R8A779[234] machine definitions".R87743 is analogous to R8A7791, not R8A779[234], not sure how it is
connected to your patch.
The comment
+ /*
+ * R8A7790 and R8A7791 can't be handled here as long as they need SMP + * initialization fallback. + */
is not about r8a7790/r8a7791 in se, but about backward compatibility support for DTBs without APMU nodes and CPU enable-methods.
For new SoCs, we mandate the presence of these in the DTB.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH v3 3/11 ARM: shmobile: r8a7743: basic SoC support
In reply to Laurent PinchartQuoted 10 lines · Laurent Pinchart
Hi Simon,
Quoted 6 lines · On Friday 07 Oct 2016 12:15:37 Simon Horman wrote:
Quoted 5 lines · Sergei Shtylyov
Add minimal support for the RZ/G1M (R8A7743) SoC.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
Quoted 7 lines
Quoted 4 lines
Quoted 2 lines
Signed-off-by Sergei Shtylyov <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>Thanks, I have queued this up.
I'd like to see this patch rebased on top of "[PATCH] ARM: shmobile:
Consolidate R8A779[234] machine definitions".
I'm happy to drop this patch if that is the desired outcome of the discussion in this sub-thread.
PATCH v3 3/11 ARM: shmobile: r8a7743: basic SoC support
Hi Simon,
Quoted 11 lines · On Saturday 08 Oct 2016 11:31:50 Simon Horman wrote:
Quoted 10 lines · Laurent Pinchart
Quoted 9 lines · On Friday 07 Oct 2016 12:15:37 Simon Horman wrote:
Quoted 7 lines · Sergei Shtylyov
Add minimal support for the RZ/G1M (R8A7743) SoC.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
Signed-off-by Sergei Shtylyov <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>
Quoted 7 lines
Quoted 4 lines
Quoted 1 line
Thanks, I have queued this up.
I'd like to see this patch rebased on top of "[PATCH] ARM: shmobile:
Consolidate R8A779[234] machine definitions".I'm happy to drop this patch if that is the desired outcome of the discussion in this sub-thread.
It's at least my desired outcome ;-)
Signature · 3 lines
Regards, Laurent Pinchart
PATCH v3 4/11 ARM: dts: r8a7743: initial SoC device tree
In reply to Sergei ShtylyovThe initial R8A7743 SoC device tree including CPU cores, GIC, timer, SYSC, CPG, and the required clock descriptions.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
---
Changes in version 3:
- changed the R8A7743 clock header #include;
- replaced the multiple clock nodes with the single CPG node, updated the "clocks" property in the CPU0 node, updated the patch description.
Changes in version 2:
- added the IRQC and Ether clocks.
arch/arm/boot/dts/r8a7743.dtsi | 125 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 125 insertions(+)
arch/arm/boot/dts/r8a7743.dtsi new file +125 -0
@@ -0,0 +1,125 @@ +/* + * Device Tree Source for the r8a7743 SoC + * + * Copyright (C) 2016 Cogent Embedded Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/r8a7743-cpg-mssr.h> +#include <dt-bindings/power/r8a7743-sysc.h> + +/ { + compatible = "renesas,r8a7743"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; + power-domains = <&sysc R8A7743_PD_CA15_CPU0>; + next-level-cache = <&L2_CA15>; + }; + + cpu1: cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency = <1500000000>; + power-domains = <&sysc R8A7743_PD_CA15_CPU1>; + next-level-cache = <&L2_CA15>; + }; + + L2_CA15: cache-controller at 0 { + compatible = "cache"; + reg = <0>; + cache-unified; + cache-level = <2>; + power-domains = <&sysc R8A7743_PD_CA15_SCU>; + }; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller at f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x1000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_LOW)>; + }; + + cpg: clock-controller at e6150000 { + compatible = "renesas,r8a7743-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + }; + + sysc: system-controller at e6180000 { + compatible = "renesas,r8a7743-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overriden by the board. */ + clock-frequency = <0>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; +};
PATCH v3 4/11 ARM: dts: r8a7743: initial SoC device tree
Hi Sergei,
Quoted 7 lines · Sergei Shtylyov
The initial R8A7743 SoC device tree including CPU cores, GIC, timer, SYSC, CPG, and the required clock descriptions.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
Signed-off-by Sergei Shtylyov <[email protected]>
I notice that this patch enables two CPUs. Have you tested SMP and:
- CPU hotplug
- Suspend to RAM
PATCH v3 4/11 ARM: dts: r8a7743: initial SoC device tree
Quoted 4 lines · Simon Horman
Quoted 3 lines · Sergei Shtylyov
The initial R8A7743 SoC device tree including CPU cores, GIC, timer, SYSC, CPG, and the required clock descriptions.
Quoted 8 lines
Quoted 4 lines
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
Signed-off-by Sergei Shtylyov <[email protected]>I notice that this patch enables two CPUs. Have you tested SMP and:
- CPU hotplug
- Suspend to RAM
The APMU node and the CPU enable-method "renesas,apmu" are missing to have working SMP.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH v3 4/11 ARM: dts: r8a7743: initial SoC device tree
In reply to Simon HormanQuoted 11 lines · Simon Horman
Quoted 7 lines
The initial R8A7743 SoC device tree including CPU cores, GIC, timer, SYSC, CPG, and the required clock descriptions.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
Signed-off-by Sergei Shtylyov <[email protected]>I notice that this patch enables two CPUs. Have you tested SMP and:
- CPU hotplug
- Suspend to RAM
No, not really. I'll remove CPU1. :-<
MBR, Sergei
PATCH v3 4/11 ARM: dts: r8a7743: initial SoC device tree
Quoted 8 lines · Sergei Shtylyov
Quoted 6 lines · Simon Horman
Quoted 6 lines
The initial R8A7743 SoC device tree including CPU cores, GIC, timer, SYSC, CPG, and the required clock descriptions.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
Quoted 7 lines
Quoted 5 lines
Quoted 1 line
Signed-off-by Sergei Shtylyov <[email protected]>I notice that this patch enables two CPUs. Have you tested SMP and:
- CPU hotplug
- Suspend to RAMNo, not really. I'll remove CPU1. :-<
Thanks.
PATCH v3 4/11 ARM: dts: r8a7743: initial SoC device tree
In reply to Sergei ShtylyovQuoted 7 lines · Sergei Shtylyov
The initial R8A7743 SoC device tree including CPU cores, GIC, timer, SYSC, CPG, and the required clock descriptions.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
Signed-off-by Sergei Shtylyov <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH v3 5/11 ARM: dts: r8a7743: add SYS-DMAC support
In reply to Sergei ShtylyovDescribe SYS-DMAC0/1 in the R8A7743 device tree.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
---
Changes in version 3:
- resolved a reject;
- updated the "clocks" properties for the CPG/MSSR driver.
Changes in version 2:
- added Geert's tag.
arch/arm/boot/dts/r8a7743.dtsi | 64 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+)
arch/arm/boot/dts/r8a7743.dtsi +64 -0
@@ -98,6 +98,70 @@ reg = <0 0xe6180000 0 0x0200>; #power-domain-cells = <1>; }; + + dmac0: dma-controller at e6700000 { + compatible = "renesas,dmac-r8a7743", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller at e6720000 { + compatible = "renesas,dmac-r8a7743", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + #dma-cells = <1>; + dma-channels = <15>; + }; }; /* External root clock */
PATCH v3 6/11 ARM: dts: r8a7743: add [H]SCIF{A|B} support
In reply to Sergei ShtylyovDescribe [H]SCIF[AB] ports in the R8A7743 device tree.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
---
Changes in version 3:
- resolved a reject;
- updated the "clocks" properties for the CPG/MSSR driver;
- renamed the patch.
Changes in version 2:
- used the new RZ/G family "compatible" prop values, reformatting where needed;
- fixed the size cells of the SCIFB device nodes' "reg" properties;
- changed the size cells of the "reg" properties to hexadecimal;
- indented the SCIFA1 device node's closing brace correctly
- adjusted the patch description, renamed the patch.
arch/arm/boot/dts/r8a7743.dtsi | 261 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 261 insertions(+)
arch/arm/boot/dts/r8a7743.dtsi +261 -0
@@ -162,6 +162,267 @@ #dma-cells = <1>; dma-channels = <15>; }; + + scifa0: serial at e6c40000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rzg-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 0x40>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa1: serial at e6c50000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rzg-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 0x40>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa2: serial at e6c60000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rzg-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 0x40>; + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa3: serial at e6c70000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rzg-scifa", "renesas,scifa"; + reg = <0 0xe6c70000 0 0x40>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1106>; + clock-names = "fck"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa4: serial at e6c78000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rzg-scifa", "renesas,scifa"; + reg = <0 0xe6c78000 0 0x40>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1107>; + clock-names = "fck"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa5: serial at e6c80000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rzg-scifa", "renesas,scifa"; + reg = <0 0xe6c80000 0 0x40>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1108>; + clock-names = "fck"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb0: serial at e6c20000 { + compatible = "renesas,scifb-r8a7743", + "renesas,rzg-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb1: serial at e6c30000 { + compatible = "renesas,scifb-r8a7743", + "renesas,rzg-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb2: serial at e6ce0000 { + compatible = "renesas,scifb-r8a7743", + "renesas,rzg-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif0: serial at e6e60000 { + compatible = "renesas,scif-r8a7743", "renesas,rzg-scif", + "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif1: serial at e6e68000 { + compatible = "renesas,scif-r8a7743", "renesas,rzg-scif", + "renesas,scif"; + reg = <0 0xe6e68000 0 0x40>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif2: serial at e6e58000 { + compatible = "renesas,scif-r8a7743", "renesas,rzg-scif", + "renesas,scif"; + reg = <0 0xe6e58000 0 0x40>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 719>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif3: serial at e6ea8000 { + compatible = "renesas,scif-r8a7743", "renesas,rzg-scif", + "renesas,scif"; + reg = <0 0xe6ea8000 0 0x40>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 718>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif4: serial at e6ee0000 { + compatible = "renesas,scif-r8a7743", "renesas,rzg-scif", + "renesas,scif"; + reg = <0 0xe6ee0000 0 0x40>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 715>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif5: serial at e6ee8000 { + compatible = "renesas,scif-r8a7743", "renesas,rzg-scif", + "renesas,scif"; + reg = <0 0xe6ee8000 0 0x40>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 714>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif0: serial at e62c0000 { + compatible = "renesas,hscif-r8a7743", + "renesas,rzg-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 0x60>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif1: serial at e62c8000 { + compatible = "renesas,hscif-r8a7743", + "renesas,rzg-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 0x60>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif2: serial at e62d0000 { + compatible = "renesas,hscif-r8a7743", + "renesas,rzg-hscif", "renesas,hscif"; + reg = <0 0xe62d0000 0 0x60>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 713>, + <&cpg CPG_CORE R8A7743_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; }; /* External root clock */
PATCH v3 6/11 ARM: dts: r8a7743: add [H]SCIF{A|B} support
Quoted 6 lines · Sergei Shtylyov
Describe [H]SCIF[AB] ports in the R8A7743 device tree.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
Signed-off-by Sergei Shtylyov <[email protected]>
With the modifications indicated below:
arch/arm/boot/dts/r8a7743.dtsi line 168
Quoted 10 lines
arch/arm/boot/dts/r8a7743.dtsi +4
-0@@ -162,6 +162,267 @@ #dma-cells = <1>; dma-channels = <15>; }; + + scifa0: serial at e6c40000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rzg-scifa", "renesas,scifa";
Please use "renesas,rcar-gen2-scifa" instead of "renesas,rzg-scifa".
arch/arm/boot/dts/r8a7743.dtsi line 252
Quoted 3 lines
arch/arm/boot/dts/r8a7743.dtsi +3
-0+ scifb0: serial at e6c20000 { + compatible = "renesas,scifb-r8a7743", + "renesas,rzg-scifb", "renesas,scifb";
"renesas,rcar-gen2-scifb"
arch/arm/boot/dts/r8a7743.dtsi line 173
Quoted 2 lines
arch/arm/boot/dts/r8a7743.dtsi +2
-0+ scif0: serial at e6e60000 { + compatible = "renesas,scif-r8a7743", "renesas,rzg-scif",
"renesas,rcar-gen2-scif"
arch/arm/boot/dts/r8a7743.dtsi line 384
Quoted 3 lines
arch/arm/boot/dts/r8a7743.dtsi +3
-0+ hscif0: serial at e62c0000 { + compatible = "renesas,hscif-r8a7743", + "renesas,rzg-hscif", "renesas,hscif";
"renesas,rcar-gen2-hscif"
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH v3 7/11 ARM: dts: r8a7743: add Ether support
In reply to Sergei ShtylyovDefine the generic R8A7743 part of the Ether device node.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
---
Changes in version 3:
- resoled a reject;
- updated the "clocks" property for the CPG/MSSR driver.
Changes in version 2:
- new patch.
arch/arm/boot/dts/r8a7743.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)
arch/arm/boot/dts/r8a7743.dtsi +12 -0
@@ -423,6 +423,18 @@ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; status = "disabled"; }; + + ether: ethernet at ee700000 { + compatible = "renesas,ether-r8a7743"; + reg = <0 0xee700000 0 0x400>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; /* External root clock */
PATCH v3 7/11 ARM: dts: r8a7743: add Ether support
Quoted 6 lines · Sergei Shtylyov
Define the generic R8A7743 part of the Ether device node.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
Signed-off-by Sergei Shtylyov <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH v3 8/11 ARM: dts: r8a7743: add IRQC support
In reply to Sergei ShtylyovDescribe the IRQC interrupt controller in the R8A7743 device tree.
---
Changes in version 3:
- updated the "clocks" property for the CPG/MSSR driver.
Changes in version 2:
- new patch.
arch/arm/boot/dts/r8a7743.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
arch/arm/boot/dts/r8a7743.dtsi +19 -0
@@ -72,6 +72,25 @@ IRQ_TYPE_LEVEL_HIGH)>; }; + irqc: interrupt-controller at e61c0000 { + compatible = "renesas,irqc-r8a7743", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
PATCH v3 8/11 ARM: dts: r8a7743: add IRQC support
Quoted 3 lines · Sergei Shtylyov
Describe the IRQC interrupt controller in the R8A7743 device tree.
Signed-off-by Sergei Shtylyov <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
A message that is not in the archive (sent off-list or not yet received): 2056698.ncAHq8vRQ3-gHKXc3Y1Z8zGSmamagVegGFoWSdPRAKMAL8bYrjMMd8@public.gmane.org
PATCH v3 9/11 DT: arm: shmobile: document SK-RZG1M board
Document the SK-RZG1M device tree bindings, listing it as a supported board.
This allows to use checkpatch.pl to validate .dts files referring to the SK-RZG1M board.
---
Changes in version 3:
- added Geert's tag.
Changes in version 2:
- new patch.
Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/arm/shmobile.txt +2 -0
@@ -75,5 +75,7 @@ Boards: compatible = "renesas,salvator-x", "renesas,r8a7796"; - SILK (RTP0RC7794LCB00011S) compatible = "renesas,silk", "renesas,r8a7794" + - SK-RZG1M (YR8A77430S000BE) + compatible = "renesas,sk-rzg1m", "renesas,r8a7743" - Wheat compatible = "renesas,wheat", "renesas,r8a7792"
--
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Re: [PATCH v3 09/11] DT: arm: shmobile: document SK-RZG1M board
Quoted 7 lines · Sergei Shtylyov
Document the SK-RZG1M device tree bindings, listing it as a supported board.
This allows to use checkpatch.pl to validate .dts files referring to the SK-RZG1M board.
Reviewed-by Geert Uytterhoeven <[email protected]>
Thanks, I have queued this up as "ARM: shmobile: document SK-RZG1M board" --
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PATCH v3 10/11 ARM: dts: sk-rzg1m: initial device tree
In reply to Sergei ShtylyovAdd the initial device tree for the R8A7743 SoC based SK-RZG1M board. The board has one debug serial port (SCIF0); include support for it, so that the serial console can work.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
---
Changes in version 3:
- added Geert's tag.
arch/arm/boot/dts/Makefile | 1 arch/arm/boot/dts/r8a7743-sk-rzg1m.dts | 44 +++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+)
arch/arm/boot/dts/Makefile +1 -0
@@ -654,6 +654,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ r7s72100-rskrza1.dtb \ r8a73a4-ape6evm.dtb \ r8a7740-armadillo800eva.dtb \ + r8a7743-sk-rzg1m.dtb \ r8a7778-bockw.dtb \ r8a7779-marzen.dtb \ r8a7790-lager.dtb \
arch/arm/boot/dts/r8a7743-sk-rzg1m.dts new file +44 -0
44 lines not on this page · raw message
PATCH v3 11/11 ARM: dts: sk-rzg1m: add Ether support
In reply to Sergei ShtylyovDefine the SK-RZG1M board dependent part of the Ether device node. Enable DHCP and NFS root for the kernel booting.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
---
Changes in version 2:
- new patch.
arch/arm/boot/dts/r8a7743-sk-rzg1m.dts | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-)
arch/arm/boot/dts/r8a7743-sk-rzg1m.dts +14 -1
@@ -20,7 +20,7 @@ }; chosen { - bootargs = "ignore_loglevel"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; stdout-path = "serial0:115200n8"; };
@@ -42,3 +42,16 @@ &scif0 { status = "okay"; }; + +ðer { + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy at 1 { + reg = <1>; + interrupt-parent = <&irqc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + }; +};
PATCH v3 11/11 ARM: dts: sk-rzg1m: add Ether support
Quoted 7 lines · Sergei Shtylyov
Define the SK-RZG1M board dependent part of the Ether device node. Enable DHCP and NFS root for the kernel booting.
Based on the original (and large) patch by Dmitry Shifrin <[email protected]>.
Signed-off-by Sergei Shtylyov <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
v3 cover Add R8A7743/SK-RZG1M board support
In reply to Sergei ShtylyovQuoted 5 lines · Sergei Shtylyov
Here's the set of 11 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20161003-v4.8' tag. I'm adding the device tree support for the R8A7743-based SK-RZG1M board. The SoC is close to R8A7791 and the board seems identical to the R8A7791/Porter board. The device tree patches depend on the R8A7743 CPG/MSSR driver series just posted in order to compile and work.
Forgot to mention that this version causes a regression with the sh_eth
driver (well, actually with phylib): since IRQC now gets a deferred probing, PHY IRQ doesn't work anymore -- phylib falls back to polling.
MBR, Sergei
v3 cover Add R8A7743/SK-RZG1M board support
Quoted 11 lines · Sergei Shtylyov
Quoted 5 lines · Sergei Shtylyov
Here's the set of 11 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20161003-v4.8' tag. I'm adding the device tree support for the R8A7743-based SK-RZG1M board. The SoC is close to R8A7791 and the board seems identical to the R8A7791/Porter board. The device tree patches depend on the R8A7743 CPG/MSSR driver series just posted in order to compile and work.Forgot to mention that this version causes a regression with the
sh_eth
driver (well, actually with phylib): since IRQC now gets a deferred probing, PHY IRQ doesn't work anymore -- phylib falls back to polling.
Is there a resolution to that problem?
v3 cover Add R8A7743/SK-RZG1M board support
Quoted 11 lines · Simon Horman
Quoted 9 lines
Quoted 5 lines
Here's the set of 11 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20161003-v4.8' tag. I'm adding the device tree support for the R8A7743-based SK-RZG1M board. The SoC is close to R8A7791 and the board seems identical to the R8A7791/Porter board. The device tree patches depend on the R8A7743 CPG/MSSR driver series just posted in order to compile and work.Forgot to mention that this version causes a regression with the
sh_eth
driver (well, actually with phylib): since IRQC now gets a deferred probing, PHY IRQ doesn't work anymore -- phylib falls back to polling.Is there a resolution to that problem?
Geert has posted his IRQC driver patch recently. Not sure if it was
intended for merging but it solves the issue.
MBR, Sergei
v3 cover Add R8A7743/SK-RZG1M board support
Quoted 8 lines · Sergei Shtylyov
Quoted 6 lines · Simon Horman
Quoted 6 lines
Quoted 5 lines
Here's the set of 11 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20161003-v4.8' tag. I'm adding the device tree support for the R8A7743-based SK-RZG1M board. The SoC is close to R8A7791 and the board seems identical to the R8A7791/Porter board. The device tree patches depend on the R8A7743 CPG/MSSR driver series just posted in order to compile and work.
Quoted 8 lines
Quoted 5 lines
Quoted 3 lines
Forgot to mention that this version causes a regression with the
sh_eth
driver (well, actually with phylib): since IRQC now gets a deferred probing, PHY IRQ doesn't work anymore -- phylib falls back to polling.Is there a resolution to that problem?
Geert has posted his IRQC driver patch recently. Not sure if it was
intended for merging but it solves the issue.
Ok. I think it is ok to merge support for a new board even if there are problems as its not regressing (can't break something that previously didn't exist imho). But of course it would be best if things did work.
Geert, do you have any comments on the relevance of your IRQC driver patch?
v3 cover Add R8A7743/SK-RZG1M board support
Hi Simon,
Quoted 14 lines · Simon Horman
Quoted 13 lines · Sergei Shtylyov
Quoted 11 lines · Simon Horman
Quoted 9 lines
Quoted 5 lines
Here's the set of 11 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20161003-v4.8' tag. I'm adding the device tree support for the R8A7743-based SK-RZG1M board. The SoC is close to R8A7791 and the board seems identical to the R8A7791/Porter board. The device tree patches depend on the R8A7743 CPG/MSSR driver series just posted in order to compile and work.Forgot to mention that this version causes a regression with the
sh_eth
driver (well, actually with phylib): since IRQC now gets a deferred probing, PHY IRQ doesn't work anymore -- phylib falls back to polling.Is there a resolution to that problem?
Quoted 8 lines
Quoted 2 lines
Geert has posted his IRQC driver patch recently. Not sure if it was
intended for merging but it solves the issue.Ok. I think it is ok to merge support for a new board even if there are problems as its not regressing (can't break something that previously didn't exist imho). But of course it would be best if things did work.
Geert, do you have any comments on the relevance of your IRQC driver patch?
That patch is relevant, until the MDIO framework is fixed.
It will start to matter more when migrating more (R-Car Gen2) SoCs to the new CPG/MSSR driver.
It would be good to give that patch some testing on more R-Car Gen2 boards with NFS root (difficult for me with remote access and network latencies).
After that I can submit it to the irqchip maintainers, as I don't believe MDIO will be fixed soonish...
Thanks for testing ;-)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds