clk: vc5: Add support for IDT VersaClock 5P49V5923B
Subsystems (3)
PATCH v2 1/1 clk: vc5: Add support for IDT VersaClock 5P49V5923B
Add driver for IDT VersaClock 5 5P49V5923B chip. This chip has two clock inputs, XTAL or CLK, which are muxed into single PLL/VCO input. The PLL feeds two fractional dividers. Each fractional divider feeds output mux, which allows selecting between clock from the fractional divider itself or from output mux on output N-1. In case of output mux 0, the output N-1 is instead connected to the output from the mux feeding the PLL.
The driver thus far supports only the 5P49V5923B, while it should be easily extensible to the whole 5P49V59xx family of chips as they are all pretty similar.
---
V2: - Drop address-cells and size-cells from the binding
- Add clock-names to the binding
- Drop vc5_input_names
- Fix assortment of spelling mistakes
- Switch div_frc and div_int datatype to uXX
- Switch f_in to u32
- Add missing remove
- Define macros for handling XIN and CLKIN
- Rework the FOD fractional divider calculation, this was wrong and made the output clock be off considerably under certain circumstances (when the fractional part was large).
--- .../devicetree/bindings/clock/idt,versaclock5.txt | 38 ++ drivers/clk/Kconfig | 10 + drivers/clk/Makefile | 1 + drivers/clk/clk-versaclock5.c | 714 +++++++++++++++++++++ 4 files changed, 763 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/idt,versaclock5.txt create mode 100644 drivers/clk/clk-versaclock5.c
Documentation/devicetree/bindings/clock/idt,versaclock5.txt new file +38 -0
@@ -0,0 +1,38 @@ +Binding for IDT VersaClock5 programmable i2c clock generator. + +The IDT VersaClock5 are programmable i2c clock generators providing +from 3 to 12 output clocks. + +==I2C device node== + +Required properties: +- compatible: shall be one of "idt,5p49v5923b". +- reg: i2c device address, shall be 0x68 or 0x6a. +- #clock-cells: from common clock binding; shall be set to 1. +- clocks: from common clock binding; list of parent clock handles, + shall be XTAL or CLKIN reference clock. +- clock-names: from common clock binding; clock input names, can be + either or both of "xin", "clkin". + +==Example== + +/* 25MHz reference crystal */ +ref25: ref25m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; +}; + +i2c-master-node { + + /* IDT 5P49V5923B i2c clock generator */ + vc5: clock-generator@6a { + compatible = "idt,5p49v5923b"; + reg = <0x6a>; + #clock-cells = <1>; + + /* Connect XIN input to 25MHz reference */ + clocks = <&ref25m>; + clock-names = "xin"; + }; +};
drivers/clk/Kconfig +10 -0
@@ -198,6 +198,16 @@ config COMMON_CLK_OXNAS ---help--- Support for the OXNAS SoC Family clocks. +config COMMON_CLK_VC5 + tristate "Clock driver for IDT VersaClock5 devices" + depends on I2C + depends on OF + select REGMAP_I2C + help + ---help--- + This driver supports the IDT VersaClock5 programmable clock + generator. + source "drivers/clk/bcm/Kconfig" source "drivers/clk/hisilicon/Kconfig" source "drivers/clk/mediatek/Kconfig"
drivers/clk/Makefile +1 -0
@@ -46,6 +46,7 @@ obj-$(CONFIG_ARCH_TANGO) += clk-tango4.o obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o obj-$(CONFIG_ARCH_U300) += clk-u300.o obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o +obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
drivers/clk/clk-versaclock5.c new file +714 -0
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2.11.0