clk: vc5: Add bindings for IDT VersaClock 5P49V5923 and 5P49V5933
Subsystems (4)
PATCH 1/2 clk: vc5: Add bindings for IDT VersaClock 5P49V5923 and 5P49V5933
Add bindings for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These are I2C clock generators with optional clock source from either XTal or dedicated clock generator and, depending on the model, two or more clock outputs.
--- .../devicetree/bindings/clock/idt,versaclock5.txt | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/idt,versaclock5.txt
Documentation/devicetree/bindings/clock/idt,versaclock5.txt new file +43 -0
@@ -0,0 +1,43 @@ +Binding for IDT VersaClock5 programmable i2c clock generator. + +The IDT VersaClock5 are programmable i2c clock generators providing +from 3 to 12 output clocks. + +==I2C device node== + +Required properties: +- compatible: shall be one of "idt,5p49v5923" , "idt,5p49v5933". +- reg: i2c device address, shall be 0x68 or 0x6a. +- #clock-cells: from common clock binding; shall be set to 1. +- clocks: from common clock binding; list of parent clock handles, + - 5p49v5923: (required) either or both of XTAL or CLKIN + reference clock. + - 5p49v5933: (optional) property not present (internal + Xtal used) or CLKIN reference + clock. +- clock-names: from common clock binding; clock input names, can be + - 5p49v5923: (required) either or both of "xin", "clkin". + - 5p49v5933: (optional) property not present or "clkin". + +==Example== + +/* 25MHz reference crystal */ +ref25: ref25m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; +}; + +i2c-master-node { + + /* IDT 5P49V5923 i2c clock generator */ + vc5: clock-generator@6a { + compatible = "idt,5p49v5923"; + reg = <0x6a>; + #clock-cells = <1>; + + /* Connect XIN input to 25MHz reference */ + clocks = <&ref25m>; + clock-names = "xin"; + }; +};
Signature · 1 line
2.11.0
PATCH v5 2/2 clk: vc5: Add support for IDT VersaClock 5P49V5923 and 5P49V5933
Add driver for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These chips have two clock inputs, XTAL or CLK, which are muxed into single PLL/VCO input. In case of 5P49V5923, the XTAL in built into the chip while the 5P49V5923 requires external XTAL.
The PLL feeds two fractional dividers. Each fractional divider feeds output mux, which allows selecting between clock from the fractional divider itself or from output mux on output N-1. In case of output mux 0, the output N-1 is instead connected to the output from the mux feeding the PLL.
The driver thus far supports only the 5P49V5923 and 5P49V5933, while it should be easily extensible to the whole 5P49V59xx family of chips as they are all pretty similar.
---
V2: - Drop address-cells and size-cells from the binding
- Add clock-names to the binding
- Drop vc5_input_names
- Fix assortment of spelling mistakes
- Switch div_frc and div_int datatype to uXX
- Switch f_in to u32
- Add missing remove
- Define macros for handling XIN and CLKIN
- Rework the FOD fractional divider calculation, this was wrong and made the output clock be off considerably under certain circumstances (when the fractional part was large).
V3: - Rework the MUX frequency recalculation and divider configration
so that it fits into the clock framework
- Add support for 5P49V5933 chip to lay groundwork for adding more chips easily.
- Export the OUT0_SEL_I2CB output into the clock framework, so it can be accessed from DT as well. WARNING: This does change the bindings, clock0 is now the OUT0_SEL_I2CB, clock1 is OUT1 and clock2 is OUT2 (or OUT4 on the 5P49V5933).
- Drop unnecessary caching of pin_*_name clock name and clk_hw structures in driver data.
- Add missing MAINTAINERS entry
V4: - Support also 5P49V5923A by dropping the B from the bindings and
code. According to the update notice, the chips are identical except for disabling the VCO monitoring, which is internal factory-defined bit and has no impact on silicon performance.
V5: - Make the CCF handle upstream clock enabling and disabling
- Drop test for unsigned value reg being less than zero
- Streamline vc5_map_index_to_output
--- MAINTAINERS | 5 + drivers/clk/Kconfig | 10 + drivers/clk/Makefile | 1 + drivers/clk/clk-versaclock5.c | 795 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 811 insertions(+) create mode 100644 drivers/clk/clk-versaclock5.c
MAINTAINERS +5 -0
@@ -6113,6 +6113,11 @@ S: Maintained F: drivers/mfd/lpc_ich.c F: drivers/gpio/gpio-ich.c +IDT VersaClock 5 CLOCK DRIVER +M: Marek Vasut <[email protected]> +S: Maintained +F: drivers/clk/clk-versaclock5.c + IDE SUBSYSTEM M: "David S. Miller" <[email protected]> L: [email protected]
drivers/clk/Kconfig +10 -0
@@ -198,6 +198,16 @@ config COMMON_CLK_OXNAS ---help--- Support for the OXNAS SoC Family clocks. +config COMMON_CLK_VC5 + tristate "Clock driver for IDT VersaClock5 devices" + depends on I2C + depends on OF + select REGMAP_I2C + help + ---help--- + This driver supports the IDT VersaClock5 programmable clock + generator. + source "drivers/clk/bcm/Kconfig" source "drivers/clk/hisilicon/Kconfig" source "drivers/clk/mediatek/Kconfig"
drivers/clk/Makefile +1 -0
@@ -46,6 +46,7 @@ obj-$(CONFIG_ARCH_TANGO) += clk-tango4.o obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o obj-$(CONFIG_ARCH_U300) += clk-u300.o obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o +obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
drivers/clk/clk-versaclock5.c new file +795 -0
795 lines not on this page · raw message
Signature · 1 line
2.11.0
PATCH 1/1 arm64: dts: r8a7795: salvator-x: Add DU0 and DU3 external dot clocks
The clocks are generated by an I2C-controlled programmable clock generator.
--- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 29 ++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-)
Hi Marek,
With this patch applied on top of a merge of my HDMI output series and your VC5 series, I've successfully tested VGA output and LVDS output on the Salvator-X H3 board. You can thus add
to patch 2/2.
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +27 -2
@@ -178,6 +178,12 @@ clock-frequency = <33000000>; }; + x23_clk: x23-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + hdmi0-out { compatible = "hdmi-connector"; label = "HDMI0 OUT";
@@ -271,10 +277,15 @@ <&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>, <&cpg CPG_MOD 727>, + <&versaclock5 1>, <&x21_clk>, - <&x22_clk>; + <&x22_clk>, + <&versaclock5 2>; clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0", - "dclkin.1", "dclkin.2"; + "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; + + assigned-clocks = <&versaclock5 1>, <&versaclock5 2>; + assigned-clock-rates = <148500000>, <108000000>; ports { port@0 {
@@ -460,6 +471,20 @@ }; }; +&i2c4 { + status = "okay"; + + clock-frequency = <100000>; + + versaclock5: clock-generator@6a { + compatible = "idt,5p49v5923"; + reg = <0x6a>; + #clock-cells = <1>; + clocks = <&x23_clk>; + clock-names = "xin"; + }; +}; + &rcar_sound { pinctrl-0 = <&sound_pins &sound_clk_pins>; pinctrl-names = "default";
Signature · 3 lines
Regards, Laurent Pinchart
Re: [PATCH] arm64: dts: r8a7795: salvator-x: Add DU0 and DU3 external dot clocks
Quoted 8 lines · Laurent Pinchart
The clocks are generated by an I2C-controlled programmable clock generator.
Signed-off-by Laurent Pinchart <[email protected]>--- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 29 ++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-)
Quoted 7 lines
Hi Marek,
With this patch applied on top of a merge of my HDMI output series and your VC5 series, I've successfully tested VGA output and LVDS output on the Salvator-X H3 board. You can thus add
Tested-by Laurent Pinchart <[email protected]>
Thanks!
Minor nit below :)
Quoted 24 lines
to patch 2/2.
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +7
-0@@ -178,6 +178,12 @@ clock-frequency = <33000000>; }; + x23_clk: x23-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + hdmi0-out { compatible = "hdmi-connector"; label = "HDMI0 OUT";@@ -271,10 +277,15 @@ <&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>, <&cpg CPG_MOD 727>, + <&versaclock5 1>,
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts line 288
Quoted 10 lines
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +6
-2<&x21_clk>, - <&x22_clk>; + <&x22_clk>, + <&versaclock5 2>; clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0", - "dclkin.1", "dclkin.2"; + "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; + + assigned-clocks = <&versaclock5 1>, <&versaclock5 2>; + assigned-clock-rates = <148500000>, <108000000>;
I think you want to remove these two lines ^^^^^^^^^
Quoted 24 lines
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +14
-0ports { port@0 {@@ -460,6 +471,20 @@ }; }; +&i2c4 { + status = "okay"; + + clock-frequency = <100000>; + + versaclock5: clock-generator@6a { + compatible = "idt,5p49v5923"; + reg = <0x6a>; + #clock-cells = <1>; + clocks = <&x23_clk>; + clock-names = "xin"; + }; +}; + &rcar_sound { pinctrl-0 = <&sound_pins &sound_clk_pins>; pinctrl-names = "default";
Signature · 2 lines
Best regards, Marek Vasut
Re: [PATCH] arm64: dts: r8a7795: salvator-x: Add DU0 and DU3 external dot clocks
Hi Marek,
Quoted 53 lines · On Thursday 12 Jan 2017 01:57:09 Marek Vasut wrote:
Quoted 10 lines · Laurent Pinchart
The clocks are generated by an I2C-controlled programmable clock generator.
Signed-off-by: Laurent Pinchart
<[email protected]>
---arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 29 +++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-)Quoted 7 lines
Hi Marek,
With this patch applied on top of a merge of my HDMI output series and your VC5 series, I've successfully tested VGA output and LVDS output on the Salvator-X H3 board. You can thus add
Tested-by Laurent Pinchart <[email protected]>Thanks!
Minor nit below :)
Quoted 30 lines
to patch 2/2.
(quoted diff) +0
-0
b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dtsindex2dc0887fc400..22be583be4bc100644arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +9
-1@@ -178,6 +178,12 @@ clock-frequency = <33000000>; }; + x23_clk: x23-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + hdmi0-out { compatible = "hdmi-connector"; label = "HDMI0 OUT";@@ -271,10 +277,15 @@ <&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>, <&cpg CPG_MOD 727>, + <&versaclock5 1>, <&x21_clk>, - <&x22_clk>; + <&x22_clk>, + <&versaclock5 2>;
Quoted 8 lines
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts line 288
Quoted 6 lines
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +4
-1clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0", - "dclkin.1", "dclkin.2"; + "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; + + assigned-clocks = <&versaclock5 1>, <&versaclock5 2>; + assigned-clock-rates = <148500000>, <108000000>;I think you want to remove these two lines ^^^^^^^^^
You're right. I've tested the patch with those two lines removed, and things still work fine. I'll resubmit.
Signature · 3 lines
Regards, Laurent Pinchart
Hi Marek,
Thank you for the patch.
Quoted 5 lines · On Wednesday 11 Jan 2017 17:16:02 Marek Vasut wrote:
Add bindings for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These are I2C clock generators with optional clock source from either XTal or dedicated clock generator and, depending on the model, two or more clock outputs.
Quoted 7 lines
Signed-off-by Marek Vasut <[email protected]>Cc Michael Turquette <[email protected]>Cc Stephen Boyd <[email protected]>Cc Laurent Pinchart <[email protected]>Cc Rob Herring <[email protected]>
Quoted 56 lines
--- .../devicetree/bindings/clock/idt,versaclock5.txt | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644
Documentation/devicetree/bindings/clock/idt,versaclock5.txt(quoted diff) +0
-0
b/Documentation/devicetree/bindings/clock/idt,versaclock5.txtnew file mode 100644
index 000000000000..82ebed9a8a15Documentation/devicetree/bindings/clock/idt,versaclock5.txt new file +43
-0@@ -0,0 +1,43 @@ +Binding for IDT VersaClock5 programmable i2c clock generator. + +The IDT VersaClock5 are programmable i2c clock generators providing +from 3 to 12 output clocks. + +==I2C device node== + +Required properties: +- compatible: shall be one of "idt,5p49v5923" , "idt,5p49v5933". +- reg: i2c device address, shall be 0x68 or 0x6a. +- #clock-cells: from common clock binding; shall be set to 1. +- clocks: from common clock binding; list of parent clock handles, + - 5p49v5923: (required) either or both of XTAL or CLKIN + reference clock. + - 5p49v5933: (optional) property not present (internal + Xtal used) or CLKIN reference + clock. +- clock-names: from common clock binding; clock input names, can be + - 5p49v5923: (required) either or both of "xin", "clkin". + - 5p49v5933: (optional) property not present or "clkin". + +==Example== + +/* 25MHz reference crystal */ +ref25: ref25m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; +}; + +i2c-master-node { + + /* IDT 5P49V5923 i2c clock generator */ + vc5: clock-generator@6a { + compatible = "idt,5p49v5923"; + reg = <0x6a>; + #clock-cells = <1>; + + /* Connect XIN input to 25MHz reference */ + clocks = <&ref25m>; + clock-names = "xin"; + }; +};
Signature · 3 lines
Regards, Laurent Pinchart