omap_hsmmc: Add ADMA support and UHS/HS200/DDR support
Subsystems (8)
cover omap_hsmmc: Add ADMA support and UHS/HS200/DDR support
This series adds UHS, HS200, DDR mode and ADMA support to omap_hsmmc driver used to improve the throughput of MMC/SD in dra7 SoCs.
The functionality implemented in this series was sent before ([1]) but was never followed up since supporting high speed modes in dra7 required IODelay values to be configured. With IODelay driver being merged into kernel, sending it as a fresh series with support for configuring IODelay values.
Suggestions of migrating to sdhci driver (from omap_hsmmc driver) is not addressed since
*) tuning ratio of MMC in dra7 is different from sdhci
*) IOdelay is required for dra7
*) GPIO based card detect is not supported in sdhci
*) Some of the registers don't always have correct values as in sdhci
(like PSTATE).
Supporting all of these in sdhci will result in adding lot of quirks in sdhci driver.
This series has been tested on beagleboard, pandaboard, beaglebone-black, beaglebone, am335x-evm, am437x-evm, dra7xx-evm, dra72x-evm, am571x-idk and am572x-idk.
I can split the series to go into Ulf Hansson's tree and Tony's tree separately if that is required.
[1] -> https://lkml.org/lkml/2015/8/25/213
Balaji T K (1):
mmc: host: omap_hsmmc: Add voltage switch support for UHS SD card
Kishon Vijay Abraham I (30):
mmc: host: omap_hsmmc: Support pbias and vmmc_aux to switch to 1.8v
mmc: host: omap_hsmmc: Separate setting voltage capabilities from bus
power
mmc: host: omap_hsmmc: Program HCTL based on signal_voltage set by mmc
core
mmc: host: omap_hsmmc: Set clk rate to the max frequency
mmc: host: omap_hsmmc: Add tuning support
mmc: host: omap_hsmmc: Allow io voltage switch even for fixed vdd
mmc: host: omap_hsmmc: Remove incorrect voltage switch sequence
mmc: host: omap_hsmmc: Prepare *set_timing() to be used for iodelay
setting
mmc: host: omap_hsmmc: Add new compatible string to support dra7
mmc: host: omap_hsmmc: Fix error path sequence
mmc: host: omap_hsmmc: Add support to set IODELAY values
mmc: host: omap_hsmmc: Remove *use_dma* member
mmc: host: omap_hsmmc: Enable ADMA2
ARM: dts: dra72-evm: Add vmmc_aux supply to mmc1
ARM: dts: dra72-evm-revc: Add vmmc_aux supply to mmc1
ARM: dts: am57xx-beagle-x15-revb1: Fix supply name used for MMC1 IO
lines
ARM: dts: dra7-evm: Add pinmux configuration for MMC
ARM: dts: am57xx-beagle-x15: Add pinmux configuration for MMC
ARM: dts: am571x-idk: Add pinmux configuration for MMC
ARM: dts: am572x-idk: Add pinmux configuration for MMC
ARM: dts: dra72-evm: Add pinmux configuration for MMC
ARM: dts: dra72-evm-revc: Add pinmux configuration for MMC
ARM: dts: dra71-evm: Add pinmux configuration for MMC
ARM: dts: dra7: Add "max-frequency" property to MMC dt nodes
ARM: dts: dra7: Use new dra7-specific compatible string
ARM: dts: dra7: Add supported MMC/SD modes in MMC dt nodes
ARM: dts: am57xx-beagle-x15-common: Set MMC2 IO voltage to 3.3V
ARM: omap2plus_defconfig: Enable PINCTRL_TI_IODELAY
ARM: multi_v7_defconfig: Enable PINCTRL_TI_IODELAY
Documentation: ARM: Document new dependencies for MMC on DRA7
Mugunthan V N (1):
mmc: host: omap_hsmmc: Add software timer when timeout greater than
hardware capablility
Ravikumar Kattekola (2):
ARM: dts: dra7-evm: Correct the vmmc-supply for mmc2
ARM: dts: dra72-evm-common: Correct vmmc-supply for mmc2
Sekhar Nori (6):
mmc: omap_hsmmc: Support non-1.8V IO controllers
ARM: dts: dra72x: Create a common file with MMC/SD IOdelay data
ARM: dts: dra74x: Create a common file with MMC/SD IOdelay data
ARM: dts: am57xx-idk: Move common MMC/SD properties to common file
ARM: dts: am57xx-idk: Set MMC2 IO voltage to 3.3V
ARM: OMAP2+: Add pdata-quirks for MMC/SD on DRA74x EVM
Tony Lindgren (1):
ARM: dts: Add dra7 iodelay configuration
Documentation/arm/OMAP/README | 4 + .../devicetree/bindings/mmc/ti-omap-hsmmc.txt | 6 + arch/arm/boot/dts/am571x-idk.dts | 27 +- arch/arm/boot/dts/am572x-idk.dts | 27 +- arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi | 30 +- arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts | 18 +- arch/arm/boot/dts/am57xx-beagle-x15.dts | 17 + arch/arm/boot/dts/am57xx-idk-common.dtsi | 10 + arch/arm/boot/dts/dra7-evm.dts | 28 +- arch/arm/boot/dts/dra7.dtsi | 35 +- arch/arm/boot/dts/dra71-evm.dts | 28 + arch/arm/boot/dts/dra72-evm-common.dtsi | 2 - arch/arm/boot/dts/dra72-evm-revc.dts | 32 + arch/arm/boot/dts/dra72-evm.dts | 32 + arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi | 350 ++++++ arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi | 648 +++++++++++ arch/arm/configs/multi_v7_defconfig | 1 + arch/arm/configs/omap2plus_defconfig | 1 + arch/arm/mach-omap2/pdata-quirks.c | 31 + drivers/mmc/host/omap_hsmmc.c | 1158 ++++++++++++++++---- include/dt-bindings/pinctrl/dra.h | 3 + include/linux/platform_data/hsmmc-omap.h | 10 + 22 files changed, 2256 insertions(+), 242 deletions(-) create mode 100644 arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi create mode 100644 arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi
Signature · 1 line
2.11.0
PATCH 1/41 mmc: host: omap_hsmmc: Support pbias and vmmc_aux to switch to 1.8v
Add support for vmmc_aux to switch to 1.8v. Also use "iov" instead of "vdd" to indicate io voltage. This is in preparation for adding support for io signal voltage switch.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
Signed-off-by Sekhar Nori <[email protected]>
--- drivers/mmc/host/omap_hsmmc.c | 50 ++++++++++++++++++++++++++++--------------- 1 file changed, 33 insertions(+), 17 deletions(-)
drivers/mmc/host/omap_hsmmc.c +33 -17
@@ -244,11 +244,12 @@ static int omap_hsmmc_get_cover_state(struct device *dev)return mmc_gpio_get_cd (host->mmc); } -static int omap_hsmmc_enable_supply (struct mmc_host *mmc) +static int omap_hsmmc_enable_supply (struct mmc_host *mmc,int iov) {int ret;struct omap_hsmmc_host *host =mmc_priv (mmc);struct mmc_ios *ios = &mmc->ios; +int uvoltage;if (mmc->supply.vmmc) { ret =mmc_regulator_set_ocr (mmc, mmc->supply.vmmc, ios->vdd);
@@ -257,7 +258,25 @@ static int omap_hsmmc_enable_supply(struct mmc_host *mmc) }/* Enable interface voltage rail, if needed */ -if (mmc->supply.vqmmc && !host->vqmmc_enabled) { +if (mmc->supply.vqmmc) { +if (host->vqmmc_enabled) { + ret =regulator_disable (mmc->supply.vqmmc); +if (ret) { +dev_err (mmc_dev (mmc), +"vmmc_aux reg disable failed\n" ); + goto err_vqmmc; + } + host->vqmmc_enabled =0 ; + } + + uvoltage = (iov ==VDD_165_195 ) ?VDD_1V8 :VDD_3V0 ; + ret =regulator_set_voltage (mmc->supply.vqmmc, uvoltage, + uvoltage); +if (ret) { +dev_err (mmc_dev (mmc),"vmmc_aux set voltage failed\n" ); + goto err_vqmmc; + } + ret =regulator_enable (mmc->supply.vqmmc);if (ret) {dev_err (mmc_dev (mmc),"vmmc_aux reg enable failed\n" );
@@ -309,22 +328,19 @@ static int omap_hsmmc_disable_supply(struct mmc_host *mmc) }static int omap_hsmmc_set_pbias (struct omap_hsmmc_host *host,bool power_on, -int vdd) +int iov) {int ret; +int uvoltage;if (!host->pbias)return 0 ;if (power_on) { -if (vdd <=VDD_165_195 ) - ret =regulator_set_voltage (host->pbias,VDD_1V8 , -VDD_1V8 ); -else - ret =regulator_set_voltage (host->pbias,VDD_3V0 , -VDD_3V0 ); -if (ret <0 ) { -dev_err (host->dev,"pbias set voltage fail\n" ); + uvoltage = (iov <=VDD_165_195 ) ?VDD_1V8 :VDD_3V0 ; + ret =regulator_set_voltage (host->pbias, uvoltage, uvoltage); +if (ret) { +dev_err (host->dev,"pbias set voltage failed\n" );return ret; }
@@ -351,13 +367,13 @@ static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on, }static int omap_hsmmc_set_power (struct omap_hsmmc_host *host,int power_on, -int vdd) +int iov) {struct mmc_host *mmc = host->mmc;int ret =0 ;if (mmc_pdata (host)->set_power) -return mmc_pdata (host)->set_power (host->dev, power_on, vdd); +return mmc_pdata (host)->set_power (host->dev, power_on, iov);/* * If we don't see a Vcc regulator, assume it's a fixed
@@ -367,7 +383,7 @@ static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on,return 0 ;if (mmc_pdata (host)->before_set_reg) -mmc_pdata (host)->before_set_reg (host->dev, power_on, vdd); +mmc_pdata (host)->before_set_reg (host->dev, power_on, iov); ret =omap_hsmmc_set_pbias (host, false,0 );if (ret)
@@ -387,11 +403,11 @@ static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on,* chips/cards need an interface voltage rail too. */ if (power_on) { - ret =omap_hsmmc_enable_supply (mmc); + ret =omap_hsmmc_enable_supply (mmc, iov);if (ret)return ret; - ret =omap_hsmmc_set_pbias (host, true, vdd); + ret =omap_hsmmc_set_pbias (host, true, iov);if (ret) goto err_set_voltage; }else {
@@ -401,7 +417,7 @@ static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on, }if (mmc_pdata (host)->after_set_reg) -mmc_pdata (host)->after_set_reg (host->dev, power_on, vdd); +mmc_pdata (host)->after_set_reg (host->dev, power_on, iov);return 0 ;
Signature · 1 line
2.11.0
PATCH 2/41 mmc: host: omap_hsmmc: Separate setting voltage capabilities from bus power
In reply to Kishon Vijay Abraham IAdd a separate function to set the voltage capabilities of the host controller. Voltage capabilities should be set only once during controller initialization but bus power can be changed every time there is a voltage switch and whenever a different card is inserted. This allows omap_hsmmc_conf_bus_power to be invoked every time there is a voltage switch.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
Signed-off-by Sekhar Nori <[email protected]>
--- drivers/mmc/host/omap_hsmmc.c | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-)
drivers/mmc/host/omap_hsmmc.c +19 -9
@@ -1809,25 +1809,34 @@ static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)return ret; } +static void omap_hsmmc_set_capabilities (struct omap_hsmmc_host *host) +{ +u32 val; + + val =OMAP_HSMMC_READ (host->base,CAPA ); + +/* Only MMC1 supports 3.0V */ +if (host->pdata->controller_flags &OMAP_HSMMC_SUPPORTS_DUAL_VOLT ) + val |= (VS30 |VS18 ); +else + val |=VS18 ; + +OMAP_HSMMC_WRITE (host->base,CAPA , val); +} +static void omap_hsmmc_conf_bus_power (struct omap_hsmmc_host *host) { -u32 hctl, capa, value; +u32 hctl, value;/* Only MMC1 supports 3.0V */ -if (host->pdata->controller_flags &OMAP_HSMMC_SUPPORTS_DUAL_VOLT ) { +if (host->pdata->controller_flags &OMAP_HSMMC_SUPPORTS_DUAL_VOLT ) hctl =SDVS30 ; - capa =VS30 |VS18 ; - }else { +else hctl =SDVS18 ; - capa =VS18 ; - } value =OMAP_HSMMC_READ (host->base,HCTL ) & ~SDVS_MASK ;OMAP_HSMMC_WRITE (host->base,HCTL , value | hctl); - value =OMAP_HSMMC_READ (host->base,CAPA ); -OMAP_HSMMC_WRITE (host->base,CAPA , value | capa); -/* Set SD bus power bit */ set_sd_bus_power (host); }
@@ -2134,6 +2143,7 @@ static int omap_hsmmc_probe(struct platform_device *pdev) mmc->pm_caps |=mmc_pdata (host)->pm_caps; +omap_hsmmc_set_capabilities (host);omap_hsmmc_conf_bus_power (host); host->rx_chan =dma_request_chan (&pdev->dev,"rx" );
Signature · 1 line
2.11.0
PATCH 3/41 mmc: host: omap_hsmmc: Program HCTL based on signal_voltage set by mmc core
In reply to Kishon Vijay Abraham IHCTL is now set based on ios.signal_voltage set by mmc core and not hardcoded to 3V0 if OMAP_HSMMC_SUPPORTS_DUAL_VOLT is set. If OMAP_HSMMC_SUPPORTS_DUAL_VOLT is set, it means HCTL can be set to either 3V0 or 1V8. And it should be set to 3V0 or 1V8 depending on ios.signal_voltage.
Also it is now set on power mode status being changed to MMC_POWER_ON.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
Signed-off-by Sekhar Nori <[email protected]>
--- drivers/mmc/host/omap_hsmmc.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-)
drivers/mmc/host/omap_hsmmc.c +7 -9
@@ -229,6 +229,7 @@ struct omap_mmc_of_data { };static void omap_hsmmc_start_dma_transfer (struct omap_hsmmc_host *host); +static void omap_hsmmc_conf_bus_power (struct omap_hsmmc_host *host,int iov);static int omap_hsmmc_card_detect (struct device *dev) {
@@ -1664,6 +1665,7 @@ static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)omap_hsmmc_set_power (host,1 , ios->vdd);break ;case MMC_POWER_ON : +omap_hsmmc_conf_bus_power (host, ios->signal_voltage); do_send_init_stream =1 ;break ; }
@@ -1824,17 +1826,12 @@ static void omap_hsmmc_set_capabilities(struct omap_hsmmc_host *host)OMAP_HSMMC_WRITE (host->base,CAPA , val); } -static void omap_hsmmc_conf_bus_power (struct omap_hsmmc_host *host) +static void omap_hsmmc_conf_bus_power (struct omap_hsmmc_host *host,int iov) {u32 hctl, value; -/* Only MMC1 supports 3.0V */ -if (host->pdata->controller_flags &OMAP_HSMMC_SUPPORTS_DUAL_VOLT ) - hctl =SDVS30 ; -else - hctl =SDVS18 ; - value =OMAP_HSMMC_READ (host->base,HCTL ) & ~SDVS_MASK ; + hctl = (iov ==MMC_SIGNAL_VOLTAGE_180 ) ?SDVS18 :SDVS30 ;OMAP_HSMMC_WRITE (host->base,HCTL , value | hctl);/* Set SD bus power bit */
@@ -2144,7 +2141,6 @@ static int omap_hsmmc_probe(struct platform_device *pdev) mmc->pm_caps |=mmc_pdata (host)->pm_caps;omap_hsmmc_set_capabilities (host); -omap_hsmmc_conf_bus_power (host); host->rx_chan =dma_request_chan (&pdev->dev,"rx" );if (IS_ERR (host->rx_chan)) {
@@ -2281,6 +2277,7 @@ static int omap_hsmmc_suspend(struct device *dev)static int omap_hsmmc_resume (struct device *dev) {struct omap_hsmmc_host *host =dev_get_drvdata (dev); +struct mmc_ios *ios;if (!host)return 0 ;
@@ -2290,8 +2287,9 @@ static int omap_hsmmc_resume(struct device *dev)if (host->dbclk)clk_prepare_enable (host->dbclk); + ios = &host->mmc->ios;if (!(host->mmc->pm_flags &MMC_PM_KEEP_POWER )) -omap_hsmmc_conf_bus_power (host); +omap_hsmmc_conf_bus_power (host, ios->signal_voltage);omap_hsmmc_protect_card (host);pm_runtime_mark_last_busy (host->dev);
Signature · 1 line
2.11.0
PATCH 4/41 mmc: host: omap_hsmmc: Add voltage switch support for UHS SD card
In reply to Kishon Vijay Abraham IFrom: Balaji T K <[email protected]>
UHS SD card i/o data line operates at 1.8V when in UHS speed mode.
Add support for signal voltage switch to support UHS cards.
Also, enable CIRQ before checking for CLEV/DLEV. MMC module can sense when the clock lines and data lines are driven high by the card, if MMC is active and CIRQ can be used to keep the MMC module active. This is required for voltage switching to succeed and the card to enumerate in UHS mode.
Signed-off-by Balaji T K <[email protected]>
Signed-off-by Sourav Poddar <[email protected]>
[kishon at ti.com : cleanup the voltage switch sequence]
Signed-off-by Kishon Vijay Abraham I <[email protected]>
[nsekhar at ti.com: make card busy functions preempt safe]
Signed-off-by Sekhar Nori <[email protected]>
--- drivers/mmc/host/omap_hsmmc.c | 165 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 165 insertions(+)
drivers/mmc/host/omap_hsmmc.c +165 -0
@@ -44,6 +44,7 @@#include <linux/pm_runtime.h> #include <linux/pm_wakeirq.h> #include <linux/platform_data/hsmmc-omap.h> +#include <linux/mmc/sd.h> /* OMAP HSMMC Host Controller Registers */ #define OMAP_HSMMC_SYSSTATUS 0x0014
@@ -111,6 +112,9 @@/* PSTATE */ #define DLEV_DAT (x) (1 << (20 + (x))) +/* AC12 */ +#define AC12_V1V8_SIGEN (1 << 19) +/* Interrupt masks for IE and ISE register */ #define CC_EN (1 << 0)#define TC_EN (1 << 1)
@@ -150,6 +154,13 @@#define VDD_1V8 1800000/* 180000 uV */ #define VDD_3V0 3000000/* 300000 uV */ #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1) +#define VDD_30_31 (ffs(MMC_VDD_30_31) - 1) + +#define CON_CLKEXTFREE (1 << 16) +#define CON_PADEN (1 << 15) +#define PSTATE_CLEV (1 << 24) +#define PSTATE_DLEV (0xF << 20) +#define PSTATE_DLEV_DAT0 (0x1 << 20)/* * One controller can have multiple slots, like on some omap boards using
@@ -177,6 +188,7 @@ struct omap_hsmmc_host {struct mmc_host *mmc;struct mmc_request *mrq;struct mmc_command *cmd; +u32 last_cmd;struct mmc_data *data;struct clk *fclk;struct clk *dbclk;
@@ -209,6 +221,7 @@ struct omap_hsmmc_host {unsigned int flags;#define AUTO_CMD23 (1 << 0)/* Auto CMD23 support */ #define HSMMC_SDIO_IRQ_ENABLED (1 << 1)/* SDIO irq enabled */ +#define CLKEXTFREE_ENABLED (1 << 2)/* CLKEXTFREE enabled */ struct omap_hsmmc_next next_data;struct omap_hsmmc_platform_data *pdata;
@@ -604,6 +617,9 @@ static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,if (cmd->opcode ==MMC_ERASE ) irq_mask &= ~DTO_EN ; +if (host->flags &CLKEXTFREE_ENABLED ) + irq_mask |=CIRQ_EN ; +spin_lock_irqsave (&host->irq_lock, flags);OMAP_HSMMC_WRITE (host->base,STAT ,STAT_CLEAR );OMAP_HSMMC_WRITE (host->base,ISE , irq_mask);
@@ -947,6 +963,7 @@ omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, cmdreg |=DMAE ; host->req_in_progress =1 ; + host->last_cmd = cmd->opcode;OMAP_HSMMC_WRITE (host->base,ARG , cmd->arg);OMAP_HSMMC_WRITE (host->base,CMD , cmdreg);
@@ -1848,6 +1865,152 @@ static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,return blk_size; } +static int omap_hsmmc_start_signal_voltage_switch (struct mmc_host *mmc, +struct mmc_ios *ios) +{ +struct omap_hsmmc_host *host; +u32 val =0 ; +int ret =0 ; + + host =mmc_priv (mmc); + +if (ios->signal_voltage ==MMC_SIGNAL_VOLTAGE_330 ) { + val =OMAP_HSMMC_READ (host->base,CAPA ); +if (!(val &VS30 )) +return -EOPNOTSUPP ; + +omap_hsmmc_conf_bus_power (host, ios->signal_voltage); + + val =OMAP_HSMMC_READ (host->base,AC12 ); + val &= ~AC12_V1V8_SIGEN ; +OMAP_HSMMC_WRITE (host->base,AC12 , val); + + ret =omap_hsmmc_set_power (host,1 ,VDD_30_31 ); +if (ret) { +dev_err (mmc_dev (host->mmc),"failed to switch to 3v\n" ); +return ret; + } + +dev_dbg (mmc_dev (host->mmc)," i/o voltage switch to 3V\n" ); + }else if (ios->signal_voltage ==MMC_SIGNAL_VOLTAGE_180 ) { + val =OMAP_HSMMC_READ (host->base,CAPA ); +if (!(val &VS18 )) +return -EOPNOTSUPP ; + +omap_hsmmc_conf_bus_power (host, ios->signal_voltage); + + val =OMAP_HSMMC_READ (host->base,AC12 ); + val |=AC12_V1V8_SIGEN ; +OMAP_HSMMC_WRITE (host->base,AC12 , val); + + ret =omap_hsmmc_set_power (host,1 ,VDD_165_195 ); +if (ret <0 ) { +dev_err (mmc_dev (host->mmc),"failed to switch 1.8v\n" ); +return ret; + } + }else { +return -EOPNOTSUPP ; + } + +return 0 ; +} + +static int omap_hsmmc_card_busy_low (struct omap_hsmmc_host *host) +{ +int i; +u32 val; + + val =OMAP_HSMMC_READ (host->base,CON ); + val &= ~CON_CLKEXTFREE ; + val |=CON_PADEN ; +OMAP_HSMMC_WRITE (host->base,CON , val); + +/* By observation, card busy status reflects in 100 - 200us */ +for (i =0 ; i <5 ; i++) { + val =OMAP_HSMMC_READ (host->base,PSTATE ); +if (!(val & (PSTATE_CLEV |PSTATE_DLEV ))) +return true; + +usleep_range (100 ,200 ); + } + +dev_err (mmc_dev (host->mmc),"card busy\n" ); + +return false; +} + +static int omap_hsmmc_card_busy_high (struct omap_hsmmc_host *host) +{ +int i; +u32 val; +int ret = true; + + val =OMAP_HSMMC_READ (host->base,CON ); + val |=CLKEXTFREE ; +OMAP_HSMMC_WRITE (host->base,CON , val); + + host->flags |=CLKEXTFREE_ENABLED ; +disable_irq (host->irq); +omap_hsmmc_enable_irq (host,NULL ); + +/* By observation, card busy status reflects in 100 - 200us */ +for (i =0 ; i <5 ; i++) { + val =OMAP_HSMMC_READ (host->base,PSTATE ); +if ((val &PSTATE_CLEV ) && (val &PSTATE_DLEV )) { + val =OMAP_HSMMC_READ (host->base,CON ); + val &= ~(CON_CLKEXTFREE |CON_PADEN ); +OMAP_HSMMC_WRITE (host->base,CON , val); + ret = false; + goto disable_irq; + } + +usleep_range (100 ,200 ); + } + +dev_err (mmc_dev (host->mmc),"card busy\n" ); + +disable_irq: +omap_hsmmc_disable_irq (host); +enable_irq (host->irq); + host->flags &= ~CLKEXTFREE_ENABLED ; + +return ret; +} + +static int omap_hsmmc_card_busy (struct mmc_host *mmc) +{ +struct omap_hsmmc_host *host; +u32 val; +u32 reg; +int ret; + + host =mmc_priv (mmc); + +if (host->last_cmd !=SD_SWITCH_VOLTAGE ) { +/* +* PADEN should be set for DLEV to reflect the correct +* state of data lines atleast for MMC1 on AM57x. +*/ + reg =OMAP_HSMMC_READ (host->base,CON ); + reg |=CON_PADEN ; +OMAP_HSMMC_WRITE (host->base,CON , reg); + val =OMAP_HSMMC_READ (host->base,PSTATE ); + reg &= ~CON_PADEN ; +OMAP_HSMMC_WRITE (host->base,CON , reg); +if (val &PSTATE_DLEV_DAT0 ) +return false; +return true; + } + + val =OMAP_HSMMC_READ (host->base,AC12 ); +if (val &AC12_V1V8_SIGEN ) + ret =omap_hsmmc_card_busy_high (host); +else + ret =omap_hsmmc_card_busy_low (host); + +return ret; +} +static struct mmc_host_ops omap_hsmmc_ops = { .post_req = omap_hsmmc_post_req, .pre_req = omap_hsmmc_pre_req,
@@ -1857,6 +2020,8 @@ static struct mmc_host_ops omap_hsmmc_ops = { .get_ro = mmc_gpio_get_ro, .init_card = omap_hsmmc_init_card, .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, + .start_signal_voltage_switch = omap_hsmmc_start_signal_voltage_switch, + .card_busy = omap_hsmmc_card_busy, };#ifdef CONFIG_DEBUG_FS
Signature · 1 line
2.11.0
PATCH 5/41 mmc: host: omap_hsmmc: Set clk rate to the max frequency
In reply to Kishon Vijay Abraham ISet the clock rate of the functional clock to the max frequency that is passed to the driver either using pdata or dt.
Also remove unnecessary setting of host->fclk to NULL.
This is in preparation for supporting high frequency modes of operation.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
Signed-off-by Sekhar Nori <[email protected]>
--- drivers/mmc/host/omap_hsmmc.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-)
drivers/mmc/host/omap_hsmmc.c +15 -8
@@ -2244,22 +2244,29 @@ static int omap_hsmmc_probe(struct platform_device *pdev) mmc->ops = &omap_hsmmc_ops; - mmc->f_min =OMAP_MMC_MIN_CLOCK ; - -if (pdata->max_freq >0 ) - mmc->f_max = pdata->max_freq; -else if (mmc->f_max ==0 ) - mmc->f_max =OMAP_MMC_MAX_CLOCK ; -spin_lock_init (&host->irq_lock); host->fclk =devm_clk_get (&pdev->dev,"fck" );if (IS_ERR (host->fclk)) { ret =PTR_ERR (host->fclk); - host->fclk =NULL ; goto err1; } + mmc->f_min =OMAP_MMC_MIN_CLOCK ; +if (pdata->max_freq >0 ) + mmc->f_max = pdata->max_freq; + +if (mmc->f_max) { + ret =clk_set_rate (host->fclk, mmc->f_max); +if (ret) { +dev_err (&pdev->dev,"failed to set clock to %d\n" , + mmc->f_max); + goto err1; + } + }else { + mmc->f_max =OMAP_MMC_MAX_CLOCK ; + } +if (host->pdata->controller_flags &OMAP_HSMMC_BROKEN_MULTIBLOCK_READ ) {dev_info (&pdev->dev,"multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n" ); omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
Signature · 1 line
2.11.0
PATCH 6/41 mmc: host: omap_hsmmc: Add tuning support
In reply to Kishon Vijay Abraham IMMC tuning procedure is required to support SD card UHS1-SDR104 mode and EMMC HS200 mode.
The tuning function omap_execute_tuning() will only be called by the MMC/SD core if the corresponding speed modes are supported by the OMAP silicon which is set in the mmc host "caps" field.
Add a separate function to set the UHSMS field to one of SDR104, SDR50, DDR50, SDR25 or SDR12 depending on the inserted SD card. This is required for tuning to succeed in the case of SDR104/HS200 or SDR50.
Signed-off-by Balaji T K <[email protected]>
[rk at ti.com: disable DEB interrupt during tuning]
Signed-off-by Ravikumar Kattekola <[email protected]>
Signed-off-by Viswanath Puttagunta <[email protected]>
Signed-off-by Sourav Poddar <[email protected]>
[kishon at ti.com : cleanup the tuning sequence]
Signed-off-by Kishon Vijay Abraham I <[email protected]>
[nsekhar at ti.com: add comment for tuning timeout]
Signed-off-by Sekhar Nori <[email protected]>
--- drivers/mmc/host/omap_hsmmc.c | 200 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 200 insertions(+)
drivers/mmc/host/omap_hsmmc.c +200 -0
@@ -18,6 +18,7 @@#include <linux/module.h> #include <linux/init.h> #include <linux/kernel.h> +#include <linux/slab.h> #include <linux/debugfs.h> #include <linux/dmaengine.h> #include <linux/seq_file.h>
@@ -49,6 +50,7 @@/* OMAP HSMMC Host Controller Registers */ #define OMAP_HSMMC_SYSSTATUS 0x0014#define OMAP_HSMMC_CON 0x002C +#define OMAP_HSMMC_DLL 0x0034#define OMAP_HSMMC_SDMASA 0x0100#define OMAP_HSMMC_BLK 0x0104#define OMAP_HSMMC_ARG 0x0108
@@ -66,6 +68,7 @@#define OMAP_HSMMC_ISE 0x0138#define OMAP_HSMMC_AC12 0x013C#define OMAP_HSMMC_CAPA 0x0140 +#define OMAP_HSMMC_CAPA2 0x0144#define VS18 (1 << 26)#define VS30 (1 << 25)
@@ -114,6 +117,26 @@/* AC12 */ #define AC12_V1V8_SIGEN (1 << 19) +#define AC12_SCLK_SEL (1 << 23) +#define AC12_UHSMC_MASK (7 << 16) +#define AC12_UHSMC_SDR12 (0 << 16) +#define AC12_UHSMC_SDR25 (1 << 16) +#define AC12_UHSMC_SDR50 (2 << 16) +#define AC12_UHSMC_SDR104 (3 << 16) +#define AC12_UHSMC_DDR50 (4 << 16) +#define AC12_UHSMC_RES (0x7 << 16) + +/* DLL */ +#define DLL_SWT (1 << 20) +#define DLL_FORCE_SR_C_SHIFT 13 +#define DLL_FORCE_SR_C_MASK 0x7f +#define DLL_FORCE_VALUE (1 << 12) +#define DLL_CALIB (1 << 1) + +#define MAX_PHASE_DELAY 0x7c + +/* CAPA2 */ +#define CAPA2_TSDR50 (1 << 13)/* Interrupt masks for IE and ISE register */ #define CC_EN (1 << 0)
@@ -202,6 +225,7 @@ struct omap_hsmmc_host {unsigned int dma_sg_idx;unsigned char bus_mode;unsigned char power_mode; +unsigned char timing;int suspended;u32 con;u32 hctl;
@@ -225,6 +249,8 @@ struct omap_hsmmc_host {struct omap_hsmmc_next next_data;struct omap_hsmmc_platform_data *pdata; +bool is_tuning; +/* return MMC cover switch state, can be NULL if not supported. * * possible return values:
@@ -243,6 +269,7 @@ struct omap_mmc_of_data {static void omap_hsmmc_start_dma_transfer (struct omap_hsmmc_host *host);static void omap_hsmmc_conf_bus_power (struct omap_hsmmc_host *host,int iov); +static void omap_hsmmc_disable_tuning (struct omap_hsmmc_host *host);static int omap_hsmmc_card_detect (struct device *dev) {
@@ -610,6 +637,15 @@ static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,u32 irq_mask =INT_EN_MASK ;unsigned long flags; +if (host->is_tuning) +/* +* OMAP5/DRA74X/DRA72x Errata i802: +* DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur +* during the tuning procedure. So disable it during the +* tuning procedure. +*/ + irq_mask &= ~(DCRC_EN |DEB_EN ); +if (host->use_dma) irq_mask &= ~(BRR_EN |BWR_EN );
@@ -959,6 +995,11 @@ omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, cmdreg &= ~(DDIR ); } +/* Tuning command is special. Data Present Select should be set */ +if ((cmd->opcode ==MMC_SEND_TUNING_BLOCK ) || + (cmd->opcode ==MMC_SEND_TUNING_BLOCK_HS200 )) + cmdreg |=DP_SELECT |DDIR ; +if (host->use_dma) cmdreg |=DMAE ;
@@ -1667,6 +1708,41 @@ static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)omap_hsmmc_start_command (host, req->cmd, req->data); } +static void omap_hsmmc_set_timing (struct omap_hsmmc_host *host) +{ +u32 val; +struct mmc_ios *ios = &host->mmc->ios; + +omap_hsmmc_stop_clock (host); + + val =OMAP_HSMMC_READ (host->base,AC12 ); + val &= ~AC12_UHSMC_MASK ; +switch (ios->timing) { +case MMC_TIMING_UHS_SDR104 : +case MMC_TIMING_MMC_HS200 : + val |=AC12_UHSMC_SDR104 ; +break ; +case MMC_TIMING_UHS_DDR50 : + val |=AC12_UHSMC_DDR50 ; +break ; +case MMC_TIMING_UHS_SDR50 : + val |=AC12_UHSMC_SDR50 ; +break ; +case MMC_TIMING_UHS_SDR25 : + val |=AC12_UHSMC_SDR25 ; +break ; +case MMC_TIMING_UHS_SDR12 : + val |=AC12_UHSMC_SDR12 ; +break ; +default : + val |=AC12_UHSMC_RES ; +break ; + } +OMAP_HSMMC_WRITE (host->base,AC12 , val); + +omap_hsmmc_start_clock (host); +} +/* Routine to configure clock values. Exposed API to core */ static void omap_hsmmc_set_ios (struct mmc_host *mmc,struct mmc_ios *ios) {
@@ -1676,6 +1752,7 @@ static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)if (ios->power_mode != host->power_mode) {switch (ios->power_mode) {case MMC_POWER_OFF : +omap_hsmmc_disable_tuning (host);omap_hsmmc_set_power (host,0 ,0 );break ;case MMC_POWER_UP :
@@ -1713,6 +1790,11 @@ static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)omap_hsmmc_set_clock (host); +if (ios->timing != host->timing) { +omap_hsmmc_set_timing (host); + host->timing = ios->timing; + } +if (do_send_init_stream)send_init_stream (host);
@@ -2011,6 +2093,122 @@ static int omap_hsmmc_card_busy(struct mmc_host *mmc)return ret; } +static inline void omap_hsmmc_set_dll (struct omap_hsmmc_host *host,int count) +{ +int i; +u32 dll; + + dll =OMAP_HSMMC_READ (host->base,DLL ); + dll |=DLL_FORCE_VALUE ; + dll &= ~(DLL_FORCE_SR_C_MASK <<DLL_FORCE_SR_C_SHIFT ); + dll |= (count <<DLL_FORCE_SR_C_SHIFT ); +OMAP_HSMMC_WRITE (host->base,DLL , dll); + + dll |=DLL_CALIB ; +OMAP_HSMMC_WRITE (host->base,DLL , dll); +for (i =0 ; i <1000 ; i++) { +if (OMAP_HSMMC_READ (host->base,DLL ) &DLL_CALIB ) +break ; + } + dll &= ~DLL_CALIB ; +OMAP_HSMMC_WRITE (host->base,DLL , dll); +} + +static void omap_hsmmc_disable_tuning (struct omap_hsmmc_host *host) +{ +int val; + + val =OMAP_HSMMC_READ (host->base,AC12 ); + val &= ~(AC12_SCLK_SEL ); +OMAP_HSMMC_WRITE (host->base,AC12 , val); + + val =OMAP_HSMMC_READ (host->base,DLL ); + val &= ~(DLL_FORCE_VALUE |DLL_SWT ); +OMAP_HSMMC_WRITE (host->base,DLL , val); +} + +static int omap_hsmmc_execute_tuning (struct mmc_host *mmc,u32 opcode) +{ +u32 val; +u8 cur_match, prev_match =0 ; +int ret; +u32 phase_delay =0 ; +u32 start_window =0 , max_window =0 ; +u32 length =0 , max_len =0 ; +struct mmc_ios *ios = &mmc->ios; +struct omap_hsmmc_host *host; + +/* clock tuning is not needed for upto 52MHz */ +if (ios->clock <=OMAP_MMC_MAX_CLOCK ) +return 0 ; + + host =mmc_priv (mmc); + + val =OMAP_HSMMC_READ (host->base,CAPA2 ); +if (ios->timing ==MMC_TIMING_UHS_SDR50 && !(val &CAPA2_TSDR50 )) +return 0 ; + + val =OMAP_HSMMC_READ (host->base,DLL ); + val |=DLL_SWT ; +OMAP_HSMMC_WRITE (host->base,DLL , val); + + host->is_tuning = true; + +while (phase_delay <=MAX_PHASE_DELAY ) { +omap_hsmmc_set_dll (host, phase_delay); + + cur_match = !mmc_send_tuning (mmc, opcode,NULL ); +if (cur_match) { +if (prev_match) { + length++; + }else { + start_window = phase_delay; + length =1 ; + } + } + +if (length > max_len) { + max_window = start_window; + max_len = length; + } + + prev_match = cur_match; + phase_delay +=4 ; + } + + host->is_tuning = false; + +if (!max_len) { +dev_err (mmc_dev (host->mmc),"Unable to find match\n" ); + ret = -EIO ; + goto tuning_error; + } + + val =OMAP_HSMMC_READ (host->base,AC12 ); +if (!(val &AC12_SCLK_SEL )) { + ret = -EIO ; + goto tuning_error; + } + + phase_delay = max_window +4 * ((3 * max_len) >>2 ); +omap_hsmmc_set_dll (host, phase_delay); + +omap_hsmmc_reset_controller_fsm (host,SRD ); +omap_hsmmc_reset_controller_fsm (host,SRC ); + +return 0 ; + +tuning_error: +dev_err (mmc_dev (host->mmc), +"Tuning failed. Using fixed sampling clock\n" ); + +omap_hsmmc_disable_tuning (host); +omap_hsmmc_reset_controller_fsm (host,SRD ); +omap_hsmmc_reset_controller_fsm (host,SRC ); + +return ret; +} +static struct mmc_host_ops omap_hsmmc_ops = { .post_req = omap_hsmmc_post_req, .pre_req = omap_hsmmc_pre_req,
@@ -2022,6 +2220,7 @@ static struct mmc_host_ops omap_hsmmc_ops = { .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, .start_signal_voltage_switch = omap_hsmmc_start_signal_voltage_switch, .card_busy = omap_hsmmc_card_busy, + .execute_tuning = omap_hsmmc_execute_tuning, };#ifdef CONFIG_DEBUG_FS
@@ -2229,6 +2428,7 @@ static int omap_hsmmc_probe(struct platform_device *pdev) host->mapbase = res->start + pdata->reg_offset; host->base = base + pdata->reg_offset; host->power_mode =MMC_POWER_OFF ; + host->timing =0 ; host->next_data.cookie =1 ; host->pbias_enabled =0 ; host->vqmmc_enabled =0 ;
Signature · 1 line
2.11.0
PATCH 7/41 mmc: host: omap_hsmmc: Allow io voltage switch even for fixed vdd
In reply to Kishon Vijay Abraham INow that vmmc regulator is made optional, do not bail out if vmmc regulator is not found.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
Signed-off-by Sekhar Nori <[email protected]>
--- drivers/mmc/host/omap_hsmmc.c | 7 ------- 1 file changed, 7 deletions(-)
drivers/mmc/host/omap_hsmmc.c +0 -7
@@ -416,13 +416,6 @@ static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on,if (mmc_pdata (host)->set_power)return mmc_pdata (host)->set_power (host->dev, power_on, iov); -/* -* If we don't see a Vcc regulator, assume it's a fixed -* voltage always-on regulator. -*/ -if (!mmc->supply.vmmc) -return 0 ; -if (mmc_pdata (host)->before_set_reg)mmc_pdata (host)->before_set_reg (host->dev, power_on, iov);
Signature · 1 line
2.11.0
PATCH 8/41 mmc: host: omap_hsmmc: Remove incorrect voltage switch sequence
In reply to Kishon Vijay Abraham Iios->vdd is set only in mmc_power_up and mmc_power_off and not in mmc_select_voltage() as mentioned in the code comment. This seems to be legacy code that has been carried for a long time without being tested.
This will be replaced with the correct voltage switch sequence and populated in start_signal_voltage_switch ops to be used by mmc core for switching voltages.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
--- drivers/mmc/host/omap_hsmmc.c | 79 ------------------------------------------- 1 file changed, 79 deletions(-)
drivers/mmc/host/omap_hsmmc.c +0 -79
@@ -1292,67 +1292,6 @@ static void set_sd_bus_power(struct omap_hsmmc_host *host) } } -/* -* Switch MMC interface voltage ... only relevant for MMC1. -* -* MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. -* The MMC2 transceiver controls are used instead of DAT4..DAT7. -* Some chips, like eMMC ones, use internal transceivers. -*/ -static int omap_hsmmc_switch_opcond (struct omap_hsmmc_host *host,int vdd) -{ -u32 reg_val =0 ; -int ret; - -/* Disable the clocks */ -if (host->dbclk) -clk_disable_unprepare (host->dbclk); - -/* Turn the power off */ - ret =omap_hsmmc_set_power (host,0 ,0 ); - -/* Turn the power ON with given VDD 1.8 or 3.0v */ -if (!ret) - ret =omap_hsmmc_set_power (host,1 , vdd); -if (host->dbclk) -clk_prepare_enable (host->dbclk); - -if (ret !=0 ) - goto err; - -OMAP_HSMMC_WRITE (host->base,HCTL , -OMAP_HSMMC_READ (host->base,HCTL ) &SDVSCLR ); - reg_val =OMAP_HSMMC_READ (host->base,HCTL ); - -/* -* If a MMC dual voltage card is detected, the set_ios fn calls -* this fn with VDD bit set for 1.8V. Upon card removal from the -* slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. -* -* Cope with a bit of slop in the range ... per data sheets: -* - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, -* but recommended values are 1.71V to 1.89V -* - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, -* but recommended values are 2.7V to 3.3V -* -* Board setup code shouldn't permit anything very out-of-range. -* TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the -* middle range) but VSIM can't power DAT4..DAT7 at more than 3V. -*/ -if ((1 << vdd) <=MMC_VDD_23_24 ) - reg_val |=SDVS18 ; -else - reg_val |=SDVS30 ; - -OMAP_HSMMC_WRITE (host->base,HCTL , reg_val); -set_sd_bus_power (host); - -return 0 ; -err: -dev_err (mmc_dev (host->mmc),"Unable to switch operating voltage\n" ); -return ret; -} -/* Protect the card while the cover is open */ static void omap_hsmmc_protect_card (struct omap_hsmmc_host *host) {
@@ -1763,24 +1702,6 @@ static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)omap_hsmmc_set_bus_width (host); -if (host->pdata->controller_flags &OMAP_HSMMC_SUPPORTS_DUAL_VOLT ) { -/* Only MMC1 can interface at 3V without some flavor -* of external transceiver; but they all handle 1.8V. -*/ -if ((OMAP_HSMMC_READ (host->base,HCTL ) &SDVSDET ) && - (ios->vdd ==DUAL_VOLT_OCR_BIT )) { -/* -* The mmc_select_voltage fn of the core does -* not seem to set the power_mode to -* MMC_POWER_UP upon recalculating the voltage. -* vdd 1.8v. -*/ -if (omap_hsmmc_switch_opcond (host, ios->vdd) !=0 ) -dev_dbg (mmc_dev (host->mmc), -"Switch operation failed\n" ); - } - } -omap_hsmmc_set_clock (host);if (ios->timing != host->timing) {
Signature · 1 line
2.11.0
PATCH 9/41 mmc: host: omap_hsmmc: Add software timer when timeout greater than hardware capablility
In reply to Kishon Vijay Abraham IFrom: Mugunthan V N <[email protected]>
DRA7 Errata No i834: When using high speed HS200 and SDR104 cards, the functional clock for MMC module will be 192MHz. At this frequency, the maximum obtainable timeout (DTO =0xE) in hardware is (1/192MHz)*2^27 = 700ms. Commands taking longer than 700ms will be affected by this small window frame and will be timing out frequently even without a genune timeout from the card. Workarround for this errata is use a software timer instead of hardware timer to provide the delay requested by the upper layer
So adding a software timer as a work around for the errata. Instead of using software timeout only for larger delays requested when using HS200/SDR104 cards which results in hardware and software timer race conditions, so move all the timeout request to use software timer when HS200/SDR104 card is connected and use hardware timer when other type cards are connected.
Also start the software timer after queueing to DMA to ensure we are more likely to expire within correct limits. To be ever more sure that we won't expire this soft timer too early, we're adding a 1000000ns slack to the data timeout requested by the upper layer.
[rk at ti.com: fix compiler warning in sw timeout function and use sw timeout for busy timeout]
Signed-off-by Ravikumar Kattekola <[email protected]>
Signed-off-by Mugunthan V N <[email protected]>
[kishon at ti.com: Fix the timeout value to account for the entire transfer to complete here.]
Signed-off-by Kishon Vijay Abraham I <[email protected]>
Signed-off-by Sekhar Nori <[email protected]>
--- drivers/mmc/host/omap_hsmmc.c | 126 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 109 insertions(+), 17 deletions(-)
drivers/mmc/host/omap_hsmmc.c +109 -17
@@ -185,6 +185,11 @@#define PSTATE_DLEV (0xF << 20)#define PSTATE_DLEV_DAT0 (0x1 << 20) +#define MMC_BLOCK_TRANSFER_TIME_NS (blksz, bus_width, freq) \ + ((unsigned long long) \ + (2 * (((blksz) * NSEC_PER_SEC * \ + (8 / (bus_width))) / (freq)))) +/* * One controller can have multiple slots, like on some omap boards using * omap.c controller driver. Luckily this is not currently done on any known
@@ -250,6 +255,8 @@ struct omap_hsmmc_host {struct omap_hsmmc_platform_data *pdata;bool is_tuning; +struct timer_list timer; +unsigned long long data_timeout;/* return MMC cover switch state, can be NULL if not supported. *
@@ -642,8 +649,8 @@ static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,if (host->use_dma) irq_mask &= ~(BRR_EN |BWR_EN ); -/* Disable timeout for erases */ -if (cmd->opcode ==MMC_ERASE ) +/* Disable timeout for erases or when using software timeout */ +if (cmd && (cmd->opcode ==MMC_ERASE || host->data_timeout)) irq_mask &= ~DTO_EN ;if (host->flags &CLKEXTFREE_ENABLED )
@@ -1250,8 +1257,16 @@ static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) }OMAP_HSMMC_WRITE (host->base,STAT , status); -if (end_cmd || ((status &CC_EN ) && host->cmd)) +if (end_cmd || ((status &CC_EN ) && host->cmd)) {omap_hsmmc_cmd_done (host, host->cmd); +if (host->data_timeout) { +unsigned long timeout; + + timeout = jiffies + +nsecs_to_jiffies (host->data_timeout); +mod_timer (&host->timer, timeout); + } + }if ((end_trans || (status &TC_EN )) && host->mrq)omap_hsmmc_xfer_done (host, data); }
@@ -1265,7 +1280,19 @@ static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)int status; status =OMAP_HSMMC_READ (host->base,STAT ); +while (status & (INT_EN_MASK |CIRQ_EN )) { +/* +* During a successful bulk data transfer command-completion +* interrupt and transfer-completion interrupt will be +* generated, but software-timeout timer should be deleted +* only on non-cc interrupts (transfer complete or error) +*/ +if (host->data_timeout && (status & (~CC_EN ))) { +del_timer (&host->timer); + host->data_timeout =0 ; + } +if (host->req_in_progress)omap_hsmmc_do_irq (host, status);
@@ -1279,6 +1306,25 @@ static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)return IRQ_HANDLED ; } +static void omap_hsmmc_soft_timeout (unsigned long data) +{ +struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)data; +bool end_trans = false; + +omap_hsmmc_disable_irq (host); +if (host->data || host->response_busy) { + host->response_busy =0 ; + end_trans = true; + } + +hsmmc_command_incomplete (host, -ETIMEDOUT ,0 ); +if (end_trans && host->mrq) +omap_hsmmc_xfer_done (host, host->data); +else if (host->cmd) +omap_hsmmc_cmd_done (host, host->cmd); + host->data_timeout =0 ; +} +static void set_sd_bus_power (struct omap_hsmmc_host *host) {unsigned long i;
@@ -1473,6 +1519,9 @@ static void set_data_timeout(struct omap_hsmmc_host *host,unsigned long long timeout = timeout_ns;unsigned int cycle_ns;uint32_t reg, clkd, dto =0 ; +struct mmc_ios *ios = &host->mmc->ios; +struct mmc_data *data = host->mrq->data; +struct mmc_command *cmd = host->mrq->cmd; reg =OMAP_HSMMC_READ (host->base,SYSCTL ); clkd = (reg &CLKD_MASK ) >>CLKD_SHIFT ;
@@ -1482,23 +1531,60 @@ static void set_data_timeout(struct omap_hsmmc_host *host, cycle_ns =1000000000 / (host->clk_rate / clkd);do_div (timeout, cycle_ns); timeout += timeout_clks; -if (timeout) { -while ((timeout &0x80000000 ) ==0 ) { - dto +=1 ; - timeout <<=1 ; - } - dto =31 - dto; + +if (!timeout) + goto out; + +while ((timeout &0x80000000 ) ==0 ) { + dto +=1 ; timeout <<=1 ; -if (timeout && dto) - dto +=1 ; -if (dto >=13 ) - dto -=13 ; -else - dto =0 ; -if (dto >14 ) - dto =14 ; + } + dto =31 - dto; + timeout <<=1 ; +if (timeout && dto) + dto +=1 ; +if (dto >=13 ) + dto -=13 ; +else + dto =0 ; +if (dto >14 ) { +/* +* DRA7 Errata No i834: When using high speed HS200 and +* SDR104 cards, the functional clock for MMC module +* will be 192MHz. At this frequency, the maximum +* obtainable timeout (DTO =0xE) in hardware is +* (1/192MHz)*2^27 = 700ms. Commands taking longer than +* 700ms will be affected by this small window frame +* and will be timing out frequently even without a +* genuine timeout from the card. Workaround for +* this errata is use a software timer instead of +* hardware timer to provide the timeout requested +* by the upper layer. +* +* The timeout from the upper layer denotes the delay +* between the end bit of the read command and the +* start bit of the data block and in the case of +* multiple-read operation, they also define the +* typical delay between the end bit of a data +* block and the start bit of next data block. +* +* Calculate the total timeout value for the entire +* transfer to complete from the timeout value given +* by the upper layer. +*/ +if (data) + host->data_timeout = (data->blocks * + (timeout_ns + +MMC_BLOCK_TRANSFER_TIME_NS ( + data->blksz, ios->bus_width, + ios->clock))); +else if (cmd->flags &MMC_RSP_BUSY ) + host->data_timeout = timeout_ns; + + dto =14 ; } +out: reg &= ~DTO_MASK ; reg |= dto <<DTO_SHIFT ;OMAP_HSMMC_WRITE (host->base,SYSCTL , reg);
@@ -2359,6 +2445,8 @@ static int omap_hsmmc_probe(struct platform_device *pdev) mmc->ops = &omap_hsmmc_ops;spin_lock_init (&host->irq_lock); +setup_timer (&host->timer, omap_hsmmc_soft_timeout, + (unsigned long )host); host->fclk =devm_clk_get (&pdev->dev,"fck" );if (IS_ERR (host->fclk)) {
@@ -2522,6 +2610,8 @@ static int omap_hsmmc_remove(struct platform_device *pdev)dma_release_channel (host->tx_chan);dma_release_channel (host->rx_chan); +del_timer_sync (&host->timer); +pm_runtime_dont_use_autosuspend (host->dev);pm_runtime_put_sync (host->dev);pm_runtime_disable (host->dev);
@@ -2555,6 +2645,8 @@ static int omap_hsmmc_suspend(struct device *dev)if (host->dbclk)clk_disable_unprepare (host->dbclk); +del_timer_sync (&host->timer); +pm_runtime_put_sync (host->dev);return 0 ; }
Signature · 1 line
2.11.0
PATCH 10/41 mmc: host: omap_hsmmc: Prepare *set_timing() to be used for iodelay setting
In reply to Kishon Vijay Abraham INo functional change. Add separate case statements for certain timing like MMC_TIMING_SD_HS and MMC_TIMING_MMC_HS even though AC12_UHSMC_RES has to be written to the AC12 register (same as for default modes). Also have separate case sections for MMC_TIMING_UHS_SDR104 and MMC_TIMING_UHS_HS200 even though the same UHSMC value has to be written to the AC12 register. This is in preparation for setting iodelay values.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
Signed-off-by Sekhar Nori <[email protected]>
--- drivers/mmc/host/omap_hsmmc.c | 9 +++++++++ 1 file changed, 9 insertions(+)
drivers/mmc/host/omap_hsmmc.c +9 -0
@@ -1737,6 +1737,8 @@ static void omap_hsmmc_set_timing(struct omap_hsmmc_host *host) val &= ~AC12_UHSMC_MASK ;switch (ios->timing) {case MMC_TIMING_UHS_SDR104 : + val |=AC12_UHSMC_SDR104 ; +break ;case MMC_TIMING_MMC_HS200 : val |=AC12_UHSMC_SDR104 ;break ;
@@ -1752,6 +1754,13 @@ static void omap_hsmmc_set_timing(struct omap_hsmmc_host *host)case MMC_TIMING_UHS_SDR12 : val |=AC12_UHSMC_SDR12 ;break ; +case MMC_TIMING_SD_HS : +case MMC_TIMING_MMC_HS : + val |=AC12_UHSMC_RES ; +break ; +case MMC_TIMING_MMC_DDR52 : + val |=AC12_UHSMC_RES ; +break ;default : val |=AC12_UHSMC_RES ;break ;
Signature · 1 line
2.11.0
PATCH 11/41 mmc: host: omap_hsmmc: Add new compatible string to support dra7
In reply to Kishon Vijay Abraham IAdd a new compatible string "ti,dra7-hsmmc" to support dra7 and dra72 controllers. Also create a new controller flag "OMAP_HSMMC_REQUIRE_IODELAY" to specify all controllers that use "ti,dra7-hsmmc" require iodealy configuration to be set.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
Signed-off-by Sekhar Nori <[email protected]>
--- Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt | 1 + drivers/mmc/host/omap_hsmmc.c | 10 ++++++++++ include/linux/platform_data/hsmmc-omap.h | 1 + 3 files changed, 12 insertions(+)
Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt +1 -0
@@ -12,6 +12,7 @@ Required properties: Should be "ti,omap3-hsmmc", for OMAP3 controllers Should be "ti,omap3-pre-es3-hsmmc" for OMAP3 controllers pre ES3.0 Should be "ti,omap4-hsmmc", for OMAP4 controllers + Should be "ti,dra7-hsmmc", for dra7 and dra72 controllers Should be "ti,am33xx-hsmmc", for AM335x controllers - ti,hwmods: Must be "mmc<n>", n is controller instance starting 1
drivers/mmc/host/omap_hsmmc.c +10 -0
@@ -2314,6 +2314,12 @@ static const struct omap_mmc_of_data am33xx_mmc_of_data = { .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING, }; +static const struct omap_mmc_of_data dra7_mmc_of_data = { + .reg_offset =0x100 , + .controller_flags =OMAP_HSMMC_SWAKEUP_MISSING | +OMAP_HSMMC_REQUIRE_IODELAY , +}; +static const struct of_device_id omap_mmc_of_match[] = { { .compatible ="ti,omap2-hsmmc" ,
@@ -2333,6 +2339,10 @@ static const struct of_device_id omap_mmc_of_match[] = { .compatible = "ti,am33xx-hsmmc", .data = &am33xx_mmc_of_data, }, + { + .compatible = "ti,dra7-hsmmc", + .data = &dra7_mmc_of_data, + }, {}, };MODULE_DEVICE_TABLE (of, omap_mmc_of_match);
include/linux/platform_data/hsmmc-omap.h +1 -0
@@ -27,6 +27,7 @@#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0)#define OMAP_HSMMC_BROKEN_MULTIBLOCK_READ BIT(1)#define OMAP_HSMMC_SWAKEUP_MISSING BIT(2) +#define OMAP_HSMMC_REQUIRE_IODELAY BIT(3)struct omap_hsmmc_dev_attr {u8 flags;
Signature · 1 line
2.11.0
Re: [PATCH 11/41] mmc: host: omap_hsmmc: Add new compatible string to support dra7
Quoted 5 lines · Kishon Vijay Abraham I
Add a new compatible string "ti,dra7-hsmmc" to support dra7 and dra72 controllers. Also create a new controller flag "
OMAP_HSMMC_REQUIRE_IODELAY" to specify all controllers that use "ti,dra7-hsmmc" require iodealy configuration to be set.
Quoted 7 lines
Signed-off-by Kishon Vijay Abraham I <[email protected]>Signed-off-by Sekhar Nori <[email protected]>--- Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt | 1 + drivers/mmc/host/omap_hsmmc.c | 10 ++++++++++ include/linux/platform_data/hsmmc-omap.h | 1 + 3 files changed, 12 insertions(+)
Acked-by Rob Herring <[email protected]>
PATCH 12/41 mmc: host: omap_hsmmc: Fix error path sequence
In reply to Kishon Vijay Abraham IFix the error path sequence so that clk_disable, runtime_disable etc are done in the reverse order of how they were enabled.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
Signed-off-by Sekhar Nori <[email protected]>
--- drivers/mmc/host/omap_hsmmc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/mmc/host/omap_hsmmc.c +3 -3
@@ -2602,16 +2602,16 @@ static int omap_hsmmc_probe(struct platform_device *pdev) err_slot_name:mmc_remove_host (mmc); err_irq: -device_init_wakeup (&pdev->dev, false);if (!IS_ERR_OR_NULL (host->tx_chan))dma_release_channel (host->tx_chan);if (!IS_ERR_OR_NULL (host->rx_chan))dma_release_channel (host->rx_chan); +if (host->dbclk) +clk_disable_unprepare (host->dbclk);pm_runtime_dont_use_autosuspend (host->dev);pm_runtime_put_sync (host->dev);pm_runtime_disable (host->dev); -if (host->dbclk) -clk_disable_unprepare (host->dbclk); +device_init_wakeup (&pdev->dev, false); err1: err_gpio:mmc_free_host (mmc);
Signature · 1 line
2.11.0
PATCH 13/41 mmc: host: omap_hsmmc: Add support to set IODELAY values
In reply to Kishon Vijay Abraham IThe data manual of J6/J6 Eco recommends to set different IODELAY values depending on the mode in which the MMC/SD is enumerated in order to ensure IO timings are met.
Add support to set the IODELAY values depending on the various MMC modes using the pinctrl APIs.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
[nsekhar at ti.com: introduce OMAP_HSMMC_SETUP_PINCTRL()]
Signed-off-by Sekhar Nori <[email protected]>
--- .../devicetree/bindings/mmc/ti-omap-hsmmc.txt | 5 + drivers/mmc/host/omap_hsmmc.c | 124 ++++++++++++++++++++- include/linux/platform_data/hsmmc-omap.h | 3 + 3 files changed, 129 insertions(+), 3 deletions(-)
Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt +5 -0
@@ -20,6 +20,11 @@ Optional properties: ti,dual-volt: boolean, supports dual voltage cards <supply-name>-supply: phandle to the regulator device tree node "supply-name" examples are "vmmc", "vmmc_aux" etc +pinctrl-names: Should be a list of pinctrl state names and can be "sdr104", +"hs200_1_8v", "ddr50", "sdr50", "sdr25", "sdr12", "hs", "ddr_1_8v" or +"default". +pinctrl-<num>: Phandle referencing pin configuration of the sd/emmc controller. +See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt ti,non-removable: non-removable slot (like eMMC) ti,needs-special-reset: Requires a special softreset sequence ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed
drivers/mmc/host/omap_hsmmc.c +121 -3
207 lines not on this page · raw message
include/linux/platform_data/hsmmc-omap.h +3 -0
@@ -71,6 +71,9 @@ struct omap_hsmmc_platform_data {#define HSMMC_HAS_HSPE_SUPPORT (1 << 2)unsigned features; +/* string specifying a particular variant of hardware */ +char *version; +int gpio_cd;/* gpio (card detect) */ int gpio_cod;/* gpio (cover detect) */ int gpio_wp;/* gpio (write protect) */
Signature · 1 line
2.11.0
Rob Herring
maintainerRe: [PATCH 13/41] mmc: host: omap_hsmmc: Add support to set IODELAY values
Quoted 22 lines · Kishon Vijay Abraham I
The data manual of J6/J6 Eco recommends to set different IODELAY values depending on the mode in which the MMC/SD is enumerated in order to ensure IO timings are met.
Add support to set the IODELAY values depending on the various MMC modes using the pinctrl APIs.
Signed-off-by Kishon Vijay Abraham I <[email protected]>[nsekhar at ti.com: introduce OMAP_HSMMC_SETUP_PINCTRL()]Signed-off-by Sekhar Nori <[email protected]>--- .../devicetree/bindings/mmc/ti-omap-hsmmc.txt | 5 + drivers/mmc/host/omap_hsmmc.c | 124 ++++++++++++++++++++- include/linux/platform_data/hsmmc-omap.h | 3 + 3 files changed, 129 insertions(+), 3 deletions(-)Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt +0
-0@@ -20,6 +20,11 @@ Optional properties: ti,dual-volt: boolean, supports dual voltage cards
Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt Optional properties: · line 30
Quoted 10 lines
Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt +5
-0<supply-name>-supply: phandle to the regulator device tree node "supply-name" examples are "vmmc", "vmmc_aux" etc +pinctrl-names: Should be a list of pinctrl state names and can be "sdr104", +"hs200_1_8v", "ddr50", "sdr50", "sdr25", "sdr12", "hs", "ddr_1_8v" or +"default". +pinctrl-<num>: Phandle referencing pin configuration of the sd/emmc controller. +See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt ti,non-removable: non-removable slot (like eMMC) ti,needs-special-reset: Requires a special softreset sequence ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed
Binding looks fine, but...
Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt static inline struct omap_hsmmc_platform_data · line 2431
Quoted 6 lines
Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt +2
-0@@ -2388,6 +2427,73 @@ static inline struct omap_hsmmc_platform_data } #endif +#define OMAP_HSMMC_SETUP_PINCTRL(capvar, capmask, mode) \ + do { \
This is kind of ugly. Why not make it a function. Just return pinctrl_state ptr.
Quoted 68 lines
Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt +65
-0+ struct pinctrl_state *s = ERR_PTR(-ENODEV); \ + char str[20]; \ + char *version = host->pdata->version; \ + \ + if (!(mmc->capvar & (capmask))) \ + break; \ + \ + if (host->pdata->version) { \ + sprintf(str, "%s-%s", #mode, version); \ + s = pinctrl_lookup_state(host->pinctrl, str); \ + } \ + \ + if (IS_ERR(s)) { \ + sprintf(str, "%s", #mode); \ + s = pinctrl_lookup_state(host->pinctrl, str); \ + } \ + \ + if (IS_ERR(s)) { \ + dev_err(host->dev, "no pinctrl state for %s " \ + "mode\n", #mode); \ + mmc->capvar &= ~(capmask); \ + } else { \ + host->mode##_pinctrl_state = s; \ + } \ + \ + } while (0) + +static int omap_hsmmc_get_iodelay_pinctrl_state(struct omap_hsmmc_host *host) +{ + struct mmc_host *mmc = host->mmc; + + if (!(host->pdata->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) + return 0; + + host->pinctrl = devm_pinctrl_get(host->dev); + if (IS_ERR(host->pinctrl)) { + dev_err(host->dev, "Cannot get pinctrl\n"); + return PTR_ERR(host->pinctrl); + } + + host->default_pinctrl_state = pinctrl_lookup_state(host->pinctrl, + "default"); + if (IS_ERR(host->default_pinctrl_state)) { + dev_err(host->dev, + "no pinctrl state for default mode\n"); + return PTR_ERR(host->default_pinctrl_state); + } + + OMAP_HSMMC_SETUP_PINCTRL(caps, MMC_CAP_UHS_SDR104, sdr104); + OMAP_HSMMC_SETUP_PINCTRL(caps, MMC_CAP_UHS_DDR50, ddr50); + OMAP_HSMMC_SETUP_PINCTRL(caps, MMC_CAP_UHS_SDR50, sdr50); + OMAP_HSMMC_SETUP_PINCTRL(caps, MMC_CAP_UHS_SDR25, sdr25); + OMAP_HSMMC_SETUP_PINCTRL(caps, MMC_CAP_UHS_SDR12, sdr12); + OMAP_HSMMC_SETUP_PINCTRL(caps, MMC_CAP_1_8V_DDR, ddr_1_8v); + OMAP_HSMMC_SETUP_PINCTRL(caps, + MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, + hs); + OMAP_HSMMC_SETUP_PINCTRL(caps2, MMC_CAP2_HS200_1_8V_SDR, + hs200_1_8v); + + host->pinctrl_state = host->default_pinctrl_state; + + return 0; +} + static int omap_hsmmc_probe(struct platform_device *pdev) { struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
PATCH 14/41 mmc: host: omap_hsmmc: Remove *use_dma* member
In reply to Kishon Vijay Abraham Iomap_hsmmc doesn't support polled I/O. So remove *use_dma* which is always set to '1'.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
Signed-off-by Sekhar Nori <[email protected]>
--- drivers/mmc/host/omap_hsmmc.c | 37 ++++++++++++++++--------------------- 1 file changed, 16 insertions(+), 21 deletions(-)
drivers/mmc/host/omap_hsmmc.c +16 -21
@@ -238,7 +238,7 @@ struct omap_hsmmc_host {u32 capa;int irq;int wake_irq; -int use_dma, dma_ch; +int dma_ch;struct dma_chan *tx_chan;struct dma_chan *rx_chan;int response_busy;
@@ -658,8 +658,8 @@ static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,*/ irq_mask &= ~(DCRC_EN |DEB_EN ); -if (host->use_dma) - irq_mask &= ~(BRR_EN |BWR_EN ); +/* BRR and BWR need not be enabled for DMA */ + irq_mask &= ~(BRR_EN |BWR_EN );/* Disable timeout for erases or when using software timeout */ if (cmd && (cmd->opcode ==MMC_ERASE || host->data_timeout))
@@ -1012,8 +1012,7 @@ omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, (cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)) cmdreg |=DP_SELECT |DDIR ; -if (host->use_dma) - cmdreg |=DMAE ; + cmdreg |=DMAE ; host->req_in_progress =1 ; host->last_cmd = cmd->opcode;
@@ -1040,7 +1039,7 @@ static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_reqomap_hsmmc_disable_irq (host);/* Do not complete the request if DMA is still in progress */ -if (mrq->data && host->use_dma && dma_ch !=-1 ) +if (mrq->data && dma_ch !=-1 )return ; host->mrq =NULL ;mmc_request_done (host->mmc, mrq);
@@ -1127,7 +1126,7 @@ static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) host->dma_ch =-1 ;spin_unlock_irqrestore (&host->irq_lock, flags); -if (host->use_dma && dma_ch !=-1 ) { +if (dma_ch !=-1 ) {struct dma_chan *chan =omap_hsmmc_get_dma_chan (host, host->data);dmaengine_terminate_all (chan);
@@ -1645,12 +1644,10 @@ omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)return 0 ; } -if (host->use_dma) { - ret =omap_hsmmc_setup_dma_transfer (host, req); -if (ret !=0 ) { -dev_err (mmc_dev (host->mmc),"MMC start dma failure\n" ); -return ret; - } + ret =omap_hsmmc_setup_dma_transfer (host, req); +if (ret !=0 ) { +dev_err (mmc_dev (host->mmc),"MMC start dma failure\n" ); +return ret; }return 0 ; }
@@ -1661,7 +1658,7 @@ static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,struct omap_hsmmc_host *host =mmc_priv (mmc);struct mmc_data *data = mrq->data; -if (host->use_dma && data->host_cookie) { +if (data->host_cookie) {struct dma_chan *c =omap_hsmmc_get_dma_chan (host, data); dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
@@ -1673,19 +1670,18 @@ static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,static void omap_hsmmc_pre_req (struct mmc_host *mmc,struct mmc_request *mrq) {struct omap_hsmmc_host *host =mmc_priv (mmc); +struct dma_chan *c =NULL ;if (mrq->data->host_cookie) { mrq->data->host_cookie =0 ;return ; } -if (host->use_dma) { -struct dma_chan *c =omap_hsmmc_get_dma_chan (host, mrq->data); + c =omap_hsmmc_get_dma_chan (host, mrq->data); -if (omap_hsmmc_pre_dma_transfer (host, mrq->data, - &host->next_data, c)) - mrq->data->host_cookie =0 ; - } +if (omap_hsmmc_pre_dma_transfer (host, mrq->data, + &host->next_data, c)) + mrq->data->host_cookie =0 ; }/*
@@ -2547,7 +2543,6 @@ static int omap_hsmmc_probe(struct platform_device *pdev) host->mmc = mmc; host->pdata = pdata; host->dev = &pdev->dev; - host->use_dma =1 ; host->dma_ch =-1 ; host->irq = irq; host->mapbase = res->start + pdata->reg_offset;
Signature · 1 line
2.11.0
PATCH 15/41 mmc: host: omap_hsmmc: Enable ADMA2
In reply to Kishon Vijay Abraham Iomap hsmmc host controller has ADMA2 feature. Enable it here for better read and write throughput.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
[misael.lopez at ti.com: handle ADMA errors]
Signed-off-by Misael Lopez Cruz <[email protected]>
[nsekhar at ti.com: restore adma settings after context loss]
Signed-off-by Sekhar Nori <[email protected]>
--- drivers/mmc/host/omap_hsmmc.c | 307 +++++++++++++++++++++++++++---- include/linux/platform_data/hsmmc-omap.h | 1 + 2 files changed, 271 insertions(+), 37 deletions(-)
drivers/mmc/host/omap_hsmmc.c +270 -37
@@ -48,6 +48,9 @@#include <linux/mmc/sd.h> /* OMAP HSMMC Host Controller Registers */ +#define OMAP_HSMMC_HL_REV 0x0000 +#define OMAP_HSMMC_HL_HWINFO 0x0004 +#define OMAP_HSMMC_HL_SYSCONFIG 0x0010#define OMAP_HSMMC_SYSSTATUS 0x0014#define OMAP_HSMMC_CON 0x002C#define OMAP_HSMMC_DLL 0x0034
@@ -69,7 +72,10 @@#define OMAP_HSMMC_AC12 0x013C#define OMAP_HSMMC_CAPA 0x0140#define OMAP_HSMMC_CAPA2 0x0144 +#define OMAP_HSMMC_ADMAES 0x0154 +#define OMAP_HSMMC_ADMASAL 0x0158 +#define MADMA_EN (1 << 0)#define VS18 (1 << 26)#define VS30 (1 << 25)#define HSS (1 << 21)
@@ -79,6 +85,7 @@#define SDVS_MASK 0x00000E00#define SDVSCLR 0xFFFFF1FF#define SDVSDET 0x00000400 +#define DMA_SELECT (2 << 3)#define AUTOIDLE 0x1#define SDBP (1 << 8)#define DTO 0xe
@@ -100,6 +107,7 @@#define FOUR_BIT (1 << 1)#define HSPE (1 << 2)#define IWE (1 << 24) +#define DMA_MASTER (1 << 20)#define DDR (1 << 19)#define CLKEXTFREE (1 << 16)#define CTPL (1 << 11)
@@ -153,10 +161,11 @@#define DCRC_EN (1 << 21)#define DEB_EN (1 << 22)#define ACE_EN (1 << 24) +#define ADMAE_EN (1 << 25)#define CERR_EN (1 << 28)#define BADA_EN (1 << 29) -#define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\ +#define INT_EN_MASK (BADA_EN | CERR_EN | ADMAE_EN | ACE_EN | DEB_EN | DCRC_EN |\ DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ BRR_EN | BWR_EN | TC_EN | CC_EN)
@@ -206,6 +215,33 @@#define OMAP_HSMMC_WRITE (base, reg, val) \ __raw_writel((val), (base) + OMAP_HSMMC_##reg) +struct omap_hsmmc_adma_desc { +u8 attr; +u8 reserved; +u16 len; +u32 addr; +} __packed; + +#define ADMA_DESC_SIZE 8 + +#define ADMA_MAX_LEN 65532 + +/* Decriptor table defines */ +#define ADMA_DESC_ATTR_VALID BIT(0) +#define ADMA_DESC_ATTR_END BIT(1) +#define ADMA_DESC_ATTR_INT BIT(2) +#define ADMA_DESC_ATTR_ACT1 BIT(4) +#define ADMA_DESC_ATTR_ACT2 BIT(5) + +#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2 +#define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2) + +/* ADMA error status */ +#define AES_MASK 0x3 +#define ST_STOP 0x0 +#define ST_FDS 0x1 +#define ST_TFR 0x3 +struct omap_hsmmc_next {unsigned int dma_len;s32 cookie;
@@ -239,6 +275,7 @@ struct omap_hsmmc_host {int irq;int wake_irq;int dma_ch; +int use_adma;struct dma_chan *tx_chan;struct dma_chan *rx_chan;int response_busy;
@@ -270,6 +307,9 @@ struct omap_hsmmc_host {struct pinctrl_state *hs_pinctrl_state;struct pinctrl_state *ddr_1_8v_pinctrl_state; +struct omap_hsmmc_adma_desc *adma_desc_table; +dma_addr_t adma_desc_table_addr; +/* return MMC cover switch state, can be NULL if not supported. * * possible return values:
@@ -851,6 +891,18 @@ static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)OMAP_HSMMC_WRITE (host->base,IE ,0 );OMAP_HSMMC_WRITE (host->base,STAT ,STAT_CLEAR ); +if (host->use_adma) { +u32 val; + + val =OMAP_HSMMC_READ (host->base,CON ); + val |=DMA_MASTER ; +OMAP_HSMMC_WRITE (host->base,CON , val); + + val =OMAP_HSMMC_READ (host->base,HCTL ); + val |=DMA_SELECT ; +OMAP_HSMMC_WRITE (host->base,HCTL , val); + } +/* Do not initialize card-specific things if the power is off */ if (host->power_mode ==MMC_POWER_OFF ) goto out;
@@ -1065,6 +1117,10 @@ omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)return ; } +if (host->use_adma && host->data && !data->host_cookie) +dma_unmap_sg (host->dev, data->sg, data->sg_len, +mmc_get_dma_dir (data)); + host->data =NULL ;if (!data->error)
@@ -1126,13 +1182,17 @@ static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) host->dma_ch =-1 ;spin_unlock_irqrestore (&host->irq_lock, flags); -if (dma_ch !=-1 ) { -struct dma_chan *chan =omap_hsmmc_get_dma_chan (host, host->data); - +if (host->use_adma) { +dma_unmap_sg (host->dev, host->data->sg, host->data->sg_len, +mmc_get_dma_dir (host->data)); + host->data->host_cookie =0 ; + }else if (dma_ch !=-1 ) { +struct dma_chan *chan =omap_hsmmc_get_dma_chan (host, + host->data);dmaengine_terminate_all (chan);dma_unmap_sg (chan->device->dev, - host->data->sg, host->data->sg_len, -mmc_get_dma_dir (host->data)); + host->data->sg, host->data->sg_len, +mmc_get_dma_dir (host->data)); host->data->host_cookie =0 ; }
@@ -1227,6 +1287,35 @@ static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, host->mrq->cmd->error = err; } +static void omap_hsmmc_adma_err (struct omap_hsmmc_host *host) +{ +u32 admaes, admasal; + + admaes =OMAP_HSMMC_READ (host->base,ADMAES ); + admasal =OMAP_HSMMC_READ (host->base,ADMASAL ); + +switch (admaes &AES_MASK ) { +case ST_STOP : +dev_err (mmc_dev (host->mmc), +"ADMA err: ST_STOP, desc at 0x%08x follows the erroneous one\n" , + admasal); +break ; +case ST_FDS : +dev_err (mmc_dev (host->mmc), +"ADMA err: ST_FDS, erroneous desc at 0x%08x\n" , + admasal); +break ; +case ST_TFR : +dev_err (mmc_dev (host->mmc), +"ADMA err: ST_TFR, desc at 0x%08x follows the erroneous one\n" , + admasal); +break ; +default : +dev_warn (mmc_dev (host->mmc),"Unexpected ADMA error state\n" ); +break ; + } +} +static void omap_hsmmc_do_irq (struct omap_hsmmc_host *host,int status) {struct mmc_data *data;
@@ -1245,6 +1334,13 @@ static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) end_trans = !end_cmd; host->response_busy =0 ; } + +if (status &ADMAE_EN ) { +omap_hsmmc_adma_err (host); + end_trans =1 ; + data->error = -EIO ; + } +if (status & (CTO_EN |DTO_EN ))hsmmc_command_incomplete (host, -ETIMEDOUT , end_cmd); else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN |
@@ -1426,6 +1522,7 @@ static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, struct dma_chan *chan) {int dma_len; +struct device *dev;if (!next && data->host_cookie && data->host_cookie != host->next_data.cookie) {
@@ -1435,11 +1532,15 @@ static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, data->host_cookie =0 ; } +if (chan) + dev = chan->device->dev; +else + dev =mmc_dev (host->mmc); +/* Check if next job is already prepared */ if (next || data->host_cookie != host->next_data.cookie) { - dma_len =dma_map_sg (chan->device->dev, data->sg, data->sg_len, + dma_len =dma_map_sg (dev, data->sg, data->sg_len,mmc_get_dma_dir (data)); - }else { dma_len = host->next_data.dma_len; host->next_data.dma_len =0 ;
@@ -1612,8 +1713,58 @@ static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host) | (req->data->blocks << 16));set_data_timeout (host, req->data->timeout_ns, req->data->timeout_clks); - chan =omap_hsmmc_get_dma_chan (host, req->data); -dma_async_issue_pending (chan); + +if (host->use_adma) { +OMAP_HSMMC_WRITE (host->base,ADMASAL , + (u32 )host->adma_desc_table_addr); + }else { + chan =omap_hsmmc_get_dma_chan (host, req->data); +dma_async_issue_pending (chan); + } +} + +static int omap_hsmmc_write_adma_desc (struct omap_hsmmc_host *host,void *desc, +dma_addr_t addr,u16 len,u8 attr) +{ +struct omap_hsmmc_adma_desc *dma_desc = desc; + + dma_desc->len = len; + dma_desc->addr = (u32 )addr; + dma_desc->reserved =0 ; + dma_desc->attr = attr; + +return 0 ; +} + +static int omap_hsmmc_setup_adma_transfer (struct omap_hsmmc_host *host, +struct mmc_request *req) +{ +struct mmc_data *data = req->data; +struct scatterlist *sg; +int i; +int len; +int ret; +dma_addr_t addr; +struct omap_hsmmc_adma_desc *dma_desc; + + ret =omap_hsmmc_pre_dma_transfer (host, data,NULL ,NULL ); +if (ret) +return ret; + + dma_desc = host->adma_desc_table; +for_each_sg (data->sg, sg, host->dma_len, i) { + addr =sg_dma_address (sg); + len =sg_dma_len (sg); +WARN_ON (len >ADMA_MAX_LEN ); +omap_hsmmc_write_adma_desc (host, dma_desc, addr, len, +ADMA_DESC_ATTR_VALID | +ADMA_DESC_TRANSFER_DATA ); + dma_desc++; + } +omap_hsmmc_write_adma_desc (host, dma_desc,0 ,0 ,ADMA_DESC_ATTR_END | +ADMA_DESC_ATTR_VALID ); + +return 0 ; }/*
@@ -1644,10 +1795,18 @@ omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)return 0 ; } - ret =omap_hsmmc_setup_dma_transfer (host, req); -if (ret !=0 ) { -dev_err (mmc_dev (host->mmc),"MMC start dma failure\n" ); -return ret; +if (host->use_adma) { + ret =omap_hsmmc_setup_adma_transfer (host, req); +if (ret !=0 ) { +dev_err (mmc_dev (host->mmc),"MMC adma setup failed\n" ); +return ret; + } + }else { + ret =omap_hsmmc_setup_dma_transfer (host, req); +if (ret !=0 ) { +dev_err (mmc_dev (host->mmc),"MMC start dma failure\n" ); +return ret; + } }return 0 ; }
@@ -1657,11 +1816,18 @@ static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, {struct omap_hsmmc_host *host =mmc_priv (mmc);struct mmc_data *data = mrq->data; +struct device *dev; +struct dma_chan *c;if (data->host_cookie) { -struct dma_chan *c =omap_hsmmc_get_dma_chan (host, data); +if (host->use_adma) { + dev =mmc_dev (mmc); + }else { + c =omap_hsmmc_get_dma_chan (host, mrq->data); + dev = c->device->dev; + } -dma_unmap_sg (c->device->dev, data->sg, data->sg_len, +dma_unmap_sg (dev, data->sg, data->sg_len,mmc_get_dma_dir (data)); data->host_cookie =0 ; }
@@ -1677,7 +1843,8 @@ static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)return ; } - c =omap_hsmmc_get_dma_chan (host, mrq->data); +if (!host->use_adma) + c =omap_hsmmc_get_dma_chan (host, mrq->data);if (omap_hsmmc_pre_dma_transfer (host, mrq->data, &host->next_data, c))
@@ -2337,6 +2504,7 @@ static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {static const struct omap_mmc_of_data omap4_mmc_of_data = { .reg_offset =0x100 , + .controller_flags =OMAP_HSMMC_HAS_HWPARAM , };static const struct omap_mmc_of_data am33xx_mmc_of_data = { .reg_offset =0x100 ,
@@ -2346,7 +2514,8 @@ static const struct omap_mmc_of_data am33xx_mmc_of_data = {static const struct omap_mmc_of_data dra7_mmc_of_data = { .reg_offset =0x100 , .controller_flags =OMAP_HSMMC_SWAKEUP_MISSING | -OMAP_HSMMC_REQUIRE_IODELAY , +OMAP_HSMMC_REQUIRE_IODELAY | +OMAP_HSMMC_HAS_HWPARAM , };static const struct of_device_id omap_mmc_of_match[] = {
@@ -2490,6 +2659,64 @@ static int omap_hsmmc_get_iodelay_pinctrl_state(struct omap_hsmmc_host *host)return 0 ; } +static int omap_hsmmc_adma_init (struct omap_hsmmc_host *host) +{ +struct mmc_host *mmc = host->mmc; +u32 val; + + host->adma_desc_table =dma_alloc_coherent (host->dev,ADMA_DESC_SIZE * + (mmc->max_segs +1 ), + &host->adma_desc_table_addr, +GFP_KERNEL ); +if (!host->adma_desc_table) { +dev_err (host->dev,"failed to allocate adma desc table\n" ); +return -ENOMEM ; + } + + val =OMAP_HSMMC_READ (host->base,HCTL ); + val |=DMA_SELECT ; +OMAP_HSMMC_WRITE (host->base,HCTL , val); + + val =OMAP_HSMMC_READ (host->base,CON ); + val |=DMA_MASTER ; +OMAP_HSMMC_WRITE (host->base,CON , val); + +return 0 ; +} + +static void omap_hsmmc_adma_exit (struct omap_hsmmc_host *host) +{ +struct mmc_host *mmc = host->mmc; + +dma_free_coherent (host->dev,ADMA_DESC_SIZE * (mmc->max_segs +1 ), + host->adma_desc_table, host->adma_desc_table_addr); +} + +static int omap_hsmmc_dma_init (struct omap_hsmmc_host *host) +{ + host->rx_chan =dma_request_chan (host->dev,"rx" ); +if (IS_ERR (host->rx_chan)) { +dev_err (mmc_dev (host->mmc),"RX DMA channel request failed\n" ); +return PTR_ERR (host->rx_chan); + } + + host->tx_chan =dma_request_chan (host->dev,"tx" ); +if (IS_ERR (host->tx_chan)) { +dev_err (mmc_dev (host->mmc),"TX DMA channel request failed\n" ); +return PTR_ERR (host->tx_chan); + } + +return 0 ; +} + +static void omap_hsmmc_dma_exit (struct omap_hsmmc_host *host) +{ +if (!IS_ERR_OR_NULL (host->tx_chan)) +dma_release_channel (host->tx_chan); +if (!IS_ERR_OR_NULL (host->rx_chan)) +dma_release_channel (host->rx_chan); +} +static int omap_hsmmc_probe (struct platform_device *pdev) {struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
@@ -2497,6 +2724,7 @@ static int omap_hsmmc_probe(struct platform_device *pdev)struct omap_hsmmc_host *host =NULL ;struct resource *res;int ret, irq; +u32 val;const struct of_device_id *match;const struct omap_mmc_of_data *data;void __iomem *base;
@@ -2552,6 +2780,7 @@ static int omap_hsmmc_probe(struct platform_device *pdev) host->next_data.cookie =1 ; host->pbias_enabled =0 ; host->vqmmc_enabled =0 ; + host->use_adma = false; ret =omap_hsmmc_gpio_init (mmc, host, pdata);if (ret)
@@ -2613,6 +2842,12 @@ static int omap_hsmmc_probe(struct platform_device *pdev) host->dbclk =NULL ; } +if (host->pdata->controller_flags &OMAP_HSMMC_HAS_HWPARAM ) { + val =OMAP_HSMMC_READ (base,HL_HWINFO ); +if (val &MADMA_EN ) + host->use_adma = true; + } +/* Since we do only SG emulation, we can have as many segs * as we want. */ mmc->max_segs =1024 ;
@@ -2620,7 +2855,10 @@ static int omap_hsmmc_probe(struct platform_device *pdev) mmc->max_blk_size =512 ;/* Block Length at max can be 1024 */ mmc->max_blk_count =0xFFFF ;/* No. of Blocks is 16 bits */ mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; - mmc->max_seg_size = mmc->max_req_size; +if (host->use_adma) + mmc->max_seg_size =ADMA_MAX_LEN ; +else + mmc->max_seg_size = mmc->max_req_size; mmc->caps |=MMC_CAP_MMC_HIGHSPEED |MMC_CAP_SD_HIGHSPEED |MMC_CAP_WAIT_WHILE_BUSY |MMC_CAP_ERASE ;
@@ -2640,19 +2878,12 @@ static int omap_hsmmc_probe(struct platform_device *pdev)if (ret) goto err_pinctrl; - host->rx_chan =dma_request_chan (&pdev->dev,"rx" ); -if (IS_ERR (host->rx_chan)) { -dev_err (mmc_dev (host->mmc),"RX DMA channel request failed\n" ); - ret =PTR_ERR (host->rx_chan); - goto err_irq; - } - - host->tx_chan =dma_request_chan (&pdev->dev,"tx" ); -if (IS_ERR (host->tx_chan)) { -dev_err (mmc_dev (host->mmc),"TX DMA channel request failed\n" ); - ret =PTR_ERR (host->tx_chan); +if (host->use_adma) + ret =omap_hsmmc_adma_init (host); +else + ret =omap_hsmmc_dma_init (host); +if (ret) goto err_irq; - }/* Request IRQ for MMC operations */ ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
@@ -2707,10 +2938,10 @@ static int omap_hsmmc_probe(struct platform_device *pdev) err_slot_name:mmc_remove_host (mmc); err_irq: -if (!IS_ERR_OR_NULL (host->tx_chan)) -dma_release_channel (host->tx_chan); -if (!IS_ERR_OR_NULL (host->rx_chan)) -dma_release_channel (host->rx_chan); +if (host->use_adma) +omap_hsmmc_adma_exit (host); +else +omap_hsmmc_dma_exit (host); err_pinctrl:if (host->dbclk)clk_disable_unprepare (host->dbclk);
@@ -2732,8 +2963,10 @@ static int omap_hsmmc_remove(struct platform_device *pdev)pm_runtime_get_sync (host->dev);mmc_remove_host (host->mmc); -dma_release_channel (host->tx_chan); -dma_release_channel (host->rx_chan); +if (host->use_adma) +omap_hsmmc_adma_exit (host); +else +omap_hsmmc_dma_exit (host);del_timer_sync (&host->timer);
include/linux/platform_data/hsmmc-omap.h +1 -0
@@ -28,6 +28,7 @@#define OMAP_HSMMC_BROKEN_MULTIBLOCK_READ BIT(1)#define OMAP_HSMMC_SWAKEUP_MISSING BIT(2)#define OMAP_HSMMC_REQUIRE_IODELAY BIT(3) +#define OMAP_HSMMC_HAS_HWPARAM BIT(4)struct omap_hsmmc_dev_attr {u8 flags;
Signature · 1 line
2.11.0
PATCH 16/41 mmc: omap_hsmmc: Support non-1.8V IO controllers
In reply to Kishon Vijay Abraham IFrom: Sekhar Nori <[email protected]>
OMAP HSMMC driver assumes that if the controller does not support dual-volt, then it supports only 1.8V IO.
This assumption can be incorrect. For example, on K2G MMC0 supports 3.3V IO only. AM57x Beagle-x15 and IDK boards support only 3.3V IO on eMMC interface.
Support device-tree property "no-1-8-v" to for controllers which are not dual-voltage and do not support 1.8V IO.
Note that lack of support for this property has not led to any known regression in affected platforms so far. But it will be nice to be in sync with hardware configuration.
Signed-off-by Sekhar Nori <[email protected]>
Signed-off-by Kishon Vijay Abraham I <[email protected]>
--- drivers/mmc/host/omap_hsmmc.c | 15 ++++++++++++--- include/linux/platform_data/hsmmc-omap.h | 5 +++++ 2 files changed, 17 insertions(+), 3 deletions(-)
drivers/mmc/host/omap_hsmmc.c +12 -3
@@ -865,6 +865,9 @@ static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)else hctl =SDVS30 ; capa =VS30 |VS18 ; + }else if (host->pdata->controller_flags &OMAP_HSMMC_NO_1_8_V ) { + hctl =SDVS30 ; + capa =VS30 ; }else { hctl =SDVS18 ; capa =VS18 ;
@@ -2121,11 +2124,14 @@ static void omap_hsmmc_set_capabilities(struct omap_hsmmc_host *host) val =OMAP_HSMMC_READ (host->base,CAPA ); -/* Only MMC1 supports 3.0V */ -if (host->pdata->controller_flags &OMAP_HSMMC_SUPPORTS_DUAL_VOLT ) +if (host->pdata->controller_flags &OMAP_HSMMC_SUPPORTS_DUAL_VOLT ) { val |= (VS30 |VS18 ); -else + }else if (host->pdata->controller_flags &OMAP_HSMMC_NO_1_8_V ) { + val |=VS30 ; + val &= ~VS18 ; + }else { val |=VS18 ; + }OMAP_HSMMC_WRITE (host->base,CAPA , val); }
@@ -2567,6 +2573,9 @@ static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)if (of_find_property (np,"ti,dual-volt" ,NULL )) pdata->controller_flags |=OMAP_HSMMC_SUPPORTS_DUAL_VOLT ; +if (of_find_property (np,"no-1-8-v" ,NULL )) + pdata->controller_flags |=OMAP_HSMMC_NO_1_8_V ; + pdata->gpio_cd = -EINVAL ; pdata->gpio_cod = -EINVAL ; pdata->gpio_wp = -EINVAL ;
include/linux/platform_data/hsmmc-omap.h +5 -0
@@ -23,12 +23,17 @@* for example Advisory 2.1.1.128 "MMC: Multiple Block Read * Operation Issue" in _OMAP3530/3525/3515/3503 Silicon Errata_ * Revision F (October 2010) (SPRZ278F). +* +* OMAP_HSMMC_NO_1_8_V: The controller does not support 1.8V IO voltage +* irrespective of what the capability states. +* */ #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0)#define OMAP_HSMMC_BROKEN_MULTIBLOCK_READ BIT(1)#define OMAP_HSMMC_SWAKEUP_MISSING BIT(2)#define OMAP_HSMMC_REQUIRE_IODELAY BIT(3)#define OMAP_HSMMC_HAS_HWPARAM BIT(4) +#define OMAP_HSMMC_NO_1_8_V BIT(5)struct omap_hsmmc_dev_attr {u8 flags;
Signature · 1 line
2.11.0
PATCH 17/41 ARM: dts: dra72-evm: Add vmmc_aux supply to mmc1
In reply to Kishon Vijay Abraham IAdd vmmc_aux-supply property to mmc1 dt node and populate it with ldo1_reg to reflect ldo1_out is connected to mmc1 IO lines.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
--- arch/arm/boot/dts/dra72-evm.dts | 4 ++++ 1 file changed, 4 insertions(+)
arch/arm/boot/dts/dra72-evm.dts +4 -0
@@ -43,3 +43,7 @@ phy_id = <&davinci_mdio>, <3>; phy-mode = "rgmii"; }; + +&mmc1 { + vmmc_aux-supply = <&ldo1_reg>; +};
Signature · 1 line
2.11.0
PATCH 18/41 ARM: dts: dra72-evm-revc: Add vmmc_aux supply to mmc1
In reply to Kishon Vijay Abraham IAdd vmmc_aux-supply property to mmc1 dt node and populate it with ldo1_reg to reflect ldo1_out is connected to mmc1 IO lines.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
--- arch/arm/boot/dts/dra72-evm-revc.dts | 4 ++++ 1 file changed, 4 insertions(+)
arch/arm/boot/dts/dra72-evm-revc.dts +4 -0
@@ -82,3 +82,7 @@ interrupts = <16 IRQ_TYPE_EDGE_FALLING>; }; }; + +&mmc1 { + vmmc_aux-supply = <&ldo1_reg>; +};
Signature · 1 line
2.11.0
PATCH 19/41 ARM: dts: am57xx-beagle-x15-revb1: Fix supply name used for MMC1 IO lines
In reply to Kishon Vijay Abraham IThe dt binding documentation of omap-hsmmc recommends using "vmmc_aux" for IO supply lines. However
commit 0af28cc92690d8c ("ARM: dts: am57xx-beagle-x15: Add support for rev B1") added it as "vmmc-aux". Fix it here.
Fixes commit 0af28cc92690d8c ("ARM: dts: am57xx-beagle-x15: Add
support for rev B1")
Signed-off-by Kishon Vijay Abraham I <[email protected]>
--- arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts +1 -1
@@ -20,7 +20,7 @@ &mmc1 { vmmc-supply = <&vdd_3v3>; - vmmc-aux-supply = <&ldo1_reg>; + vmmc_aux-supply = <&ldo1_reg>; }; /* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */
Signature · 1 line
2.11.0
PATCH 20/41 ARM: dts: dra7-evm: Correct the vmmc-supply for mmc2
In reply to Kishon Vijay Abraham IFrom: Ravikumar Kattekola <[email protected]>
On DRA75x EVM, MMC2 vdd/ios are connected to a common supply fixed at 1.8V not 3.3V
Fixes 6cf02dbb4b71 ("ARM: dts: dra7-evm: Add mmc2 node for eMMC support")
Signed-off-by Ravikumar Kattekola <[email protected]>
Signed-off-by Sekhar Nori <[email protected]>
Signed-off-by Kishon Vijay Abraham I <[email protected]>
--- arch/arm/boot/dts/dra7-evm.dts | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)
arch/arm/boot/dts/dra7-evm.dts +9 -1
@@ -25,6 +25,14 @@ stdout-path = &uart1; }; + evm_1v8_sw: fixedregulator-evm_1v8 { + compatible = "regulator-fixed"; + regulator-name = "evm_1v8"; + vin-supply = <&smps9_reg>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + evm_3v3_sd: fixedregulator-sd { compatible = "regulator-fixed"; regulator-name = "evm_3v3_sd";
@@ -449,7 +457,7 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins_default>; - vmmc-supply = <&evm_3v3_sw>; + vmmc-supply = <&evm_1v8_sw>; bus-width = <8>; };
Signature · 1 line
2.11.0
PATCH 21/41 ARM: dts: dra72-evm-common: Correct vmmc-supply for mmc2
In reply to Kishon Vijay Abraham IFrom: Ravikumar Kattekola <[email protected]>
On dra72/dra71 evms, mmc2 vdd/ios are connected to a common 1.8V supply not 3.3V. Also the regulator that supplies 1.8V is different on dra71-evm so move the supply property from common dtsi to evm specific dts files.
Fixes a4240d3af677 ("ARM: dts: Add support for dra72-evm rev C (SR2.0)")
Signed-off-by Ravikumar Kattekola <[email protected]>
Signed-off-by Sekhar Nori <[email protected]>
Signed-off-by Kishon Vijay Abraham I <[email protected]>
--- arch/arm/boot/dts/dra71-evm.dts | 14 ++++++++++++++ arch/arm/boot/dts/dra72-evm-common.dtsi | 2 -- arch/arm/boot/dts/dra72-evm-revc.dts | 14 ++++++++++++++ arch/arm/boot/dts/dra72-evm.dts | 14 ++++++++++++++ 4 files changed, 42 insertions(+), 2 deletions(-)
arch/arm/boot/dts/dra71-evm.dts +14 -0
@@ -32,6 +32,16 @@ 3000000 0x1>; }; + evm_1v8_sw: fixedregulator-evm_1v8 { + compatible = "regulator-fixed"; + regulator-name = "evm_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&lp8732_buck0_reg>; + regulator-always-on; + regulator-boot-on; + }; + poweroff: gpio-poweroff { compatible = "gpio-poweroff"; gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>;
@@ -165,6 +175,10 @@ vmmc_aux-supply = <&vpo_sd_1v8_3v3>; }; +&mmc2 { + vmmc-supply = <&evm_1v8_sw>; +}; + &mac { mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>, <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */
arch/arm/boot/dts/dra72-evm-common.dtsi +0 -2
@@ -418,8 +418,6 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins_default>; - - vmmc-supply = <&evm_3v3_sw>; bus-width = <8>; ti,non-removable; max-frequency = <192000000>;
arch/arm/boot/dts/dra72-evm-revc.dts +14 -0
@@ -15,6 +15,16 @@ device_type = "memory"; reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ }; + + evm_1v8_sw: fixedregulator-evm_1v8 { + compatible = "regulator-fixed"; + regulator-name = "evm_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&smps4_reg>; + regulator-always-on; + regulator-boot-on; + }; }; &i2c1 {
@@ -86,3 +96,7 @@ &mmc1 { vmmc_aux-supply = <&ldo1_reg>; }; + +&mmc2 { + vmmc-supply = <&evm_1v8_sw>; +};
arch/arm/boot/dts/dra72-evm.dts +14 -0
@@ -13,6 +13,16 @@ device_type = "memory"; reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */ }; + + evm_1v8_sw: fixedregulator-evm_1v8 { + compatible = "regulator-fixed"; + regulator-name = "evm_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&smps4_reg>; + regulator-always-on; + regulator-boot-on; + }; }; &i2c1 {
@@ -47,3 +57,7 @@ &mmc1 { vmmc_aux-supply = <&ldo1_reg>; }; + +&mmc2 { + vmmc-supply = <&evm_1v8_sw>; +};
Signature · 1 line
2.11.0
PATCH 22/41 ARM: dts: Add dra7 iodelay configuration
In reply to Kishon Vijay Abraham IFrom: Tony Lindgren <[email protected]>
Add dra7 iodelay configuration.
Signed-off-by Tony Lindgren <[email protected]>
Signed-off-by Nishanth Menon <[email protected]>
--- arch/arm/boot/dts/dra7.dtsi | 8 ++++++++ include/dt-bindings/pinctrl/dra.h | 3 +++ 2 files changed, 11 insertions(+)
arch/arm/boot/dts/dra7.dtsi +8 -0
@@ -418,6 +418,14 @@ reg = <0x40d00000 0x100>; }; + dra7_iodelay_core: padconf at 4844a000 { + compatible = "ti,dra7-iodelay"; + reg = <0x4844a000 0x0d1c>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <2>; + }; + sdma: dma-controller at 4a056000 { compatible = "ti,omap4430-sdma"; reg = <0x4a056000 0x1000>;
include/dt-bindings/pinctrl/dra.h +3 -0
@@ -73,5 +73,8 @@*/ #define DRA7XX_CORE_IOPAD (pa, val) (((pa) & 0xffff) - 0x3400) (val) +/* DRA7 IODELAY configuration parameters */ +#define A_DELAY_PS (val) ((val) & 0xffff) +#define G_DELAY_PS (val) ((val) & 0xffff)#endif
Signature · 1 line
2.11.0
PATCH 23/41 ARM: dts: dra72x: Create a common file with MMC/SD IOdelay data
In reply to Kishon Vijay Abraham IFrom: Sekhar Nori <[email protected]>
Add pinmux configuration for MMC module including IODELAY values suggested in the data manual for the various supported modes.
IOdelay data for both silicon revision 1.0 and 2.0 is added here.
The datamanual revisions used are:
* AM571x Silicon Revision 2.0: SPRS957D, Revised January 2017
* AM571x Silicon Revision 1.0: SPRS919M, Revised November 2017
* DRA71x : SPRS960B, Revised February 2017
Signed-off-by Kishon Vijay Abraham I <[email protected]>
--- arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi | 350 ++++++++++++++++++++++++++++++ 1 file changed, 350 insertions(+) create mode 100644 arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi
arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi new file +350 -0
@@ -0,0 +1,350 @@ +/* + * MMC IOdelay values for TI's DRA72x, DRA71x and AM571x SoCs. + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Rules for modifying this file: + * a) Update of this file should typically correspond to a datamanual revision. + * Datamanual revision that was used should be updated in comment below. + * If there is no update to datamanual, do not update the values. If you + * need to use values different from that recommended by the datamanual + * for your design, then you should consider adding values to the device- + * -tree file for your board directly. + * b) We keep the mode names as close to the datamanual as possible. So + * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v, + * we follow that in code too. + * c) If the values change between multiple revisions of silicon, we add + * a revision tag to both the new and old entry. Use 'rev10' for PG 1.0, + * 'rev20' for PG 2.0 and so on. + * d) The node name and node label should be the exact same string. This is + * to curb naming creativity and achieve consistency. + * e) If in future, DRA71x and DRA72x values differ, then add 'dra71_' and + * 'dra72_' tag to entries. Both the new and old entries should gain a tag. + * + * Datamanual Revisions: + * + * AM571x Silicon Revision 2.0: SPRS957D, Revised January 2017 + * AM571x Silicon Revision 1.0: SPRS919M, Revised November 2017 + * DRA71x : SPRS960B, Revised February 2017 + */ + +&dra7_pmx_core { + mmc1_pins_default: mmc1_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr12: mmc1_pins_sdr12 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_hs: mmc1_pins_hs { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr25: mmc1_pins_sdr25 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr50: mmc1_pins_sdr50 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_ddr50_rev10: mmc1_pins_ddr50_rev10 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_clk.mmc1_clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ + DRA7XX_CORE_IOPAD(0x375C, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ + >; + }; + + mmc1_pins_ddr50_rev20: mmc1_pins_ddr50_rev20 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr104: mmc1_pins_sdr104 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc2_pins_default: mmc2_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc2_pins_hs: mmc2_pins_hs { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc2_pins_ddr_rev10: mmc2_pins_ddr_rev10 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + >; + }; + + mmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc2_pins_hs200: mmc2_pins_hs200 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; +}; + +&dra7_iodelay_core { + + /* Corresponds to MMC1_MANUAL1 in datamanual */ + mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf { + pinctrl-pin-array = < + 0x618 A_DELAY_PS(588) G_DELAY_PS(0) /* CFG_MMC1_CLK_IN */ + 0x624 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */ + 0x630 A_DELAY_PS(1375) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */ + 0x63C A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */ + 0x648 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */ + 0x654 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ + 0x620 A_DELAY_PS(1230) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ + 0x62C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ + 0x638 A_DELAY_PS(56) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ + 0x644 A_DELAY_PS(76) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ + 0x650 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ + 0x65C A_DELAY_PS(99) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ + 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ + 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ + 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ + 0x64C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ + 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ + >; + }; + + /* Corresponds to MMC1_MANUAL2 in datamanual */ + mmc1_iodelay_sdr104_rev10_conf: mmc1_iodelay_sdr104_rev10_conf { + pinctrl-pin-array = < + 0x620 A_DELAY_PS(560) G_DELAY_PS(365) /* CFG_MMC1_CLK_OUT */ + 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ + 0x638 A_DELAY_PS(29) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ + 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ + 0x650 A_DELAY_PS(47) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ + 0x65c A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ + 0x628 A_DELAY_PS(125) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ + 0x634 A_DELAY_PS(43) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ + 0x640 A_DELAY_PS(433) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ + 0x64c A_DELAY_PS(287) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ + 0x658 A_DELAY_PS(351) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ + >; + }; + + /* Corresponds to MMC1_MANUAL2 in datamanual */ + mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf { + pinctrl-pin-array = < + 0x620 A_DELAY_PS(520) G_DELAY_PS(320) /* CFG_MMC1_CLK_OUT */ + 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ + 0x638 A_DELAY_PS(40) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ + 0x644 A_DELAY_PS(83) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ + 0x650 A_DELAY_PS(98) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ + 0x65c A_DELAY_PS(106) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ + 0x628 A_DELAY_PS(51) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ + 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ + 0x640 A_DELAY_PS(363) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ + 0x64c A_DELAY_PS(199) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ + 0x658 A_DELAY_PS(273) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ + >; + }; + + /* Corresponds to MMC2_MANUAL1 in datamanual */ + mmc2_iodelay_ddr_conf: mmc2_iodelay_ddr_conf { + pinctrl-pin-array = < + 0x18c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_IN */ + 0x1a4 A_DELAY_PS(119) G_DELAY_PS(0) /* CFG_GPMC_A20_IN */ + 0x1b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_IN */ + 0x1bc A_DELAY_PS(18) G_DELAY_PS(0) /* CFG_GPMC_A22_IN */ + 0x1c8 A_DELAY_PS(894) G_DELAY_PS(0) /* CFG_GPMC_A23_IN */ + 0x1d4 A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_GPMC_A24_IN */ + 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ + 0x1ec A_DELAY_PS(23) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */ + 0x1f8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_IN */ + 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ + 0x194 A_DELAY_PS(152) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ + 0x1ac A_DELAY_PS(206) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ + 0x1b8 A_DELAY_PS(78) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ + 0x1c4 A_DELAY_PS(2) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ + 0x1d0 A_DELAY_PS(266) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */ + 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ + 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ + 0x1f4 A_DELAY_PS(43) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ + 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ + 0x368 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ + 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ + 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ + 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ + 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ + 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ + 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ + 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ + 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ + 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ + >; + }; + + /* Corresponds to MMC2_MANUAL3 in datamanual */ + mmc2_iodelay_hs200_rev10_conf: mmc2_iodelay_hs200_rev10_conf { + pinctrl-pin-array = < + 0x194 A_DELAY_PS(150) G_DELAY_PS(95) /* CFG_GPMC_A19_OUT */ + 0x1ac A_DELAY_PS(250) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ + 0x1b8 A_DELAY_PS(125) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ + 0x1c4 A_DELAY_PS(100) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ + 0x1d0 A_DELAY_PS(870) G_DELAY_PS(415) /* CFG_GPMC_A23_OUT */ + 0x1dc A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ + 0x1e8 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ + 0x1f4 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ + 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ + 0x368 A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ + 0x190 A_DELAY_PS(695) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ + 0x1a8 A_DELAY_PS(924) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ + 0x1b4 A_DELAY_PS(719) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ + 0x1c0 A_DELAY_PS(824) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ + 0x1d8 A_DELAY_PS(877) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ + 0x1e4 A_DELAY_PS(446) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ + 0x1f0 A_DELAY_PS(847) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ + 0x1fc A_DELAY_PS(586) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ + 0x364 A_DELAY_PS(1039) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ + >; + }; + + /* Corresponds to MMC2_MANUAL3 in datamanual */ + mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf { + pinctrl-pin-array = < + 0x194 A_DELAY_PS(285) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ + 0x1ac A_DELAY_PS(189) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ + 0x1b8 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_OUT */ + 0x1c4 A_DELAY_PS(0) G_DELAY_PS(70) /* CFG_GPMC_A22_OUT */ + 0x1d0 A_DELAY_PS(730) G_DELAY_PS(360) /* CFG_GPMC_A23_OUT */ + 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ + 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ + 0x1f4 A_DELAY_PS(70) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ + 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ + 0x368 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_CS1_OUT */ + 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ + 0x1a8 A_DELAY_PS(231) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ + 0x1b4 A_DELAY_PS(39) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ + 0x1c0 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ + 0x1d8 A_DELAY_PS(176) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ + 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ + 0x1f0 A_DELAY_PS(101) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ + 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ + 0x364 A_DELAY_PS(360) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ + >; + }; +};
Signature · 1 line
2.11.0
PATCH 24/41 ARM: dts: dra74x: Create a common file with MMC/SD IOdelay data
In reply to Kishon Vijay Abraham IFrom: Sekhar Nori <[email protected]>
Add pinmux configuration for MMC module including IODELAY values suggested in the data manual for the various supported modes.
IOdelay data for both silicon revision 1.1 and 2.0 is added here.
The datamanual revisions used are:
* AM572x Silicon Revision 2.0: SPRS953B, Revised November 2016
* AM572x Silicon Revision 1.1: SPRS915R, Revised November 2016
Signed-off-by Kishon Vijay Abraham I <[email protected]>
--- arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi | 648 ++++++++++++++++++++++++++++++ 1 file changed, 648 insertions(+) create mode 100644 arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi
arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi new file +648 -0
@@ -0,0 +1,648 @@ +/* + * MMC IOdelay values for TI's DRA74x, DRA75x and AM572x SoCs. + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Rules for modifying this file: + * a) Update of this file should typically correspond to a datamanual revision. + * Datamanual revision that was used should be updated in comment below. + * If there is no update to datamanual, do not update the values. If you + * need to use values different from that recommended by the datamanual + * for your design, then you should consider adding values to the device- + * -tree file for your board directly. + * b) We keep the mode names as close to the datamanual as possible. So + * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v, + * we follow that in code too. + * c) If the values change between multiple revisions of silicon, we add + * a revision tag to both the new and old entry. Use 'rev11' for PG 1.1, + * 'rev20' for PG 2.0 and so on. + * d) The node name and node label should be the exact same string. This is + * to curb naming creativity and achieve consistency. + * + * Datamanual Revisions: + * + * AM572x Silicon Revision 2.0: SPRS953B, Revised November 2016 + * AM572x Silicon Revision 1.1: SPRS915R, Revised November 2016 + * + */ + +&dra7_pmx_core { + mmc1_pins_default: mmc1_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr12: mmc1_pins_sdr12 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_hs: mmc1_pins_hs { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr25: mmc1_pins_sdr25 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr50: mmc1_pins_sdr50 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_ddr50: mmc1_pins_ddr50 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr104: mmc1_pins_sdr104 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc2_pins_default: mmc2_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc2_pins_hs: mmc2_pins_hs { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc2_pins_ddr_3_3v_rev11: mmc2_pins_ddr_3_3v_rev11 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc2_pins_ddr_1_8v_rev11: mmc2_pins_ddr_1_8v_rev11 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc2_pins_hs200: mmc2_pins_hs200 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc4_pins_default: mmc4_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ + DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ + DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ + DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ + DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ + DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ + >; + }; + + mmc4_pins_hs: mmc4_pins_hs { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ + DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ + DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ + DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ + DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ + DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ + >; + }; + + mmc3_pins_default: mmc3_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ + DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ + DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ + DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ + DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ + DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ + >; + }; + + mmc3_pins_hs: mmc3_pins_hs { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ + DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ + DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ + DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ + DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ + DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ + >; + }; + + mmc3_pins_sdr12: mmc3_pins_sdr12 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ + DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ + DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ + DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ + DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ + DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ + >; + }; + + mmc3_pins_sdr25: mmc3_pins_sdr25 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ + DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ + DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ + DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ + DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ + DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ + >; + }; + + mmc3_pins_sdr50: mmc3_pins_sdr50 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ + DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ + DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ + DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ + DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ + DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ + >; + }; + + mmc4_pins_sdr12: mmc4_pins_sdr12 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ + DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ + DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ + DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ + DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ + DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ + >; + }; + + mmc4_pins_sdr25: mmc4_pins_sdr25 { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ + DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ + DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ + DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ + DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ + DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ + >; + }; +}; + +&dra7_iodelay_core { + + /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */ + mmc1_iodelay_ddr_rev11_conf: mmc1_iodelay_ddr_rev11_conf { + pinctrl-pin-array = < + 0x618 A_DELAY_PS(572) G_DELAY_PS(540) /* CFG_MMC1_CLK_IN */ + 0x620 A_DELAY_PS(1525) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ + 0x624 A_DELAY_PS(0) G_DELAY_PS(600) /* CFG_MMC1_CMD_IN */ + 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ + 0x62c A_DELAY_PS(55) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ + 0x630 A_DELAY_PS(403) G_DELAY_PS(120) /* CFG_MMC1_DAT0_IN */ + 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ + 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ + 0x63c A_DELAY_PS(23) G_DELAY_PS(60) /* CFG_MMC1_DAT1_IN */ + 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ + 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ + 0x648 A_DELAY_PS(25) G_DELAY_PS(60) /* CFG_MMC1_DAT2_IN */ + 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ + 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ + 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ + 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ + 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ + >; + }; + + /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */ + mmc1_iodelay_ddr_rev20_conf: mmc1_iodelay_ddr50_rev20_conf { + pinctrl-pin-array = < + 0x618 A_DELAY_PS(1076) G_DELAY_PS(330) /* CFG_MMC1_CLK_IN */ + 0x620 A_DELAY_PS(1271) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ + 0x624 A_DELAY_PS(722) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */ + 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ + 0x62C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ + 0x630 A_DELAY_PS(751) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */ + 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ + 0x638 A_DELAY_PS(20) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ + 0x63C A_DELAY_PS(256) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */ + 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ + 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ + 0x648 A_DELAY_PS(263) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */ + 0x64C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ + 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ + 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ + 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ + 0x65C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ + >; + }; + + /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */ + mmc1_iodelay_sdr104_rev11_conf: mmc1_iodelay_sdr104_rev11_conf { + pinctrl-pin-array = < + 0x620 A_DELAY_PS(1063) G_DELAY_PS(17) /* CFG_MMC1_CLK_OUT */ + 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ + 0x62c A_DELAY_PS(23) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ + 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ + 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ + 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ + 0x644 A_DELAY_PS(2) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ + 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ + 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ + 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ + 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ + >; + }; + + /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */ + mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf { + pinctrl-pin-array = < + 0x620 A_DELAY_PS(600) G_DELAY_PS(400) /* CFG_MMC1_CLK_OUT */ + 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ + 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ + 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ + 0x638 A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ + 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ + 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ + 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ + 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ + 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ + 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ + >; + }; + + /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */ + mmc2_iodelay_hs200_rev11_conf: mmc2_iodelay_hs200_rev11_conf { + pinctrl-pin-array = < + 0x190 A_DELAY_PS(621) G_DELAY_PS(600) /* CFG_GPMC_A19_OEN */ + 0x194 A_DELAY_PS(300) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ + 0x1a8 A_DELAY_PS(739) G_DELAY_PS(600) /* CFG_GPMC_A20_OEN */ + 0x1ac A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ + 0x1b4 A_DELAY_PS(812) G_DELAY_PS(600) /* CFG_GPMC_A21_OEN */ + 0x1b8 A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ + 0x1c0 A_DELAY_PS(954) G_DELAY_PS(600) /* CFG_GPMC_A22_OEN */ + 0x1c4 A_DELAY_PS(60) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ + 0x1d0 A_DELAY_PS(1340) G_DELAY_PS(420) /* CFG_GPMC_A23_OUT */ + 0x1d8 A_DELAY_PS(935) G_DELAY_PS(600) /* CFG_GPMC_A24_OEN */ + 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ + 0x1e4 A_DELAY_PS(525) G_DELAY_PS(600) /* CFG_GPMC_A25_OEN */ + 0x1e8 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ + 0x1f0 A_DELAY_PS(767) G_DELAY_PS(600) /* CFG_GPMC_A26_OEN */ + 0x1f4 A_DELAY_PS(225) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ + 0x1fc A_DELAY_PS(565) G_DELAY_PS(600) /* CFG_GPMC_A27_OEN */ + 0x200 A_DELAY_PS(60) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ + 0x364 A_DELAY_PS(969) G_DELAY_PS(600) /* CFG_GPMC_CS1_OEN */ + 0x368 A_DELAY_PS(180) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ + >; + }; + + /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */ + mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf { + pinctrl-pin-array = < + 0x190 A_DELAY_PS(274) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ + 0x194 A_DELAY_PS(162) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ + 0x1a8 A_DELAY_PS(401) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ + 0x1ac A_DELAY_PS(73) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ + 0x1b4 A_DELAY_PS(465) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ + 0x1b8 A_DELAY_PS(115) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ + 0x1c0 A_DELAY_PS(633) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ + 0x1c4 A_DELAY_PS(47) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ + 0x1d0 A_DELAY_PS(935) G_DELAY_PS(280) /* CFG_GPMC_A23_OUT */ + 0x1d8 A_DELAY_PS(621) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ + 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ + 0x1e4 A_DELAY_PS(183) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ + 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ + 0x1f0 A_DELAY_PS(467) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ + 0x1f4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ + 0x1fc A_DELAY_PS(262) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ + 0x200 A_DELAY_PS(46) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ + 0x364 A_DELAY_PS(684) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ + 0x368 A_DELAY_PS(76) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ + >; + }; + + /* Correspnds to MMC2_DDR_3V3_MANUAL1 in datamanual */ + mmc2_iodelay_ddr_3_3v_rev11_conf: mmc2_iodelay_ddr_3_3v_rev11_conf { + pinctrl-pin-array = < + 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */ + 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ + 0x194 A_DELAY_PS(174) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ + 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */ + 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ + 0x1ac A_DELAY_PS(168) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ + 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */ + 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ + 0x1b8 A_DELAY_PS(136) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ + 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */ + 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ + 0x1c4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ + 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */ + 0x1d0 A_DELAY_PS(879) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */ + 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */ + 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ + 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ + 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ + 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ + 0x1e8 A_DELAY_PS(34) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ + 0x1ec A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A26_IN */ + 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ + 0x1f4 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ + 0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */ + 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ + 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ + 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ + 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ + 0x368 A_DELAY_PS(11) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ + >; + }; + + /* Corresponds to MMC2_DDR_1V8_MANUAL1 in datamanual */ + mmc2_iodelay_ddr_1_8v_rev11_conf: mmc2_iodelay_ddr_1_8v_rev11_conf { + pinctrl-pin-array = < + 0x18c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_IN */ + 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ + 0x194 A_DELAY_PS(174) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ + 0x1a4 A_DELAY_PS(274) G_DELAY_PS(240) /* CFG_GPMC_A20_IN */ + 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ + 0x1ac A_DELAY_PS(168) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ + 0x1b0 A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A21_IN */ + 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ + 0x1b8 A_DELAY_PS(136) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ + 0x1bc A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A22_IN */ + 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ + 0x1c4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ + 0x1c8 A_DELAY_PS(514) G_DELAY_PS(360) /* CFG_GPMC_A23_IN */ + 0x1d0 A_DELAY_PS(879) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */ + 0x1d4 A_DELAY_PS(187) G_DELAY_PS(120) /* CFG_GPMC_A24_IN */ + 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ + 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ + 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ + 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ + 0x1e8 A_DELAY_PS(34) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ + 0x1ec A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A26_IN */ + 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ + 0x1f4 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ + 0x1f8 A_DELAY_PS(121) G_DELAY_PS(60) /* CFG_GPMC_A27_IN */ + 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ + 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ + 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ + 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ + 0x368 A_DELAY_PS(11) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ + >; + }; + + /* Corresponds to MMC3_MANUAL1 in datamanual */ + mmc3_iodelay_manual1_rev20_conf: mmc3_iodelay_manual1_conf { + pinctrl-pin-array = < + 0x678 A_DELAY_PS(0) G_DELAY_PS(386) /* CFG_MMC3_CLK_IN */ + 0x680 A_DELAY_PS(605) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ + 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ + 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ + 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ + 0x690 A_DELAY_PS(171) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ + 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ + 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ + 0x69c A_DELAY_PS(221) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ + 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ + 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ + 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ + 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ + 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ + 0x6b4 A_DELAY_PS(474) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ + 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ + 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ + >; + }; + + /* Corresponds to MMC3_MANUAL1 in datamanual */ + mmc3_iodelay_manual1_rev11_conf: mmc3_iodelay_manual1_conf { + pinctrl-pin-array = < + 0x678 A_DELAY_PS(406) G_DELAY_PS(0) /* CFG_MMC3_CLK_IN */ + 0x680 A_DELAY_PS(659) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ + 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ + 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ + 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ + 0x690 A_DELAY_PS(130) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ + 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ + 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ + 0x69c A_DELAY_PS(169) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ + 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ + 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ + 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ + 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ + 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ + 0x6b4 A_DELAY_PS(457) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ + 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ + 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ + >; + }; + + /* Corresponds to MMC4_DS_MANUAL1 in datamanual */ + mmc4_iodelay_ds_rev11_conf: mmc4_iodelay_ds_rev11_conf { + pinctrl-pin-array = < + 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ + 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ + 0x84c A_DELAY_PS(96) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ + 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ + 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ + 0x870 A_DELAY_PS(582) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ + 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ + 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ + 0x87c A_DELAY_PS(391) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ + 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ + 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ + 0x888 A_DELAY_PS(561) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ + 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ + 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ + 0x894 A_DELAY_PS(588) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ + 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ + 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ + >; + }; + + /* Corresponds to MMC4_DS_MANUAL1 in datamanual */ + mmc4_iodelay_ds_rev20_conf: mmc4_iodelay_ds_rev20_conf { + pinctrl-pin-array = < + 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ + 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ + 0x84c A_DELAY_PS(307) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ + 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ + 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ + 0x870 A_DELAY_PS(785) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ + 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ + 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ + 0x87c A_DELAY_PS(613) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ + 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ + 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ + 0x888 A_DELAY_PS(683) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ + 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ + 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ + 0x894 A_DELAY_PS(835) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ + 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ + 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ + >; + }; + + /* Corresponds to MMC4_MANUAL1 in datamanual */ + mmc4_iodelay_sdr12_hs_sdr25_rev11_conf: mmc4_iodelay_sdr12_hs_sdr25_rev11_conf { + pinctrl-pin-array = < + 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ + 0x848 A_DELAY_PS(2651) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ + 0x84c A_DELAY_PS(1572) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ + 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ + 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ + 0x870 A_DELAY_PS(1913) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ + 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ + 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ + 0x87c A_DELAY_PS(1721) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ + 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ + 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ + 0x888 A_DELAY_PS(1891) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ + 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ + 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ + 0x894 A_DELAY_PS(1919) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ + 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ + 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ + >; + }; + + /* Corresponds to MMC4_MANUAL1 in datamanual */ + mmc4_iodelay_sdr12_hs_sdr25_rev20_conf: mmc4_iodelay_sdr12_hs_sdr25_rev20_conf { + pinctrl-pin-array = < + 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ + 0x848 A_DELAY_PS(1147) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ + 0x84c A_DELAY_PS(1834) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ + 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ + 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ + 0x870 A_DELAY_PS(2165) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ + 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ + 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ + 0x87c A_DELAY_PS(1929) G_DELAY_PS(64) /* CFG_UART2_RTSN_IN */ + 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ + 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ + 0x888 A_DELAY_PS(1935) G_DELAY_PS(128) /* CFG_UART2_RXD_IN */ + 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ + 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ + 0x894 A_DELAY_PS(2172) G_DELAY_PS(44) /* CFG_UART2_TXD_IN */ + 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ + 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ + >; + }; +}; +
Signature · 1 line
2.11.0
PATCH 25/41 ARM: dts: dra7-evm: Add pinmux configuration for MMC
In reply to Kishon Vijay Abraham IInclude dra74x-mmc-iodelay.dtsi which has pinmux and IODelay configuration values for the various MMC modes for dra74 SoC and use it in the pinctrl properties of MMC devicetree nodes present in dra7-evm.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
--- arch/arm/boot/dts/dra7-evm.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
arch/arm/boot/dts/dra7-evm.dts +18 -0
@@ -8,6 +8,7 @@ /dts-v1/; #include "dra74x.dtsi" +#include "dra74x-mmc-iodelay.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clk/ti-dra7-atl.h> #include <dt-bindings/input/input.h>
@@ -451,6 +452,16 @@ * is always hardwired. */ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; + pinctrl-2 = <&mmc1_pins_sdr12>; + pinctrl-3 = <&mmc1_pins_sdr25>; + pinctrl-4 = <&mmc1_pins_sdr50>; + pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>; + pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>; + pinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>; + pinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; }; &mmc2 {
@@ -459,6 +470,13 @@ pinctrl-0 = <&mmc2_pins_default>; vmmc-supply = <&evm_1v8_sw>; bus-width = <8>; + pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_1_8v_rev11 &mmc2_iodelay_ddr_1_8v_rev11_conf>; + pinctrl-3 = <&mmc2_pins_ddr_rev20>; + pinctrl-4 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev11_conf>; + pinctrl-5 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; }; &cpu0 {
Signature · 1 line
2.11.0
PATCH 26/41 ARM: dts: am57xx-beagle-x15: Add pinmux configuration for MMC
In reply to Kishon Vijay Abraham IInclude dra74x-mmc-iodelay.dtsi which has pinmux and IODelay configuration values for the various MMC modes for dra74 SoC and use it in the pinctrl properties of MMC devicetree nodes present in am57xx-beagle-x15/am57xx-beagle-x15-revb1.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
--- arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi | 29 +------------------------ arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts | 15 +++++++++++++ arch/arm/boot/dts/am57xx-beagle-x15.dts | 11 ++++++++++ 3 files changed, 27 insertions(+), 28 deletions(-)
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi +1 -28
@@ -9,6 +9,7 @@ #include "dra74x.dtsi" #include "am57xx-commercial-grade.dtsi" +#include "dra74x-mmc-iodelay.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h>
@@ -166,34 +167,6 @@ }; }; -&dra7_pmx_core { - mmc1_pins_default: mmc1_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc2_pins_default: mmc2_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; -}; &i2c1 { status = "okay"; clock-frequency = <400000>;
arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts +15 -0
@@ -19,10 +19,25 @@ }; &mmc1 { + pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; + pinctrl-2 = <&mmc1_pins_sdr12>; + pinctrl-3 = <&mmc1_pins_sdr25>; + pinctrl-4 = <&mmc1_pins_sdr50>; + pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>; + pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>; vmmc-supply = <&vdd_3v3>; vmmc_aux-supply = <&ldo1_reg>; }; +&mmc2 { + pinctrl-names = "default", "hs", "ddr_1_8v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>; +}; + /* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */ &phy1 { max-speed = <100>;
arch/arm/boot/dts/am57xx-beagle-x15.dts +11 -0
@@ -20,9 +20,20 @@ }; &mmc1 { + pinctrl-names = "default", "hs"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; + vmmc-supply = <&ldo1_reg>; }; +&mmc2 { + pinctrl-names = "default", "hs", "ddr_1_8v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>; +}; + /* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */ &phy1 { max-speed = <100>;
Signature · 1 line
2.11.0
PATCH 27/41 ARM: dts: am57xx-idk: Move common MMC/SD properties to common file
In reply to Kishon Vijay Abraham IFrom: Sekhar Nori <[email protected]>
AM572x IDK and AM571x IDK boards have equivalent design of how SD card and eMMC are connected.
The two EVMs mainly differ in IOdelay configuration needed (because of difference in SoC used).
Move the common properties to am57xx-idk-common.dtsi file which is common for both EVMs.
Signed-off-by Sekhar Nori <[email protected]>
Signed-off-by Kishon Vijay Abraham I <[email protected]>
--- arch/arm/boot/dts/am571x-idk.dts | 7 ------- arch/arm/boot/dts/am572x-idk.dts | 8 -------- arch/arm/boot/dts/am57xx-idk-common.dtsi | 8 ++++++++ 3 files changed, 8 insertions(+), 15 deletions(-)
arch/arm/boot/dts/am571x-idk.dts +0 -7
@@ -64,13 +64,6 @@ }; }; -&mmc1 { - status = "okay"; - vmmc-supply = <&ldo1_reg>; - bus-width = <4>; - cd-gpios = <&gpio6 27 0>; /* gpio 219 */ -}; - &omap_dwc3_2 { extcon = <&extcon_usb2>; };
arch/arm/boot/dts/am572x-idk.dts +0 -8
@@ -76,14 +76,6 @@ vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>; }; -&mmc1 { - status = "okay"; - vmmc-supply = <&v3_3d>; - vmmc_aux-supply = <&ldo1_reg>; - bus-width = <4>; - cd-gpios = <&gpio6 27 0>; /* gpio 219 */ -}; - &sn65hvs882 { load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; };
arch/arm/boot/dts/am57xx-idk-common.dtsi +8 -0
@@ -399,6 +399,14 @@ dr_mode = "peripheral"; }; +&mmc1 { + status = "okay"; + vmmc-supply = <&v3_3d>; + vmmc_aux-supply = <&ldo1_reg>; + bus-width = <4>; + cd-gpios = <&gpio6 27 0>; /* gpio 219 */ +}; + &mmc2 { status = "okay"; vmmc-supply = <&v3_3d>;
Signature · 1 line
2.11.0
PATCH 28/41 ARM: dts: am571x-idk: Add pinmux configuration for MMC
In reply to Kishon Vijay Abraham IInclude dra72x-mmc-iodelay.dtsi which has pinmux and IODelay configuration values for the various MMC modes for dra72 SoC and use it in the pinctrl properties of MMC devicetree nodes present in am571x-idk.dts.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
--- arch/arm/boot/dts/am571x-idk.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
arch/arm/boot/dts/am571x-idk.dts +19 -0
@@ -11,6 +11,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> #include "am57xx-idk-common.dtsi" +#include "dra72x-mmc-iodelay.dtsi" / { model = "TI AM5718 IDK";
@@ -72,3 +73,21 @@ id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; vbus-gpio = <&gpio7 22 GPIO_ACTIVE_HIGH>; }; + +&mmc1 { + pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; + pinctrl-2 = <&mmc1_pins_sdr12>; + pinctrl-3 = <&mmc1_pins_sdr25>; + pinctrl-4 = <&mmc1_pins_sdr50>; + pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>; + pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; +}; + +&mmc2 { + pinctrl-names = "default", "hs", "ddr_1_8v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; +};
Signature · 1 line
2.11.0
PATCH 29/41 ARM: dts: am572x-idk: Add pinmux configuration for MMC
In reply to Kishon Vijay Abraham IInclude dra74x-mmc-iodelay.dtsi which has pinmux and IODelay configuration values for the various MMC modes for dra74x SoC and use it in the pinctrl properties of MMC devicetree nodes present in am572x-idk.dts.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
--- arch/arm/boot/dts/am572x-idk.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
arch/arm/boot/dts/am572x-idk.dts +19 -0
@@ -12,6 +12,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> #include "am57xx-idk-common.dtsi" +#include "dra74x-mmc-iodelay.dtsi" / { model = "TI AM5728 IDK";
@@ -67,6 +68,24 @@ }; }; +&mmc1 { + pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; + pinctrl-2 = <&mmc1_pins_sdr12>; + pinctrl-3 = <&mmc1_pins_sdr25>; + pinctrl-4 = <&mmc1_pins_sdr50>; + pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>; + pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; +}; + +&mmc2 { + pinctrl-names = "default", "hs", "ddr_1_8v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_rev20>; +}; + &omap_dwc3_2 { extcon = <&extcon_usb2>; };
Signature · 1 line
2.11.0
PATCH 30/41 ARM: dts: dra72-evm: Add pinmux configuration for MMC
In reply to Kishon Vijay Abraham IInclude dra72x-mmc-iodelay.dtsi which has pinmux and IODelay configuration values for the various MMC modes for dra72 SoC and use it in the pinctrl properties of MMC devicetree nodes present in dra72-evm.dts.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
--- arch/arm/boot/dts/dra72-evm.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
arch/arm/boot/dts/dra72-evm.dts +14 -0
@@ -6,6 +6,7 @@ * published by the Free Software Foundation. */ #include "dra72-evm-common.dtsi" +#include "dra72x-mmc-iodelay.dtsi" / { model = "TI DRA722";
@@ -55,9 +56,22 @@ }; &mmc1 { + pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; + pinctrl-2 = <&mmc1_pins_sdr12>; + pinctrl-3 = <&mmc1_pins_sdr25>; + pinctrl-4 = <&mmc1_pins_sdr50>; + pinctrl-5 = <&mmc1_pins_ddr50_rev10>; + pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev10_conf>; vmmc_aux-supply = <&ldo1_reg>; }; &mmc2 { + pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_rev10>; + pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev10_conf>; vmmc-supply = <&evm_1v8_sw>; };
Signature · 1 line
2.11.0
PATCH 31/41 ARM: dts: dra72-evm-revc: Add pinmux configuration for MMC
In reply to Kishon Vijay Abraham IInclude dra72x-mmc-iodelay.dtsi which has pinmux and IODelay configuration values for the various MMC modes for dra72 SoC and use it in the pinctrl properties of MMC devicetree nodes present in dra72-evm-revc.dts.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
--- arch/arm/boot/dts/dra72-evm-revc.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
arch/arm/boot/dts/dra72-evm-revc.dts +14 -0
@@ -6,6 +6,7 @@ * published by the Free Software Foundation. */ #include "dra72-evm-common.dtsi" +#include "dra72x-mmc-iodelay.dtsi" #include <dt-bindings/net/ti-dp83867.h> / {
@@ -94,9 +95,22 @@ }; &mmc1 { + pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; + pinctrl-2 = <&mmc1_pins_sdr12>; + pinctrl-3 = <&mmc1_pins_sdr25>; + pinctrl-4 = <&mmc1_pins_sdr50>; + pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>; + pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; vmmc_aux-supply = <&ldo1_reg>; }; &mmc2 { + pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; + pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; vmmc-supply = <&evm_1v8_sw>; };
Signature · 1 line
2.11.0
PATCH 32/41 ARM: dts: dra71-evm: Add pinmux configuration for MMC
In reply to Kishon Vijay Abraham IInclude dra72x-mmc-iodelay.dtsi which has pinmux and IODelay configuration values for the various MMC modes for dra72 SoC and use it in the pinctrl properties of MMC devicetree nodes present in dra71-evm.dts.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
--- arch/arm/boot/dts/dra71-evm.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
arch/arm/boot/dts/dra71-evm.dts +14 -0
@@ -7,6 +7,7 @@ */ #include "dra72-evm-common.dtsi" +#include "dra72x-mmc-iodelay.dtsi" #include <dt-bindings/net/ti-dp83867.h> / {
@@ -172,10 +173,23 @@ }; &mmc1 { + pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; + pinctrl-2 = <&mmc1_pins_sdr12>; + pinctrl-3 = <&mmc1_pins_sdr25>; + pinctrl-4 = <&mmc1_pins_sdr50>; + pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>; + pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; vmmc_aux-supply = <&vpo_sd_1v8_3v3>; }; &mmc2 { + pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; + pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; vmmc-supply = <&evm_1v8_sw>; };
Signature · 1 line
2.11.0
PATCH 33/41 ARM: dts: dra7: Add "max-frequency" property to MMC dt nodes
In reply to Kishon Vijay Abraham IAdd "max-frequency" property to MMC dt nodes and set the maximum frequency to 192MHz for MMC1/MMC2, 64MHz for MMC3 and 192MHz for MMC4. pdata quirks must be utilized to detect presence of rev 1.1/1.0 of silicon and adjust maximum frequencies as per restrictions documented in i843.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
Signed-off-by Sekhar Nori <[email protected]>
--- arch/arm/boot/dts/dra7.dtsi | 5 +++++ 1 file changed, 5 insertions(+)
arch/arm/boot/dts/dra7.dtsi +5 -0
@@ -1045,6 +1045,7 @@ dma-names = "tx", "rx"; status = "disabled"; pbias-supply = <&pbias_mmc_reg>; + max-frequency = <192000000>; }; mmc2: mmc at 480b4000 {
@@ -1056,6 +1057,7 @@ dmas = <&sdma_xbar 47>, <&sdma_xbar 48>; dma-names = "tx", "rx"; status = "disabled"; + max-frequency = <192000000>; }; mmc3: mmc at 480ad000 {
@@ -1067,6 +1069,8 @@ dmas = <&sdma_xbar 77>, <&sdma_xbar 78>; dma-names = "tx", "rx"; status = "disabled"; + /* Errata i887 limits max-frequency of MMC3 to 64 MHz */ + max-frequency = <64000000>; }; mmc4: mmc at 480d1000 {
@@ -1078,6 +1082,7 @@ dmas = <&sdma_xbar 57>, <&sdma_xbar 58>; dma-names = "tx", "rx"; status = "disabled"; + max-frequency = <192000000>; }; mmu0_dsp1: mmu at 40d01000 {
Signature · 1 line
2.11.0
PATCH 34/41 ARM: dts: dra7: Use new dra7-specific compatible string
In reply to Kishon Vijay Abraham IUse the new compatible string "ti,dra7-hsmmc" that was specifically added for dra7 and dra72. This is required since for dra7 and dra72 processors iodelay values has to be set unlike other processors.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
Signed-off-by Sekhar Nori <[email protected]>
--- arch/arm/boot/dts/dra7.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
arch/arm/boot/dts/dra7.dtsi +4 -4
@@ -1035,7 +1035,7 @@ }; mmc1: mmc at 4809c000 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; reg = <0x4809c000 0x400>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mmc1";
@@ -1049,7 +1049,7 @@ }; mmc2: mmc at 480b4000 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; reg = <0x480b4000 0x400>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mmc2";
@@ -1061,7 +1061,7 @@ }; mmc3: mmc at 480ad000 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; reg = <0x480ad000 0x400>; interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mmc3";
@@ -1074,7 +1074,7 @@ }; mmc4: mmc at 480d1000 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; reg = <0x480d1000 0x400>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mmc4";
Signature · 1 line
2.11.0
PATCH 35/41 ARM: dts: dra7: Add supported MMC/SD modes in MMC dt nodes
In reply to Kishon Vijay Abraham IOn DRA7 family SoCs, MMC1 controller supports SDR104, SDR50, DDR50, SDR25 and SDR12 UHS modes (These UHS modes are not supported in beagle-x15 because it's not possible to switch IO lines supply voltage to 1.8v).
MMC2 controller supports HS200 and DDR modes. (Since some of the boards like am57xx-evm reva3, beagle-x15 and am57xx idk has 3.3v line connected to IO lines, HS200 cannot be supported in these boards).
MMC3 controller supports SDR12, SDR25 and SDR50 modes.
MMC4 controller supports SDR12 and SDR25 modes.
Add these supported modes in device-tree file.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
Signed-off-by Sekhar Nori <[email protected]>
--- arch/arm/boot/dts/am571x-idk.dts | 1 + arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts | 1 + arch/arm/boot/dts/am57xx-beagle-x15.dts | 6 ++++++ arch/arm/boot/dts/am57xx-idk-common.dtsi | 1 + arch/arm/boot/dts/dra7.dtsi | 14 ++++++++++++++ 5 files changed, 23 insertions(+)
arch/arm/boot/dts/am571x-idk.dts +1 -0
@@ -90,4 +90,5 @@ pinctrl-0 = <&mmc2_pins_default>; pinctrl-1 = <&mmc2_pins_hs>; pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; + /delete-property/ mmc-hs200-1_8v; };
arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts +1 -0
@@ -36,6 +36,7 @@ pinctrl-0 = <&mmc2_pins_default>; pinctrl-1 = <&mmc2_pins_hs>; pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>; + /delete-property/ mmc-hs200-1_8v; }; /* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */
arch/arm/boot/dts/am57xx-beagle-x15.dts +6 -0
@@ -25,6 +25,11 @@ pinctrl-1 = <&mmc1_pins_hs>; vmmc-supply = <&ldo1_reg>; + /delete-property/ sd-uhs-sdr104; + /delete-property/ sd-uhs-sdr50; + /delete-property/ sd-uhs-ddr50; + /delete-property/ sd-uhs-sdr25; + /delete-property/ sd-uhs-sdr12; }; &mmc2 {
@@ -32,6 +37,7 @@ pinctrl-0 = <&mmc2_pins_default>; pinctrl-1 = <&mmc2_pins_hs>; pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>; + /delete-property/ mmc-hs200-1_8v; }; /* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */
arch/arm/boot/dts/am57xx-idk-common.dtsi +1 -0
@@ -413,6 +413,7 @@ bus-width = <8>; ti,non-removable; max-frequency = <96000000>; + /delete-property/ mmc-hs200-1_8v; }; &dcan1 {
arch/arm/boot/dts/dra7.dtsi +14 -0
@@ -1046,6 +1046,11 @@ status = "disabled"; pbias-supply = <&pbias_mmc_reg>; max-frequency = <192000000>; + sd-uhs-sdr104; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr25; + sd-uhs-sdr12; }; mmc2: mmc at 480b4000 {
@@ -1058,6 +1063,10 @@ dma-names = "tx", "rx"; status = "disabled"; max-frequency = <192000000>; + sd-uhs-sdr25; + sd-uhs-sdr12; + mmc-hs200-1_8v; + mmc-ddr-1_8v; }; mmc3: mmc at 480ad000 {
@@ -1071,6 +1080,9 @@ status = "disabled"; /* Errata i887 limits max-frequency of MMC3 to 64 MHz */ max-frequency = <64000000>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; }; mmc4: mmc at 480d1000 {
@@ -1083,6 +1095,8 @@ dma-names = "tx", "rx"; status = "disabled"; max-frequency = <192000000>; + sd-uhs-sdr12; + sd-uhs-sdr25; }; mmu0_dsp1: mmu at 40d01000 {
Signature · 1 line
2.11.0
PATCH 36/41 ARM: dts: am57xx-idk: Set MMC2 IO voltage to 3.3V
In reply to Kishon Vijay Abraham IFrom: Sekhar Nori <[email protected]>
MMC2 interface on AM57xx IDK, connected to onboard eMMC, has IO voltage fixed to 3.3V.
Add no-1-8-v device-tree property to mmc2 node in the board's device-tree file to reflect this.
Note that the AM57xx SoC itself supports dual-voltage on MMC2. The limitation above is due to the board.
Signed-off-by Sekhar Nori <[email protected]>
Signed-off-by Kishon Vijay Abraham I <[email protected]>
--- arch/arm/boot/dts/am57xx-idk-common.dtsi | 1 + 1 file changed, 1 insertion(+)
arch/arm/boot/dts/am57xx-idk-common.dtsi +1 -0
@@ -413,6 +413,7 @@ bus-width = <8>; ti,non-removable; max-frequency = <96000000>; + no-1-8-v; /delete-property/ mmc-hs200-1_8v; };
Signature · 1 line
2.11.0
PATCH 37/41 ARM: dts: am57xx-beagle-x15-common: Set MMC2 IO voltage to 3.3V
In reply to Kishon Vijay Abraham IMMC2 interface on AM57xx Beagle-x15, connected to onboard eMMC, has IO voltage fixed to 3.3V.
Add no-1-8-v device-tree property to mmc2 node in the board's device-tree file to reflect this.
Note that the AM57xx SoC itself supports dual-voltage on MMC2. The limitation above is due to the board.
Signed-off-by Sekhar Nori <[email protected]>
Signed-off-by Kishon Vijay Abraham I <[email protected]>
--- arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi | 1 + 1 file changed, 1 insertion(+)
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi +1 -0
@@ -445,6 +445,7 @@ bus-width = <8>; ti,non-removable; cap-mmc-dual-data-rate; + no-1-8-v; }; &sata {
Signature · 1 line
2.11.0
PATCH 38/41 ARM: OMAP2+: Add pdata-quirks for MMC/SD on DRA74x EVM
In reply to Kishon Vijay Abraham IFrom: Sekhar Nori <[email protected]>
DRA74x EVM Rev H EVM comes with revision 2.0 silicon. However, earlier versions of EVM can come with either revision 1.1 or revision 1.0 of silicon.
The device-tree file is written to support rev 2.0 of silicon. pdata quirks are used to then override the settings needed for PG 1.1 silicon.
PG 1.1 silicon has limitations w.r.t frequencies at which MMC1/2/3 can operate as well as different IOdelay numbers.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
Signed-off-by Sekhar Nori <[email protected]>
--- arch/arm/mach-omap2/pdata-quirks.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+)
arch/arm/mach-omap2/pdata-quirks.c +31 -0
@@ -434,6 +434,26 @@ static void __init omap5_uevm_legacy_init(void) }#endif +#ifdef CONFIG_SOC_DRA7XX +static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc1; +static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc2; +static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc3; + +static void __init dra7x_evm_mmc_quirk (void ) +{ +if (omap_rev () ==DRA752_REV_ES1_1 ||omap_rev () ==DRA752_REV_ES1_0 ) { + dra7_hsmmc_data_mmc1.version ="rev11" ; + dra7_hsmmc_data_mmc1.max_freq =96000000 ; + + dra7_hsmmc_data_mmc2.version ="rev11" ; + dra7_hsmmc_data_mmc2.max_freq =48000000 ; + + dra7_hsmmc_data_mmc3.version ="rev11" ; + dra7_hsmmc_data_mmc3.max_freq =48000000 ; + } +} +#endif +static struct pcs_pdata pcs_pdata;void omap_pcs_legacy_init (int irq,void (*rearm)(void ))
@@ -561,6 +581,14 @@ static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("ti,omap4-iommu", 0x55082000, "55082000.mmu", &omap4_iommu_pdata),#endif +#ifdef CONFIG_SOC_DRA7XX +OF_DEV_AUXDATA ("ti,dra7-hsmmc" ,0x4809c000 ,"4809c000.mmc" , + &dra7_hsmmc_data_mmc1), +OF_DEV_AUXDATA ("ti,dra7-hsmmc" ,0x480b4000 ,"480b4000.mmc" , + &dra7_hsmmc_data_mmc2), +OF_DEV_AUXDATA ("ti,dra7-hsmmc" ,0x480ad000 ,"480ad000.mmc" , + &dra7_hsmmc_data_mmc3), +#endif/* Common auxdata */ OF_DEV_AUXDATA("pinctrl-single", 0, NULL, &pcs_pdata), { /* sentinel */ },
@@ -590,6 +618,9 @@ static struct pdata_init pdata_quirks[] __initdata = { #ifdef CONFIG_SOC_OMAP5 { "ti,omap5-uevm", omap5_uevm_legacy_init, }, #endif +#ifdef CONFIG_SOC_DRA7XX + { "ti,dra7-evm", dra7x_evm_mmc_quirk, }, +#endif { /* sentinel */ }, };
Signature · 1 line
2.11.0
PATCH 39/41 ARM: omap2plus_defconfig: Enable PINCTRL_TI_IODELAY
In reply to Kishon Vijay Abraham IEnable PINCTRL_TI_IODELAY since it is required for MMC module in DRA7 family of processors to configure "IODelay" values depending on the enumerated MMC modes.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
--- arch/arm/configs/omap2plus_defconfig | 1 + 1 file changed, 1 insertion(+)
arch/arm/configs/omap2plus_defconfig +1 -0
@@ -246,6 +246,7 @@ CONFIG_HSI=m CONFIG_OMAP_SSI=m CONFIG_SSI_PROTOCOL=m CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_TI_IODELAY=y CONFIG_DEBUG_GPIO=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_PCA953X=m
Signature · 1 line
2.11.0
PATCH 40/41 ARM: multi_v7_defconfig: Enable PINCTRL_TI_IODELAY
In reply to Kishon Vijay Abraham IEnable PINCTRL_TI_IODELAY since it is required for MMC module in DRA7 family of processors to configure "IODelay" values depending on the enumerated MMC modes.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
--- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+)
arch/arm/configs/multi_v7_defconfig +1 -0
@@ -412,6 +412,7 @@ CONFIG_PINCTRL_MSM8X74=y CONFIG_PINCTRL_MSM8916=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y CONFIG_PINCTRL_QCOM_SSBI_PMIC=y +CONFIG_PINCTRL_TI_IODELAY=y CONFIG_GPIO_GENERIC_PLATFORM=y CONFIG_GPIO_DAVINCI=y CONFIG_GPIO_DWAPB=y
Signature · 1 line
2.11.0
PATCH 41/41 Documentation: ARM: Document new dependencies for MMC on DRA7
In reply to Kishon Vijay Abraham IMMC on DRA7 SoCs require different IO Delay values to be configured depending on the MMC mode. In order to confgiure these IO Delay values CONFIG_PINCTRL_TI_IODELAY must be enabled. Document this dependency here so that it can be added by anyone using custom .config.
Signed-off-by Kishon Vijay Abraham I <[email protected]>
--- Documentation/arm/OMAP/README | 4 ++++ 1 file changed, 4 insertions(+)
Documentation/arm/OMAP/README +4 -0
@@ -5,3 +5,7 @@ KERNEL NEW DEPENDENCIES v4.3+ Update is needed for custom .config files to make sure CONFIG_REGULATOR_PBIAS is enabled for MMC1 to work properly. + +v4.13+ Update is needed for custom .config files to make sure + CONFIG_PINCTRL_TI_IODELAY is enabled for all MMC instances + to work properly in DRA7 based boards.
Signature · 1 line
2.11.0
Tony Lindgren
maintainerHi,
Quoted 3 lines · Kishon Vijay Abraham I
This series adds UHS, HS200, DDR mode and ADMA support to
omap_hsmmcdriver used to improve the throughput of MMC/SD in dra7 SoCs.
Certainly seems way less intrusive than earlier before the dmaengine changes :)
Quoted 1 line
*) tuning ratio of MMC in dra7 is different from sdhci
Hmm what's the tuning ratio?
Quoted 3 lines
This series has been tested on beagleboard, pandaboard, beaglebone-black, beaglebone, am335x-evm, am437x-evm, dra7xx-evm, dra72x-evm, am571x-idk and am572x-idk.
I gave this a quick try after manally applying next-20170519 after reverting 67d0687224a9 ("mm: drop HASH_ADAPT"). Looks like something is missing as I got:
arch/arm/mach-omap2/pdata-quirks.c:445:23: error:
'struct omap_hsmmc_platform_data' has no member named 'version'
...
It's possible I messed up something while manually applying.
Quoted 2 lines
I can split the series to go into Ulf Hansson's tree and Tony's tree separately if that is required.
Yes please. Maybe send the dts parts first that are ready to get merged, like the fixes and all the iodelay configuration.
Then the mmc driver changes as a separate set.
Then third set to follow-up and enable things once the mmc driver changes are merged.
Regards,
Tony
Hi,
Quoted 7 lines · Tony Lindgren
Hi,
Quoted 3 lines · Kishon Vijay Abraham I
This series adds UHS, HS200, DDR mode and ADMA support to
omap_hsmmcdriver used to improve the throughput of MMC/SD in dra7 SoCs.
Quoted 6 lines
Certainly seems way less intrusive than earlier before the dmaengine changes :)
Quoted 1 line
*) tuning ratio of MMC in dra7 is different from sdhci
Hmm what's the tuning ratio?
For high speed modes like UHS SDR104 and HS200, sampling clock has to adjusted according to the position of the data window and it varies depending on the host and the card.
For this we configure the controller with phase delay from 0 to 0x7c (in steps of 4) and send the tuning command (CMD19 or CMD21) for which the card responds with a known pattern. We keep track of the phase delay's for which we received the known patterns (without errors) and select one of the phase delays (3/4th ratio from largest consecutive successful phase delay window).
sdhci driver makes use of the HW feature for tuning (no manual setting of phase delays etc). Sdhci has an ops for platform specific tuning but that again has to be implemented in omap_hsmmc driver.
Quoted 9 lines
Quoted 4 lines
This series has been tested on beagleboard, pandaboard, beaglebone-black, beaglebone, am335x-evm, am437x-evm, dra7xx-evm, dra72x-evm, am571x-idk and am572x-idk.
I gave this a quick try after manally applying next-20170519 after reverting
67d0687224a9("mm: dropHASH_ADAPT"). Looks like something is missing as I got:
Quoted 5 lines
arch/arm/mach-omap2/pdata-quirks.c:445:23: error:
'structomap_hsmmc_platform_data' has no member named 'version'
...It's possible I messed up something while manually applying.
[PATCH 13/41] mmc: host: omap_hsmmc: Add support to set IODELAY values adds version member to 'struct omap_hsmmc_platform_data'.
Quoted 11 lines
Quoted 3 lines
I can split the series to go into Ulf Hansson's tree and Tony's tree separately if that is required.
Yes please. Maybe send the dts parts first that are ready to get merged, like the fixes and all the iodelay configuration.
Then the mmc driver changes as a separate set.
Then third set to follow-up and enable things once the mmc driver changes are merged.
Sure.
Thanks
Kishon