Fix Skylake PEBS data source for perf
Subsystems (2)
Fix data source reporting for Skylake and Skylake Server. The encodings have changed to express support for L4 and persistent memory.
The first patch is a (independent) cleanup.
The second is for the kernel and the third for perf/tools. The kernel part and perf tools will compile independently.
v1:
Initial post
v2:
Merged some patches.
Change encoding to use special bit for each combination instead of modifiers.
v3:
Switch to new generic lvlnum indication
PATCH v3 1/4 perf/x86: Move Nehalem PEBS code to flag
From: Andi Kleen <[email protected]>
Minor cleanup: use an explicit x86_pmu flag to handle the missing Lock / TLB information on Nehalem, instead of always checking the model number for each PEBS sample.
--- arch/x86/events/intel/core.c | 1 + arch/x86/events/intel/ds.c | 5 +---- arch/x86/events/perf_event.h | 3 ++- 3 files changed, 4 insertions(+), 5 deletions(-)
arch/x86/events/intel/core.c +1 -0
@@ -3775,6 +3775,7 @@ __init int intel_pmu_init(void)intel_pmu_pebs_data_source_nhm ();x86_add_quirk (intel_nehalem_quirk); + x86_pmu.pebs_no_tlb =1 ;pr_cont ("Nehalem events, " );break ;
arch/x86/events/intel/ds.c +1 -4
@@ -149,8 +149,6 @@ static u64 load_latency_data(u64 status) {union intel_x86_pebs_dse dse;u64 val; -int model = boot_cpu_data.x86_model; -int fam = boot_cpu_data.x86; dse.val = status;
@@ -162,8 +160,7 @@ static u64 load_latency_data(u64 status)/* * Nehalem models do not support TLB, Lock infos */ -if (fam ==0x6 && (model ==26 || model ==30 - || model ==31 || model ==46 )) { +if (x86_pmu.pebs_no_tlb) { val |=P (TLB ,NA ) |P (LOCK ,NA );return val; }
arch/x86/events/perf_event.h +2 -1
@@ -591,7 +591,8 @@ struct x86_pmu { pebs :1, pebs_active :1, pebs_broken :1, - pebs_prec_dist :1; + pebs_prec_dist :1, + pebs_no_tlb :1;int pebs_record_size;int pebs_buffer_size;void (*drain_pebs)(struct pt_regs *regs);
Signature · 1 line
2.9.4
PATCH v3 2/4 perf/x86: Fix data source decoding for Skylake
In reply to Andi KleenFrom: Andi Kleen <[email protected]>
Skylake changed the encoding of the PEBS data source field. Some combinations are not available anymore, but some new cases e.g. for L4 cache hit are added.
Fix up the conversion table for Skylake, similar as had been done for Nehalem.
On Skylake server the encoding for L4 actually means persistent memory. Handle this case too.
To properly describe it in the abstracted perf format I had to add some new fields. Since a hit can have only one level add a new field that is an enumeration, not a bit field to describe the level. It can describe any level. Some numbers are also used to describe PMEM and LFB.
Also add a new generic remote flag that can be combined with the generic level to signify a remote cache.
And there is an extension field for the snoop indication to handle the Forward state.
I didn't add a generic flag for hops because it's not needed for Skylake.
I changed the existing encodings for older CPUs to also fill in the new level and remote fields.
v2: Merge with persistent memory patch.
Add explicit bit for each case instead of using generic modifier.
v3: Rework with new lvlnum and remote fields.
Change older CPUs to report the new fields too.
--- arch/x86/events/intel/core.c | 2 ++ arch/x86/events/intel/ds.c | 51 ++++++++++++++++++++++++++--------------- arch/x86/events/perf_event.h | 2 ++ include/uapi/linux/perf_event.h | 30 ++++++++++++++++++++++-- 4 files changed, 64 insertions(+), 21 deletions(-)
arch/x86/events/intel/core.c +2 -0
@@ -4052,6 +4052,8 @@ __init int intel_pmu_init(void) skl_format_attr);WARN_ON (!x86_pmu.format_attrs); x86_pmu.cpu_events = hsw_events_attrs; +intel_pmu_pebs_data_source_skl ( + boot_cpu_data.x86_model ==INTEL_FAM6_SKYLAKE_X );pr_cont ("Skylake events, " );break ;
arch/x86/events/intel/ds.c +32 -19
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arch/x86/events/perf_event.h +2 -0
@@ -946,6 +946,8 @@ void intel_pmu_lbr_init_knl(void);void intel_pmu_pebs_data_source_nhm (void ); +void intel_pmu_pebs_data_source_skl (bool pmem); +int intel_pmu_setup_lbr_filter (struct perf_event *event);void intel_pt_interrupt (void );
include/uapi/linux/perf_event.h +28 -2
@@ -931,14 +931,20 @@ union perf_mem_data_src { mem_snoop:5, /* snoop mode */ mem_lock:2, /* lock instr */ mem_dtlb:7, /* tlb access */ - mem_rsvd:31; + mem_lvl_num:4, /* memory hierarchy level number */ + mem_remote:1, /* remote */ + mem_snoopx:2, /* snoop mode, ext */ + mem_rsvd:24; }; };#elif defined(__BIG_ENDIAN_BITFIELD)union perf_mem_data_src {__u64 val;struct { -__u64 mem_rsvd:31 , +__u64 mem_rsvd:24 , + mem_snoopx:2 ,/* snoop mode, ext */ + mem_remote:1 ,/* remote */ + mem_lvl_num:4 ,/* memory hierarchy level number */ mem_dtlb:7 ,/* tlb access */ mem_lock:2 ,/* lock instr */ mem_snoop:5, /* snoop mode */
@@ -975,6 +981,22 @@ union perf_mem_data_src {#define PERF_MEM_LVL_UNC 0x2000/* Uncached memory */ #define PERF_MEM_LVL_SHIFT 5 +#define PERF_MEM_REMOTE_REMOTE 0x01/* Remote */ +#define PERF_MEM_REMOTE_SHIFT 37 + +#define PERF_MEM_LVLNUM_L1 0x01/* L1 */ +#define PERF_MEM_LVLNUM_L2 0x02/* L2 */ +#define PERF_MEM_LVLNUM_L3 0x03/* L3 */ +#define PERF_MEM_LVLNUM_L4 0x04/* L4 */ +/* 5-0xa available */ +#define PERF_MEM_LVLNUM_ANY_CACHE 0x0b/* Any cache */ +#define PERF_MEM_LVLNUM_LFB 0x0c/* LFB */ +#define PERF_MEM_LVLNUM_RAM 0x0d/* RAM */ +#define PERF_MEM_LVLNUM_PMEM 0x0e/* PMEM */ +#define PERF_MEM_LVLNUM_NA 0x0f/* N/A */ + +#define PERF_MEM_LVLNUM_SHIFT 33 +/* snoop mode */ #define PERF_MEM_SNOOP_NA 0x01/* not available */ #define PERF_MEM_SNOOP_NONE 0x02/* no snoop */
@@ -983,6 +1005,10 @@ union perf_mem_data_src {#define PERF_MEM_SNOOP_HITM 0x10/* snoop hit modified */ #define PERF_MEM_SNOOP_SHIFT 19 +#define PERF_MEM_SNOOPX_FWD 0x01/* forward */ +/* 1 free */ +#define PERF_MEM_SNOOPX_SHIFT 37 +/* locked instruction */ #define PERF_MEM_LOCK_NA 0x01/* not available */ #define PERF_MEM_LOCK_LOCKED 0x02/* locked transaction */
Signature · 1 line
2.9.4
PATCH v3 3/4 perf, tools: Add support for printing new mem_info encodings
In reply to Andi KleenFrom: Andi Kleen <[email protected]>
Add decoding for the new lvlx and snoopx field meminfo field added earlier to the kernel so that "perf mem report" and other tools can print it properly.
v2: Merge with persistent memory patch.
Switch to new bit encoding for each combination.
v3: Switch to generic lvlnum field.
--- tools/include/uapi/linux/perf_event.h | 30 ++++++++++++++++++++++-- tools/perf/util/mem-events.c | 43 ++++++++++++++++++++++++++++++++--- 2 files changed, 68 insertions(+), 5 deletions(-)
tools/include/uapi/linux/perf_event.h +28 -2
@@ -931,14 +931,20 @@ union perf_mem_data_src { mem_snoop:5, /* snoop mode */ mem_lock:2, /* lock instr */ mem_dtlb:7, /* tlb access */ - mem_rsvd:31; + mem_lvl_num:4, /* memory hierarchy level number */ + mem_remote:1, /* remote */ + mem_snoopx:2, /* snoop mode, ext */ + mem_rsvd:24; }; };#elif defined(__BIG_ENDIAN_BITFIELD)union perf_mem_data_src {__u64 val;struct { -__u64 mem_rsvd:31 , +__u64 mem_rsvd:24 , + mem_snoopx:2 ,/* snoop mode, ext */ + mem_remote:1 ,/* remote */ + mem_lvl_num:4 ,/* memory hierarchy level number */ mem_dtlb:7 ,/* tlb access */ mem_lock:2 ,/* lock instr */ mem_snoop:5, /* snoop mode */
@@ -975,6 +981,22 @@ union perf_mem_data_src {#define PERF_MEM_LVL_UNC 0x2000/* Uncached memory */ #define PERF_MEM_LVL_SHIFT 5 +#define PERF_MEM_REMOTE_REMOTE 0x01/* Remote */ +#define PERF_MEM_REMOTE_SHIFT 37 + +#define PERF_MEM_LVLNUM_L1 0x01/* L1 */ +#define PERF_MEM_LVLNUM_L2 0x02/* L2 */ +#define PERF_MEM_LVLNUM_L3 0x03/* L3 */ +#define PERF_MEM_LVLNUM_L4 0x04/* L4 */ +/* 5-0xa available */ +#define PERF_MEM_LVLNUM_ANY_CACHE 0x0b/* Any cache */ +#define PERF_MEM_LVLNUM_LFB 0x0c/* LFB */ +#define PERF_MEM_LVLNUM_RAM 0x0d/* RAM */ +#define PERF_MEM_LVLNUM_PMEM 0x0e/* PMEM */ +#define PERF_MEM_LVLNUM_NA 0x0f/* N/A */ + +#define PERF_MEM_LVLNUM_SHIFT 33 +/* snoop mode */ #define PERF_MEM_SNOOP_NA 0x01/* not available */ #define PERF_MEM_SNOOP_NONE 0x02/* no snoop */
@@ -983,6 +1005,10 @@ union perf_mem_data_src {#define PERF_MEM_SNOOP_HITM 0x10/* snoop hit modified */ #define PERF_MEM_SNOOP_SHIFT 19 +#define PERF_MEM_SNOOPX_FWD 0x01/* forward */ +/* 1 free */ +#define PERF_MEM_SNOOPX_SHIFT 37 +/* locked instruction */ #define PERF_MEM_LOCK_NA 0x01/* not available */ #define PERF_MEM_LOCK_LOCKED 0x02/* locked transaction */
tools/perf/util/mem-events.c +40 -3
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Signature · 1 line
2.9.4
PATCH v3 4/4 perf, tools: Add test cases for new data source encoding
In reply to Andi KleenFrom: Andi Kleen <[email protected]>
Add some simple tests to perf test to test data source printing.
v2: Make the tests actually checked for the correct name of Forward
v3: Adjust to new encoding
--- tools/perf/tests/Build | 1 + tools/perf/tests/builtin-test.c | 4 ++++ tools/perf/tests/mem.c | 53 +++++++++++++++++++++++++++++++++++++++++ tools/perf/tests/tests.h | 1 + 4 files changed, 59 insertions(+) create mode 100644 tools/perf/tests/mem.c
tools/perf/tests/Build +1 -0
@@ -34,6 +34,7 @@ perf-y += thread-map.o perf-y += llvm.o llvm-src-base.o llvm-src-kbuild.o llvm-src-prologue.o llvm-src-relocation.o perf-y += bpf.o perf-y += topology.o +perf-y += mem.o perf-y += cpumap.o perf-y += stat.o perf-y += event_update.o
tools/perf/tests/builtin-test.c +4 -0
@@ -43,6 +43,10 @@ static struct test generic_tests[] = { .func = test__basic_mmap, }, { + .desc = "Test data source output", + .func = test__mem, + }, + { .desc = "Parse event definition strings", .func = test__parse_events, },
tools/perf/tests/mem.c new file +53 -0
53 lines not on this page · raw message
tools/perf/tests/tests.h +1 -0
@@ -57,6 +57,7 @@ int test__python_use(int subtest);int test__bp_signal (int subtest);int test__bp_signal_overflow (int subtest);int test__task_exit (int subtest); +int test__mem (int subtest);int test__sw_clock_freq (int subtest);int test__code_reading (int subtest);int test__sample_parsing (int subtest);
Signature · 1 line
2.9.4