target/s390x: implement MVCOS and allow to enable it
cover target/s390x: implement MVCOS and allow to enable it
This will not change the qemu model, we simply allow to enable the facility for the qemu model.
A current upstream kernel (compiled for e.g. z900) can be tricked into using MVCOS for uaccess by simply enabling the facility. This will work even though the kernel is not compiled with z10+ support, as this facility is also detected and used dynamically.
qemu-system-s390x ... -cpu qemu,mvcos=on ...
This might not be the fastest implementation, but it seems to work and that is what we care about for now.
Requires my PGM fix series:
https://lists.nongnu.org/archive/html/qemu-devel/2017-06/msg02631.html
Based on an original patch by Miroslav Benes
David Hildenbrand (3):
target/s390x: change PSW_SHIFT_KEY target/s390x: implement mvcos instruction s390x/cpumodel: allow to enable MVCOS for qemu cpu model
target/s390x/cpu.h | 21 ++++++++- target/s390x/cpu_models.c | 1 + target/s390x/helper.c | 4 +- target/s390x/helper.h | 1 + target/s390x/insn-data.def | 2 + target/s390x/mem_helper.c | 107 +++++++++++++++++++++++++++++++++++++++++++++ target/s390x/translate.c | 12 ++++- 7 files changed, 143 insertions(+), 5 deletions(-)
Signature · 1 line
2.9.3
PATCH 1/3 target/s390x: change PSW_SHIFT_KEY
Such shifts are usually used to easily extract the PSW KEY from the PSW mask, so let's avoid the confisuing offset of 4.
--- target/s390x/cpu.h | 2 +- target/s390x/translate.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
target/s390x/cpu.h +1 -1
@@ -315,7 +315,7 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);#define PSW_MASK_IO 0x0200000000000000ULL#define PSW_MASK_EXT 0x0100000000000000ULL#define PSW_MASK_KEY 0x00F0000000000000ULL -#define PSW_SHIFT_KEY 56 +#define PSW_SHIFT_KEY 52#define PSW_MASK_MCHECK 0x0004000000000000ULL#define PSW_MASK_WAIT 0x0002000000000000ULL#define PSW_MASK_PSTATE 0x0001000000000000ULL
target/s390x/translate.c +1 -1
@@ -3780,7 +3780,7 @@ static ExitStatus op_spka(DisasContext *s, DisasOps *o) {check_privileged (s);tcg_gen_shri_i64 (o->in2, o->in2,4 ); -tcg_gen_deposit_i64 (psw_mask, psw_mask, o->in2,PSW_SHIFT_KEY -4 ,4 ); +tcg_gen_deposit_i64 (psw_mask, psw_mask, o->in2,PSW_SHIFT_KEY ,4 );return NO_EXIT ; }
Signature · 1 line
2.9.3
Re: [Qemu-devel] [PATCH v1 1/3] target/s390x: change PSW_SHIFT_KEY
Quoted 2 lines · David Hildenbrand
Such shifts are usually used to easily extract the PSW KEY from the PSW mask, so let's avoid the confisuing offset of 4.
s/confisuing/confusing/
Quoted 24 lines
Signed-off-by David Hildenbrand <[email protected]>--- target/s390x/cpu.h | 2 +- target/s390x/translate.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)target/s390x/cpu.h +1
-1@@ -315,7 +315,7 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);#define PSW_MASK_IO 0x0200000000000000ULL#define PSW_MASK_EXT 0x0100000000000000ULL#define PSW_MASK_KEY 0x00F0000000000000ULL -#define PSW_SHIFT_KEY 56 +#define PSW_SHIFT_KEY 52#define PSW_MASK_MCHECK 0x0004000000000000ULL#define PSW_MASK_WAIT 0x0002000000000000ULL#define PSW_MASK_PSTATE 0x0001000000000000ULLtarget/s390x/translate.c +0
-0
target/s390x/translate.c static ExitStatus op_spka(DisasContext *s, DisasOps *o) · line 3785
Quoted 7 lines
target/s390x/translate.c +1
-1@@ -3780,7 +3780,7 @@ static ExitStatus op_spka(DisasContext *s, DisasOps *o) {check_privileged (s);tcg_gen_shri_i64 (o->in2, o->in2,4 ); -tcg_gen_deposit_i64 (psw_mask, psw_mask, o->in2,PSW_SHIFT_KEY -4 ,4 ); +tcg_gen_deposit_i64 (psw_mask, psw_mask, o->in2,PSW_SHIFT_KEY ,4 );return NO_EXIT ; }
PATCH 2/3 target/s390x: implement mvcos instruction
In reply to David HildenbrandThis adds support for the MOVE WITH OPTIONAL SPECIFICATIONS (MVCOS) instruction (in a relatively slow way). But it is enough to boot a linux kernel that uses it for uacccess (primary <-> seconardy).
We are missing (as for most other part) low address protection checks, PSW key / storage key checks and support for AR-mode.
We fake an ADDRESSING exception when called from problem state (which seems to rely on PSW key checks to be in place) and if AR-mode is used.
This patch is based on an original patch by Miroslav Benes (thanks!).
--- target/s390x/cpu.h | 19 ++++++++- target/s390x/helper.c | 4 +- target/s390x/helper.h | 1 + target/s390x/insn-data.def | 2 + target/s390x/mem_helper.c | 104 +++++++++++++++++++++++++++++++++++++++++++++ target/s390x/translate.c | 10 +++++ 6 files changed, 137 insertions(+), 3 deletions(-)
target/s390x/cpu.h +18 -1
@@ -304,6 +304,7 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);#undef PSW_MASK_WAIT#undef PSW_MASK_PSTATE#undef PSW_MASK_ASC +#undef PSW_SHIFT_ASC#undef PSW_MASK_CC#undef PSW_MASK_PM#undef PSW_MASK_64
@@ -320,6 +321,7 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);#define PSW_MASK_WAIT 0x0002000000000000ULL#define PSW_MASK_PSTATE 0x0001000000000000ULL#define PSW_MASK_ASC 0x0000C00000000000ULL +#define PSW_SHIFT_ASC 46#define PSW_MASK_CC 0x0000300000000000ULL#define PSW_MASK_PM 0x00000F0000000000ULL#define PSW_MASK_64 0x0000000100000000ULL
@@ -353,15 +355,30 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);#define FLAG_MASK_32 0x00001000/* Control register 0 bits */ +#define CR0_SECONDARY 0x0000002000000000ULL#define CR0_LOWPROT 0x0000000010000000ULL#define CR0_EDAT 0x0000000000800000ULL +/* Control register 3 bits */ +#define CR3_PKM 0x00000000ffff0000ULL +/* MMU */ #define MMU_PRIMARY_IDX 0#define MMU_SECONDARY_IDX 1#define MMU_HOME_IDX 2 -static inline int cpu_mmu_index (CPUS390XState *env,bool ifetch) +static inline bool psw_key_valid (CPUS390XState *env,uint8_t psw_key) +{ +uint16_t pkm = ((env->cregs[3 ] &CR3_PKM ) >>16 ); + +if (env->psw.mask &PSW_MASK_PSTATE ) { +/* PSW key has range 0..15, it is valid if the bit is 1 in the PKM */ +return pkm & (1 << (psw_key &0xff )); + } +return true; +} + +static inline int cpu_mmu_index (CPUS390XState *env,bool ifetch) {switch (env->psw.mask &PSW_MASK_ASC ) {case PSW_ASC_PRIMARY :
target/s390x/helper.c +2 -2
@@ -749,8 +749,8 @@ void s390x_cpu_debug_excp_handler(CPUState *cs) }/* Unaligned accesses are only diagnosed with MO_ALIGN. At the moment, -this is only for the atomic operations, for which we want to raise a -specification exception. */ +this is only for operations, for which we want to raise a specification +exception. */ void s390x_cpu_do_unaligned_access (CPUState *cs,vaddr addr,MMUAccessType access_type,int mmu_idx,uintptr_t retaddr)
target/s390x/helper.h +1 -0
@@ -126,6 +126,7 @@ DEF_HELPER_FLAGS_2(tprot, TCG_CALL_NO_RWG, i32, i64, i64) DEF_HELPER_FLAGS_2(iske, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_3(sske, TCG_CALL_NO_RWG, void, env, i64, i64) DEF_HELPER_FLAGS_2(rrbe, TCG_CALL_NO_RWG, i32, env, i64) +DEF_HELPER_4(mvcos, i32, env, i64, i64, i64) DEF_HELPER_4(mvcs, i32, env, i64, i64, i64) DEF_HELPER_4(mvcp, i32, env, i64, i64, i64)DEF_HELPER_4 (sigp, i32, env, i64, i32, i64)
target/s390x/insn-data.def +2 -0
@@ -918,6 +918,8 @@ /* LOAD USING REAL ADDRESS */ C(0xb24b, LURA, RRE, Z, 0, r2, new, r1_32, lura, 0) C(0xb905, LURAG, RRE, Z, 0, r2, r1, 0, lurag, 0) +/* MOVE WITH OPTIONAL SPECIFICATION */ + C(0xc800, MVCOS, SSF, MVCOS, la1, a2, 0, 0, mvcos, 0) /* MOVE TO PRIMARY */ C(0xda00, MVCP, SS_d, Z, la1, a2, 0, 0, mvcp, 0) /* MOVE TO SECONDARY */
target/s390x/mem_helper.c +104 -0
110 lines not on this page · raw message
target/s390x/translate.c +10 -0
@@ -1202,6 +1202,7 @@ typedef enum DisasFacility {FAC_SCF ,/* store clock fast */ FAC_SFLE ,/* store facility list extended */ FAC_ILA ,/* interlocked access facility 1 */ +FAC_MVCOS ,/* move-with-optional-specification */ FAC_LPP ,/* load-program-parameter */ FAC_DAT_ENH ,/* DAT-enhancement */ FAC_E2, /* extended-translation facility 2 */
@@ -3069,6 +3070,15 @@ static ExitStatus op_mvclu(DisasContext *s, DisasOps *o) }#ifndef CONFIG_USER_ONLY +static ExitStatus op_mvcos (DisasContext *s,DisasOps *o) +{ +int r3 =get_field (s->fields, r3); +potential_page_fault (s); +gen_helper_mvcos (cc_op, cpu_env, o->addr1, o->in2, regs[r3]); +set_cc_static (s); +return NO_EXIT ; +} +static ExitStatus op_mvcp (DisasContext *s,DisasOps *o) {int r1 =get_field (s->fields, l1);
Signature · 1 line
2.9.3
Re: [Qemu-devel] [PATCH v1 2/3] target/s390x: implement mvcos instruction
target/s390x/cpu.h void s390x_cpu_debug_excp_handler(CPUState *cs); · line 376
Quoted 7 lines · David Hildenbrand
target/s390x/cpu.h +7
-0+static inline bool psw_key_valid (CPUS390XState *env,uint8_t psw_key) +{ +uint16_t pkm = ((env->cregs[3 ] &CR3_PKM ) >>16 ); + +if (env->psw.mask &PSW_MASK_PSTATE ) { +/* PSW key has range 0..15, it is valid if the bit is 1 in the PKM */ +return pkm & (1 << (psw_key &0xff ));
Did you intend to write & 0xf? Otherwise this mask is pointless...
Quoted 12 lines
target/s390x/mem_helper.c +12
-0+switch (src_as) { +case 0x0 : + x =cpu_ldub_primary_ra (env, src, ra); +break ; +case 0x2 : + x =cpu_ldub_secondary_ra (env, src, ra); +break ; +case 0x3 : + x =cpu_ldub_home_ra (env, src, ra); +break ; + } +switch (dest_as) {
target/s390x/mem_helper.c uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2) · line 1594
Quoted 10 lines
target/s390x/mem_helper.c +10
-0+case 0x0 : +cpu_stb_primary_ra (env, dest, x, ra); +break ; +case 0x2 : +cpu_stb_secondary_ra (env, dest, x, ra); +break ; +case 0x3 : +cpu_stb_home_ra (env, dest, x, ra); +break ; + }
Rather than these switches, you can use helper_ret_ldub_mmu. Of course, that will only work for SOFTMMU. But for CONFIG_USER_ONLY, there's surely only one address space that's legal, so you could simply forward to fast_memmove.
target/s390x/mem_helper.c uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2) · line 1513
Quoted 3 lines
target/s390x/mem_helper.c +3
-0+if (!(env->psw.mask &PSW_MASK_DAT )) { +program_interrupt (env,PGM_SPECIAL_OP ,6 ); + }
You should use restore_program_state before program_interrupt (or add a new entry-point to do both). Then you can drop ...
target/s390x/translate.c static ExitStatus op_mvclu(DisasContext *s, DisasOps *o) · line 3077
Quoted 2 lines
target/s390x/translate.c +2
-0+potential_page_fault (s); +gen_helper_mvcos (cc_op, cpu_env, o->addr1, o->in2, regs[r3]);
... the potential_page_fault.
r~
Re: [Qemu-devel] [PATCH v1 2/3] target/s390x: implement mvcos instruction
Quoted 10 lines · Richard Henderson
target/s390x/cpu.h void s390x_cpu_debug_excp_handler(CPUState *cs); · line 376
Quoted 7 lines · David Hildenbrand
target/s390x/cpu.h +7
-0+static inline bool psw_key_valid (CPUS390XState *env,uint8_t psw_key) +{ +uint16_t pkm = ((env->cregs[3 ] &CR3_PKM ) >>16 ); + +if (env->psw.mask &PSW_MASK_PSTATE ) { +/* PSW key has range 0..15, it is valid if the bit is 1 in the PKM */ +return pkm & (1 << (psw_key &0xff ));Did you intend to write &
0xf? Otherwise this mask is pointless...
Yes, we will always get only 4 bits set ... but I don't want any compiler to complain about the shift. So 0xf it is. Thanks!
Quoted 25 lines
Quoted 14 lines
target/s390x/mem_helper.c +12
-0+switch (src_as) { +case 0x0 : + x =cpu_ldub_primary_ra (env, src, ra); +break ; +case 0x2 : + x =cpu_ldub_secondary_ra (env, src, ra); +break ; +case 0x3 : + x =cpu_ldub_home_ra (env, src, ra); +break ; + } +switch (dest_as) {target/s390x/mem_helper.c uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2) · line 1594
Quoted 10 lines
target/s390x/mem_helper.c +10
-0+case 0x0 : +cpu_stb_primary_ra (env, dest, x, ra); +break ; +case 0x2 : +cpu_stb_secondary_ra (env, dest, x, ra); +break ; +case 0x3 : +cpu_stb_home_ra (env, dest, x, ra); +break ; + }
Quoted 3 lines
Rather than these switches, you can use
helper_ret_ldub_mmu. Of course, that will only work for SOFTMMU. But forCONFIG_USER_ONLY, there's surely only one address space that's legal, so you could simply forward tofast_memmove.
That sounds like a good idea. I will look into it. This would then allow to expose the facility also for CONFIG_USER_ONLY.
Quoted 7 lines
target/s390x/mem_helper.c uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2) · line 1513
Quoted 4 lines
target/s390x/mem_helper.c +3
-0+if (!(env->psw.mask &PSW_MASK_DAT )) { +program_interrupt (env,PGM_SPECIAL_OP ,6 ); + }You should use
restore_program_statebeforeprogram_interrupt(or add a new entry-point to do both). Then you can drop ...
restore_program_state - you mean cpu_restore_state() I assume.
Would it makes sense to
a) move cpu_restore_state() into program_interrupt()
b) make all callers forward ra from GETPC() (problem with kvm code that share handlers?)
c) fixup callers that already do the cpu_restore_state()
c) drop potential_page_fault() completely
Two questions:
a) Could we avoid having to forward the ra by doing GETPC directly in program_interrupt()? In mem_helper, I can see that we do GETPC on several places and pass it around, so I assume GETPC() has to be called in the first handler?
b) With cpu_restore_state(), there is no need for update_psw_addr() + update_cc_op(), correct?
Any other nice solution for cleaning potential_page_fault() up?
Quoted 5 lines
target/s390x/translate.c static ExitStatus op_mvclu(DisasContext *s, DisasOps *o) · line 3077
Quoted 3 lines
target/s390x/translate.c +2
-0+potential_page_fault (s); +gen_helper_mvcos (cc_op, cpu_env, o->addr1, o->in2, regs[r3]);... the
potential_page_fault.
I would suggest to leave it in this patch as it and then clean it up all together in one shot (adding 5 cpu_restore_state() vs. one potential_page_fault() temporarily looks better to me).
Quoted 4 lines
r~
Signature · 3 lines
Thanks, David
Re: [Qemu-devel] [PATCH v1 2/3] target/s390x: implement mvcos instruction
Quoted 8 lines · David Hildenbrand
Quoted 6 lines
target/s390x/mem_helper.c uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2) · line 1513
Quoted 3 lines
target/s390x/mem_helper.c +3
-0+if (!(env->psw.mask &PSW_MASK_DAT )) { +program_interrupt (env,PGM_SPECIAL_OP ,6 ); + }You should use
restore_program_statebeforeprogram_interrupt(or add a new entry-point to do both). Then you can drop ...
restore_program_state- you meancpu_restore_state()I assume.
Yes, sorry.
Quoted 7 lines
Would it makes sense to
a) move
cpu_restore_state()intoprogram_interrupt()
b) make all callers forward ra fromGETPC()(problem with kvm code that share handlers?)
c) fixup callers that already do thecpu_restore_state()
d) droppotential_page_fault()completely
Yes, that makes sense. For B, kvm can pass 0 for RA and nothing will happen. For C, that project is on-going but not complete; D is indeed the ultimate goal.
Quoted 5 lines
Two questions:
a) Could we avoid having to forward the ra by doing GETPC directly inprogram_interrupt()? Inmem_helper, I can see that we do GETPC on several places and pass it around, so I assumeGETPC()has to be called in the first handler?
You must use GETPC in the first handler. We're looking for the address of the TCG generated code from where we were called. So, no, you can't use GETPC from program_interrupt.
Quoted 2 lines
b) With
cpu_restore_state(), there is no need forupdate_psw_addr()+update_cc_op(), correct?
Correct.
Quoted 8 lines
Quoted 4 lines
target/s390x/translate.c static ExitStatus op_mvclu(DisasContext *s, DisasOps *o) · line 3077
Quoted 2 lines
target/s390x/translate.c +2
-0+potential_page_fault (s); +gen_helper_mvcos (cc_op, cpu_env, o->addr1, o->in2, regs[r3]);... the
potential_page_fault.I would suggest to leave it in this patch as it and then clean it up all together in one shot (adding 5
cpu_restore_state()vs. onepotential_page_fault()temporarily looks better to me).
I would say the opposite, since the code generated by potential_page_fault is always executed, whereas the cpu_restore_state is on an error path which for a well-behaved guest will never be executed.
r~
Re: [Qemu-devel] [PATCH v1 2/3] target/s390x: implement mvcos instruction
Quoted 18 lines
Quoted 8 lines
Would it makes sense to
a) move
cpu_restore_state()intoprogram_interrupt()
b) make all callers forward ra fromGETPC()(problem with kvm code that share handlers?)
c) fixup callers that already do thecpu_restore_state()
d) droppotential_page_fault()completelyYes, that makes sense. For B, kvm can pass 0 for RA and nothing will happen. For C, that project is on-going but not complete; D is indeed the ultimate goal.
Quoted 5 lines
Two questions:
a) Could we avoid having to forward the ra by doing GETPC directly inprogram_interrupt()? Inmem_helper, I can see that we do GETPC on several places and pass it around, so I assumeGETPC()has to be called in the first handler?
Quoted 8 lines
You must use GETPC in the first handler. We're looking for the address of the TCG generated code from where we were called. So, no, you can't use GETPC from
program_interrupt.Quoted 2 lines
b) With
cpu_restore_state(), there is no need forupdate_psw_addr()+update_cc_op(), correct?Correct.
Thanks for the clarification!
Quoted 6 lines
Quoted 6 lines
Quoted 5 lines
target/s390x/translate.c static ExitStatus op_mvclu(DisasContext *s, DisasOps *o) · line 3077
Quoted 3 lines
target/s390x/translate.c +2
-0+potential_page_fault (s); +gen_helper_mvcos (cc_op, cpu_env, o->addr1, o->in2, regs[r3]);... the
potential_page_fault.
Quoted 7 lines
Quoted 3 lines
I would suggest to leave it in this patch as it and then clean it up all together in one shot (adding 5
cpu_restore_state()vs. onepotential_page_fault()temporarily looks better to me).I would say the opposite, since the code generated by
potential_page_faultis always executed, whereas thecpu_restore_stateis on an error path which for a well-behaved guest will never be executed.
By temporary I meant:
I will be looking into cleaning this all up and getting rid of potential_page_fault() soon :)
However, in v2 I avoided potential_page_fault().
Quoted 4 lines
r~
Thanks!
Signature · 3 lines
Thanks, David
Re: [Qemu-devel] [PATCH v1 2/3] target/s390x: implement mvcos instruction
In reply to David HildenbrandQuoted 52 lines · David Hildenbrand
This adds support for the MOVE WITH OPTIONAL SPECIFICATIONS (MVCOS) instruction (in a relatively slow way). But it is enough to boot a linux kernel that uses it for uacccess (primary <-> seconardy).
We are missing (as for most other part) low address protection checks, PSW key / storage key checks and support for AR-mode.
We fake an ADDRESSING exception when called from problem state (which seems to rely on PSW key checks to be in place) and if AR-mode is used.
This patch is based on an original patch by Miroslav Benes (thanks!).
Signed-off-by David Hildenbrand <[email protected]>--- target/s390x/cpu.h | 19 ++++++++- target/s390x/helper.c | 4 +- target/s390x/helper.h | 1 + target/s390x/insn-data.def | 2 + target/s390x/mem_helper.c | 104 +++++++++++++++++++++++++++++++++++++++++++++ target/s390x/translate.c | 10 +++++ 6 files changed, 137 insertions(+), 3 deletions(-)target/s390x/cpu.h +5
-0@@ -304,6 +304,7 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);#undef PSW_MASK_WAIT#undef PSW_MASK_PSTATE#undef PSW_MASK_ASC +#undef PSW_SHIFT_ASC#undef PSW_MASK_CC#undef PSW_MASK_PM#undef PSW_MASK_64@@ -320,6 +321,7 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);#define PSW_MASK_WAIT 0x0002000000000000ULL#define PSW_MASK_PSTATE 0x0001000000000000ULL#define PSW_MASK_ASC 0x0000C00000000000ULL +#define PSW_SHIFT_ASC 46#define PSW_MASK_CC 0x0000300000000000ULL#define PSW_MASK_PM 0x00000F0000000000ULL#define PSW_MASK_64 0x0000000100000000ULL@@ -353,15 +355,30 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);#define FLAG_MASK_32 0x00001000/* Control register 0 bits */ +#define CR0_SECONDARY 0x0000002000000000ULL#define CR0_LOWPROT 0x0000000010000000ULL#define CR0_EDAT 0x0000000000800000ULL +/* Control register 3 bits */ +#define CR3_PKM 0x00000000ffff0000ULL
target/s390x/cpu.h void s390x_cpu_debug_excp_handler(CPUState *cs); · line 372
Quoted 10 lines
target/s390x/cpu.h +4
-1+/* MMU */ #define MMU_PRIMARY_IDX 0#define MMU_SECONDARY_IDX 1#define MMU_HOME_IDX 2 -static inline int cpu_mmu_index (CPUS390XState *env,bool ifetch) +static inline bool psw_key_valid (CPUS390XState *env,uint8_t psw_key) +{ +uint16_t pkm = ((env->cregs[3 ] &CR3_PKM ) >>16 );
Since you're storing the value in an uint16_t anyway, I think you could also do this without the CR3_PKM masking.
target/s390x/cpu.h void s390x_cpu_debug_excp_handler(CPUState *cs); · line 376
Quoted 3 lines
target/s390x/cpu.h +3
-0+if (env->psw.mask &PSW_MASK_PSTATE ) { +/* PSW key has range 0..15, it is valid if the bit is 1 in the PKM */ +return pkm & (1 << (psw_key &0xff ));
As Richard already noted, the "0xff" looks fishy here ... I'd remove it completely - if someone calls this function with a psw_key > 15, they should be punished by a "false" as return value anyway.
Also, not sure, but don't you need to use IBM-bit-numbering here? i.e. rather use 0x80 >> psw_key instead?
Quoted 13 lines
target/s390x/cpu.h +5
-0+ } +return true; +} + +static inline int cpu_mmu_index (CPUS390XState *env,bool ifetch) {switch (env->psw.mask &PSW_MASK_ASC ) {case PSW_ASC_PRIMARY :target/s390x/helper.c +0
-0
target/s390x/helper.c void s390x_cpu_debug_excp_handler(CPUState *cs) · line 753
Quoted 7 lines
target/s390x/helper.c +2
-2@@ -749,8 +749,8 @@ void s390x_cpu_debug_excp_handler(CPUState *cs) }/* Unaligned accesses are only diagnosed with MO_ALIGN. At the moment, -this is only for the atomic operations, for which we want to raise a -specification exception. */ +this is only for operations, for which we want to raise a specification +exception. */
Unrelated to this patch?
Quoted 51 lines
target/s390x/helper.c +0
-0void s390x_cpu_do_unaligned_access (CPUState *cs,vaddr addr,MMUAccessType access_type,int mmu_idx,uintptr_t retaddr)target/s390x/helper.h +1
-0@@ -126,6 +126,7 @@ DEF_HELPER_FLAGS_2(tprot, TCG_CALL_NO_RWG, i32, i64, i64) DEF_HELPER_FLAGS_2(iske, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_3(sske, TCG_CALL_NO_RWG, void, env, i64, i64) DEF_HELPER_FLAGS_2(rrbe, TCG_CALL_NO_RWG, i32, env, i64) +DEF_HELPER_4(mvcos, i32, env, i64, i64, i64) DEF_HELPER_4(mvcs, i32, env, i64, i64, i64) DEF_HELPER_4(mvcp, i32, env, i64, i64, i64)DEF_HELPER_4 (sigp, i32, env, i64, i32, i64)target/s390x/insn-data.def +2
-0@@ -918,6 +918,8 @@ /* LOAD USING REAL ADDRESS */ C(0xb24b, LURA, RRE, Z, 0, r2, new, r1_32, lura, 0) C(0xb905, LURAG, RRE, Z, 0, r2, r1, 0, lurag, 0) +/* MOVE WITH OPTIONAL SPECIFICATION */ + C(0xc800, MVCOS, SSF, MVCOS, la1, a2, 0, 0, mvcos, 0) /* MOVE TO PRIMARY */ C(0xda00, MVCP, SS_d, Z, la1, a2, 0, 0, mvcp, 0) /* MOVE TO SECONDARY */target/s390x/mem_helper.c +15
-0@@ -1493,6 +1493,110 @@ uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2)return re >>1 ; } +uint32_t HELPER (mvcos )(CPUS390XState *env,uint64_t dest,uint64_t src, +uint64_t len) +{ +const uint64_t r0 = env->regs[0 ]; +const uint8_t psw_key = (env->psw.mask &PSW_MASK_KEY ) >>PSW_SHIFT_KEY ; +const uint8_t psw_as = (env->psw.mask &PSW_MASK_ASC ) >>PSW_SHIFT_ASC ; +const uintptr_t ra =GETPC (); +uint8_t dest_key, dest_as, dest_k, dest_a; +uint8_t src_key, src_as, src_k, src_a; +uint64_t val; +int cc =0 , i; + +HELPER_LOG ("%s dest %" PRIx64", src %" PRIx64", len %" PRIx64"\n" , + __func__, dest, src, len); +
target/s390x/mem_helper.c uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2) · line 1520
Quoted 10 lines
target/s390x/mem_helper.c +10
-0+if (!(env->psw.mask &PSW_MASK_DAT )) { +program_interrupt (env,PGM_SPECIAL_OP ,6 ); + } + +/* OAC (operand access control) for the first operand -> dest */ + val = (r0 &0xffff0000ULL ) >>16 ; + dest_key = (val >>12 ) &0xf ; + dest_as = (val >>6 ) &0x3 ; + dest_k = (val >>1 ) &0x1 ; + dest_a = (val) &0x1 ;
You could omit the parentheses in the last line.
target/s390x/mem_helper.c uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2) · line 1527
Quoted 6 lines
target/s390x/mem_helper.c +6
-0+/* OAC (operand access control) for the second operand -> src */ + val = (r0 &0x0000ffffULL ); + src_key = (val >>12 ) &0xf ; + src_as = (val >>6 ) &0x3 ; + src_k = (val >>1 ) &0x1 ; + src_a = (val) &0x1 ;
dito.
Quoted 4 lines
target/s390x/mem_helper.c +4
-0+if (!dest_k) { + dest_key = psw_key; + } +if (!src_k) {
target/s390x/mem_helper.c uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2) · line 1542
Quoted 10 lines
target/s390x/mem_helper.c +10
-0+ src_key = psw_key; + } +if (!dest_a) { + dest_as = psw_as; + } +if (!src_a) { + src_as = psw_as; + } + +if (dest_a && dest_as ==0x11 && (env->psw.mask &PSW_MASK_PSTATE )) {
s/0x11/0b11/ ... or better use 3.
target/s390x/mem_helper.c uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2) · line 1546
Quoted 4 lines
target/s390x/mem_helper.c +4
-0+program_interrupt (env,PGM_SPECIAL_OP ,6 ); + } +if (!(env->cregs[0 ] &CR0_SECONDARY ) && + (dest_as ==0x10 || src_as ==0x10 )) {
s/0x10/2/g
target/s390x/mem_helper.c uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2) · line 1553
Quoted 7 lines
target/s390x/mem_helper.c +7
-0+program_interrupt (env,PGM_SPECIAL_OP ,6 ); + } +if (!psw_key_valid (env, dest_key) || !psw_key_valid (env, src_key)) { +program_interrupt (env,PGM_PRIVILEGED ,6 ); + } +/* FIXME: AR-mode and proper problem state mode (using PSW keys) missing */ +if ((src_as | dest_as) ==0x01 || (env->psw.mask &PSW_MASK_PSTATE )) {
Could you also use a qemu_log_mask(LOG_UNIMP, ...) statement here, please?
target/s390x/mem_helper.c uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2) · line 1553
Quoted 2 lines
target/s390x/mem_helper.c +2
-0+program_interrupt (env,PGM_ADDRESSING ,6 ); + }
I think you should also mask the length with 0xffffffff if the PSW was not in 64-bit mode? Or is this done automagically by the generated TCG code already?
Quoted 28 lines
target/s390x/mem_helper.c +28
-0+if (len >4096 ) { + cc =3 ; + len =4096 ; + } + +/* +* FIXME: a) LAP protection +* b) Access using correct PSW keys +* c) AR-mode (mmu support missing) +* d) bulk transfer +*/ +for (i =0 ; i < len; i++, src++, dest++) { +uint8_t x =0 ; + + src =wrap_address (env, src); + dest =wrap_address (env, dest); +switch (src_as) { +case 0x0 : + x =cpu_ldub_primary_ra (env, src, ra); +break ; +case 0x2 : + x =cpu_ldub_secondary_ra (env, src, ra); +break ; +case 0x3 : + x =cpu_ldub_home_ra (env, src, ra); +break ; + } +switch (dest_as) {
target/s390x/mem_helper.c uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2) · line 1594
Quoted 10 lines
target/s390x/mem_helper.c +10
-0+case 0x0 : +cpu_stb_primary_ra (env, dest, x, ra); +break ; +case 0x2 : +cpu_stb_secondary_ra (env, dest, x, ra); +break ; +case 0x3 : +cpu_stb_home_ra (env, dest, x, ra); +break ; + }
I wonder whether we should have some proper #defines for those AS values ... something like:
#define AS_PRIMARY 0 #define AS_ACCREG 1 #define AS_SECONDARY 2 #define AS_HOME 3
?
Thomas
Quoted 5 lines
target/s390x/mem_helper.c +5
-0+ } + +return cc; +} +
Re: [Qemu-devel] [PATCH v1 2/3] target/s390x: implement mvcos instruction
Quoted 8 lines
target/s390x/cpu.h void s390x_cpu_debug_excp_handler(CPUState *cs); · line 372
Quoted 5 lines
target/s390x/cpu.h +3
-1-static inline int cpu_mmu_index (CPUS390XState *env,bool ifetch) +static inline bool psw_key_valid (CPUS390XState *env,uint8_t psw_key) +{ +uint16_t pkm = ((env->cregs[3 ] &CR3_PKM ) >>16 );Since you're storing the value in an
uint16_tanyway, I think you could also do this without theCR3_PKMmasking.
That makes sense.
Quoted 8 lines
target/s390x/cpu.h void s390x_cpu_debug_excp_handler(CPUState *cs); · line 376
Quoted 4 lines
target/s390x/cpu.h +3
-0+if (env->psw.mask &PSW_MASK_PSTATE ) { +/* PSW key has range 0..15, it is valid if the bit is 1 in the PKM */ +return pkm & (1 << (psw_key &0xff ));As Richard already noted, the "
0xff" looks fishy here ... I'd remove it completely - if someone calls this function with apsw_key> 15, they should be punished by a "false" as return value anyway.
I think with the change below, I can drop it.
Quoted 3 lines
Also, not sure, but don't you need to use IBM-bit-numbering here? i.e. rather use
0x80>>psw_keyinstead?
That's a very good point. Yes, I think bit 0 is mapped to bit 32.
Quoted 16 lines
Quoted 16 lines
target/s390x/cpu.h +5
-0+ } +return true; +} + +static inline int cpu_mmu_index (CPUS390XState *env,bool ifetch) {switch (env->psw.mask &PSW_MASK_ASC ) {case PSW_ASC_PRIMARY :target/s390x/helper.c +0
-0@@ -749,8 +749,8 @@ void s390x_cpu_debug_excp_handler(CPUState *cs) }
Quoted 7 lines
target/s390x/helper.c void s390x_cpu_debug_excp_handler(CPUState *cs) · line 753
Quoted 5 lines
target/s390x/helper.c +2
-2/* Unaligned accesses are only diagnosed with MO_ALIGN. At the moment, -this is only for the atomic operations, for which we want to raise a -specification exception. */ +this is only for operations, for which we want to raise a specification +exception. */ Unrelated to this patch?
Uh, I didn't want to include that. Will drop it.
Quoted 56 lines
Quoted 56 lines
target/s390x/helper.c +0
-0void s390x_cpu_do_unaligned_access (CPUState *cs,vaddr addr,MMUAccessType access_type,int mmu_idx,uintptr_t retaddr)target/s390x/helper.h +1
-0@@ -126,6 +126,7 @@ DEF_HELPER_FLAGS_2(tprot, TCG_CALL_NO_RWG, i32, i64, i64) DEF_HELPER_FLAGS_2(iske, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_3(sske, TCG_CALL_NO_RWG, void, env, i64, i64) DEF_HELPER_FLAGS_2(rrbe, TCG_CALL_NO_RWG, i32, env, i64) +DEF_HELPER_4(mvcos, i32, env, i64, i64, i64) DEF_HELPER_4(mvcs, i32, env, i64, i64, i64) DEF_HELPER_4(mvcp, i32, env, i64, i64, i64)DEF_HELPER_4 (sigp, i32, env, i64, i32, i64)target/s390x/insn-data.def +2
-0@@ -918,6 +918,8 @@ /* LOAD USING REAL ADDRESS */ C(0xb24b, LURA, RRE, Z, 0, r2, new, r1_32, lura, 0) C(0xb905, LURAG, RRE, Z, 0, r2, r1, 0, lurag, 0) +/* MOVE WITH OPTIONAL SPECIFICATION */ + C(0xc800, MVCOS, SSF, MVCOS, la1, a2, 0, 0, mvcos, 0) /* MOVE TO PRIMARY */ C(0xda00, MVCP, SS_d, Z, la1, a2, 0, 0, mvcp, 0) /* MOVE TO SECONDARY */target/s390x/mem_helper.c +19
-0@@ -1493,6 +1493,110 @@ uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2)return re >>1 ; } +uint32_t HELPER (mvcos )(CPUS390XState *env,uint64_t dest,uint64_t src, +uint64_t len) +{ +const uint64_t r0 = env->regs[0 ]; +const uint8_t psw_key = (env->psw.mask &PSW_MASK_KEY ) >>PSW_SHIFT_KEY ; +const uint8_t psw_as = (env->psw.mask &PSW_MASK_ASC ) >>PSW_SHIFT_ASC ; +const uintptr_t ra =GETPC (); +uint8_t dest_key, dest_as, dest_k, dest_a; +uint8_t src_key, src_as, src_k, src_a; +uint64_t val; +int cc =0 , i; + +HELPER_LOG ("%s dest %" PRIx64", src %" PRIx64", len %" PRIx64"\n" , + __func__, dest, src, len); + +if (!(env->psw.mask &PSW_MASK_DAT )) { +program_interrupt (env,PGM_SPECIAL_OP ,6 ); + } +
Quoted 8 lines
target/s390x/mem_helper.c uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2) · line 1520
Quoted 6 lines
target/s390x/mem_helper.c +6
-0+/* OAC (operand access control) for the first operand -> dest */ + val = (r0 &0xffff0000ULL ) >>16 ; + dest_key = (val >>12 ) &0xf ; + dest_as = (val >>6 ) &0x3 ; + dest_k = (val >>1 ) &0x1 ; + dest_a = (val) &0x1 ;You could omit the parentheses in the last line.
Yes, will do.
Quoted 25 lines
target/s390x/mem_helper.c uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2) · line 1527
Quoted 7 lines
target/s390x/mem_helper.c +6
-0+/* OAC (operand access control) for the second operand -> src */ + val = (r0 &0x0000ffffULL ); + src_key = (val >>12 ) &0xf ; + src_as = (val >>6 ) &0x3 ; + src_k = (val >>1 ) &0x1 ; + src_a = (val) &0x1 ;dito.
Quoted 4 lines
target/s390x/mem_helper.c +4
-0+if (!dest_k) { + dest_key = psw_key; + } +if (!src_k) {target/s390x/mem_helper.c uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2) · line 1542
Quoted 10 lines
target/s390x/mem_helper.c +10
-0+ src_key = psw_key; + } +if (!dest_a) { + dest_as = psw_as; + } +if (!src_a) { + src_as = psw_as; + } + +if (dest_a && dest_as ==0x11 && (env->psw.mask &PSW_MASK_PSTATE )) {
Quoted 1 line
s/0x11/0b11/ ... or better use 3.
Will use the new defines then!
Quoted 16 lines
target/s390x/mem_helper.c uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2) · line 1546
Quoted 5 lines
target/s390x/mem_helper.c +4
-0+program_interrupt (env,PGM_SPECIAL_OP ,6 ); + } +if (!(env->cregs[0 ] &CR0_SECONDARY ) && + (dest_as ==0x10 || src_as ==0x10 )) {s/0x10/2/g
target/s390x/mem_helper.c uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2) · line 1553
Quoted 7 lines
target/s390x/mem_helper.c +7
-0+program_interrupt (env,PGM_SPECIAL_OP ,6 ); + } +if (!psw_key_valid (env, dest_key) || !psw_key_valid (env, src_key)) { +program_interrupt (env,PGM_PRIVILEGED ,6 ); + } +/* FIXME: AR-mode and proper problem state mode (using PSW keys) missing */ +if ((src_as | dest_as) ==0x01 || (env->psw.mask &PSW_MASK_PSTATE )) {
Quoted 1 line
Could you also use a
qemu_log_mask(LOG_UNIMP, ...)statement here, please?
Good Idea!
Quoted 7 lines
target/s390x/mem_helper.c uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2) · line 1553
Quoted 3 lines
target/s390x/mem_helper.c +2
-0+program_interrupt (env,PGM_ADDRESSING ,6 ); + }I think you should also mask the length with
0xffffffffif the PSW was not in 64-bit mode? Or is this done automagically by the generated TCG code already?
I was asking myself the same question, but it shouldn't really matter as was we will be using a maximum of 4096, no? We don't modify this register. I think only the caller has to care about that when trying to store bigger values.
Quoted 43 lines
Quoted 29 lines
target/s390x/mem_helper.c +28
-0+if (len >4096 ) { + cc =3 ; + len =4096 ; + } + +/* +* FIXME: a) LAP protection +* b) Access using correct PSW keys +* c) AR-mode (mmu support missing) +* d) bulk transfer +*/ +for (i =0 ; i < len; i++, src++, dest++) { +uint8_t x =0 ; + + src =wrap_address (env, src); + dest =wrap_address (env, dest); +switch (src_as) { +case 0x0 : + x =cpu_ldub_primary_ra (env, src, ra); +break ; +case 0x2 : + x =cpu_ldub_secondary_ra (env, src, ra); +break ; +case 0x3 : + x =cpu_ldub_home_ra (env, src, ra); +break ; + } +switch (dest_as) {target/s390x/mem_helper.c uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2) · line 1594
Quoted 10 lines
target/s390x/mem_helper.c +10
-0+case 0x0 : +cpu_stb_primary_ra (env, dest, x, ra); +break ; +case 0x2 : +cpu_stb_secondary_ra (env, dest, x, ra); +break ; +case 0x3 : +cpu_stb_home_ra (env, dest, x, ra); +break ; + }I wonder whether we should have some proper #defines for those AS values ... something like:
Quoted 6 lines
#define AS_PRIMARY 0 #define AS_ACCREG 1 #define AS_SECONDARY 2 #define AS_HOME 3?
We have PSW_ASC_PRIMARY and friends that map to the actual bit positions in the PSW. Adding these makes sense.
Thanks!
Quoted 9 lines
Thomas
Quoted 5 lines
target/s390x/mem_helper.c +5
-0+ } + +return cc; +} +
Signature · 3 lines
Thanks, David
Re: [Qemu-devel] [PATCH v1 2/3] target/s390x: implement mvcos instruction
On 14.06.2017 09:56, David Hildenbrand wrote:
[...]
Quoted 6 lines
Quoted 3 lines
I think you should also mask the length with
0xffffffffif the PSW was not in 64-bit mode? Or is this done automagically by the generated TCG code already?I was asking myself the same question, but it shouldn't really matter as was we will be using a maximum of 4096, no?
Question is whether we can end up here somehow in 32-bit mode and the upper part of the register is still != 0 ... something like 0x100000010 for example. Can we be sure that the upper half is always cleared if we switch from 64-bit mode to the 32-bit mode before?
Thomas
Re: [Qemu-devel] [PATCH v1 2/3] target/s390x: implement mvcos instruction
Quoted 6 lines · Thomas Huth
On 14.06.2017 09:56, David Hildenbrand wrote:
[...]Quoted 4 lines
Quoted 3 lines
I think you should also mask the length with
0xffffffffif the PSW was not in 64-bit mode? Or is this done automagically by the generated TCG code already?
Quoted 7 lines
Quoted 2 lines
I was asking myself the same question, but it shouldn't really matter as was we will be using a maximum of 4096, no?
Question is whether we can end up here somehow in 32-bit mode and the upper part of the register is still != 0 ... something like
0x100000010for example. Can we be sure that the upper half is always cleared if we switch from 64-bit mode to the 32-bit mode before?
We don't currently have any length masking at the translate level. Within mem_helper.c, we have wrap_length.
r~
PATCH 3/3 s390x/cpumodel: allow to enable MVCOS for qemu cpu model
In reply to David HildenbrandThis allows botting a recent linux kernel (e.g. compiled for z900) and using mvcos for uaccess:
qemu-system-s390x ... -cpu qemu,mvcos=on ...
While at it, correctly fake its abscence.
--- target/s390x/cpu_models.c | 1 + target/s390x/mem_helper.c | 3 +++ 2 files changed, 4 insertions(+)
target/s390x/cpu_models.c +1 -0
@@ -682,6 +682,7 @@ static void add_qemu_cpu_model_features(S390FeatBitmap fbm)S390_FEAT_LONG_DISPLACEMENT_FAST ,S390_FEAT_ETF2_ENH ,S390_FEAT_STORE_CLOCK_FAST , +S390_FEAT_MOVE_WITH_OPTIONAL_SPEC ,S390_FEAT_GENERAL_INSTRUCTIONS_EXT ,S390_FEAT_EXECUTE_EXT , S390_FEAT_STFLE_45,
target/s390x/mem_helper.c +3 -0
@@ -1508,6 +1508,9 @@ uint32_t HELPER(mvcos)(CPUS390XState *env, uint64_t dest, uint64_t src,HELPER_LOG ("%s dest %" PRIx64", src %" PRIx64", len %" PRIx64"\n" , __func__, dest, src, len); +if (!s390_has_feat (S390_FEAT_MOVE_WITH_OPTIONAL_SPEC )) { +program_interrupt (env,PGM_OPERATION ,6 ); + }if (!(env->psw.mask &PSW_MASK_DAT )) {program_interrupt (env,PGM_SPECIAL_OP ,6 ); }
Signature · 1 line
2.9.3
Re: [Qemu-devel] [PATCH v1 3/3] s390x/cpumodel: allow to enable MVCOS for qemu cpu model
target/s390x/mem_helper.c uint32_t HELPER(mvcos)(CPUS390XState *env, uint64_t dest, uint64_t src, · line 1513
Quoted 3 lines · David Hildenbrand
target/s390x/mem_helper.c +3
-0+if (!s390_has_feat (S390_FEAT_MOVE_WITH_OPTIONAL_SPEC )) { +program_interrupt (env,PGM_OPERATION ,6 ); + }
This is (supposed to be) done via the feature field of insn-data.def.
Except that we do not yet enforce that; we haven't updated that bit of the translator since we actually added support for the feature bits.
r~
Re: [Qemu-devel] [PATCH v1 3/3] s390x/cpumodel: allow to enable MVCOS for qemu cpu model
Quoted 9 lines · Richard Henderson
target/s390x/mem_helper.c uint32_t HELPER(mvcos)(CPUS390XState *env, uint64_t dest, uint64_t src, · line 1513
Quoted 3 lines · David Hildenbrand
target/s390x/mem_helper.c +3
-0+if (!s390_has_feat (S390_FEAT_MOVE_WITH_OPTIONAL_SPEC )) { +program_interrupt (env,PGM_OPERATION ,6 ); + }This is (supposed to be) done via the feature field of insn-data.def.
Except that we do not yet enforce that; we haven't updated that bit of the translator since we actually added support for the feature bits.
That makes sense, I'll drop this hunk then. So wiring up these bits with the CPU model directly sounds like what we want to do.
Thanks!
Quoted 4 lines
r~
Signature · 3 lines
Thanks, David
Re: [Qemu-devel] [PATCH v1 3/3] s390x/cpumodel: allow to enable MVCOS for qemu cpu model
Quoted 6 lines · David Hildenbrand
Quoted 5 lines · Richard Henderson
Quoted 3 lines · David Hildenbrand
target/s390x/mem_helper.c +3
-0+if (!s390_has_feat (S390_FEAT_MOVE_WITH_OPTIONAL_SPEC )) { +program_interrupt (env,PGM_OPERATION ,6 ); + }
Quoted 6 lines
Quoted 4 lines
This is (supposed to be) done via the feature field of insn-data.def.
Except that we do not yet enforce that; we haven't updated that bit of the translator since we actually added support for the feature bits.
That makes sense, I'll drop this hunk then.
I think you could then also simply put the one-line-change to target/s390x/cpu_models.c into the previous patch instead.
Thomas
This series failed automatic build test. Please find the testing commands and their output below. If you have docker installed, you can probably reproduce it locally.
Hi,
This series failed automatic build test. Please find the testing commands and their output below. If you have docker installed, you can probably reproduce it locally.
Type: series
Message-id: [email protected]
Subject: [Qemu-devel] [PATCH v1 0/3] target/s390x: implement MVCOS and allow to enable it
=== TEST SCRIPT BEGIN ===
#!/bin/bash
set -e
git submodule update --init dtc
# Let docker tests dump environment info
export SHOW_ENV=1
export J=8
time make docker-test-quick@centos6
time make docker-test-mingw@fedora
time make docker-test-build@min-glib
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/[email protected] -> patchew/[email protected]
Switched to a new branch 'test'
03109d4 s390x/cpumodel: allow to enable MVCOS for qemu cpu model a3c7caf target/s390x: implement mvcos instruction a546f1c target/s390x: change PSW_SHIFT_KEY
=== OUTPUT BEGIN ===
Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc' Cloning into '/var/tmp/patchew-tester-tmp-gltza398/src/dtc'... Submodule path 'dtc': checked out '558cd81bdd432769b59bff01240c44f82cfb1a9d'
BUILD centos6
make[1]: Entering directory '/var/tmp/patchew-tester-tmp-gltza398/src'
ARCHIVE qemu.tgz
ARCHIVE dtc.tgz
COPY RUNNER
RUN test-quick in qemu:centos6
Packages installed:
SDL-devel-1.2.14-7.el6_7.1.x86_64
ccache-3.1.6-2.el6.x86_64
epel-release-6-8.noarch
gcc-4.4.7-17.el6.x86_64
git-1.7.1-4.el6_7.1.x86_64
glib2-devel-2.28.8-5.el6.x86_64
libfdt-devel-1.4.0-1.el6.x86_64
make-3.81-23.el6.x86_64
package g++ is not installed
pixman-devel-0.32.8-1.el6.x86_64
tar-1.23-15.el6_8.x86_64
zlib-devel-1.2.3-29.el6.x86_64
Environment variables:
PACKAGES=libfdt-devel ccache tar git make gcc g++ zlib-devel glib2-devel SDL-devel pixman-devel epel-release
HOSTNAME=f6d12a3831b4
TERM=xterm
MAKEFLAGS= -j8
HISTSIZE=1000
J=8
USER=root
CCACHE_DIR=/var/tmp/ccache
EXTRA_CONFIGURE_OPTS=
V=
SHOW_ENV=1
MAIL=/var/spool/mail/root PATH=/usr/lib/ccache:/usr/lib64/ccache:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin PWD=/
LANG=en_US.UTF-8
TARGET_LIST=
HISTCONTROL=ignoredups
SHLVL=1
HOME=/root
TEST_DIR=/tmp/qemu-test
LOGNAME=root
LESSOPEN=||/usr/bin/lesspipe.sh %s
FEATURES= dtc
DEBUG=
G_BROKEN_FILENAMES=1
CCACHE_HASHDIR=
_=/usr/bin/env
Configure options:
--enable-werror --target-list=x86_64-softmmu,aarch64-softmmu --prefix=/var/tmp/qemu-build/install /tmp/qemu-test/src/configure: line 4683: c++: command not found
No C++ compiler available; disabling C++ specific optional code
Install prefix /var/tmp/qemu-build/install BIOS directory /var/tmp/qemu-build/install/share/qemu binary directory /var/tmp/qemu-build/install/bin
library directory /var/tmp/qemu-build/install/lib module directory /var/tmp/qemu-build/install/lib/qemu libexec directory /var/tmp/qemu-build/install/libexec include directory /var/tmp/qemu-build/install/include config directory /var/tmp/qemu-build/install/etc
local state directory /var/tmp/qemu-build/install/var
Manual directory /var/tmp/qemu-build/install/share/man ELF interp prefix /usr/gnemul/qemu-%M
Source path /tmp/qemu-test/src C compiler cc Host C compiler cc C++ compiler Objective-C compiler cc ARFLAGS rv CFLAGS -O2 -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 -g QEMU_CFLAGS -I/usr/include/pixman-1 -I$(SRC_PATH)/dtc/libfdt -pthread -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -fPIE -DPIE -m64 -mcx16 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -Wendif-labels -Wno-missing-include-dirs -Wempty-body -Wnested-externs -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wold-style-declaration -Wold-style-definition -Wtype-limits -fstack-protector-all LDFLAGS -Wl,--warn-common -Wl,-z,relro -Wl,-z,now -pie -m64 -g make make install install python python -B smbd /usr/sbin/smbd module support no host CPU x86_64 host big endian no target list x86_64-softmmu aarch64-softmmu tcg debug enabled no gprof enabled no sparse enabled no strip binaries yes profiler no static build no pixman system SDL support yes (1.2.14) GTK support no GTK GL support no VTE support no TLS priority NORMAL GNUTLS support no GNUTLS rnd no libgcrypt no libgcrypt kdf no nettle no nettle kdf no libtasn1 no curses support no virgl support no curl support no mingw32 support no Audio drivers oss Block whitelist (rw) Block whitelist (ro) VirtFS support no VNC support yes VNC SASL support no VNC JPEG support no VNC PNG support no xen support no brlapi support no bluez support no Documentation no PIE yes vde support no netmap support no Linux AIO support no ATTR/XATTR support yes Install blobs yes KVM support yes HAX support no RDMA support no TCG interpreter no fdt support yes preadv support yes fdatasync yes madvise yes posix_madvise yes
libcap-ng support no
vhost-net support yes
vhost-scsi support yes
vhost-vsock support yes
Trace backends log spice support no rbd support no xfsctl support no smartcard support no libusb no usb net redir no OpenGL support no OpenGL dmabufs no libiscsi support no libnfs support no
build guest agent yes
QGA VSS support no
QGA w32 disk info no
QGA MSI support no
seccomp support no
coroutine backend ucontext
coroutine pool yes
debug stack usage no
GlusterFS support no
gcov gcov gcov enabled no TPM support yes libssh2 support no TPM passthrough yes QOM debugging yes Live block migration yes lzo support no snappy support no bzip2 support no
NUMA host support no
tcmalloc support no
jemalloc support no
avx2 optimization no
replication support yes
VxHS block device no
GEN x86_64-softmmu/config-devices.mak.tmp
mkdir -p dtc/libfdt
GEN aarch64-softmmu/config-devices.mak.tmp
mkdir -p dtc/tests
GEN config-host.h GEN qemu-options.def GEN qmp-commands.h GEN qapi-types.h GEN qapi-visit.h GEN qapi-event.h GEN x86_64-softmmu/config-devices.mak GEN qmp-marshal.c GEN aarch64-softmmu/config-devices.mak GEN qapi-types.c GEN qapi-visit.c GEN qapi-event.c GEN qmp-introspect.h GEN qmp-introspect.c GEN trace/generated-tcg-tracers.h GEN trace/generated-helpers-wrappers.h GEN trace/generated-helpers.h GEN trace/generated-helpers.c GEN module_block.h GEN tests/test-qapi-types.h GEN tests/test-qapi-visit.h GEN tests/test-qmp-commands.h GEN tests/test-qapi-event.h GEN tests/test-qmp-introspect.h GEN trace-root.h GEN util/trace.h GEN crypto/trace.h GEN io/trace.h GEN migration/trace.h GEN block/trace.h GEN backends/trace.h GEN chardev/trace.h GEN hw/block/trace.h GEN hw/block/dataplane/trace.h GEN hw/char/trace.h GEN hw/intc/trace.h GEN hw/net/trace.h GEN hw/virtio/trace.h GEN hw/audio/trace.h GEN hw/misc/trace.h GEN hw/usb/trace.h GEN hw/scsi/trace.h GEN hw/nvram/trace.h GEN hw/display/trace.h GEN hw/input/trace.h GEN hw/timer/trace.h GEN hw/dma/trace.h GEN hw/sparc/trace.h GEN hw/sd/trace.h GEN hw/isa/trace.h GEN hw/mem/trace.h GEN hw/i386/trace.h GEN hw/i386/xen/trace.h GEN hw/9pfs/trace.h GEN hw/ppc/trace.h GEN hw/pci/trace.h GEN hw/s390x/trace.h GEN hw/vfio/trace.h GEN hw/acpi/trace.h GEN hw/arm/trace.h GEN hw/alpha/trace.h GEN hw/xen/trace.h GEN ui/trace.h GEN audio/trace.h GEN net/trace.h GEN target/arm/trace.h GEN target/i386/trace.h GEN target/mips/trace.h GEN target/sparc/trace.h GEN target/s390x/trace.h GEN target/ppc/trace.h GEN qom/trace.h GEN linux-user/trace.h GEN trace-root.c GEN qapi/trace.h GEN util/trace.c GEN crypto/trace.c GEN io/trace.c GEN migration/trace.c GEN block/trace.c GEN backends/trace.c GEN chardev/trace.c GEN hw/block/trace.c GEN hw/block/dataplane/trace.c GEN hw/char/trace.c GEN hw/intc/trace.c GEN hw/net/trace.c GEN hw/virtio/trace.c GEN hw/audio/trace.c GEN hw/misc/trace.c GEN hw/usb/trace.c GEN hw/scsi/trace.c GEN hw/nvram/trace.c GEN hw/display/trace.c GEN hw/input/trace.c GEN hw/timer/trace.c GEN hw/dma/trace.c GEN hw/sparc/trace.c GEN hw/sd/trace.c GEN hw/isa/trace.c GEN hw/mem/trace.c GEN hw/i386/trace.c GEN hw/i386/xen/trace.c GEN hw/9pfs/trace.c GEN hw/ppc/trace.c GEN hw/pci/trace.c GEN hw/s390x/trace.c GEN hw/vfio/trace.c GEN hw/acpi/trace.c GEN hw/arm/trace.c GEN hw/alpha/trace.c GEN hw/xen/trace.c GEN ui/trace.c GEN audio/trace.c GEN net/trace.c GEN target/arm/trace.c GEN target/i386/trace.c GEN target/mips/trace.c GEN target/sparc/trace.c GEN target/s390x/trace.c GEN target/ppc/trace.c GEN qom/trace.c GEN linux-user/trace.c GEN qapi/trace.c GEN config-all-devices.mak
DEP /tmp/qemu-test/src/dtc/tests/dumptrees.c
DEP /tmp/qemu-test/src/dtc/tests/trees.S
DEP /tmp/qemu-test/src/dtc/tests/testutils.c
DEP /tmp/qemu-test/src/dtc/tests/value-labels.c DEP /tmp/qemu-test/src/dtc/tests/asm_tree_dump.c DEP /tmp/qemu-test/src/dtc/tests/truncated_property.c DEP /tmp/qemu-test/src/dtc/tests/check_path.c
DEP /tmp/qemu-test/src/dtc/tests/overlay_bad_fixup.c DEP /tmp/qemu-test/src/dtc/tests/overlay.c
DEP /tmp/qemu-test/src/dtc/tests/subnode_iterate.c DEP /tmp/qemu-test/src/dtc/tests/property_iterate.c DEP /tmp/qemu-test/src/dtc/tests/integer-expressions.c DEP /tmp/qemu-test/src/dtc/tests/utilfdt_test.c DEP /tmp/qemu-test/src/dtc/tests/path_offset_aliases.c DEP /tmp/qemu-test/src/dtc/tests/add_subnode_with_nops.c DEP /tmp/qemu-test/src/dtc/tests/dtbs_equal_unordered.c DEP /tmp/qemu-test/src/dtc/tests/dtb_reverse.c DEP /tmp/qemu-test/src/dtc/tests/dtbs_equal_ordered.c DEP /tmp/qemu-test/src/dtc/tests/incbin.c
DEP /tmp/qemu-test/src/dtc/tests/extra-terminating-null.c DEP /tmp/qemu-test/src/dtc/tests/boot-cpuid.c
DEP /tmp/qemu-test/src/dtc/tests/path-references.c DEP /tmp/qemu-test/src/dtc/tests/phandle_format.c DEP /tmp/qemu-test/src/dtc/tests/references.c
DEP /tmp/qemu-test/src/dtc/tests/string_escapes.c DEP /tmp/qemu-test/src/dtc/tests/propname_escapes.c DEP /tmp/qemu-test/src/dtc/tests/appendprop1.c DEP /tmp/qemu-test/src/dtc/tests/appendprop2.c DEP /tmp/qemu-test/src/dtc/tests/del_node.c
DEP /tmp/qemu-test/src/dtc/tests/del_property.c DEP /tmp/qemu-test/src/dtc/tests/setprop.c
DEP /tmp/qemu-test/src/dtc/tests/set_name.c
DEP /tmp/qemu-test/src/dtc/tests/rw_tree1.c
DEP /tmp/qemu-test/src/dtc/tests/open_pack.c
DEP /tmp/qemu-test/src/dtc/tests/nopulate.c
DEP /tmp/qemu-test/src/dtc/tests/mangle-layout.c DEP /tmp/qemu-test/src/dtc/tests/move_and_save.c DEP /tmp/qemu-test/src/dtc/tests/sw_tree1.c
DEP /tmp/qemu-test/src/dtc/tests/nop_node.c
DEP /tmp/qemu-test/src/dtc/tests/nop_property.c DEP /tmp/qemu-test/src/dtc/tests/setprop_inplace.c DEP /tmp/qemu-test/src/dtc/tests/stringlist.c
DEP /tmp/qemu-test/src/dtc/tests/notfound.c
DEP /tmp/qemu-test/src/dtc/tests/addr_size_cells.c DEP /tmp/qemu-test/src/dtc/tests/sized_cells.c DEP /tmp/qemu-test/src/dtc/tests/char_literal.c DEP /tmp/qemu-test/src/dtc/tests/get_alias.c
DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_compatible.c DEP /tmp/qemu-test/src/dtc/tests/node_check_compatible.c DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_prop_value.c DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_phandle.c DEP /tmp/qemu-test/src/dtc/tests/parent_offset.c DEP /tmp/qemu-test/src/dtc/tests/supernode_atdepth_offset.c DEP /tmp/qemu-test/src/dtc/tests/get_path.c
DEP /tmp/qemu-test/src/dtc/tests/get_phandle.c DEP /tmp/qemu-test/src/dtc/tests/getprop.c
DEP /tmp/qemu-test/src/dtc/tests/get_name.c
DEP /tmp/qemu-test/src/dtc/tests/path_offset.c DEP /tmp/qemu-test/src/dtc/tests/subnode_offset.c DEP /tmp/qemu-test/src/dtc/tests/find_property.c DEP /tmp/qemu-test/src/dtc/tests/root_node.c
DEP /tmp/qemu-test/src/dtc/tests/get_mem_rsv.c DEP /tmp/qemu-test/src/dtc/libfdt/fdt_overlay.c DEP /tmp/qemu-test/src/dtc/libfdt/fdt_addresses.c DEP /tmp/qemu-test/src/dtc/libfdt/fdt_empty_tree.c DEP /tmp/qemu-test/src/dtc/libfdt/fdt_strerror.c DEP /tmp/qemu-test/src/dtc/libfdt/fdt_rw.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_sw.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_wip.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_ro.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt.c
DEP /tmp/qemu-test/src/dtc/util.c
DEP /tmp/qemu-test/src/dtc/fdtget.c
DEP /tmp/qemu-test/src/dtc/fdtput.c
DEP /tmp/qemu-test/src/dtc/fdtdump.c
LEX convert-dtsv0-lexer.lex.c
make[1]: flex: Command not found
DEP /tmp/qemu-test/src/dtc/srcpos.c
BISON dtc-parser.tab.c
make[1]: bison: Command not found
LEX dtc-lexer.lex.c
DEP /tmp/qemu-test/src/dtc/treesource.c
make[1]: flex: Command not found
DEP /tmp/qemu-test/src/dtc/livetree.c
DEP /tmp/qemu-test/src/dtc/fstree.c
DEP /tmp/qemu-test/src/dtc/flattree.c
DEP /tmp/qemu-test/src/dtc/dtc.c
DEP /tmp/qemu-test/src/dtc/data.c
DEP /tmp/qemu-test/src/dtc/checks.c
CHK version_gen.h
LEX convert-dtsv0-lexer.lex.c
make[1]: flex: Command not found
BISON dtc-parser.tab.c
make[1]: bison: Command not found
LEX dtc-lexer.lex.c
UPD version_gen.h
make[1]: flex: Command not found
DEP /tmp/qemu-test/src/dtc/util.c
LEX convert-dtsv0-lexer.lex.c
BISON dtc-parser.tab.c
make[1]: flex: Command not found
LEX dtc-lexer.lex.c
make[1]: bison: Command not found
make[1]: flex: Command not found
CC libfdt/fdt.o
CC libfdt/fdt_ro.o
CC libfdt/fdt_wip.o
CC libfdt/fdt_sw.o
CC libfdt/fdt_rw.o
CC libfdt/fdt_strerror.o
CC libfdt/fdt_empty_tree.o
CC libfdt/fdt_addresses.o
CC libfdt/fdt_overlay.o
AR libfdt/libfdt.a
ar: creating libfdt/libfdt.a
a - libfdt/fdt.o
a - libfdt/fdt_ro.o
a - libfdt/fdt_wip.o
a - libfdt/fdt_sw.o
a - libfdt/fdt_rw.o
a - libfdt/fdt_strerror.o
a - libfdt/fdt_empty_tree.o
a - libfdt/fdt_addresses.o
a - libfdt/fdt_overlay.o
BISON dtc-parser.tab.c
make[1]: bison: Command not found
LEX convert-dtsv0-lexer.lex.c
LEX dtc-lexer.lex.c
make[1]: flex: Command not found
make[1]: flex: Command not found
CC tests/qemu-iotests/socket_scm_helper.o GEN qga/qapi-generated/qga-qapi-types.h GEN qga/qapi-generated/qga-qmp-commands.h GEN qga/qapi-generated/qga-qapi-visit.h GEN qga/qapi-generated/qga-qapi-types.c GEN qga/qapi-generated/qga-qapi-visit.c GEN qga/qapi-generated/qga-qmp-marshal.c CC qmp-introspect.o CC qapi-types.o CC qapi-visit.o CC qapi-event.o CC qapi/qapi-visit-core.o CC qapi/qapi-dealloc-visitor.o CC qapi/qobject-input-visitor.o CC qapi/qobject-output-visitor.o CC qapi/qmp-registry.o CC qapi/string-input-visitor.o CC qapi/qmp-dispatch.o CC qapi/string-output-visitor.o CC qapi/qmp-event.o CC qobject/qnull.o CC qapi/opts-visitor.o CC qapi/qapi-util.o CC qapi/qapi-clone-visitor.o CC qobject/qint.o CC qobject/qstring.o CC qobject/qdict.o CC qobject/qlist.o CC qobject/qfloat.o CC qobject/qbool.o CC qobject/qjson.o CC qobject/json-lexer.o CC qobject/json-streamer.o CC qobject/json-parser.o CC trace/control.o CC util/osdep.o CC qobject/qobject.o CC trace/qmp.o CC util/cutils.o CC util/unicode.o CC util/qemu-timer-common.o CC util/bufferiszero.o CC util/lockcnt.o CC util/aiocb.o CC util/thread-pool.o CC util/qemu-timer.o CC util/main-loop.o CC util/async.o CC util/aio-posix.o CC util/compatfd.o CC util/iohandler.o CC util/event_notifier-posix.o CC util/mmap-alloc.o CC util/oslib-posix.o CC util/qemu-openpty.o CC util/qemu-thread-posix.o CC util/memfd.o CC util/envlist.o CC util/path.o CC util/host-utils.o CC util/module.o CC util/bitmap.o CC util/bitops.o CC util/hbitmap.o CC util/fifo8.o CC util/acl.o CC util/error.o CC util/qemu-error.o CC util/id.o CC util/qemu-config.o CC util/iov.o CC util/qemu-sockets.o CC util/uri.o CC util/notify.o CC util/qemu-option.o CC util/qemu-progress.o CC util/keyval.o CC util/hexdump.o CC util/crc32c.o CC util/uuid.o CC util/throttle.o CC util/getauxval.o CC util/readline.o CC util/rcu.o CC util/qemu-coroutine.o CC util/qemu-coroutine-lock.o CC util/qemu-coroutine-io.o CC util/qemu-coroutine-sleep.o CC util/buffer.o CC util/coroutine-ucontext.o CC util/timed-average.o CC util/base64.o CC util/log.o CC util/qdist.o CC util/qht.o CC util/range.o CC util/systemd.o CC trace-root.o CC util/trace.o CC crypto/trace.o CC io/trace.o CC block/trace.o CC chardev/trace.o CC backends/trace.o CC hw/block/trace.o CC hw/block/dataplane/trace.o CC migration/trace.o CC hw/char/trace.o CC hw/intc/trace.o CC hw/net/trace.o CC hw/virtio/trace.o CC hw/misc/trace.o CC hw/audio/trace.o CC hw/usb/trace.o CC hw/scsi/trace.o CC hw/nvram/trace.o CC hw/display/trace.o CC hw/input/trace.o CC hw/timer/trace.o CC hw/sparc/trace.o CC hw/dma/trace.o CC hw/isa/trace.o CC hw/sd/trace.o CC hw/i386/trace.o CC hw/mem/trace.o CC hw/i386/xen/trace.o CC hw/9pfs/trace.o CC hw/ppc/trace.o CC hw/pci/trace.o CC hw/s390x/trace.o CC hw/acpi/trace.o CC hw/vfio/trace.o CC hw/alpha/trace.o CC hw/arm/trace.o CC hw/xen/trace.o CC ui/trace.o CC audio/trace.o CC net/trace.o CC target/arm/trace.o CC target/i386/trace.o CC target/mips/trace.o CC target/sparc/trace.o CC target/s390x/trace.o CC qom/trace.o CC target/ppc/trace.o CC linux-user/trace.o CC qapi/trace.o CC crypto/pbkdf-stub.o CC stubs/arch-query-cpu-def.o CC stubs/arch-query-cpu-model-expansion.o CC stubs/arch-query-cpu-model-comparison.o CC stubs/bdrv-next-monitor-owned.o CC stubs/arch-query-cpu-model-baseline.o CC stubs/blk-commit-all.o CC stubs/blockdev-close-all-bdrv-states.o CC stubs/clock-warp.o CC stubs/cpu-get-clock.o CC stubs/cpu-get-icount.o CC stubs/dump.o CC stubs/error-printf.o CC stubs/fdset.o CC stubs/get-vm-name.o CC stubs/gdbstub.o CC stubs/iothread.o CC stubs/iothread-lock.o CC stubs/is-daemonized.o CC stubs/migr-blocker.o CC stubs/machine-init-done.o CC stubs/monitor.o CC stubs/notify-event.o CC stubs/qtest.o CC stubs/replay.o CC stubs/set-fd-handler.o CC stubs/runstate-check.o CC stubs/slirp.o CC stubs/sysbus.o CC stubs/trace-control.o CC stubs/uuid.o CC stubs/vmstate.o CC stubs/vm-stop.o CC stubs/qmp_pc_dimm_device_list.o CC stubs/target-monitor-defs.o CC stubs/pc_madt_cpu_entry.o CC stubs/target-get-monitor-def.o CC stubs/vmgenid.o CC stubs/xen-common.o CC stubs/xen-hvm.o CC contrib/ivshmem-client/ivshmem-client.o CC contrib/ivshmem-client/main.o CC contrib/ivshmem-server/ivshmem-server.o CC contrib/ivshmem-server/main.o CC qemu-nbd.o CC block.o CC blockjob.o CC qemu-io-cmds.o CC replication.o CC block/raw-format.o CC block/vdi.o CC block/vmdk.o CC block/qcow.o CC block/cloop.o CC block/vpc.o CC block/bochs.o CC block/vvfat.o CC block/dmg.o CC block/qcow2.o CC block/qcow2-refcount.o CC block/qcow2-snapshot.o CC block/qcow2-cluster.o CC block/qcow2-cache.o CC block/qed.o CC block/qed-gencb.o CC block/qed-l2-cache.o CC block/qed-cluster.o CC block/qed-table.o CC block/qed-check.o CC block/vhdx.o CC block/vhdx-endian.o CC block/vhdx-log.o CC block/quorum.o CC block/parallels.o CC block/blkdebug.o CC block/blkverify.o CC block/blkreplay.o CC block/block-backend.o CC block/qapi.o CC block/snapshot.o CC block/null.o CC block/mirror.o CC block/file-posix.o CC block/commit.o CC block/io.o CC block/throttle-groups.o CC block/nbd.o CC block/nbd-client.o CC block/sheepdog.o CC block/accounting.o CC block/dirty-bitmap.o CC block/write-threshold.o CC block/backup.o CC block/replication.o CC block/crypto.o CC nbd/server.o CC nbd/client.o CC nbd/common.o CC crypto/init.o CC crypto/hash.o CC crypto/hash-glib.o CC crypto/hmac.o CC crypto/hmac-glib.o CC crypto/aes.o CC crypto/desrfb.o CC crypto/cipher.o CC crypto/tlscreds.o CC crypto/tlscredsx509.o CC crypto/tlscredsanon.o CC crypto/tlssession.o CC crypto/secret.o CC crypto/random-platform.o CC crypto/pbkdf.o CC crypto/ivgen.o CC crypto/ivgen-essiv.o CC crypto/ivgen-plain.o CC crypto/ivgen-plain64.o CC crypto/afsplit.o CC crypto/xts.o CC crypto/block.o CC crypto/block-qcow.o CC crypto/block-luks.o CC io/channel.o CC io/channel-buffer.o CC io/channel-command.o CC io/channel-file.o CC io/channel-socket.o CC io/channel-tls.o CC io/channel-watch.o CC io/channel-websock.o CC io/channel-util.o CC io/dns-resolver.o CC io/task.o CC qom/object.o CC qom/container.o CC qom/qom-qobject.o CC qom/object_interfaces.o GEN qemu-img-cmds.h CC qemu-io.o CC qemu-bridge-helper.o CC blockdev.o CC iothread.o CC blockdev-nbd.o CC qdev-monitor.o CC device-hotplug.o CC accel.o CC os-posix.o CC bt-host.o CC bt-vhci.o CC dma-helpers.o CC vl.o CC tpm.o CC qmp-marshal.o CC device_tree.o CC qmp.o CC hmp.o CC audio/audio.o CC cpus-common.o CC audio/noaudio.o CC audio/mixeng.o CC audio/sdlaudio.o CC audio/wavaudio.o CC audio/wavcapture.o CC audio/ossaudio.o CC backends/rng.o CC backends/rng-egd.o CC backends/rng-random.o CC backends/tpm.o CC backends/hostmem.o CC backends/hostmem-ram.o CC backends/cryptodev.o CC backends/hostmem-file.o CC backends/cryptodev-builtin.o CC block/stream.o CC chardev/msmouse.o CC chardev/wctablet.o CC chardev/testdev.o CC disas/arm.o CC disas/i386.o CC fsdev/qemu-fsdev-dummy.o CC fsdev/qemu-fsdev-opts.o CC fsdev/qemu-fsdev-throttle.o CC hw/acpi/core.o CC hw/acpi/piix4.o CC hw/acpi/pcihp.o CC hw/acpi/ich9.o CC hw/acpi/tco.o CC hw/acpi/cpu_hotplug.o CC hw/acpi/memory_hotplug.o CC hw/acpi/cpu.o CC hw/acpi/nvdimm.o CC hw/acpi/vmgenid.o CC hw/acpi/acpi_interface.o CC hw/acpi/bios-linker-loader.o CC hw/acpi/aml-build.o CC hw/acpi/ipmi.o CC hw/acpi/acpi-stub.o CC hw/acpi/ipmi-stub.o CC hw/audio/sb16.o CC hw/audio/es1370.o CC hw/audio/ac97.o CC hw/audio/fmopl.o CC hw/audio/adlib.o CC hw/audio/gus.o CC hw/audio/gusemu_hal.o CC hw/audio/gusemu_mixer.o CC hw/audio/cs4231a.o CC hw/audio/hda-codec.o CC hw/audio/intel-hda.o CC hw/audio/pcspk.o CC hw/audio/wm8750.o CC hw/audio/pl041.o CC hw/audio/lm4549.o CC hw/audio/marvell_88w8618.o CC hw/audio/soundhw.o CC hw/block/cdrom.o CC hw/block/block.o CC hw/block/hd-geometry.o CC hw/block/fdc.o CC hw/block/m25p80.o CC hw/block/nand.o CC hw/block/pflash_cfi01.o CC hw/block/pflash_cfi02.o CC hw/block/onenand.o CC hw/block/ecc.o CC hw/block/nvme.o CC hw/bt/core.o CC hw/bt/l2cap.o CC hw/bt/sdp.o CC hw/bt/hci.o CC hw/bt/hid.o CC hw/bt/hci-csr.o CC hw/char/ipoctal232.o CC hw/char/parallel.o CC hw/char/pl011.o CC hw/char/serial.o CC hw/char/serial-isa.o CC hw/char/serial-pci.o CC hw/char/virtio-console.o CC hw/char/cadence_uart.o CC hw/char/debugcon.o CC hw/char/imx_serial.o CC hw/core/qdev-properties.o CC hw/core/qdev.o CC hw/core/bus.o CC hw/core/reset.o CC hw/core/fw-path-provider.o CC hw/core/irq.o CC hw/core/hotplug.o CC hw/core/nmi.o CC hw/core/ptimer.o CC hw/core/sysbus.o CC hw/core/machine.o CC hw/core/loader.o CC hw/core/qdev-properties-system.o CC hw/core/platform-bus.o CC hw/core/register.o CC hw/core/or-irq.o CC hw/cpu/core.o CC hw/display/ads7846.o CC hw/display/cirrus_vga.o CC hw/display/pl110.o CC hw/display/ssd0303.o CC hw/display/ssd0323.o CC hw/display/vga-pci.o CC hw/display/vga-isa.o CC hw/display/vmware_vga.o CC hw/display/blizzard.o CC hw/display/exynos4210_fimd.o CC hw/display/framebuffer.o CC hw/display/tc6393xb.o CC hw/dma/pl080.o CC hw/dma/pl330.o CC hw/dma/i8257.o CC hw/dma/xlnx-zynq-devcfg.o CC hw/gpio/max7310.o CC hw/gpio/pl061.o CC hw/gpio/zaurus.o CC hw/gpio/gpio_key.o CC hw/i2c/core.o CC hw/i2c/smbus.o CC hw/i2c/i2c-ddc.o CC hw/i2c/smbus_eeprom.o CC hw/i2c/versatile_i2c.o CC hw/i2c/smbus_ich9.o CC hw/i2c/pm_smbus.o CC hw/i2c/bitbang_i2c.o CC hw/i2c/exynos4210_i2c.o CC hw/i2c/imx_i2c.o CC hw/i2c/aspeed_i2c.o CC hw/ide/core.o CC hw/ide/atapi.o CC hw/ide/qdev.o CC hw/ide/pci.o CC hw/ide/isa.o CC hw/ide/piix.o CC hw/ide/microdrive.o CC hw/ide/ahci.o CC hw/ide/ich.o CC hw/input/hid.o CC hw/input/lm832x.o CC hw/input/pckbd.o CC hw/input/pl050.o CC hw/input/ps2.o CC hw/input/stellaris_input.o CC hw/input/vmmouse.o CC hw/input/virtio-input.o CC hw/input/tsc2005.o CC hw/input/virtio-input-hid.o CC hw/input/virtio-input-host.o CC hw/intc/i8259_common.o CC hw/intc/pl190.o CC hw/intc/i8259.o CC hw/intc/imx_avic.o CC hw/intc/realview_gic.o CC hw/intc/ioapic_common.o CC hw/intc/arm_gic_common.o CC hw/intc/arm_gicv3_common.o CC hw/intc/arm_gicv2m.o CC hw/intc/arm_gicv3.o CC hw/intc/arm_gicv3_dist.o CC hw/intc/arm_gic.o CC hw/intc/arm_gicv3_redist.o CC hw/intc/arm_gicv3_its_common.o CC hw/ipack/ipack.o CC hw/ipack/tpci200.o CC hw/ipmi/ipmi.o CC hw/intc/intc.o CC hw/ipmi/ipmi_bmc_sim.o CC hw/ipmi/isa_ipmi_kcs.o CC hw/ipmi/ipmi_bmc_extern.o CC hw/ipmi/isa_ipmi_bt.o CC hw/isa/isa-bus.o CC hw/isa/apm.o CC hw/mem/pc-dimm.o CC hw/mem/nvdimm.o CC hw/misc/applesmc.o CC hw/misc/max111x.o CC hw/misc/tmp421.o CC hw/misc/tmp105.o CC hw/misc/sga.o CC hw/misc/pc-testdev.o CC hw/misc/pci-testdev.o CC hw/misc/unimp.o CC hw/misc/debugexit.o CC hw/misc/arm_l2x0.o CC hw/misc/arm_integrator_debug.o CC hw/misc/a9scu.o CC hw/misc/arm11scu.o CC hw/net/ne2000.o CC hw/net/eepro100.o CC hw/net/pcnet-pci.o CC hw/net/pcnet.o CC hw/net/e1000x_common.o CC hw/net/net_tx_pkt.o CC hw/net/e1000.o CC hw/net/net_rx_pkt.o CC hw/net/e1000e_core.o CC hw/net/rtl8139.o CC hw/net/e1000e.o CC hw/net/vmxnet3.o CC hw/net/smc91c111.o CC hw/net/lan9118.o CC hw/net/ne2000-isa.o CC hw/net/xgmac.o CC hw/net/allwinner_emac.o CC hw/net/imx_fec.o CC hw/net/cadence_gem.o CC hw/net/stellaris_enet.o CC hw/net/ftgmac100.o CC hw/net/rocker/rocker.o CC hw/net/rocker/rocker_fp.o CC hw/net/rocker/rocker_desc.o CC hw/net/rocker/rocker_world.o CC hw/net/rocker/rocker_of_dpa.o CC hw/nvram/eeprom93xx.o CC hw/nvram/fw_cfg.o CC hw/nvram/chrp_nvram.o CC hw/pci-bridge/pci_bridge_dev.o CC hw/pci-bridge/pcie_root_port.o CC hw/pci-bridge/gen_pcie_root_port.o CC hw/pci-bridge/pci_expander_bridge.o CC hw/pci-bridge/xio3130_upstream.o CC hw/pci-bridge/xio3130_downstream.o CC hw/pci-bridge/ioh3420.o CC hw/pci-bridge/i82801b11.o CC hw/pci-host/pam.o CC hw/pci-host/versatile.o CC hw/pci-host/piix.o CC hw/pci-host/q35.o CC hw/pci-host/gpex.o CC hw/pci/pci.o CC hw/pci/pci_bridge.o CC hw/pci/msix.o CC hw/pci/msi.o CC hw/pci/shpc.o CC hw/pci/slotid_cap.o CC hw/pci/pci_host.o CC hw/pci/pcie_host.o CC hw/pci/pcie.o CC hw/pci/pcie_aer.o CC hw/pci/pcie_port.o CC hw/pci/pci-stub.o CC hw/pcmcia/pcmcia.o CC hw/scsi/scsi-disk.o CC hw/scsi/scsi-bus.o CC hw/scsi/scsi-generic.o CC hw/scsi/lsi53c895a.o CC hw/scsi/mptsas.o CC hw/scsi/mptconfig.o
In file included from /tmp/qemu-test/src/hw/net/vmxnet3.c:30:/tmp/qemu-test/src/include/migration/register.h:18: error: redefinition of typedef ‘LoadStateHandler’ /tmp/qemu-test/src/include/migration/vmstate.h:32: note: previous declaration of ‘LoadStateHandler’ was here
make: *** [hw/net/vmxnet3.o] Error 1
make: *** Waiting for unfinished jobs....
tests/docker/Makefile.include:118: recipe for target 'docker-run' failed
make[1]: *** [docker-run] Error 2
make[1]: Leaving directory '/var/tmp/patchew-tester-tmp-gltza398/src' tests/docker/Makefile.include:149: recipe for target 'docker-run-test-quick@centos6' failed
make: *** [docker-run-test-quick@centos6] Error 2
=== OUTPUT END ===
Test command exited with code: 2
---
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