Skip to contentSkip to conversation

drm/i915: Speed up DMC firmware loading

PATCH Superseded David Weinehall 3 participants 18 messages Sep 4, 2017 – Sep 25, 2017

Subsystems (2)
DRM drivers Intel i915
lore
Share & tools
lore

David Weinehall

author
#0 lore raw

PATCH v2 1/1 drm/i915: Speed up DMC firmware loading

Currently we're doing:

1. acquire lock
2. write word to hardware
3. release lock
4. repeat from 1

to load the DMC firmware. Due to the cost of acquiring/releasing a lock, and the size of the DMC firmware, this slows down DMC loading a lot.

This patch simply acquires the lock, writes the entire firmware, then releases the lock. Testing shows resume speedups in the order of 10ms on platforms with DMC firmware (GEN9+).

v2: Per feedback from Chris & Ville there's no need to do the whole
forcewake dance, so lose that bit (Chris, Ville)

Signed-off-by David Weinehall <[email protected]>
---
 drivers/gpu/drm/i915/intel_csr.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)
drivers/gpu/drm/i915/intel_csr.c +14 -1
index 965988f79a55..b7a6ef7e0d53 100644
@@ -239,7 +239,9 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
 void intel_csr_load_program(struct drm_i915_private *dev_priv)
 {
 	u32 *payload = dev_priv->csr.dmc_payload;
+	enum forcewake_domains fw_domains;
 	uint32_t i, fw_size;
+	unsigned long flags;
 
 	if (!HAS_CSR(dev_priv)) {
 		DRM_ERROR("No CSR support available for this platform\n");

@@ -251,9 +253,20 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
 		return;
 	}
 
+	fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
+						    CSR_PROGRAM(0),
+						    FW_REG_WRITE);
+
 	fw_size = dev_priv->csr.dmc_fw_size;
+	assert_rpm_wakelock_held(dev_priv);
+	spin_lock_irqsave(&dev_priv->uncore.lock, flags);
+	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
+
 	for (i = 0; i < fw_size; i++)
-		I915_WRITE(CSR_PROGRAM(i), payload[i]);
+		I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
+
+	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
+	spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
 
 	for (i = 0; i < dev_priv->csr.mmio_count; i++) {
 		I915_WRITE(dev_priv->csr.mmioaddr[i],
Signature · 6 lines
2.14.1

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
#1 lore raw

Quoting David Weinehall (2017-09-04 19:38:04)

Quoted 5 lines

v2: Per feedback from Chris & Ville there's no need to do the whole
forcewake dance, so lose that bit (Chris, Ville)

drivers/gpu/drm/i915/intel_csr.c +0 -0
@@ -251,9 +253,20 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
                return;

drivers/gpu/drm/i915/intel_csr.c void intel_csr_load_program(struct drm_i915_private *dev_priv) · line 263

Quoted 10 lines
drivers/gpu/drm/i915/intel_csr.c +7 -0
        }
 
+       fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
+                                                   CSR_PROGRAM(0),
+                                                   FW_REG_WRITE);
+
        fw_size = dev_priv->csr.dmc_fw_size;
+       assert_rpm_wakelock_held(dev_priv);
+       spin_lock_irqsave(&dev_priv->uncore.lock, flags);
+       intel_uncore_forcewake_get__locked(dev_priv, fw_domains);

Still there!
-Chris
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

author
#2 lore raw
Quoted 8 lines · Chris Wilson

Quoting David Weinehall (2017-09-04 19:38:04)

Quoted 7 lines

v2: Per feedback from Chris & Ville there's no need to do the whole
forcewake dance, so lose that bit (Chris, Ville)

(quoted diff) +0 -0
@@ -251,9 +253,20 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
                return;
        }
Quoted 10 lines

drivers/gpu/drm/i915/intel_csr.c void intel_csr_load_program(struct drm_i915_private *dev_priv) · line 263

Quoted 8 lines
drivers/gpu/drm/i915/intel_csr.c +7 -0
+       fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
+                                                   CSR_PROGRAM(0),
+                                                   FW_REG_WRITE);
+
        fw_size = dev_priv->csr.dmc_fw_size;
+       assert_rpm_wakelock_held(dev_priv);
+       spin_lock_irqsave(&dev_priv->uncore.lock, flags);
+       intel_uncore_forcewake_get__locked(dev_priv, fw_domains);

Still there!

Yeah, I missed the git add... Whooopsie; check v3.

Kind regards, David
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

CI
#3 lore raw

✓ Fi.CI.BAT: success for drm/i915: Speed up DMC firmware loading (rev2)

In reply to David Weinehall
== Series Details ==

== Series Details ==

Series: drm/i915: Speed up DMC firmware loading (rev2)
URL : https://patchwork.freedesktop.org/series/29688/
State : success

== Summary ==

Series 29688v2 drm/i915: Speed up DMC firmware loading
https://patchwork.freedesktop.org/api/1.0/series/29688/revisions/2/mbox/

Test chamelium:

        Subgroup dp-crc-fast:
                dmesg-fail -> PASS       (fi-kbl-7500u) fdo#102514
Test gem_exec_reloc:
        Subgroup basic-cpu-active:
                incomplete -> PASS       (fi-byt-j1900)
Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-atomic:
                fail       -> PASS       (fi-snb-2600) fdo#100215 +1
                dmesg-warn -> PASS       (fi-glk-2a)

fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215

fi-bdw-5557u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:457s
fi-bdw-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:432s
fi-blb-e6850     total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  time:362s
fi-bsw-n3050     total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  time:559s
fi-bwr-2160      total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 time:253s
fi-bxt-j4205     total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:518s
fi-byt-j1900     total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  time:519s
fi-byt-n2820     total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  time:514s
fi-cfl-s         total:288  pass:250  dwarn:4   dfail:0   fail:0   skip:34  time:461s
fi-elk-e7500     total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  time:429s
fi-glk-2a        total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:610s
fi-hsw-4770      total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  time:447s
fi-hsw-4770r     total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  time:425s
fi-ilk-650       total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:421s
fi-ivb-3520m     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:495s
fi-ivb-3770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:480s
fi-kbl-7500u     total:288  pass:264  dwarn:1   dfail:0   fail:0   skip:23  time:514s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:596s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:604s
fi-pnv-d510      total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:528s
fi-skl-6260u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:467s
fi-skl-6700k     total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:542s
fi-skl-6770hq    total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:516s
fi-skl-gvtdvm    total:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  time:444s
fi-skl-x1585l    total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:501s
fi-snb-2520m     total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  time:545s
fi-snb-2600      total:288  pass:249  dwarn:0   dfail:0   fail:1   skip:38  time:414s

233bea3d23383193c4dfab14828a1b156eb96575 drm-tip: 2017y-09m-04d-16h-58m-50s UTC integration manifest e82615b56b42 drm/i915: Speed up DMC firmware loading

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5576/
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

author
#4 lore raw

PATCH v3 1/1 drm/i915: Speed up DMC firmware loading

In reply to David Weinehall

Currently we're doing:

1. acquire lock
2. write word to hardware
3. release lock
4. repeat from 1

to load the DMC firmware. Due to the cost of acquiring/releasing a lock, and the size of the DMC firmware, this slows down DMC loading a lot.

This patch simply acquires the lock, writes the entire firmware, then releases the lock. Testing shows resume speedups in the order of 10ms on platforms with DMC firmware (GEN9+).

v2: Per feedback from Chris & Ville there's no need to do the whole
forcewake dance, so lose that bit (Chris, Ville)

v3: Actually send the new version of the patch...

Signed-off-by David Weinehall <[email protected]>
---
 drivers/gpu/drm/i915/intel_csr.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)
drivers/gpu/drm/i915/intel_csr.c +7 -1
index 965988f79a55..28ea24932ef1 100644
@@ -240,6 +240,7 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
 {
 	u32 *payload = dev_priv->csr.dmc_payload;
 	uint32_t i, fw_size;
+	unsigned long flags;
 
 	if (!HAS_CSR(dev_priv)) {
 		DRM_ERROR("No CSR support available for this platform\n");

@@ -252,8 +253,13 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
 	}
 
 	fw_size = dev_priv->csr.dmc_fw_size;
+	assert_rpm_wakelock_held(dev_priv);
+	spin_lock_irqsave(&dev_priv->uncore.lock, flags);
+
 	for (i = 0; i < fw_size; i++)
-		I915_WRITE(CSR_PROGRAM(i), payload[i]);
+		I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
+
+	spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
 
 	for (i = 0; i < dev_priv->csr.mmio_count; i++) {
 		I915_WRITE(dev_priv->csr.mmioaddr[i],
Signature · 6 lines
2.14.1

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
#5 lore raw

Quoting David Weinehall (2017-09-04 20:08:06)

Quoted 38 lines

Currently we're doing:

1. acquire lock
2. write word to hardware
3. release lock
4. repeat from 1

to load the DMC firmware. Due to the cost of acquiring/releasing a lock, and the size of the DMC firmware, this slows down DMC loading a lot.

This patch simply acquires the lock, writes the entire firmware, then releases the lock. Testing shows resume speedups in the order of 10ms on platforms with DMC firmware (GEN9+).

v2: Per feedback from Chris & Ville there's no need to do the whole
forcewake dance, so lose that bit (Chris, Ville)

v3: Actually send the new version of the patch...

Signed-off-by David Weinehall <[email protected]>
---
 drivers/gpu/drm/i915/intel_csr.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)
drivers/gpu/drm/i915/intel_csr.c +1 -0
index 965988f79a55..28ea24932ef1 100644
@@ -240,6 +240,7 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
 {
        u32 *payload = dev_priv->csr.dmc_payload;
        uint32_t i, fw_size;
+       unsigned long flags;
 
        if (!HAS_CSR(dev_priv)) {
                DRM_ERROR("No CSR support available for this platform\n");

@@ -252,8 +253,13 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
        }

drivers/gpu/drm/i915/intel_csr.c void intel_csr_load_program(struct drm_i915_private *dev_priv) · line 262

Quoted 10 lines
drivers/gpu/drm/i915/intel_csr.c +6 -1
 
        fw_size = dev_priv->csr.dmc_fw_size;
+       assert_rpm_wakelock_held(dev_priv);
+       spin_lock_irqsave(&dev_priv->uncore.lock, flags);
+
        for (i = 0; i < fw_size; i++)
-               I915_WRITE(CSR_PROGRAM(i), payload[i]);
+               I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
+
+       spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);

Still would like to see the version without the uncore.lock. Afaict, there isn't a requirement here -- unless you are serialising between multiple users (concurrent intel_csr_load_program?) of CSR_PROGRAM. -Chris
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

#6 lore raw

Quoting Chris Wilson (2017-09-04 20:14:32)

Quoted 40 lines

Quoting David Weinehall (2017-09-04 20:08:06)

Quoted 39 lines

Currently we're doing:

1. acquire lock
2. write word to hardware
3. release lock
4. repeat from 1

to load the DMC firmware. Due to the cost of acquiring/releasing a lock, and the size of the DMC firmware, this slows down DMC loading a lot.

This patch simply acquires the lock, writes the entire firmware, then releases the lock. Testing shows resume speedups in the order of 10ms on platforms with DMC firmware (GEN9+).

v2: Per feedback from Chris & Ville there's no need to do the whole
forcewake dance, so lose that bit (Chris, Ville)

v3: Actually send the new version of the patch...

Signed-off-by David Weinehall <[email protected]>
---
 drivers/gpu/drm/i915/intel_csr.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)
drivers/gpu/drm/i915/intel_csr.c +1 -0
index 965988f79a55..28ea24932ef1 100644
@@ -240,6 +240,7 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
 {
        u32 *payload = dev_priv->csr.dmc_payload;
        uint32_t i, fw_size;
+       unsigned long flags;
 
        if (!HAS_CSR(dev_priv)) {
                DRM_ERROR("No CSR support available for this platform\n");

@@ -252,8 +253,13 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
        }
Quoted 13 lines

drivers/gpu/drm/i915/intel_csr.c void intel_csr_load_program(struct drm_i915_private *dev_priv) · line 262

Quoted 9 lines
drivers/gpu/drm/i915/intel_csr.c +6 -1
        fw_size = dev_priv->csr.dmc_fw_size;
+       assert_rpm_wakelock_held(dev_priv);
+       spin_lock_irqsave(&dev_priv->uncore.lock, flags);
+
        for (i = 0; i < fw_size; i++)
-               I915_WRITE(CSR_PROGRAM(i), payload[i]);
+               I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
+
+       spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);

Still would like to see the version without the uncore.lock. Afaict, there isn't a requirement here -- unless you are serialising between multiple users (concurrent intel_csr_load_program?) of CSR_PROGRAM.

You may also want to consider a preempt_disable around this block as well, the argument being that we want the writes tightly grouped. -Chris
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

author
#7 lore raw
Quoted 55 lines · Chris Wilson

Quoting Chris Wilson (2017-09-04 20:14:32)

Quoted 40 lines

Quoting David Weinehall (2017-09-04 20:08:06)

Quoted 39 lines

Currently we're doing:

1. acquire lock
2. write word to hardware
3. release lock
4. repeat from 1

to load the DMC firmware. Due to the cost of acquiring/releasing a lock, and the size of the DMC firmware, this slows down DMC loading a lot.

This patch simply acquires the lock, writes the entire firmware, then releases the lock. Testing shows resume speedups in the order of 10ms on platforms with DMC firmware (GEN9+).

v2: Per feedback from Chris & Ville there's no need to do the whole
forcewake dance, so lose that bit (Chris, Ville)

v3: Actually send the new version of the patch...

Signed-off-by David Weinehall <[email protected]>
---
 drivers/gpu/drm/i915/intel_csr.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)
drivers/gpu/drm/i915/intel_csr.c +1 -0
index 965988f79a55..28ea24932ef1 100644
@@ -240,6 +240,7 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
 {
        u32 *payload = dev_priv->csr.dmc_payload;
        uint32_t i, fw_size;
+       unsigned long flags;
 
        if (!HAS_CSR(dev_priv)) {
                DRM_ERROR("No CSR support available for this platform\n");

@@ -252,8 +253,13 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
        }
Quoted 13 lines

drivers/gpu/drm/i915/intel_csr.c void intel_csr_load_program(struct drm_i915_private *dev_priv) · line 262

Quoted 9 lines
drivers/gpu/drm/i915/intel_csr.c +6 -1
        fw_size = dev_priv->csr.dmc_fw_size;
+       assert_rpm_wakelock_held(dev_priv);
+       spin_lock_irqsave(&dev_priv->uncore.lock, flags);
+
        for (i = 0; i < fw_size; i++)
-               I915_WRITE(CSR_PROGRAM(i), payload[i]);
+               I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
+
+       spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);

Still would like to see the version without the uncore.lock. Afaict, there isn't a requirement here -- unless you are serialising between multiple users (concurrent intel_csr_load_program?) of CSR_PROGRAM.

Quoted 3 lines

You may also want to consider a preempt_disable around this block as well, the argument being that we want the writes tightly grouped. -Chris

OK, I'll spin a non-spinning v4 tomorrow :)

Kind regards, David
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

CI
#8 lore raw

✓ Fi.CI.BAT: success for drm/i915: Speed up DMC firmware loading (rev3)

In reply to David Weinehall
== Series Details ==

== Series Details ==

Series: drm/i915: Speed up DMC firmware loading (rev3)
URL : https://patchwork.freedesktop.org/series/29688/
State : success

== Summary ==

Series 29688v3 drm/i915: Speed up DMC firmware loading
https://patchwork.freedesktop.org/api/1.0/series/29688/revisions/3/mbox/

Test kms_flip:

        Subgroup basic-flip-vs-modeset:
                skip       -> PASS       (fi-skl-x1585l) fdo#101781

fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:458s
fi-bdw-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:440s
fi-blb-e6850     total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  time:356s
fi-bsw-n3050     total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  time:562s
fi-bwr-2160      total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 time:253s
fi-bxt-j4205     total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:520s
fi-byt-j1900     total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  time:533s
fi-byt-n2820     total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  time:518s
fi-cfl-s         total:288  pass:250  dwarn:4   dfail:0   fail:0   skip:34  time:471s
fi-elk-e7500     total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  time:437s
fi-glk-2a        total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:616s
fi-hsw-4770      total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  time:446s
fi-hsw-4770r     total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  time:425s
fi-ilk-650       total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:424s
fi-ivb-3520m     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:497s
fi-ivb-3770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:472s
fi-kbl-7500u     total:288  pass:264  dwarn:1   dfail:0   fail:0   skip:23  time:510s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:599s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:603s
fi-pnv-d510      total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:530s
fi-skl-6260u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:469s
fi-skl-6700k     total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:544s
fi-skl-6770hq    total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:517s
fi-skl-gvtdvm    total:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  time:445s
fi-skl-x1585l    total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:504s
fi-snb-2520m     total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  time:559s
fi-snb-2600      total:288  pass:249  dwarn:0   dfail:0   fail:1   skip:38  time:407s

9dd459ef87a90495aac4cee73831f4cd694048ca drm-tip: 2017y-09m-04d-19h-10m-24s UTC integration manifest 292f6d3959ee drm/i915: Speed up DMC firmware loading

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5577/
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

CI
#9 lore raw

✗ Fi.CI.IGT: warning for drm/i915: Speed up DMC firmware loading (rev2)

In reply to David Weinehall
== Series Details ==

== Series Details ==

Series: drm/i915: Speed up DMC firmware loading (rev2)
URL : https://patchwork.freedesktop.org/series/29688/
State : warning

== Summary ==

Test kms_cursor_crc:

        Subgroup cursor-256x256-offscreen:
                pass       -> SKIP       (shard-hsw)
Test perf:
        Subgroup blocking:
                pass       -> FAIL       (shard-hsw) fdo#102252
Test kms_setmode:
        Subgroup basic:
                fail       -> PASS       (shard-hsw) fdo#99912

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hsw total:2265 pass:1231 dwarn:1 dfail:0 fail:16 skip:1017 time:9590s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5576/shards.html
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

CI
#10 lore raw

✗ Fi.CI.IGT: warning for drm/i915: Speed up DMC firmware loading (rev3)

In reply to David Weinehall
== Series Details ==

== Series Details ==

Series: drm/i915: Speed up DMC firmware loading (rev3)
URL : https://patchwork.freedesktop.org/series/29688/
State : warning

== Summary ==

Test tools_test:

        Subgroup tools_test:
                pass       -> DMESG-WARN (shard-hsw)

shard-hsw total:2265 pass:1232 dwarn:1 dfail:0 fail:16 skip:1016 time:9668s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5577/shards.html
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

author
#11 lore raw

PATCH v4 1/1 drm/i915: Speed up DMC firmware loading

In reply to David Weinehall

Currently we're doing:

1. acquire lock
2. write word to hardware
3. release lock
4. repeat from 1

to load the DMC firmware. Due to the cost of acquiring/releasing a lock, and the size of the DMC firmware, this slows down DMC loading a lot.

This patch simply acquires the lock, writes the entire firmware, then releases the lock. Testing shows resume speedups in the order of 10ms on platforms with DMC firmware (GEN9+).

v2: Per feedback from Chris & Ville there's no need to do the whole
forcewake dance, so lose that bit (Chris, Ville)

v3: Actually send the new version of the patch...

v4: Don't acquire the uncore lock. Disable preempt. (Chris)

Signed-off-by David Weinehall <[email protected]>
---
 drivers/gpu/drm/i915/intel_csr.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)
drivers/gpu/drm/i915/intel_csr.c +7 -1
index 965988f79a55..cdfb624eb82d 100644
@@ -252,8 +252,14 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
 	}
 
 	fw_size = dev_priv->csr.dmc_fw_size;
+	assert_rpm_wakelock_held(dev_priv);
+
+	preempt_disable();
+
 	for (i = 0; i < fw_size; i++)
-		I915_WRITE(CSR_PROGRAM(i), payload[i]);
+		I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
+
+	preempt_enable();
 
 	for (i = 0; i < dev_priv->csr.mmio_count; i++) {
 		I915_WRITE(dev_priv->csr.mmioaddr[i],
Signature · 6 lines
2.14.1

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
#12 lore raw

Quoting David Weinehall (2017-09-05 14:10:50)

Quoted 36 lines

Currently we're doing:

1. acquire lock
2. write word to hardware
3. release lock
4. repeat from 1

to load the DMC firmware. Due to the cost of acquiring/releasing a lock, and the size of the DMC firmware, this slows down DMC loading a lot.

This patch simply acquires the lock, writes the entire firmware, then releases the lock. Testing shows resume speedups in the order of 10ms on platforms with DMC firmware (GEN9+).

v2: Per feedback from Chris & Ville there's no need to do the whole
forcewake dance, so lose that bit (Chris, Ville)

v3: Actually send the new version of the patch...

v4: Don't acquire the uncore lock. Disable preempt. (Chris)

Signed-off-by David Weinehall <[email protected]>
---
 drivers/gpu/drm/i915/intel_csr.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)
drivers/gpu/drm/i915/intel_csr.c +2 -0
index 965988f79a55..cdfb624eb82d 100644
@@ -252,8 +252,14 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
        }
 
        fw_size = dev_priv->csr.dmc_fw_size;
+       assert_rpm_wakelock_held(dev_priv);
+

drivers/gpu/drm/i915/intel_csr.c void intel_csr_load_program(struct drm_i915_private *dev_priv) · line 265

Quoted 10 lines
drivers/gpu/drm/i915/intel_csr.c +5 -1
+       preempt_disable();
+
        for (i = 0; i < fw_size; i++)
-               I915_WRITE(CSR_PROGRAM(i), payload[i]);
+               I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
+
+       preempt_enable();
 
        for (i = 0; i < dev_priv->csr.mmio_count; i++) {
                I915_WRITE(dev_priv->csr.mmioaddr[i],

Looked into extending the coverage to the second loop? -Chris
_______________________________________________
Intel-gfx mailing list [email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

author
#13 lore raw
Quoted 45 lines · Chris Wilson

Quoting David Weinehall (2017-09-05 14:10:50)

Quoted 44 lines

Currently we're doing:

1. acquire lock
2. write word to hardware
3. release lock
4. repeat from 1

to load the DMC firmware. Due to the cost of acquiring/releasing a lock, and the size of the DMC firmware, this slows down DMC loading a lot.

This patch simply acquires the lock, writes the entire firmware, then releases the lock. Testing shows resume speedups in the order of 10ms on platforms with DMC firmware (GEN9+).

v2: Per feedback from Chris & Ville there's no need to do the whole
forcewake dance, so lose that bit (Chris, Ville)

v3: Actually send the new version of the patch...

v4: Don't acquire the uncore lock. Disable preempt. (Chris)

Signed-off-by David Weinehall <[email protected]>
---
 drivers/gpu/drm/i915/intel_csr.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)
drivers/gpu/drm/i915/intel_csr.c +7 -1
index 965988f79a55..cdfb624eb82d 100644
@@ -252,8 +252,14 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
        }
 
        fw_size = dev_priv->csr.dmc_fw_size;
+       assert_rpm_wakelock_held(dev_priv);
+
+       preempt_disable();
+
        for (i = 0; i < fw_size; i++)
-               I915_WRITE(CSR_PROGRAM(i), payload[i]);
+               I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
+
+       preempt_enable();
Quoted 4 lines

drivers/gpu/drm/i915/intel_csr.c void intel_csr_load_program(struct drm_i915_private *dev_priv) · line 265

Quoted 2 lines
drivers/gpu/drm/i915/intel_csr.c +0 -0
        for (i = 0; i < dev_priv->csr.mmio_count; i++) {
                I915_WRITE(dev_priv->csr.mmioaddr[i],

Looked into extending the coverage to the second loop?

The second loop didn't really show up in my benchmarks, so I decided to minimise the changes.

The only other I915_WRITE() loops that show up when measuring are the LUT loading; I'll fix those in a future patch.

Kind regards, David
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Reviewed-by
#14 lore raw

Quoting David Weinehall (2017-09-05 14:33:25)

Quoted 46 lines · Chris Wilson
Quoted 45 lines

Quoting David Weinehall (2017-09-05 14:10:50)

Quoted 44 lines

Currently we're doing:

1. acquire lock
2. write word to hardware
3. release lock
4. repeat from 1

to load the DMC firmware. Due to the cost of acquiring/releasing a lock, and the size of the DMC firmware, this slows down DMC loading a lot.

This patch simply acquires the lock, writes the entire firmware, then releases the lock. Testing shows resume speedups in the order of 10ms on platforms with DMC firmware (GEN9+).

v2: Per feedback from Chris & Ville there's no need to do the whole
forcewake dance, so lose that bit (Chris, Ville)

v3: Actually send the new version of the patch...

v4: Don't acquire the uncore lock. Disable preempt. (Chris)

Signed-off-by David Weinehall <[email protected]>
---
 drivers/gpu/drm/i915/intel_csr.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)
drivers/gpu/drm/i915/intel_csr.c +7 -1
index 965988f79a55..cdfb624eb82d 100644
@@ -252,8 +252,14 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
        }
 
        fw_size = dev_priv->csr.dmc_fw_size;
+       assert_rpm_wakelock_held(dev_priv);
+
+       preempt_disable();
+
        for (i = 0; i < fw_size; i++)
-               I915_WRITE(CSR_PROGRAM(i), payload[i]);
+               I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
+
+       preempt_enable();
Quoted 7 lines
Quoted 4 lines

drivers/gpu/drm/i915/intel_csr.c void intel_csr_load_program(struct drm_i915_private *dev_priv) · line 265

Quoted 2 lines
drivers/gpu/drm/i915/intel_csr.c +0 -0
        for (i = 0; i < dev_priv->csr.mmio_count; i++) {
                I915_WRITE(dev_priv->csr.mmioaddr[i],

Looked into extending the coverage to the second loop?

The second loop didn't really show up in my benchmarks, so I decided to minimise the changes.

Fair enough, looks like it is limited to 8 writes.

Reviewed-by Chris Wilson <[email protected]>

-Chris
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

CI
#15 lore raw

✓ Fi.CI.BAT: success for drm/i915: Speed up DMC firmware loading (rev4)

In reply to David Weinehall
== Series Details ==

== Series Details ==

Series: drm/i915: Speed up DMC firmware loading (rev4)
URL : https://patchwork.freedesktop.org/series/29688/
State : success

== Summary ==

Series 29688v4 drm/i915: Speed up DMC firmware loading
https://patchwork.freedesktop.org/api/1.0/series/29688/revisions/4/mbox/

Test kms_cursor_legacy:

        Subgroup basic-busy-flip-before-cursor-legacy:
                pass       -> FAIL       (fi-snb-2600) fdo#100215
Test kms_flip:
        Subgroup basic-flip-vs-modeset:
                pass       -> SKIP       (fi-skl-x1585l) fdo#101781

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u     total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:458s
fi-bdw-gvtdvm    total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:437s
fi-blb-e6850     total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  time:366s
fi-bsw-n3050     total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  time:569s
fi-bwr-2160      total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 time:254s
fi-bxt-j4205     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:530s
fi-byt-j1900     total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  time:522s
fi-byt-n2820     total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  time:513s
fi-elk-e7500     total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  time:439s
fi-glk-2a        total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:603s
fi-hsw-4770      total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:444s
fi-hsw-4770r     total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:423s
fi-ilk-650       total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  time:424s
fi-ivb-3520m     total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:509s
fi-ivb-3770      total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:480s
fi-kbl-7500u     total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  time:512s
fi-kbl-7560u     total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  time:600s
fi-kbl-r         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:600s
fi-skl-6260u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:480s
fi-skl-6700k     total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:532s
fi-skl-6770hq    total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:511s
fi-skl-gvtdvm    total:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  time:445s
fi-skl-x1585l    total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:487s
fi-snb-2520m     total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  time:563s
fi-snb-2600      total:289  pass:249  dwarn:0   dfail:0   fail:1   skip:39  time:408s

fi-pnv-d510 failed to connect after reboot

229aae71d40f142bc0fbc011d6610ac4ddbd7cd6 drm-tip: 2017y-09m-05d-11h-05m-56s UTC integration manifest 9d504cd2b50c drm/i915: Speed up DMC firmware loading

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5581/
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

CI
#16 lore raw

✓ Fi.CI.IGT: success for drm/i915: Speed up DMC firmware loading (rev4)

In reply to David Weinehall
== Series Details ==

== Series Details ==

Series: drm/i915: Speed up DMC firmware loading (rev4)
URL : https://patchwork.freedesktop.org/series/29688/
State : success

== Summary ==

shard-hsw total:2255 pass:1225 dwarn:0 dfail:0 fail:15 skip:1014 time:9484s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5581/shards.html
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

#17 lore raw

Re: ✓ Fi.CI.IGT: success for drm/i915: Speed up DMC firmware loading (rev4)

Quoting Patchwork (2017-09-05 16:10:55)

Quoted 9 lines

== Series Details ==

Series: drm/i915: Speed up DMC firmware loading (rev4)
URL : https://patchwork.freedesktop.org/series/29688/
State : success

== Summary ==

shard-hsw total:2255 pass:1225 dwarn:0 dfail:0 fail:15 skip:1014 time:9484s

And pushed. Thanks for the patch and the poke.
-Chris
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx