drm/i915/gen8+: Init/reset display interrupts only if i915 IRQs are enabled
Subsystems (2)
PATCH 1/1 drm/i915/gen8+: Init/reset display interrupts only if i915 IRQs are enabled
Only init / reset the display interrupts during power well enabling / disabling if the i915 interrupts are enabled. So far we did the init / reset during driver loading / resuming too, where initialization / enabling of the i915 interrupts happens only at a later point. This didn't cause a problem due to GEN8_MASTER_IRQ_CONTROL being cleared, but triggered gen3_assert_iir_is_zero() in GEN8_IRQ_INIT_NDX().
References: https://bugs.freedesktop.org/show_bug.cgi?id=102988
--- drivers/gpu/drm/i915/i915_irq.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
drivers/gpu/drm/i915/i915_irq.c +14 -0
@@ -3132,10 +3132,17 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,enum pipe pipe;spin_lock_irq (&dev_priv->irq_lock); + +if (!intel_irqs_enabled (dev_priv)) { +spin_unlock_irq (&dev_priv->irq_lock); +return ; + } +for_each_pipe_masked (dev_priv, pipe, pipe_mask)GEN8_IRQ_INIT_NDX (DE_PIPE , pipe, dev_priv->de_irq_mask[pipe], ~dev_priv->de_irq_mask[pipe] | extra_ier); +spin_unlock_irq (&dev_priv->irq_lock); }
@@ -3145,8 +3152,15 @@ void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,enum pipe pipe;spin_lock_irq (&dev_priv->irq_lock); + +if (!intel_irqs_enabled (dev_priv)) { +spin_unlock_irq (&dev_priv->irq_lock); +return ; + } +for_each_pipe_masked (dev_priv, pipe, pipe_mask)GEN8_IRQ_RESET_NDX (DE_PIPE , pipe); +spin_unlock_irq (&dev_priv->irq_lock);/* make sure we're done processing display irqs */
Signature · 6 lines
2.13.2 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoting Imre Deak (2017-09-28 11:06:24)
Quoted 10 lines
Only init / reset the display interrupts during power well enabling / disabling if the i915 interrupts are enabled. So far we did the init / reset during driver loading / resuming too, where initialization / enabling of the i915 interrupts happens only at a later point. This didn't cause a problem due to
GEN8_MASTER_IRQ_CONTROLbeing cleared, but triggeredgen3_assert_iir_is_zero()inGEN8_IRQ_INIT_NDX().References: https://bugs.freedesktop.org/show_bug.cgi?id=102988
Cc Chris Wilson <[email protected]>Signed-off-by Imre Deak <[email protected]>
Patch makes sense, so
There's an irq powerwell! When is it taken? We don't take it for GT as far as I am aware (we should for execlists plus whenever we enable the user interrupt). Should we?
-Chris
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Quoted 8 lines · Chris Wilson
Quoting Imre Deak (2017-09-28 11:06:24)
Quoted 7 lines
Only init / reset the display interrupts during power well enabling / disabling if the i915 interrupts are enabled. So far we did the init / reset during driver loading / resuming too, where initialization / enabling of the i915 interrupts happens only at a later point. This didn't cause a problem due to
GEN8_MASTER_IRQ_CONTROLbeing cleared, but triggeredgen3_assert_iir_is_zero()inGEN8_IRQ_INIT_NDX().
Quoted 6 lines
Quoted 3 lines
References: https://bugs.freedesktop.org/show_bug.cgi?id=102988
Cc Chris Wilson <[email protected]>Signed-off-by Imre Deak <[email protected]>Patch makes sense, so
Reviewed-by Chris Wilson <[email protected]>
Thanks.
Quoted 4 lines
There's an irq powerwell! When is it taken? We don't take it for GT as far as I am aware (we should for execlists plus whenever we enable the user interrupt). Should we?
Only the display interrupt registers have a power well that we toggle from the driver (display power well/power well 2). The rest of interrupt regs including the GT ones are backed by a power well that the HW/DMC FW toggles automatically (always-on power well/power well 0). So no need to take it explicitly; there is the slow-down problem where the context restore during such enabling by DMC adds overhead, which will be solved by Tvrtko's WA.
--Imre
Quoted 1 line
-Chris
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Quoting Imre Deak (2017-09-28 12:59:16)
Quoted 23 lines · Chris Wilson
Quoted 8 lines
Quoting Imre Deak (2017-09-28 11:06:24)
Quoted 7 lines
Only init / reset the display interrupts during power well enabling / disabling if the i915 interrupts are enabled. So far we did the init / reset during driver loading / resuming too, where initialization / enabling of the i915 interrupts happens only at a later point. This didn't cause a problem due to
GEN8_MASTER_IRQ_CONTROLbeing cleared, but triggeredgen3_assert_iir_is_zero()inGEN8_IRQ_INIT_NDX().Quoted 6 lines
Quoted 3 lines
References: https://bugs.freedesktop.org/show_bug.cgi?id=102988
Cc Chris Wilson <[email protected]>Signed-off-by Imre Deak <[email protected]>Patch makes sense, so
Reviewed-by Chris Wilson <[email protected]>Thanks.
Quoted 4 lines
There's an irq powerwell! When is it taken? We don't take it for GT as far as I am aware (we should for execlists plus whenever we enable the user interrupt). Should we?
Quoted 7 lines
Only the display interrupt registers have a power well that we toggle from the driver (display power well/power well 2). The rest of interrupt regs including the GT ones are backed by a power well that the HW/DMC FW toggles automatically (always-on power well/power well 0). So no need to take it explicitly; there is the slow-down problem where the context restore during such enabling by DMC adds overhead, which will be solved by Tvrtko's WA.
For that w/a can we make the powerwell request more explicit? Instead of POWERWLL_MODESET maybe POWERWELL_GT_IRQ?
-Chris
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Quoted 32 lines · Chris Wilson
Quoting Imre Deak (2017-09-28 12:59:16)
Quoted 23 lines · Chris Wilson
Quoted 8 lines
Quoting Imre Deak (2017-09-28 11:06:24)
Quoted 7 lines
Only init / reset the display interrupts during power well enabling / disabling if the i915 interrupts are enabled. So far we did the init / reset during driver loading / resuming too, where initialization / enabling of the i915 interrupts happens only at a later point. This didn't cause a problem due to
GEN8_MASTER_IRQ_CONTROLbeing cleared, but triggeredgen3_assert_iir_is_zero()inGEN8_IRQ_INIT_NDX().Quoted 6 lines
Quoted 3 lines
References: https://bugs.freedesktop.org/show_bug.cgi?id=102988
Cc Chris Wilson <[email protected]>Signed-off-by Imre Deak <[email protected]>Patch makes sense, so
Reviewed-by Chris Wilson <[email protected]>Thanks.
Quoted 4 lines
There's an irq powerwell! When is it taken? We don't take it for GT as far as I am aware (we should for execlists plus whenever we enable the user interrupt). Should we?
Quoted 7 lines
Only the display interrupt registers have a power well that we toggle from the driver (display power well/power well 2). The rest of interrupt regs including the GT ones are backed by a power well that the HW/DMC FW toggles automatically (always-on power well/power well 0). So no need to take it explicitly; there is the slow-down problem where the context restore during such enabling by DMC adds overhead, which will be solved by Tvrtko's WA.
Quoted 2 lines
For that w/a can we make the powerwell request more explicit? Instead of
POWERWLL_MODESETmaybePOWERWELL_GT_IRQ?
Yes, sounds good to have a power domain for this purpose.
--Imre
Quoted 1 line
-Chris
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Patchwork
CI✗ Fi.CI.BAT: warning for drm/i915/gen8+: Init/reset display interrupts only if i915 IRQs are enabled
In reply to Imre Deak== Series Details ==
== Series Details ==
Series: drm/i915/gen8+: Init/reset display interrupts only if i915 IRQs are enabled
URL : https://patchwork.freedesktop.org/series/31058/
State : warning
== Summary ==
Series 31058v1 drm/i915/gen8+: Init/reset display interrupts only if i915 IRQs are enabled
https://patchwork.freedesktop.org/api/1.0/series/31058/revisions/1/mbox/
Test kms_force_connector_basic:
Subgroup force-connector-state:
pass -> SKIP (fi-ivb-3520m)
Subgroup force-edid:
pass -> SKIP (fi-ivb-3520m)
Subgroup force-load-detect:
pass -> SKIP (fi-ivb-3520m)
Subgroup prune-stale-modes:
pass -> SKIP (fi-ivb-3520m)fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:443s fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:473s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:415s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:511s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:281s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:504s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:508s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:500s fi-cnl-y total:289 pass:258 dwarn:0 dfail:0 fail:4 skip:27 time:643s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:413s fi-glk-1 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:562s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:427s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:402s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:433s fi-ivb-3520m total:289 pass:257 dwarn:0 dfail:0 fail:0 skip:32 time:485s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:470s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:470s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:620s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:589s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:544s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:452s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:746s fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:491s fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:475s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:572s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:417s
c1ed501217782b35094792696924a1d22ee83c0f drm-tip: 2017y-09m-28d-04h-52m-47s UTC integration manifest 052c5c13b17f drm/i915/gen8+: Init/reset display interrupts only if i915 IRQs are enabled
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5845/
_______________________________________________
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[email protected]
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Patchwork
CI✗ Fi.CI.BAT: warning for drm/i915/gen8+: Init/reset display interrupts only if i915 IRQs are enabled
In reply to Imre Deak== Series Details ==
== Series Details ==
Series: drm/i915/gen8+: Init/reset display interrupts only if i915 IRQs are enabled
URL : https://patchwork.freedesktop.org/series/31058/
State : warning
== Summary ==
Series 31058v1 drm/i915/gen8+: Init/reset display interrupts only if i915 IRQs are enabled
https://patchwork.freedesktop.org/api/1.0/series/31058/revisions/1/mbox/
Test chamelium:
Subgroup hdmi-crc-fast:
pass -> DMESG-WARN (fi-skl-6700k) fdo#103019
Test gem_exec_suspend:
Subgroup basic-s3:
pass -> DMESG-WARN (fi-cfl-s)
Subgroup basic-s4-devices:
dmesg-warn -> PASS (fi-cfl-s) fdo#102294 +20
Test kms_frontbuffer_tracking:
Subgroup basic:
dmesg-warn -> PASS (fi-cfl-s) fdo#102374
Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-c:
incomplete -> SKIP (fi-cfl-s) fdo#103022
Test drv_module_reload:
Subgroup basic-reload:
pass -> DMESG-WARN (fi-glk-1) fdo#102777fdo#103019 https://bugs.freedesktop.org/show_bug.cgi?id=103019
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294
fdo#102374 https://bugs.freedesktop.org/show_bug.cgi?id=102374
fdo#103022 https://bugs.freedesktop.org/show_bug.cgi?id=103022
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:443s fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:475s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:425s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:519s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:280s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:505s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:509s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:503s fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 time:546s fi-cnl-y total:289 pass:259 dwarn:0 dfail:0 fail:3 skip:27 time:671s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:420s fi-glk-1 total:289 pass:259 dwarn:1 dfail:0 fail:0 skip:29 time:568s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:425s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:405s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:440s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:495s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:469s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:471s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:582s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:589s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:554s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:455s fi-skl-6700k total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:756s fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:494s fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:476s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:570s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:429s
c1ed501217782b35094792696924a1d22ee83c0f drm-tip: 2017y-09m-28d-04h-52m-47s UTC integration manifest 3b58c2e42208 drm/i915/gen8+: Init/reset display interrupts only if i915 IRQs are enabled
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5846/
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Re: ✗ Fi.CI.BAT: warning for drm/i915/gen8+: Init/reset display interrupts only if i915 IRQs are enabled
Quoted 11 lines · Patchwork
== Series Details ==
Series: drm/i915/gen8+: Init/reset display interrupts only if i915 IRQs are enabled
URL : https://patchwork.freedesktop.org/series/31058/
State : warning== Summary ==
Series 31058v1 drm/i915/gen8+: Init/reset display interrupts only if i915 IRQs are enabled
https://patchwork.freedesktop.org/api/1.0/series/31058/revisions/1/mbox/
Quoted 6 lines
Test chamelium:
Subgroup hdmi-crc-fast: pass -> DMESG-WARN (fi-skl-6700k) fdo#103019 Test gem_exec_suspend: Subgroup basic-s3: pass -> DMESG-WARN (fi-cfl-s)
[ 208.434941] ======================================================
[ 208.434941] WARNING: possible circular locking dependency detected
[ 208.434942] 4.14.0-rc2-CI-Patchwork_5846+ #1 Tainted: G U
[ 208.434943] ------------------------------------------------------
[ 208.434944] rtcwake/3287 is trying to acquire lock:
[ 208.434944] ((complete)&st->done){+.+.}, at: [<ffffffff81909e0d>] wait_for_completion+0x1d/0x20
[ 208.434948]
but task is already holding lock:
[ 208.434948] (sparse_irq_lock){+.+.}, at: [<ffffffff810f22e7>] irq_lock_sparse+0x17/0x20looks like
https://bugs.freedesktop.org/show_bug.cgi?id=103026
The rest look like independent pre-existing issues based on the fdo links.
Thanks for the review, I pushed the patch to -dinq.
Quoted 46 lines
Subgroup basic-s4-devices: dmesg-warn -> PASS (fi-cfl-s) fdo#102294 +20 Test kms_frontbuffer_tracking: Subgroup basic: dmesg-warn -> PASS (fi-cfl-s) fdo#102374 Test kms_pipe_crc_basic: Subgroup nonblocking-crc-pipe-c: incomplete -> SKIP (fi-cfl-s) fdo#103022 Test drv_module_reload: Subgroup basic-reload: pass -> DMESG-WARN (fi-glk-1) fdo#102777fdo#103019 https://bugs.freedesktop.org/show_bug.cgi?id=103019
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294
fdo#102374 https://bugs.freedesktop.org/show_bug.cgi?id=102374
fdo#103022 https://bugs.freedesktop.org/show_bug.cgi?id=103022
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:443s fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:475s fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:425s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:519s fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:280s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:505s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:509s fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:503s fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 time:546s fi-cnl-y total:289 pass:259 dwarn:0 dfail:0 fail:3 skip:27 time:671s fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:420s fi-glk-1 total:289 pass:259 dwarn:1 dfail:0 fail:0 skip:29 time:568s fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:425s fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:405s fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:440s fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:495s fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:469s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:471s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:582s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:589s fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:554s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:455s fi-skl-6700k total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:756s fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:494s fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:476s fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:570s fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:429s
Quoted 6 lines
c1ed501217782b35094792696924a1d22ee83c0fdrm-tip: 2017y-09m-28d-04h-52m-47s UTC integration manifest3b58c2e42208drm/i915/gen8+: Init/reset display interrupts only if i915 IRQs are enabled== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5846/
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