Andes(nds32) Linux Kernel Port
Subsystems (11)
v2 cover Andes(nds32) Linux Kernel Port
This is the 2nd version patchset to add the Linux kernel port for Andes(nds32) processors. Almost all of the feedback from v1 patchseries has been addressed. Thanks to everyone who provided feedback on the previous version.
This patchset adds core architecture support to Linux for Andestech's N13, N15, D15, N10, D10 processor cores.
Based on the 16/32-bit AndeStar RISC-like architecture, we designed the configurable AndesCore series of embedded processor families. AndesCores range from highly performance-efficient small-footprint cores for microcontrollers and deeply-embedded applications to 1GHz+ cores running Linux, covering general-purpose N-series cores for a wide range of computing need, DSP-capable D-series cores for digital signal control, instruction-extensible E-series cores for application-specific acceleration, and secure S-series cores for best protection of the most valuable.
The patches are based on v4.14-rc8, and can also be found in the following git tree:
https://github.com/andestech/linux.git nds32-4.14-rc8-v2
The build script and toolchain repositories are able to be found here:
https://github.com/andestech/build_script.git
Freely available instruction set and architecture overview documents can be found on the following page:
http://www.andestech.com/product.php?cls=9
Vincent Ren-Wei Chen and I will maintain this port. Thanks to everyone who helped us and contributed to it. :) Any feedback is welcome.
Changes in v2:
- Set GENERIC_CALIBRATE_DELAY default n
- Add earlycon support
- Remove earlyprintk
- Add CPU_BIG_ENDIAN, CPU_LITTLE_ENDIAN support
- Refine unalignment access exception handler
- Add VMSPLIT support
- Use only one defconfig
- Change interrupt-cells from 2 to 1
- Refine andestech cpu names in bindings/nds32/cpus.txt
- Get clock frequency in dts because fpga bitmap doesn't include this feature
- Update MAINTAINERS for bindings
- Remove unused configs in Kconfig
- Refine device tree scripts
- Refine coding style
- Use generic ioremap_nocache
- Remove L2CC_PA_BASE define and its codes in head.S. It will be moved to bootloader.
- Set PHYS_OFFSET to 0x0 instead of CONFIG_MEMORY_START
- Remove unused macros
- Simplify cpu_cache_* API
- Change __asm__ __volatile__ to asm volatile
- Refine uaccess.h
- Remove unused/deprecated syscall
- Use generic posix_types.h
- Remove arch_trace_hardirqs_on/arch_trace_hardirqs_off
- Fix bug of restart syscall
- Refine syscall implementations
- Use IS_ENABLED to replace ifdef as possible
- Remove device_initcall(nds32_device_probe)
- Refine vdso implementations
- Refine copy_from_user()/copy_to_user()/clear_user()/get_user()/memmove()/memcpy()
- Refine ioremap.c
- Refine irq-ativic32.c
- Fix a bug of earlycon.c
- Export ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt
- Add atcpit100 driver
Greentime Hu (32):
nds32: Assembly macros and definitions
nds32: Kernel booting and initialization
nds32: Exception handling
nds32: MMU definitions
nds32: MMU initialization
nds32: MMU fault handling and page table management
nds32: Cache and TLB routines
nds32: Process management
nds32: IRQ handling
nds32: Atomic operations
nds32: Device specific operations
nds32: DMA mapping API
nds32: ELF definitions
nds32: System calls handling
nds32: VDSO support
nds32: Signal handling support
nds32: Library functions
nds32: Debugging support
nds32: L2 cache support
nds32: Loadable modules
nds32: Generic timers support
nds32: Device tree support
nds32: Miscellaneous header files
nds32: defconfig
nds32: Build infrastructure
dt-bindings: interrupt-controller: Andestech Internal Vector
Interrupt Controller
irqchip: Andestech Internal Vector Interrupt Controller driver
MAINTAINERS: Add nds32
dt-bindings: nds32 CPU Bindings
net: faraday add nds32 support.
earlycon: add reg-offset to physical address before mapping asm-generic/io.h: move
ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef
CONFIG_MMU
Rick Chen (3):
clocksource/drivers/atcpit100: Add andestech atcpit100 timer clocksource/drivers/Kconfig: Support andestech atcpit100 timer
dt-bindings: timer: Add andestech atcpit100 timer binding doc
.../interrupt-controller/andestech,ativic32.txt | 19 + Documentation/devicetree/bindings/nds32/cpus.txt | 32 + .../bindings/timer/andestech,atcpit100-timer.txt | 33 + MAINTAINERS | 11 + arch/nds32/Kconfig | 107 +++ arch/nds32/Kconfig.cpu | 131 +++ arch/nds32/Makefile | 66 ++ arch/nds32/boot/Makefile | 15 + arch/nds32/boot/dts/Makefile | 8 + arch/nds32/boot/dts/ae3xx.dts | 55 ++ arch/nds32/boot/dts/ag101p.dts | 60 ++ arch/nds32/configs/defconfig | 111 +++ arch/nds32/include/asm/Kbuild | 54 ++ arch/nds32/include/asm/assembler.h | 52 ++ arch/nds32/include/asm/bitfield.h | 974 ++++++++++++++++++++ arch/nds32/include/asm/cache.h | 25 + arch/nds32/include/asm/cache_info.h | 26 + arch/nds32/include/asm/cacheflush.h | 57 ++ arch/nds32/include/asm/current.h | 25 + arch/nds32/include/asm/delay.h | 51 + arch/nds32/include/asm/dma-mapping.h | 27 + arch/nds32/include/asm/elf.h | 192 ++++ arch/nds32/include/asm/fixmap.h | 42 + arch/nds32/include/asm/futex.h | 116 +++ arch/nds32/include/asm/highmem.h | 78 ++ arch/nds32/include/asm/io.h | 25 + arch/nds32/include/asm/irqflags.h | 49 + arch/nds32/include/asm/l2_cache.h | 155 ++++ arch/nds32/include/asm/linkage.h | 24 + arch/nds32/include/asm/memory.h | 118 +++ arch/nds32/include/asm/mmu.h | 25 + arch/nds32/include/asm/mmu_context.h | 81 ++ arch/nds32/include/asm/module.h | 24 + arch/nds32/include/asm/nds32.h | 96 ++ arch/nds32/include/asm/page.h | 78 ++ arch/nds32/include/asm/pgalloc.h | 109 +++ arch/nds32/include/asm/pgtable.h | 426 +++++++++ arch/nds32/include/asm/proc-fns.h | 57 ++ arch/nds32/include/asm/processor.h | 116 +++ arch/nds32/include/asm/ptrace.h | 79 ++ arch/nds32/include/asm/shmparam.h | 32 + arch/nds32/include/asm/spinlock.h | 184 ++++ arch/nds32/include/asm/string.h | 30 + arch/nds32/include/asm/swab.h | 48 + arch/nds32/include/asm/syscall.h | 203 ++++ arch/nds32/include/asm/syscalls.h | 27 + arch/nds32/include/asm/thread_info.h | 91 ++ arch/nds32/include/asm/tlb.h | 41 + arch/nds32/include/asm/tlbflush.h | 60 ++ arch/nds32/include/asm/uaccess.h | 296 ++++++ arch/nds32/include/asm/unistd.h | 19 + arch/nds32/include/asm/vdso.h | 35 + arch/nds32/include/asm/vdso_datapage.h | 51 + arch/nds32/include/uapi/asm/Kbuild | 27 + arch/nds32/include/uapi/asm/auxvec.h | 25 + arch/nds32/include/uapi/asm/byteorder.h | 26 + arch/nds32/include/uapi/asm/cachectl.h | 19 + arch/nds32/include/uapi/asm/param.h | 24 + arch/nds32/include/uapi/asm/ptrace.h | 42 + arch/nds32/include/uapi/asm/sigcontext.h | 73 ++ arch/nds32/include/uapi/asm/signal.h | 23 + arch/nds32/include/uapi/asm/unistd.h | 32 + arch/nds32/kernel/Makefile | 23 + arch/nds32/kernel/asm-offsets.c | 41 + arch/nds32/kernel/atl2c.c | 77 ++ arch/nds32/kernel/cacheinfo.c | 62 ++ arch/nds32/kernel/devtree.c | 45 + arch/nds32/kernel/dma.c | 472 ++++++++++ arch/nds32/kernel/ex-entry.S | 170 ++++ arch/nds32/kernel/ex-exit.S | 206 +++++ arch/nds32/kernel/ex-scall.S | 145 +++ arch/nds32/kernel/head.S | 198 ++++ arch/nds32/kernel/irq.c | 22 + arch/nds32/kernel/module.c | 299 ++++++ arch/nds32/kernel/nds32_ksyms.c | 44 + arch/nds32/kernel/process.c | 217 +++++ arch/nds32/kernel/ptrace.c | 325 +++++++ arch/nds32/kernel/setup.c | 407 ++++++++ arch/nds32/kernel/signal.c | 354 +++++++ arch/nds32/kernel/stacktrace.c | 60 ++ arch/nds32/kernel/sys_nds32.c | 74 ++ arch/nds32/kernel/syscall_table.c | 28 + arch/nds32/kernel/time.c | 22 + arch/nds32/kernel/traps.c | 441 +++++++++ arch/nds32/kernel/vdso.c | 245 +++++ arch/nds32/kernel/vdso/Makefile | 82 ++ arch/nds32/kernel/vdso/datapage.S | 34 + arch/nds32/kernel/vdso/gen_vdso_offsets.sh | 15 + arch/nds32/kernel/vdso/gettimeofday.c | 266 ++++++ arch/nds32/kernel/vdso/note.S | 29 + arch/nds32/kernel/vdso/sigreturn.S | 33 + arch/nds32/kernel/vdso/vdso.S | 33 + arch/nds32/kernel/vdso/vdso.lds.S | 87 ++ arch/nds32/kernel/vmlinux.lds.S | 70 ++ arch/nds32/lib/Makefile | 3 + arch/nds32/lib/clear_user.S | 55 ++ arch/nds32/lib/copy_from_user.S | 58 ++ arch/nds32/lib/copy_page.S | 50 + arch/nds32/lib/copy_template.S | 83 ++ arch/nds32/lib/copy_to_user.S | 58 ++ arch/nds32/lib/memcpy.S | 43 + arch/nds32/lib/memmove.S | 83 ++ arch/nds32/lib/memset.S | 46 + arch/nds32/lib/memzero.S | 31 + arch/nds32/mm/Makefile | 7 + arch/nds32/mm/alignment.c | 622 +++++++++++++ arch/nds32/mm/cacheflush.c | 331 +++++++ arch/nds32/mm/extable.c | 29 + arch/nds32/mm/fault.c | 420 +++++++++ arch/nds32/mm/highmem.c | 92 ++ arch/nds32/mm/init.c | 318 +++++++ arch/nds32/mm/ioremap.c | 75 ++ arch/nds32/mm/mm-nds32.c | 103 +++ arch/nds32/mm/mmap.c | 86 ++ arch/nds32/mm/proc.c | 601 ++++++++++++ arch/nds32/mm/tlb.c | 63 ++ drivers/clocksource/Kconfig | 6 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-atcpit100.c | 247 +++++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-ativic32.c | 119 +++ drivers/net/ethernet/faraday/Kconfig | 6 +- drivers/tty/serial/earlycon.c | 3 +- include/asm-generic/io.h | 18 +- 124 files changed, 13508 insertions(+), 13 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt create mode 100644 Documentation/devicetree/bindings/nds32/cpus.txt create mode 100644 Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt create mode 100644 arch/nds32/Kconfig create mode 100644 arch/nds32/Kconfig.cpu create mode 100644 arch/nds32/Makefile create mode 100644 arch/nds32/boot/Makefile create mode 100644 arch/nds32/boot/dts/Makefile create mode 100644 arch/nds32/boot/dts/ae3xx.dts create mode 100644 arch/nds32/boot/dts/ag101p.dts create mode 100644 arch/nds32/configs/defconfig create mode 100644 arch/nds32/include/asm/Kbuild create mode 100644 arch/nds32/include/asm/assembler.h create mode 100644 arch/nds32/include/asm/bitfield.h create mode 100644 arch/nds32/include/asm/cache.h create mode 100644 arch/nds32/include/asm/cache_info.h create mode 100644 arch/nds32/include/asm/cacheflush.h create mode 100644 arch/nds32/include/asm/current.h create mode 100644 arch/nds32/include/asm/delay.h create mode 100644 arch/nds32/include/asm/dma-mapping.h create mode 100644 arch/nds32/include/asm/elf.h create mode 100644 arch/nds32/include/asm/fixmap.h create mode 100644 arch/nds32/include/asm/futex.h create mode 100644 arch/nds32/include/asm/highmem.h create mode 100644 arch/nds32/include/asm/io.h create mode 100644 arch/nds32/include/asm/irqflags.h create mode 100644 arch/nds32/include/asm/l2_cache.h create mode 100644 arch/nds32/include/asm/linkage.h create mode 100644 arch/nds32/include/asm/memory.h create mode 100644 arch/nds32/include/asm/mmu.h create mode 100644 arch/nds32/include/asm/mmu_context.h create mode 100644 arch/nds32/include/asm/module.h create mode 100644 arch/nds32/include/asm/nds32.h create mode 100644 arch/nds32/include/asm/page.h create mode 100644 arch/nds32/include/asm/pgalloc.h create mode 100644 arch/nds32/include/asm/pgtable.h create mode 100644 arch/nds32/include/asm/proc-fns.h create mode 100644 arch/nds32/include/asm/processor.h create mode 100644 arch/nds32/include/asm/ptrace.h create mode 100644 arch/nds32/include/asm/shmparam.h create mode 100644 arch/nds32/include/asm/spinlock.h create mode 100644 arch/nds32/include/asm/string.h create mode 100644 arch/nds32/include/asm/swab.h create mode 100644 arch/nds32/include/asm/syscall.h create mode 100644 arch/nds32/include/asm/syscalls.h create mode 100644 arch/nds32/include/asm/thread_info.h create mode 100644 arch/nds32/include/asm/tlb.h create mode 100644 arch/nds32/include/asm/tlbflush.h create mode 100644 arch/nds32/include/asm/uaccess.h create mode 100644 arch/nds32/include/asm/unistd.h create mode 100644 arch/nds32/include/asm/vdso.h create mode 100644 arch/nds32/include/asm/vdso_datapage.h create mode 100644 arch/nds32/include/uapi/asm/Kbuild create mode 100644 arch/nds32/include/uapi/asm/auxvec.h create mode 100644 arch/nds32/include/uapi/asm/byteorder.h create mode 100644 arch/nds32/include/uapi/asm/cachectl.h create mode 100644 arch/nds32/include/uapi/asm/param.h create mode 100644 arch/nds32/include/uapi/asm/ptrace.h create mode 100644 arch/nds32/include/uapi/asm/sigcontext.h create mode 100644 arch/nds32/include/uapi/asm/signal.h create mode 100644 arch/nds32/include/uapi/asm/unistd.h create mode 100644 arch/nds32/kernel/Makefile create mode 100644 arch/nds32/kernel/asm-offsets.c create mode 100644 arch/nds32/kernel/atl2c.c create mode 100644 arch/nds32/kernel/cacheinfo.c create mode 100644 arch/nds32/kernel/devtree.c create mode 100644 arch/nds32/kernel/dma.c create mode 100644 arch/nds32/kernel/ex-entry.S create mode 100644 arch/nds32/kernel/ex-exit.S create mode 100644 arch/nds32/kernel/ex-scall.S create mode 100644 arch/nds32/kernel/head.S create mode 100644 arch/nds32/kernel/irq.c create mode 100644 arch/nds32/kernel/module.c create mode 100644 arch/nds32/kernel/nds32_ksyms.c create mode 100644 arch/nds32/kernel/process.c create mode 100644 arch/nds32/kernel/ptrace.c create mode 100644 arch/nds32/kernel/setup.c create mode 100644 arch/nds32/kernel/signal.c create mode 100644 arch/nds32/kernel/stacktrace.c create mode 100644 arch/nds32/kernel/sys_nds32.c create mode 100644 arch/nds32/kernel/syscall_table.c create mode 100644 arch/nds32/kernel/time.c create mode 100644 arch/nds32/kernel/traps.c create mode 100644 arch/nds32/kernel/vdso.c create mode 100644 arch/nds32/kernel/vdso/Makefile create mode 100644 arch/nds32/kernel/vdso/datapage.S create mode 100755 arch/nds32/kernel/vdso/gen_vdso_offsets.sh create mode 100644 arch/nds32/kernel/vdso/gettimeofday.c create mode 100644 arch/nds32/kernel/vdso/note.S create mode 100644 arch/nds32/kernel/vdso/sigreturn.S create mode 100644 arch/nds32/kernel/vdso/vdso.S create mode 100644 arch/nds32/kernel/vdso/vdso.lds.S create mode 100644 arch/nds32/kernel/vmlinux.lds.S create mode 100644 arch/nds32/lib/Makefile create mode 100644 arch/nds32/lib/clear_user.S create mode 100644 arch/nds32/lib/copy_from_user.S create mode 100644 arch/nds32/lib/copy_page.S create mode 100644 arch/nds32/lib/copy_template.S create mode 100644 arch/nds32/lib/copy_to_user.S create mode 100644 arch/nds32/lib/memcpy.S create mode 100644 arch/nds32/lib/memmove.S create mode 100644 arch/nds32/lib/memset.S create mode 100644 arch/nds32/lib/memzero.S create mode 100644 arch/nds32/mm/Makefile create mode 100644 arch/nds32/mm/alignment.c create mode 100644 arch/nds32/mm/cacheflush.c create mode 100644 arch/nds32/mm/extable.c create mode 100644 arch/nds32/mm/fault.c create mode 100644 arch/nds32/mm/highmem.c create mode 100644 arch/nds32/mm/init.c create mode 100644 arch/nds32/mm/ioremap.c create mode 100644 arch/nds32/mm/mm-nds32.c create mode 100644 arch/nds32/mm/mmap.c create mode 100644 arch/nds32/mm/proc.c create mode 100644 arch/nds32/mm/tlb.c create mode 100644 drivers/clocksource/timer-atcpit100.c create mode 100644 drivers/irqchip/irq-ativic32.c
Signature · 1 line
1.7.9.5
PATCH v2 1/35 nds32: Assembly macros and definitions
From: Greentime Hu <[email protected]>
This patch includes assembly macros, bit field definitions used in .S files across arch/nds32/.
--- arch/nds32/include/asm/assembler.h | 52 ++ arch/nds32/include/asm/bitfield.h | 974 ++++++++++++++++++++++++++++++++++++ arch/nds32/include/asm/nds32.h | 96 ++++ arch/nds32/kernel/asm-offsets.c | 41 ++ 4 files changed, 1163 insertions(+) create mode 100644 arch/nds32/include/asm/assembler.h create mode 100644 arch/nds32/include/asm/bitfield.h create mode 100644 arch/nds32/include/asm/nds32.h create mode 100644 arch/nds32/kernel/asm-offsets.c
arch/nds32/include/asm/assembler.h new file +52 -0
@@ -0,0 +1,52 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef __NDS32_ASSEMBLER_H__ +#define __NDS32_ASSEMBLER_H__ + +.macro gie_disable + setgie.d + dsb +.endm + +.macro gie_enable + setgie.e + dsb +.endm + +.macro gie_save oldpsw + mfsr \oldpsw, $ir0 + setgie.d + dsb +.endm + +.macro gie_restore oldpsw + andi \oldpsw, \oldpsw, #0x1 + beqz \oldpsw, 7001f + setgie.e + dsb +7001: +.endm + + +#define USER(insn, reg, addr, opr) \ +9999: insn reg, addr, opr; \ + .section __ex_table,"a"; \ + .align 3; \ + .long 9999b, 9001f; \ + .previous + +#endif /* __NDS32_ASSEMBLER_H__ */
arch/nds32/include/asm/bitfield.h new file +974 -0
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arch/nds32/include/asm/nds32.h new file +96 -0
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arch/nds32/kernel/asm-offsets.c new file +41 -0
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Signature · 1 line
1.7.9.5
PATCH v2 2/35 nds32: Kernel booting and initialization
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
This patch includes the kernel startup code. It can get dtb pointer passed from bootloader. It will create a temp mapping by tlb instructions at beginning and goto start_kernel.
--- arch/nds32/kernel/head.S | 198 ++++++++++++++++++++++ arch/nds32/kernel/setup.c | 407 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 605 insertions(+) create mode 100644 arch/nds32/kernel/head.S create mode 100644 arch/nds32/kernel/setup.c
arch/nds32/kernel/head.S new file +198 -0
@@ -0,0 +1,198 @@ +/* + * Copyright (C) 2005-2017 Andes Technology Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/linkage.h> +#include <linux/init.h> +#include <asm/ptrace.h> +#include <asm/asm-offsets.h> +#include <asm/page.h> +#include <asm/pgtable.h> +#include <asm/l2_cache.h> +#include <asm/sizes.h> +#include <asm/thread_info.h> + +#ifdef CONFIG_CPU_BIG_ENDIAN +#define OF_DT_MAGIC 0xd00dfeed +#else +#define OF_DT_MAGIC 0xedfe0dd0 +#endif + + .globl swapper_pg_dir + .equ swapper_pg_dir, TEXTADDR - 0x4000 + +/* + * Kernel startup entry point. + */ + .section ".head.text", "ax" + .type _stext, %function +ENTRY(_stext) + setgie.d ! Disable interrupt + isb +/* + * Disable I/D-cache and enable it at a proper time + */ + mfsr $r0, $mr8 + li $r1, #~(CACHE_CTL_mskIC_EN|CACHE_CTL_mskDC_EN) + and $r0, $r0, $r1 + mtsr $r0, $mr8 + +/* + * Process device tree blob + */ + andi $r0,$r2,#0x3 + li $r10, 0 + bne $r0, $r10, _nodtb + lwi $r0, [$r2] + li $r1, OF_DT_MAGIC + bne $r0, $r1, _nodtb + move $r10, $r2 +_nodtb: + +/* + * Create a temporary mapping area for booting, before start_kernel + */ + sethi $r4, hi20(swapper_pg_dir) + li $p0, (PAGE_OFFSET - PHYS_OFFSET) + sub $r4, $r4, $p0 + tlbop FlushAll ! invalidate TLB\n" + isb + mtsr $r4, $L1_PPTB ! load page table pointer\n" + +/* set NTC0 cacheable/writeback, mutliple page size in use */ + mfsr $r3, $MMU_CTL + li $r0, #~MMU_CTL_mskNTC0 + and $r3, $r3, $r0 +#ifdef CONFIG_ANDES_PAGE_SIZE_4KB + ori $r3, $r3, #(MMU_CTL_mskMPZIU|(MMU_CTL_CACHEABLE_WB << MMU_CTL_offNTC0)) +#else + ori $r3, $r3, #(MMU_CTL_mskMPZIU|(MMU_CTL_CACHEABLE_WB << MMU_CTL_offNTC0)|MMU_CTL_mskD) +#endif + mtsr $r3, $MMU_CTL + isb + +/* set page size and size of kernel image */ + mfsr $r0, $MMU_CFG + srli $r3, $r0, MMU_CFG_offfEPSZ + zeb $r3, $r3 + bnez $r3, _extra_page_size_support +#ifdef CONFIG_ANDES_PAGE_SIZE_4KB + li $r5, #SZ_4K ! Use 4KB page size +#else + li $r5, #SZ_8K ! Use 8KB page size + li $r3, #1 +#endif + mtsr $r3, $TLB_MISC + b _image_size_check + +_extra_page_size_support: ! Use epzs pages size + clz $r6, $r3 + subri $r2, $r6, #31 + li $r3, #1 + sll $r3, $r3, $r2 + /* MMU_CFG.EPSZ value -> meaning */ + mul $r5, $r3, $r3 + slli $r5, $r5, #14 + /* MMU_CFG.EPSZ -> TLB_MISC.ACC_PSZ */ + addi $r3, $r2, #0x2 + mtsr $r3, $TLB_MISC + +_image_size_check: + /* calculate the image maximum size accepted by TLB config */ + andi $r6, $r0, MMU_CFG_mskTBW + andi $r0, $r0, MMU_CFG_mskTBS + srli $r6, $r6, MMU_CFG_offTBW + srli $r0, $r0, MMU_CFG_offTBS + /* + * we just map the kernel to the maximum way - 1 of tlb + * reserver one way for UART VA mapping + * it will cause page fault if UART mapping cover the kernel mapping + * + * direct mapping is not supported now. + */ + li $r2, 't' + beqz $r6, __error ! MMU_CFG.TBW = 0 is direct mappin + addi $r0, $r0, #0x2 ! MMU_CFG.TBS value -> meaning + sll $r0, $r6, $r0 ! entries = k-way * n-set + mul $r6, $r0, $r5 ! max size = entries * page size + /* check kernel image size */ + la $r3, (_end - PAGE_OFFSET) + li $r2, 's' + bgt $r3, $r6, __error + + li $r2, #(PHYS_OFFSET + TLB_DATA_kernel_text_attr) + li $r3, PAGE_OFFSET + add $r6, $r6, $r3 + +_tlb: + mtsr $r3, $TLB_VPN + dsb + tlbop $r2, RWR + isb + add $r3, $r3, $r5 + add $r2, $r2, $r5 + bgt $r6, $r3, _tlb + mfsr $r3, $TLB_MISC ! setup access page size + li $r2, #~0xf + and $r3, $r3, $r2 +#ifdef CONFIG_ANDES_PAGE_SIZE_8KB + ori $r3, $r3, #0x1 +#endif + mtsr $r3, $TLB_MISC + + mfsr $r0, $MISC_CTL ! Enable BTB and RTP and shadow sp + ori $r0, $r0, #MISC_init + mtsr $r0, $MISC_CTL + + mfsr $p1, $PSW + li $r15, #~PSW_clr ! clear WBNA|DME|IME|DT|IT|POM|INTL|GIE + and $p1, $p1, $r15 + ori $p1, $p1, #PSW_init + mtsr $p1, $IPSW ! when iret, it will automatically enable MMU + la $lp, __mmap_switched + mtsr $lp, $IPC + iret + nop + + .type __switch_data, %object +__switch_data: + .long __bss_start ! $r6 + .long _end ! $r7 + .long __atags_pointer ! $atag_pointer + .long init_task ! $r9, move to $r25 + .long init_thread_union + THREAD_SIZE ! $sp + + +/* + * The following fragment of code is executed with the MMU on in MMU mode, + * and uses absolute addresses; this is not position independent. + */ + .align + .type __mmap_switched, %function +__mmap_switched: + la $r3, __switch_data + lmw.bim $r6, [$r3], $r9, #0b0001 + move $r25, $r9 + move $fp, #0 ! Clear BSS (and zero $fp) + beq $r7, $r6, _RRT +1: swi.bi $fp, [$r6], #4 + bne $r7, $r6, 1b + swi $r10, [$r8] + +_RRT: + b start_kernel + +__error: + b __error
arch/nds32/kernel/setup.c new file +407 -0
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1.7.9.5
PATCH v2 3/35 nds32: Exception handling
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
This patch includes the exception/interrupt entries, pt_reg structure and related accessors.
--- arch/nds32/include/asm/ptrace.h | 79 +++++ arch/nds32/kernel/ex-entry.S | 170 +++++++++++ arch/nds32/kernel/ex-exit.S | 206 +++++++++++++ arch/nds32/kernel/stacktrace.c | 60 ++++ arch/nds32/kernel/traps.c | 441 +++++++++++++++++++++++++++ arch/nds32/mm/alignment.c | 622 +++++++++++++++++++++++++++++++++++++++ 6 files changed, 1578 insertions(+) create mode 100644 arch/nds32/include/asm/ptrace.h create mode 100644 arch/nds32/kernel/ex-entry.S create mode 100644 arch/nds32/kernel/ex-exit.S create mode 100644 arch/nds32/kernel/stacktrace.c create mode 100644 arch/nds32/kernel/traps.c create mode 100644 arch/nds32/mm/alignment.c
arch/nds32/include/asm/ptrace.h new file +79 -0
@@ -0,0 +1,79 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef __ASM_NDS32_PTRACE_H +#define __ASM_NDS32_PTRACE_H + +#define PTRACE_GETREGS 12 +#define PTRACE_SETREGS 13 +#define PTRACE_GETFPREGS 14 +#define PTRACE_SETFPREGS 15 + +#include <uapi/asm/ptrace.h> + +#ifndef __ASSEMBLY__ + +struct pt_regs { +union { +struct user_pt_regs user_regs; +struct { +long uregs[26 ]; +long fp; +long gp; +long lp; +long sp; +long ipc; +#if defined(CONFIG_HWZOL ) +long lb; +long le; +long lc; +#else +long dummy[3 ]; +#endif +long syscallno; + }; + }; +long orig_r0; +long ir0; +long ipsw; +long pipsw; +long pipc; +long pp0; +long pp1; +long fucop_ctl; +long osp; +}; + +#include <asm/bitfield.h> +extern void show_regs (struct pt_regs *); +/* Avoid circular header include via sched.h */ +struct task_struct ; +extern void send_sigtrap (struct task_struct *tsk,struct pt_regs *regs, +int error_code,int si_code); + +#define arch_has_single_step () (1) +#define user_mode (regs) (((regs)->ipsw & PSW_mskPOM) == 0) +#define interrupts_enabled (regs) (!!((regs)->ipsw & PSW_mskGIE)) +#define valid_user_regs (regs) (user_mode(regs) && interrupts_enabled(regs)) +#define regs_return_value (regs) ((regs)->uregs[0]) +#define instruction_pointer (regs) ((regs)->ipc) +#define user_stack_pointer (regs) ((regs)->sp) +#define profile_pc (regs) instruction_pointer(regs) + +#define ARCH_HAS_USER_SINGLE_STEP_INFO + +#endif /* __ASSEMBLY__ */ +#endif
arch/nds32/kernel/ex-entry.S new file +170 -0
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arch/nds32/kernel/ex-exit.S new file +206 -0
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arch/nds32/kernel/stacktrace.c new file +60 -0
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arch/nds32/kernel/traps.c new file +441 -0
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arch/nds32/mm/alignment.c new file +622 -0
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1.7.9.5
PATCH v2 4/35 nds32: MMU definitions
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
This patch includes virtual memory layout, PHYS_OFFSET is defined as 0x0. It also includes the 4KB/8KB page size configurations and pte operations.
--- arch/nds32/include/asm/fixmap.h | 42 ++++ arch/nds32/include/asm/highmem.h | 78 +++++++ arch/nds32/include/asm/memory.h | 118 ++++++++++ arch/nds32/include/asm/mmu.h | 25 +++ arch/nds32/include/asm/page.h | 78 +++++++ arch/nds32/include/asm/pgalloc.h | 109 ++++++++++ arch/nds32/include/asm/pgtable.h | 426 +++++++++++++++++++++++++++++++++++++ arch/nds32/include/asm/shmparam.h | 32 +++ 8 files changed, 908 insertions(+) create mode 100644 arch/nds32/include/asm/fixmap.h create mode 100644 arch/nds32/include/asm/highmem.h create mode 100644 arch/nds32/include/asm/memory.h create mode 100644 arch/nds32/include/asm/mmu.h create mode 100644 arch/nds32/include/asm/page.h create mode 100644 arch/nds32/include/asm/pgalloc.h create mode 100644 arch/nds32/include/asm/pgtable.h create mode 100644 arch/nds32/include/asm/shmparam.h
arch/nds32/include/asm/fixmap.h new file +42 -0
@@ -0,0 +1,42 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef __ASM_NDS32_FIXMAP_H +#define __ASM_NDS32_FIXMAP_H + +#ifdef CONFIG_HIGHMEM +#include <linux/threads.h> +#include <asm/kmap_types.h> +#endif + +enum fixed_addresses { +FIX_HOLE , +FIX_KMAP_RESERVED , +FIX_KMAP_BEGIN , +#ifdef CONFIG_HIGHMEM +FIX_KMAP_END =FIX_KMAP_BEGIN + (KM_TYPE_NR *NR_CPUS ), +#endif +FIX_EARLYCON_MEM_BASE , + __end_of_fixed_addresses +}; +#define FIXADDR_TOP ((unsigned long) (-(16 * PAGE_SIZE))) +#define FIXADDR_SIZE ((__end_of_fixed_addresses) << PAGE_SHIFT) +#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) +#define FIXMAP_PAGE_IO __pgprot(PAGE_DEVICE) +void __set_fixmap (enum fixed_addresses idx,phys_addr_t phys,pgprot_t prot); + +#include <asm-generic/fixmap.h> +#endif /* __ASM_NDS32_FIXMAP_H */
arch/nds32/include/asm/highmem.h new file +78 -0
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arch/nds32/include/asm/memory.h new file +118 -0
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arch/nds32/include/asm/mmu.h new file +25 -0
@@ -0,0 +1,25 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef __NDS32_MMU_H +#define __NDS32_MMU_H + +typedef struct { +unsigned int id; +void *vdso; +}mm_context_t ; + +#endif
arch/nds32/include/asm/page.h new file +78 -0
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arch/nds32/include/asm/pgalloc.h new file +109 -0
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arch/nds32/include/asm/pgtable.h new file +426 -0
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arch/nds32/include/asm/shmparam.h new file +32 -0
@@ -0,0 +1,32 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef _ASMNDS32_SHMPARAM_H +#define _ASMNDS32_SHMPARAM_H + +/* +* This should be the size of the virtually indexed cache/ways, +* whichever is greater since the cache aliases every size/ways +* bytes. +*/ +#define SHMLBA (4 * SZ_8K)/* attach addr a multiple of this */ + +/* +* Enforce SHMLBA in shmat +*/ +#define __ARCH_FORCE_SHMLBA + +#endif /* _ASMNDS32_SHMPARAM_H */
Signature · 1 line
1.7.9.5
PATCH v2 5/35 nds32: MMU initialization
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
This patch includes memory initializations and highmem supporting.
--- arch/nds32/mm/highmem.c | 92 ++++++++++++++ arch/nds32/mm/init.c | 318 ++++++++++++++++++++++++++++++++++++++++++++++ arch/nds32/mm/mm-nds32.c | 103 +++++++++++++++ 3 files changed, 513 insertions(+) create mode 100644 arch/nds32/mm/highmem.c create mode 100644 arch/nds32/mm/init.c create mode 100644 arch/nds32/mm/mm-nds32.c
arch/nds32/mm/highmem.c new file +92 -0
@@ -0,0 +1,92 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <linux/export.h> +#include <linux/highmem.h> +#include <linux/sched.h> +#include <linux/smp.h> +#include <linux/interrupt.h> +#include <linux/bootmem.h> +#include <asm/fixmap.h> +#include <asm/tlbflush.h> + +void *kmap (struct page *page) +{ +unsigned long vaddr; +might_sleep (); +if (!PageHighMem (page)) +return page_address (page); + vaddr = (unsigned long )kmap_high (page); +return (void *)vaddr; +} + +EXPORT_SYMBOL (kmap); + +void kunmap (struct page *page) +{ +BUG_ON (in_interrupt ()); +if (!PageHighMem (page)) +return ; +kunmap_high (page); +} + +EXPORT_SYMBOL (kunmap); + +void *kmap_atomic (struct page *page) +{ +unsigned int idx; +unsigned long vaddr, pte; +int type; +pte_t *ptep; + +preempt_disable (); +pagefault_disable (); +if (!PageHighMem (page)) +return page_address (page); + + type =kmap_atomic_idx_push (); + + idx = type +KM_TYPE_NR *smp_processor_id (); + vaddr =__fix_to_virt (FIX_KMAP_BEGIN + idx); + pte = (page_to_pfn (page) <<PAGE_SHIFT ) | (PAGE_KERNEL ); + ptep =pte_offset_kernel (pmd_off_k (vaddr), vaddr); +set_pte (ptep, pte); + +__nds32__tlbop_inv (vaddr); +__nds32__mtsr_dsb (vaddr,NDS32_SR_TLB_VPN ); +__nds32__tlbop_rwr (pte); +__nds32__isb (); +return (void *)vaddr; +} + +EXPORT_SYMBOL (kmap_atomic); + +void __kunmap_atomic (void *kvaddr) +{ +if (kvaddr >= (void *)FIXADDR_START ) { +unsigned long vaddr = (unsigned long )kvaddr; +pte_t *ptep; +kmap_atomic_idx_pop (); +__nds32__tlbop_inv (vaddr); +__nds32__isb (); + ptep =pte_offset_kernel (pmd_off_k (vaddr), vaddr); +set_pte (ptep,0 ); + } +pagefault_enable (); +preempt_enable (); +} + +EXPORT_SYMBOL (__kunmap_atomic);
arch/nds32/mm/init.c new file +318 -0
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arch/nds32/mm/mm-nds32.c new file +103 -0
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1.7.9.5
PATCH v2 6/35 nds32: MMU fault handling and page table management
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
This patch includes page fault handler, mmap and fixup implementations.
--- arch/nds32/lib/copy_page.S | 50 ++++++ arch/nds32/mm/extable.c | 29 +++ arch/nds32/mm/fault.c | 420 ++++++++++++++++++++++++++++++++++++++++++++ arch/nds32/mm/mmap.c | 86 +++++++++ 4 files changed, 585 insertions(+) create mode 100644 arch/nds32/lib/copy_page.S create mode 100644 arch/nds32/mm/extable.c create mode 100644 arch/nds32/mm/fault.c create mode 100644 arch/nds32/mm/mmap.c
arch/nds32/lib/copy_page.S new file +50 -0
@@ -0,0 +1,50 @@ +/* + * Copyright (C) 2005-2017 Andes Technology Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/linkage.h> +#include <asm/page.h> + + .text +ENTRY(copy_page) + pushm $r2, $r10 + movi $r2, PAGE_SIZE >> 5 +.Lcopy_loop: + lmw.bim $r3, [$r1], $r10 + smw.bim $r3, [$r0], $r10 + subi45 $r2, #1 + bnez38 $r2, .Lcopy_loop + popm $r2, $r10 + ret +ENDPROC(copy_page) + +ENTRY(clear_page) + pushm $r1, $r9 + movi $r1, PAGE_SIZE >> 5 + movi55 $r2, #0 + movi55 $r3, #0 + movi55 $r4, #0 + movi55 $r5, #0 + movi55 $r6, #0 + movi55 $r7, #0 + movi55 $r8, #0 + movi55 $r9, #0 +.Lclear_loop: + smw.bim $r2, [$r0], $r9 + subi45 $r1, #1 + bnez38 $r1, .Lclear_loop + popm $r1, $r9 + ret +ENDPROC(clear_page)
arch/nds32/mm/extable.c new file +29 -0
@@ -0,0 +1,29 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <linux/extable.h> +#include <asm/uaccess.h> + +int fixup_exception (struct pt_regs *regs) +{ +const struct exception_table_entry *fixup; + + fixup =search_exception_tables (instruction_pointer (regs)); +if (fixup) + regs->ipc = fixup->fixup; + +return fixup !=NULL ; +}
arch/nds32/mm/fault.c new file +420 -0
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arch/nds32/mm/mmap.c new file +86 -0
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Signature · 1 line
1.7.9.5
Re: [PATCH v2 06/35] nds32: MMU fault handling and page table management
Hi,
Quoted 27 lines · Greentime Hu
arch/nds32/mm/fault.c new file +26
-0+void do_page_fault (unsigned long entry,unsigned long addr, +unsigned int error_code,struct pt_regs *regs) +{ +/* +* As per x86, we may deadlock here. However, since the kernel only +* validly references user space from well defined areas of the code, +* we can bug out early if this is from code which shouldn't. +*/ +if (unlikely (!down_read_trylock (&mm->mmap_sem))) { +if (!user_mode (regs) && + !search_exception_tables (instruction_pointer (regs))) + goto no_context; +retry: +down_read (&mm->mmap_sem); + }else { +/* +* The above down_read_trylock() might have succeeded in which +* case, we'll have missed the might_sleep() from down_read(). +*/ +might_sleep (); +if (IS_ENABLED (CONFIG_DEBUG_VM )) { +if (!user_mode (regs) && + !search_exception_tables (instruction_pointer (regs))) + goto no_context; + } + }
arch/nds32/mm/fault.c line 228
Quoted 10 lines
arch/nds32/mm/fault.c new file +9
-0+ fault =handle_mm_fault (vma, addr, flags); + +/* +* If we need to retry but a fatal signal is pending, handle the +* signal first. We do not need to release the mmap_sem because it +* would already be released in __lock_page_or_retry in mm/filemap.c. +*/ +if ((fault &VM_FAULT_RETRY ) &&fatal_signal_pending (current)) +return ;
I believe you can get stuck in a livelock here (with an unkillable task), if a uaccess primitive tries to access a region protected by a userfaultfd. Please see:
... for details and a test case.
Thanks,
Mark.
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Re: [PATCH v2 06/35] nds32: MMU fault handling and page table management
Hi, Mark:
2017-11-27 21:51 GMT+08:00 Mark Rutland <[email protected]>:
Quoted 41 lines
Hi,
Quoted 27 lines · Greentime Hu
arch/nds32/mm/fault.c new file +26
-0+void do_page_fault (unsigned long entry,unsigned long addr, +unsigned int error_code,struct pt_regs *regs) +{ +/* +* As per x86, we may deadlock here. However, since the kernel only +* validly references user space from well defined areas of the code, +* we can bug out early if this is from code which shouldn't. +*/ +if (unlikely (!down_read_trylock (&mm->mmap_sem))) { +if (!user_mode (regs) && + !search_exception_tables (instruction_pointer (regs))) + goto no_context; +retry: +down_read (&mm->mmap_sem); + }else { +/* +* The above down_read_trylock() might have succeeded in which +* case, we'll have missed the might_sleep() from down_read(). +*/ +might_sleep (); +if (IS_ENABLED (CONFIG_DEBUG_VM )) { +if (!user_mode (regs) && + !search_exception_tables (instruction_pointer (regs))) + goto no_context; + } + }arch/nds32/mm/fault.c line 228
Quoted 10 lines
arch/nds32/mm/fault.c new file +9
-0+ fault =handle_mm_fault (vma, addr, flags); + +/* +* If we need to retry but a fatal signal is pending, handle the +* signal first. We do not need to release the mmap_sem because it +* would already be released in __lock_page_or_retry in mm/filemap.c. +*/ +if ((fault &VM_FAULT_RETRY ) &&fatal_signal_pending (current)) +return ;
Quoted 8 lines
I believe you can get stuck in a livelock here (with an unkillable task), if a uaccess primitive tries to access a region protected by a userfaultfd. Please see:
... for details and a test case.
Thanks for your teatcase and patch. It works.
I will apply it to the next version patch.
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Re: [PATCH v2 06/35] nds32: MMU fault handling and page table management
In reply to Greentime HuQuoted 2 lines · Greentime Hu
arch/nds32/mm/fault.c new file +2
-0+void do_page_fault (unsigned long entry,unsigned long addr, +unsigned int error_code,struct pt_regs *regs)
[snip]
arch/nds32/mm/fault.c line 130
Quoted 5 lines
arch/nds32/mm/fault.c new file +5
-0+/* +* If we're in an interrupt or have no user +* context, we must not take the fault.. +*/ +if (unlikely (in_atomic () || !mm))
Broken. in_atomic() is wrong here - it should be faulthandler_disabled().
Re: [PATCH v2 06/35] nds32: MMU fault handling and page table management
2017-12-08 0:40 GMT+08:00 Al Viro <viro-RmSDqhL/[email protected]>:
Quoted 11 lines · Greentime Hu
Quoted 2 lines
arch/nds32/mm/fault.c new file +2
-0+void do_page_fault (unsigned long entry,unsigned long addr, +unsigned int error_code,struct pt_regs *regs)[snip]
arch/nds32/mm/fault.c line 130
Quoted 5 lines
arch/nds32/mm/fault.c new file +5
-0+/* +* If we're in an interrupt or have no user +* context, we must not take the fault.. +*/ +if (unlikely (in_atomic () || !mm))Broken.
in_atomic()is wrong here - it should befaulthandler_disabled().
Thanks.
I will include <linux/uaccess.h> and replace in_atomic() with faulthandler_disabled()
I will fix it in the next version patch.
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PATCH v2 7/35 nds32: Cache and TLB routines
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
This patch contains cache and TLB maintenance functions.
--- arch/nds32/include/asm/cache.h | 25 ++ arch/nds32/include/asm/cache_info.h | 26 ++ arch/nds32/include/asm/cacheflush.h | 57 +++ arch/nds32/include/asm/mmu_context.h | 81 +++++ arch/nds32/include/asm/proc-fns.h | 57 +++ arch/nds32/include/asm/tlb.h | 41 +++ arch/nds32/include/asm/tlbflush.h | 60 ++++ arch/nds32/include/uapi/asm/cachectl.h | 19 + arch/nds32/kernel/cacheinfo.c | 62 ++++ arch/nds32/mm/cacheflush.c | 331 ++++++++++++++++++ arch/nds32/mm/proc.c | 601 ++++++++++++++++++++++++++++++++ arch/nds32/mm/tlb.c | 63 ++++ 12 files changed, 1423 insertions(+) create mode 100644 arch/nds32/include/asm/cache.h create mode 100644 arch/nds32/include/asm/cache_info.h create mode 100644 arch/nds32/include/asm/cacheflush.h create mode 100644 arch/nds32/include/asm/mmu_context.h create mode 100644 arch/nds32/include/asm/proc-fns.h create mode 100644 arch/nds32/include/asm/tlb.h create mode 100644 arch/nds32/include/asm/tlbflush.h create mode 100644 arch/nds32/include/uapi/asm/cachectl.h create mode 100644 arch/nds32/kernel/cacheinfo.c create mode 100644 arch/nds32/mm/cacheflush.c create mode 100644 arch/nds32/mm/proc.c create mode 100644 arch/nds32/mm/tlb.c
arch/nds32/include/asm/cache.h new file +25 -0
@@ -0,0 +1,25 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef __NDS32_CACHE_H__ +#define __NDS32_CACHE_H__ + +#define L1_CACHE_BYTES 32 +#define L1_CACHE_SHIFT 5 + +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES + +#endif /* __NDS32_CACHE_H__ */
arch/nds32/include/asm/cache_info.h new file +26 -0
@@ -0,0 +1,26 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +struct cache_info { +unsigned char ways; +unsigned char line_size; +unsigned short sets; +unsigned short size; +#if !defined(CONFIG_CPU_CACHE_NONALIASING ) +unsigned short aliasing_num; +unsigned int aliasing_mask; +#endif +};
arch/nds32/include/asm/cacheflush.h new file +57 -0
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arch/nds32/include/asm/mmu_context.h new file +81 -0
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arch/nds32/include/asm/proc-fns.h new file +57 -0
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arch/nds32/include/asm/tlb.h new file +41 -0
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arch/nds32/include/asm/tlbflush.h new file +60 -0
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arch/nds32/include/uapi/asm/cachectl.h new file +19 -0
@@ -0,0 +1,19 @@ +/* +* This file is subject to the terms and conditions of the GNU General Public +* License. See the file "COPYING" in the main directory of this archive +* for more details. +* +* Copyright (C) 1994, 1995, 1996 by Ralf Baechle +* Copyright (C) 2005-2017 Andes Technology Corporation +*/ +#ifndef _ASM_CACHECTL +#define _ASM_CACHECTL + +/* +* Options for cacheflush system call +*/ +#define ICACHE 0/* flush instruction cache */ +#define DCACHE 1/* writeback and flush data cache */ +#define BCACHE 2/* flush instruction cache + writeback and flush data cache */ + +#endif /* _ASM_CACHECTL */
arch/nds32/kernel/cacheinfo.c new file +62 -0
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arch/nds32/mm/cacheflush.c new file +331 -0
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arch/nds32/mm/proc.c new file +601 -0
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arch/nds32/mm/tlb.c new file +63 -0
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1.7.9.5
PATCH v2 8/35 nds32: Process management
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
This patch includes copy_thread(), start_thread() implementation and cpu_context structure definition. nds32 uses $r25 to get current task_struct.
--- arch/nds32/include/asm/current.h | 25 ++++ arch/nds32/include/asm/processor.h | 116 ++++++++++++++++++ arch/nds32/include/asm/thread_info.h | 91 ++++++++++++++ arch/nds32/kernel/process.c | 217 ++++++++++++++++++++++++++++++++++ 4 files changed, 449 insertions(+) create mode 100644 arch/nds32/include/asm/current.h create mode 100644 arch/nds32/include/asm/processor.h create mode 100644 arch/nds32/include/asm/thread_info.h create mode 100644 arch/nds32/kernel/process.c
arch/nds32/include/asm/current.h new file +25 -0
@@ -0,0 +1,25 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef _ASM_NDS32_CURRENT_H +#define _ASM_NDS32_CURRENT_H + +#ifndef __ASSEMBLY__ +registerstruct task_struct *current asm("$r25" ); +#endif /* __ASSEMBLY__ */ +#define tsk $r25 + +#endif /* _ASM_NDS32_CURRENT_H */
arch/nds32/include/asm/processor.h new file +116 -0
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arch/nds32/include/asm/thread_info.h new file +91 -0
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arch/nds32/kernel/process.c new file +217 -0
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1.7.9.5
Re: [PATCH v2 08/35] nds32: Process management
arch/nds32/include/asm/processor.h line 81
Quoted 3 lines · Greentime Hu
arch/nds32/include/asm/processor.h new file +3
-0+#define start_thread (regs,pc,stack) \ +({ \ + set_fs(USER_DS); \
Not the job of start_thread() - its users (->load_binary() methods of assorted binfmt) must (and do) call flush_old_exec() first. And that will switch to USER_DS just fine.
Re: [PATCH v2 08/35] nds32: Process management
2017-12-08 0:45 GMT+08:00 Al Viro <[email protected]>:
Quoted 9 lines · Greentime Hu
arch/nds32/include/asm/processor.h line 81
Quoted 4 lines
arch/nds32/include/asm/processor.h new file +3
-0+#define start_thread (regs,pc,stack) \ +({ \ + set_fs(USER_DS); \Not the job of
start_thread()- its users (->load_binary() methods of assorted binfmt) must (and do) callflush_old_exec()first. And that will switch toUSER_DSjust fine.
Thanks. I will remove this setting in the next version patch.
PATCH v2 9/35 nds32: IRQ handling
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
This patch includes irq related functions and irqchip_init().
--- arch/nds32/include/asm/irqflags.h | 49 +++++++++++++++++++++++++++++++++++++ arch/nds32/kernel/irq.c | 22 +++++++++++++++++ 2 files changed, 71 insertions(+) create mode 100644 arch/nds32/include/asm/irqflags.h create mode 100644 arch/nds32/kernel/irq.c
arch/nds32/include/asm/irqflags.h new file +49 -0
@@ -0,0 +1,49 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <asm/nds32.h> +#include <nds32_intrinsic.h> + +#define arch_local_irq_disable () \ + GIE_DISABLE(); + +#define arch_local_irq_enable () \ + GIE_ENABLE(); +static inline unsigned long arch_local_irq_save (void ) +{ +unsigned long flags; + flags =__nds32__mfsr (NDS32_SR_PSW ) & PSW_mskGIE; +GIE_DISABLE (); +return flags; +} + +static inline unsigned long arch_local_save_flags (void ) +{ +unsigned long flags; + flags =__nds32__mfsr (NDS32_SR_PSW ) & PSW_mskGIE; +return flags; +} + +static inline void arch_local_irq_restore (unsigned long flags) +{ +if (flags) +GIE_ENABLE (); +} + +static inline int arch_irqs_disabled_flags (unsigned long flags) +{ +return !flags; +}
arch/nds32/kernel/irq.c new file +22 -0
@@ -0,0 +1,22 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <linux/irqchip.h> + +void __init init_IRQ (void ) +{ +irqchip_init (); +}
Signature · 1 line
1.7.9.5
PATCH v2 10/35 nds32: Atomic operations
In reply to Greentime HuFrom: Greentime Hu <greentime-MUIXKm3Oiri1Z/[email protected]>
This patch includes the atomic and futex operations. Many atomic operations use the load-lock word(llw) and store-condition word(scw) operations.
--- arch/nds32/include/asm/futex.h | 116 +++++++++++++++++++++++ arch/nds32/include/asm/spinlock.h | 184 +++++++++++++++++++++++++++++++++++++ 2 files changed, 300 insertions(+) create mode 100644 arch/nds32/include/asm/futex.h create mode 100644 arch/nds32/include/asm/spinlock.h
arch/nds32/include/asm/futex.h new file +116 -0
@@ -0,0 +1,116 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef __NDS32_FUTEX_H__ +#define __NDS32_FUTEX_H__ + +#include <linux/futex.h> +#include <linux/uaccess.h> +#include <asm/errno.h> + +#define __futex_atomic_ex_table (err_reg) \ + " .pushsection __ex_table,\"a\"\n" \ + " .align 3\n" \ + " .long 1b, 4f\n" \ + " .long 2b, 4f\n" \ + " .popsection\n" \ + " .pushsection .fixup,\"ax\"\n" \ + "4: move %0, " err_reg "\n" \ + " j 3b\n" \ + " .popsection" + +#define __futex_atomic_op (insn, ret, oldval, tmp, uaddr, oparg) \ + smp_mb(); \ + asm volatile( \ + " movi $ta, #0\n" \ + "1: llw %1, [%2+$ta]\n" \ + " " insn "\n" \ + "2: scw %0, [%2+$ta]\n" \ + " beqz %0, 1b\n" \ + " movi %0, #0\n" \ + "3:\n" \ + __futex_atomic_ex_table("%4") \ + : "=&r" (ret), "=&r" (oldval) \ + : "r" (uaddr), "r" (oparg), "i" (-EFAULT) \ + : "cc", "memory") +static inline int +futex_atomic_cmpxchg_inatomic (u32 * uval,u32 __user * uaddr, +u32 oldval,u32 newval) +{ +int ret =0 ; +u32 val, tmp, flags; + +if (!access_ok (VERIFY_WRITE , uaddr,sizeof (u32))) +return -EFAULT ; + +smp_mb (); + asmvolatile (" movi $ta, #0\n" +"1: llw %1, [%6 + $ta]\n" +" sub %3, %1, %4\n" +" cmovz %2, %5, %3\n" +" cmovn %2, %1, %3\n" +"2: scw %2, [%6 + $ta]\n" +" beqz %2, 1b\n" + "3:\n " __futex_atomic_ex_table("%7") + :"+&r"(ret), "=&r"(val), "=&r"(tmp), "=&r"(flags) + :"r"(oldval), "r"(newval), "r"(uaddr), "i"(-EFAULT) + :"$ta", "memory"); + smp_mb(); + + *uval = val; +return ret; +} + +static inline int +arch_futex_atomic_op_inuser (int op,int oparg,int *oval,u32 __user *uaddr) +{ +int oldval =0 , ret; + + +pagefault_disable (); +switch (op) { +case FUTEX_OP_SET : +__futex_atomic_op ("move %0, %3" , ret, oldval, tmp, uaddr, + oparg); +break ; +case FUTEX_OP_ADD : +__futex_atomic_op ("add %0, %1, %3" , ret, oldval, tmp, uaddr, + oparg); +break ; +case FUTEX_OP_OR : +__futex_atomic_op ("or %0, %1, %3" , ret, oldval, tmp, uaddr, + oparg); +break ; +case FUTEX_OP_ANDN : +__futex_atomic_op ("and %0, %1, %3" , ret, oldval, tmp, uaddr, + ~oparg); +break ; +case FUTEX_OP_XOR : +__futex_atomic_op ("xor %0, %1, %3" , ret, oldval, tmp, uaddr, + oparg); +break ; +default : + ret = -ENOSYS ; + } + +pagefault_enable (); + +if (!ret) + *oval = oldval; + +return ret; +} +#endif /* __NDS32_FUTEX_H__ */
arch/nds32/include/asm/spinlock.h new file +184 -0
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Re: [PATCH v2 10/35] nds32: Atomic operations
Hi,
arch/nds32/include/asm/spinlock.h line 67
Quoted 9 lines · Greentime Hu
arch/nds32/include/asm/spinlock.h new file +9
-0+static inline void arch_spin_unlock (arch_spinlock_t * lock) +{ + asmvolatile ( +"xor $r15, $r15, $r15\n" +"swi $r15, [%0]\n" + : + :"r" (&lock->lock) + :"memory" ); +}
This looks suspicious. There's no clobber for $r15, so isn't this corrupting a GPR behind the back of the compiler?
Shouldn't there be a tmp variable for the register allocation rather than hard-coding $r15?
arch/nds32/include/asm/spinlock.h line 93
Quoted 9 lines
arch/nds32/include/asm/spinlock.h new file +9
-0+static inline void arch_write_unlock (arch_rwlock_t * rw) +{ + asmvolatile ( +"xor $r15, $r15, $r15\n" +"swi $r15, [%0]\n" + : + :"r" (&rw->lock) + :"memory" ,"$r15" ); +}
This time you have a clobber, but it's still not clear to me why you don't use a tmp variable and leave the register allocation to the compiler.
Thanks,
Mark.
Re: [PATCH v2 10/35] nds32: Atomic operations
2017-11-27 21:57 GMT+08:00 Mark Rutland <[email protected]>:
Quoted 16 lines
Hi,
arch/nds32/include/asm/spinlock.h line 67
Quoted 9 lines · Greentime Hu
arch/nds32/include/asm/spinlock.h new file +9
-0+static inline void arch_spin_unlock (arch_spinlock_t * lock) +{ + asmvolatile ( +"xor $r15, $r15, $r15\n" +"swi $r15, [%0]\n" + : + :"r" (&lock->lock) + :"memory" ); +}This looks suspicious. There's no clobber for $r15, so isn't this corrupting a GPR behind the back of the compiler?
Thanks.
$r15 is reserved for assembler.
For safety, compiler always put $r15 in clobber register list by default.
Quoted 17 lines
Shouldn't there be a tmp variable for the register allocation rather than hard-coding $r15?
arch/nds32/include/asm/spinlock.h line 93
Quoted 9 lines
arch/nds32/include/asm/spinlock.h new file +9
-0+static inline void arch_write_unlock (arch_rwlock_t * rw) +{ + asmvolatile ( +"xor $r15, $r15, $r15\n" +"swi $r15, [%0]\n" + : + :"r" (&rw->lock) + :"memory" ,"$r15" ); +}This time you have a clobber, but it's still not clear to me why you don't use a tmp variable and leave the register allocation to the compiler.
Thanks.
When I recheck the code, I found spinlock.h is not needed due that we do not support SMP.
So, We decide to remove spinlock.h in the next version patch.
Vincent
Quoted 2 lines
Thanks,
Mark.
PATCH v2 11/35 nds32: Device specific operations
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
This patch introduces ioremap implementations.
--- arch/nds32/include/asm/io.h | 25 +++++++++++++++ arch/nds32/mm/ioremap.c | 75 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 100 insertions(+) create mode 100644 arch/nds32/include/asm/io.h create mode 100644 arch/nds32/mm/ioremap.c
arch/nds32/include/asm/io.h new file +25 -0
@@ -0,0 +1,25 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef __ASM_NDS32_IO_H +#define __ASM_NDS32_IO_H + +#ifdef __KERNEL__ +void iounmap (void __iomem * addr); +#include <asm-generic/io.h> + +#endif /* __KERNEL__ */ +#endif /* __ASM_NDS32_IO_H */
arch/nds32/mm/ioremap.c new file +75 -0
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1.7.9.5
Arnd Bergmann
maintainerRe: [PATCH v2 11/35] nds32: Device specific operations
Quoted 19 lines · Greentime Hu
From: Greentime Hu <[email protected]>
This patch introduces ioremap implementations.
Signed-off-by Vincent Chen <[email protected]>Signed-off-by Greentime Hu <[email protected]>--- arch/nds32/include/asm/io.h | 25 +++++++++++++++ arch/nds32/mm/ioremap.c | 75 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 100 insertions(+) create mode 100644 arch/nds32/include/asm/io.h create mode 100644 arch/nds32/mm/ioremap.carch/nds32/include/asm/io.h new file +0
-0
arch/nds32/include/asm/io.h line 25
Quoted 10 lines
arch/nds32/include/asm/io.h new file +9
-0@@ -0,0 +1,25 @@ +#ifndef __ASM_NDS32_IO_H +#define __ASM_NDS32_IO_H + +#ifdef __KERNEL__ +void iounmap (void __iomem * addr); +#include <asm-generic/io.h> + +#endif /* __KERNEL__ */ +#endif /* __ASM_NDS32_IO_H */
Here, you should define a lot of the I/O accessor functions, dereferencing a pointer
is generally not enough to guarantee an atomic MMIO operation. You need to force the access to use the correct size to prevent the compiler from issuing byte-sized operations when it thinks the pointer might be unaligned, and there should be barriers that ensure a memory access is synchronized with a DMA that might be triggered by a writel, or claimed to be completed after a readl. Please see the risc-v header for this, it has many good explanations.
Arnd
PATCH v2 12/35 nds32: DMA mapping API
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
This patch adds support for the DMA mapping API. It uses dma_map_ops for flexibility.
--- arch/nds32/include/asm/dma-mapping.h | 27 ++ arch/nds32/kernel/dma.c | 472 ++++++++++++++++++++++++++++++++++ 2 files changed, 499 insertions(+) create mode 100644 arch/nds32/include/asm/dma-mapping.h create mode 100644 arch/nds32/kernel/dma.c
arch/nds32/include/asm/dma-mapping.h new file +27 -0
@@ -0,0 +1,27 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef ASMNDS32_DMA_MAPPING_H +#define ASMNDS32_DMA_MAPPING_H + +extern struct dma_map_ops nds32_dma_ops; + +static inline struct dma_map_ops *get_arch_dma_ops (struct bus_type *bus) +{ +return &nds32_dma_ops; +} + +#endif
arch/nds32/kernel/dma.c new file +472 -0
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1.7.9.5
PATCH v2 13/35 nds32: ELF definitions
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
This patch adds definitions for the ELF format, relocation types, vdso locations and EXEC_PAGESIZE.
--- arch/nds32/include/asm/elf.h | 192 ++++++++++++++++++++++++++++++++++ arch/nds32/include/uapi/asm/auxvec.h | 25 +++++ arch/nds32/include/uapi/asm/param.h | 24 +++++ 3 files changed, 241 insertions(+) create mode 100644 arch/nds32/include/asm/elf.h create mode 100644 arch/nds32/include/uapi/asm/auxvec.h create mode 100644 arch/nds32/include/uapi/asm/param.h
arch/nds32/include/asm/elf.h new file +192 -0
@@ -0,0 +1,192 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef __ASMNDS32_ELF_H +#define __ASMNDS32_ELF_H + +/* +* ELF register definitions.. +*/ + +#include <asm/ptrace.h> + +typedef unsigned long elf_greg_t ; +typedef unsigned long elf_freg_t [3 ]; + +extern unsigned int elf_hwcap; + +#define EM_NDS32 167 + +#define R_NDS32_NONE 0 +#define R_NDS32_16_RELA 19 +#define R_NDS32_32_RELA 20 +#define R_NDS32_9_PCREL_RELA 22 +#define R_NDS32_15_PCREL_RELA 23 +#define R_NDS32_17_PCREL_RELA 24 +#define R_NDS32_25_PCREL_RELA 25 +#define R_NDS32_HI20_RELA 26 +#define R_NDS32_LO12S3_RELA 27 +#define R_NDS32_LO12S2_RELA 28 +#define R_NDS32_LO12S1_RELA 29 +#define R_NDS32_LO12S0_RELA 30 +#define R_NDS32_SDA15S3_RELA 31 +#define R_NDS32_SDA15S2_RELA 32 +#define R_NDS32_SDA15S1_RELA 33 +#define R_NDS32_SDA15S0_RELA 34 +#define R_NDS32_GOT20 37 +#define R_NDS32_25_PLTREL 38 +#define R_NDS32_COPY 39 +#define R_NDS32_GLOB_DAT 40 +#define R_NDS32_JMP_SLOT 41 +#define R_NDS32_RELATIVE 42 +#define R_NDS32_GOTOFF 43 +#define R_NDS32_GOTPC20 44 +#define R_NDS32_GOT_HI20 45 +#define R_NDS32_GOT_LO12 46 +#define R_NDS32_GOTPC_HI20 47 +#define R_NDS32_GOTPC_LO12 48 +#define R_NDS32_GOTOFF_HI20 49 +#define R_NDS32_GOTOFF_LO12 50 +#define R_NDS32_INSN16 51 +#define R_NDS32_LABEL 52 +#define R_NDS32_LONGCALL1 53 +#define R_NDS32_LONGCALL2 54 +#define R_NDS32_LONGCALL3 55 +#define R_NDS32_LONGJUMP1 56 +#define R_NDS32_LONGJUMP2 57 +#define R_NDS32_LONGJUMP3 58 +#define R_NDS32_LOADSTORE 59 +#define R_NDS32_9_FIXED_RELA 60 +#define R_NDS32_15_FIXED_RELA 61 +#define R_NDS32_17_FIXED_RELA 62 +#define R_NDS32_25_FIXED_RELA 63 +#define R_NDS32_PLTREL_HI20 64 +#define R_NDS32_PLTREL_LO12 65 +#define R_NDS32_PLT_GOTREL_HI20 66 +#define R_NDS32_PLT_GOTREL_LO12 67 +#define R_NDS32_LO12S0_ORI_RELA 72 +#define R_NDS32_DWARF2_OP1_RELA 77 +#define R_NDS32_DWARF2_OP2_RELA 78 +#define R_NDS32_DWARF2_LEB_RELA 79 +#define R_NDS32_WORD_9_PCREL_RELA 94 +#define R_NDS32_LONGCALL4 107 +#define R_NDS32_RELA_NOP_MIX 192 +#define R_NDS32_RELA_NOP_MAX 255 + +#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t)) +typedef elf_greg_t elf_gregset_t [ELF_NGREG ]; + +/* Core file format: The core file is written in such a way that gdb +can understand it and provide useful information to the user (under +linux we use the 'trad-core' bfd). There are quite a number of +obstacles to being able to view the contents of the floating point +registers, and until these are solved you will not be able to view the +contents of them. Actually, you can read in the core file and look at +the contents of the user struct to find out what the floating point +registers contain. +The actual file contents are as follows: +UPAGE: 1 page consisting of a user struct that tells gdb what is present +in the file. Directly after this is a copy of the task_struct, which +is currently not used by gdb, but it may come in useful at some point. +All of the registers are stored as part of the upage. The upage should +always be only one page. +DATA: The data area is stored. We use current->end_text to +current->brk to pick up all of the user variables, plus any memory +that may have been malloced. No attempt is made to determine if a page +is demand-zero or if a page is totally unused, we just cover the entire +range. All of the addresses are rounded in such a way that an integral +number of pages is written. +STACK: We need the stack information in order to get a meaningful +backtrace. We need to write the data from (esp) to +current->start_stack, so we round each of these off in order to be able +to write an integer number of pages. +The minimum core file size is 3 pages, or 12288 bytes. +*/ + +struct user_fp { +struct fp_reg { +unsigned int sign1:1 ; +unsigned int unused:15 ; +unsigned int sign2:1 ; +unsigned int exponent:14 ; +unsigned int j:1 ; +unsigned int mantissa1:31 ; +unsigned int mantissa0:32 ; + } fpregs[8 ]; +unsigned int fpsr:32 ; +unsigned int fpcr:32 ; +unsigned char ftype[8 ]; +unsigned int init_flag; +}; + +typedef struct user_fp elf_fpregset_t ; + +struct elf32_hdr ; +#define elf_check_arch (x) ((x)->e_machine == EM_NDS32) + +/* +* These are used to set parameters in the core dumps. +*/ +#define ELF_CLASS ELFCLASS32 +#ifdef __NDS32_EB__ +#define ELF_DATA ELFDATA2MSB; +#else +#define ELF_DATA ELFDATA2LSB; +#endif +#define ELF_ARCH EM_NDS32 +#define USE_ELF_CORE_DUMP +#define ELF_EXEC_PAGESIZE PAGE_SIZE + +/* This is the location that an ET_DYN program is loaded if exec'ed. Typical +use of this is to invoke "./ld.so someprog" to test out a new version of +the loader. We need to make sure that it is out of the way of the program +that it will "exec", and that there is sufficient room for the brk. */ + +#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3) + +/* When the program starts, a1 contains a pointer to a function to be +registered with atexit, as per the SVR4 ABI. A value of 0 means we +have no such handler. */ +#define ELF_PLAT_INIT (_r, load_addr) (_r)->uregs[0] = 0 + +/* This yields a mask that user programs can use to figure out what +instruction set this cpu supports. */ + +#define ELF_HWCAP (elf_hwcap) + +#ifdef __KERNEL__ + +#define ELF_PLATFORM (NULL) + +/* Old NetWinder binaries were compiled in such a way that the iBCS +heuristic always trips on them. Until these binaries become uncommon +enough not to care, don't trust the `ibcs' flag here. In any case +there is no other ELF system currently supported by iBCS. +@@ Could print a warning message to encourage users to upgrade. */ +#define SET_PERSONALITY (ex) set_personality(PER_LINUX) + +#endif + +#define ARCH_DLINFO \ +do { \ + NEW_AUX_ENT(AT_SYSINFO_EHDR, \ + (elf_addr_t)current->mm->context.vdso); \ +} while (0) +#define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1 +struct linux_binprm ; +int arch_setup_additional_pages (struct linux_binprm *,int ); + +#endif
arch/nds32/include/uapi/asm/auxvec.h new file +25 -0
@@ -0,0 +1,25 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef __ASM_AUXVEC_H +#define __ASM_AUXVEC_H + +/* VDSO location */ +#define AT_SYSINFO_EHDR 33 + +#define AT_VECTOR_SIZE_ARCH 1 + +#endif
arch/nds32/include/uapi/asm/param.h new file +24 -0
@@ -0,0 +1,24 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef __ASM_NDS32_PARAM_H +#define __ASM_NDS32_PARAM_H + +#define EXEC_PAGESIZE 8192 + +#include <asm-generic/param.h> + +#endif /* __ASM_NDS32_PARAM_H */
Signature · 1 line
1.7.9.5
PATCH v2 14/35 nds32: System calls handling
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
This patch adds support for system calls.
--- arch/nds32/include/asm/syscall.h | 203 ++++++++++++++++++++++++++++++++++ arch/nds32/include/asm/syscalls.h | 27 +++++ arch/nds32/include/asm/unistd.h | 19 ++++ arch/nds32/include/uapi/asm/unistd.h | 32 ++++++ arch/nds32/kernel/ex-scall.S | 145 ++++++++++++++++++++++++ arch/nds32/kernel/sys_nds32.c | 74 +++++++++++++ arch/nds32/kernel/syscall_table.c | 28 +++++ 7 files changed, 528 insertions(+) create mode 100644 arch/nds32/include/asm/syscall.h create mode 100644 arch/nds32/include/asm/syscalls.h create mode 100644 arch/nds32/include/asm/unistd.h create mode 100644 arch/nds32/include/uapi/asm/unistd.h create mode 100644 arch/nds32/kernel/ex-scall.S create mode 100644 arch/nds32/kernel/sys_nds32.c create mode 100644 arch/nds32/kernel/syscall_table.c
arch/nds32/include/asm/syscall.h new file +203 -0
@@ -0,0 +1,203 @@ +/* +* Access to user system call parameters and results +* +* Copyright (C) 2008-2009 Red Hat, Inc. All rights reserved. +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This copyrighted material is made available to anyone wishing to use, +* modify, copy, or redistribute it subject to the terms and conditions +* of the GNU General Public License v.2. +* +* This file is a stub providing documentation for what functions +* asm-ARCH/syscall.h files need to define. Most arch definitions +* will be simple inlines. +* +* All of these functions expect to be called with no locks, +* and only when the caller is sure that the task of interest +* cannot return to user mode while we are looking at it. +*/ + +#ifndef _ASM_NDS32_SYSCALL_H +#define _ASM_NDS32_SYSCALL_H 1 + +#include <linux/err.h> +struct task_struct ; +struct pt_regs ; + +/** +* syscall_get_nr - find what system call a task is executing +* @task: task of interest, must be blocked +* @regs: task_pt_regs() of @task +* +* If @task is executing a system call or is at system call +* tracing about to attempt one, returns the system call number. +* If @task is not executing a system call, i.e. it's blocked +* inside the kernel for a fault or signal, returns -1. +* +* Note this returns int even on 64-bit machines. Only 32 bits of +* system call number can be meaningful. If the actual arch value +* is 64 bits, this truncates to 32 bits so 0xffffffff means -1. +* +* It's only valid to call this when @task is known to be blocked. +*/ +int syscall_get_nr (struct task_struct *task,struct pt_regs *regs) +{ +return regs->syscallno; +} + +/** +* syscall_rollback - roll back registers after an aborted system call +* @task: task of interest, must be in system call exit tracing +* @regs: task_pt_regs() of @task +* +* It's only valid to call this when @task is stopped for system +* call exit tracing (due to TIF_SYSCALL_TRACE or TIF_SYSCALL_AUDIT), +* after tracehook_report_syscall_entry() returned nonzero to prevent +* the system call from taking place. +* +* This rolls back the register state in @regs so it's as if the +* system call instruction was a no-op. The registers containing +* the system call number and arguments are as they were before the +* system call instruction. This may not be the same as what the +* register state looked like at system call entry tracing. +*/ +void syscall_rollback (struct task_struct *task,struct pt_regs *regs) +{ + regs->uregs[0 ] = regs->orig_r0; +} + +/** +* syscall_get_error - check result of traced system call +* @task: task of interest, must be blocked +* @regs: task_pt_regs() of @task +* +* Returns 0 if the system call succeeded, or -ERRORCODE if it failed. +* +* It's only valid to call this when @task is stopped for tracing on exit +* from a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT. +*/ +long syscall_get_error (struct task_struct *task,struct pt_regs *regs) +{ +unsigned long error = regs->uregs[0 ]; +return IS_ERR_VALUE (error) ? error :0 ; +} + +/** +* syscall_get_return_value - get the return value of a traced system call +* @task: task of interest, must be blocked +* @regs: task_pt_regs() of @task +* +* Returns the return value of the successful system call. +* This value is meaningless if syscall_get_error() returned nonzero. +* +* It's only valid to call this when @task is stopped for tracing on exit +* from a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT. +*/ +long syscall_get_return_value (struct task_struct *task,struct pt_regs *regs) +{ +return regs->uregs[0 ]; +} + +/** +* syscall_set_return_value - change the return value of a traced system call +* @task: task of interest, must be blocked +* @regs: task_pt_regs() of @task +* @error: negative error code, or zero to indicate success +* @val: user return value if @error is zero +* +* This changes the results of the system call that user mode will see. +* If @error is zero, the user sees a successful system call with a +* return value of @val. If @error is nonzero, it's a negated errno +* code; the user sees a failed system call with this errno code. +* +* It's only valid to call this when @task is stopped for tracing on exit +* from a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT. +*/ +void syscall_set_return_value (struct task_struct *task,struct pt_regs *regs, +int error,long val) +{ + regs->uregs[0 ] = (long )error ? error : val; +} + +/** +* syscall_get_arguments - extract system call parameter values +* @task: task of interest, must be blocked +* @regs: task_pt_regs() of @task +* @i: argument index [0,5] +* @n: number of arguments; n+i must be [1,6]. +* @args: array filled with argument values +* +* Fetches @n arguments to the system call starting with the @i'th argument +* (from 0 through 5). Argument @i is stored in @args[0], and so on. +* An arch inline version is probably optimal when @i and @n are constants. +* +* It's only valid to call this when @task is stopped for tracing on +* entry to a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT. +* It's invalid to call this with @i + @n > 6; we only support system calls +* taking up to 6 arguments. +*/ +#define SYSCALL_MAX_ARGS 6 +void syscall_get_arguments (struct task_struct *task,struct pt_regs *regs, +unsigned int i,unsigned int n,unsigned long *args) +{ +if (n ==0 ) +return ; +if (i + n >SYSCALL_MAX_ARGS ) { +unsigned long *args_bad = args +SYSCALL_MAX_ARGS - i; +unsigned int n_bad = n + i -SYSCALL_MAX_ARGS ; +pr_warning ("%s called with max args %d, handling only %d\n" , + __func__, i + n,SYSCALL_MAX_ARGS ); +memset (args_bad,0 , n_bad *sizeof (args[0 ])); +memset (args_bad,0 , n_bad *sizeof (args[0 ])); + } + +if (i ==0 ) { + args[0 ] = regs->orig_r0; + args++; + i++; + n--; + } + +memcpy (args, ®s->uregs[0 ] + i, n *sizeof (args[0 ])); +} + +/** +* syscall_set_arguments - change system call parameter value +* @task: task of interest, must be in system call entry tracing +* @regs: task_pt_regs() of @task +* @i: argument index [0,5] +* @n: number of arguments; n+i must be [1,6]. +* @args: array of argument values to store +* +* Changes @n arguments to the system call starting with the @i'th argument. +* Argument @i gets value @args[0], and so on. +* An arch inline version is probably optimal when @i and @n are constants. +* +* It's only valid to call this when @task is stopped for tracing on +* entry to a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT. +* It's invalid to call this with @i + @n > 6; we only support system calls +* taking up to 6 arguments. +*/ +void syscall_set_arguments (struct task_struct *task,struct pt_regs *regs, +unsigned int i,unsigned int n, +const unsigned long *args) +{ +if (n ==0 ) +return ; + +if (i + n >SYSCALL_MAX_ARGS ) { +pr_warn ("%s called with max args %d, handling only %d\n" , + __func__, i + n,SYSCALL_MAX_ARGS ); + n =SYSCALL_MAX_ARGS - i; + } + +if (i ==0 ) { + regs->orig_r0 = args[0 ]; + args++; + i++; + n--; + } + +memcpy (®s->uregs[0 ] + i, args, n *sizeof (args[0 ])); +} +#endif /* _ASM_NDS32_SYSCALL_H */
arch/nds32/include/asm/syscalls.h new file +27 -0
@@ -0,0 +1,27 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef __ASM_NDS32_SYSCALLS_H +#define __ASM_NDS32_SYSCALLS_H + +int sys_cacheflush (unsigned long addr,unsigned long len,unsigned int op); +long sys_fadvise64_64_wrapper (int fd,int advice,loff_t offset,loff_t len); +asmlinkage int sys_syscall(void); +asmlinkage int sys_rt_sigreturn_wrapper(void); + +#include <asm-generic/syscalls.h> + +#endif /* __ASM_NDS32_SYSCALLS_H */
arch/nds32/include/asm/unistd.h new file +19 -0
@@ -0,0 +1,19 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#define __ARCH_WANT_SYS_CLONE + +#include <uapi/asm/unistd.h>
arch/nds32/include/uapi/asm/unistd.h new file +32 -0
@@ -0,0 +1,32 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#define __ARCH_WANT_RENAMEAT +#define __ARCH_WANT_SYSCALL_OFF_T +#define __ARCH_WANT_SYNC_FILE_RANGE2 + +/* Use the standard ABI for syscalls */ +#include <asm-generic/unistd.h> + +/* Additional NDS32 specific syscalls. */ +#define __NR_cacheflush (__NR_arch_specific_syscall) +#define __NR__llseek __NR_llseek +__SYSCALL(__NR_cacheflush, sys_cacheflush) + +__SYSCALL(__NR_fadvise64_64, sys_fadvise64_64_wrapper) +__SYSCALL (__NR_rt_sigreturn, sys_rt_sigreturn_wrapper) + +
arch/nds32/kernel/ex-scall.S new file +145 -0
145 lines not on this page · raw message
arch/nds32/kernel/sys_nds32.c new file +74 -0
74 lines not on this page · raw message
arch/nds32/kernel/syscall_table.c new file +28 -0
@@ -0,0 +1,28 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <linux/syscalls.h> +#include <linux/signal.h> +#include <linux/unistd.h> +#include <asm/syscalls.h> + +#undef __SYSCALL +#define __SYSCALL (nr, call) [nr] = (call), + +void *sys_call_table[__NR_syscalls]__aligned(8192) = { + [0 ... __NR_syscalls -1 ] = sys_ni_syscall, +#include <asm/unistd.h> +};
Signature · 1 line
1.7.9.5
Arnd Bergmann
maintainerRe: [PATCH v2 14/35] nds32: System calls handling
Quoted 19 lines · Greentime Hu
arch/nds32/include/asm/syscalls.h new file +13
-0@@ -0,0 +1,27 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License
arch/nds32/include/asm/syscalls.h line 23
Quoted 10 lines
arch/nds32/include/asm/syscalls.h new file +10
-0+* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef __ASM_NDS32_SYSCALLS_H +#define __ASM_NDS32_SYSCALLS_H + +int sys_cacheflush (unsigned long addr,unsigned long len,unsigned int op); +long sys_fadvise64_64_wrapper (int fd,int advice,loff_t offset,loff_t len); +asmlinkage int sys_syscall(void); +asmlinkage int sys_rt_sigreturn_wrapper(void);
You mentioned that sys_syscall() should be removed in this version.
By convention, all syscall declarations should start with 'asmlinkage long', even though this has no effect in your architecture.
arch/nds32/include/uapi/asm/unistd.h line 18
Quoted 9 lines
arch/nds32/include/uapi/asm/unistd.h new file +3
-0+ +#define __ARCH_WANT_RENAMEAT +#define __ARCH_WANT_SYSCALL_OFF_T
These two should not be here.
Quoted 1 line
+#define
__ARCH_WANT_SYNC_FILE_RANGE2
This one is fine though
arch/nds32/include/uapi/asm/unistd.h line 30
Quoted 5 lines
arch/nds32/include/uapi/asm/unistd.h new file +5
-0+/* Use the standard ABI for syscalls */ +#include <asm-generic/unistd.h> + +__SYSCALL(__NR_fadvise64_64, sys_fadvise64_64_wrapper) +__SYSCALL (__NR_rt_sigreturn, sys_rt_sigreturn_wrapper)
I think you are overriding the array assignment here, this may cause a compiler warning when building with "make C=1 V=1" since you have the same index assigned to two pointers. A better way to do this is to override the name:
#define sys_rt_sigreturn sys_rt_sigreturn_wrapper
#define sys_fadvise64_64 sys_fadvise64_64_wrapper
#include <asm-generic/unistd.h>
Arnd
Re: [PATCH v2 14/35] nds32: System calls handling
2017-11-27 22:46 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 25 lines · Greentime Hu
Quoted 24 lines
arch/nds32/include/asm/syscalls.h new file +17
-0@@ -0,0 +1,27 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef __ASM_NDS32_SYSCALLS_H
Quoted 9 lines
arch/nds32/include/asm/syscalls.h line 23
Quoted 6 lines
arch/nds32/include/asm/syscalls.h new file +6
-0+#define __ASM_NDS32_SYSCALLS_H + +int sys_cacheflush (unsigned long addr,unsigned long len,unsigned int op); +long sys_fadvise64_64_wrapper (int fd,int advice,loff_t offset,loff_t len); +asmlinkage int sys_syscall(void); +asmlinkage int sys_rt_sigreturn_wrapper(void);You mentioned that
sys_syscall()should be removed in this version.
Sorry, I will remove it in next version patch.
Quoted 3 lines
By convention, all syscall declarations should start with 'asmlinkage long', even though this has no effect in your architecture.
Thanks.
I will modify it in next version patch.
Quoted 6 lines
Quoted 5 lines
arch/nds32/include/uapi/asm/unistd.h new file +0
-0
Quoted 6 lines
arch/nds32/include/uapi/asm/unistd.h line 18
Quoted 3 lines
arch/nds32/include/uapi/asm/unistd.h new file +3
-0+ +#define __ARCH_WANT_RENAMEAT +#define __ARCH_WANT_SYSCALL_OFF_TThese two should not be here.
Thanks.
But, I don't know I should move these two macro to which file. In asm-generic/unistd.h, these two are used to decide whether relative syscall number is defined or not.
Therefore, I put these two macros here in order that these two definitions are available in user space.
Quoted 15 lines
Quoted 1 line
+#define
__ARCH_WANT_SYNC_FILE_RANGE2This one is fine though
arch/nds32/include/uapi/asm/unistd.h line 30
Quoted 5 lines
arch/nds32/include/uapi/asm/unistd.h new file +5
-0+/* Use the standard ABI for syscalls */ +#include <asm-generic/unistd.h> + +__SYSCALL(__NR_fadvise64_64, sys_fadvise64_64_wrapper) +__SYSCALL (__NR_rt_sigreturn, sys_rt_sigreturn_wrapper)I think you are overriding the array assignment here, this may cause a compiler warning when building with "make C=1 V=1" since you have the same index assigned to two pointers. A better way to do this is to override the name:
Quoted 4 lines
#define
sys_rt_sigreturnsys_rt_sigreturn_wrapper
#definesys_fadvise64_64sys_fadvise64_64_wrapper
#include <asm-generic/unistd.h>
Thanks,
I will follow your suggestion to modify it in the next version patch.
Quoted 2 lines
Arnd
Vincent
Arnd Bergmann
maintainerRe: [PATCH v2 14/35] nds32: System calls handling
Quoted 16 lines · Vincent Chen
2017-11-27 22:46 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 8 lines · Greentime Hu
Quoted 6 lines
arch/nds32/include/uapi/asm/unistd.h new file +0
-0Quoted 6 lines
arch/nds32/include/uapi/asm/unistd.h line 18
Quoted 3 lines
arch/nds32/include/uapi/asm/unistd.h new file +3
-0+ +#define __ARCH_WANT_RENAMEAT +#define __ARCH_WANT_SYSCALL_OFF_TThese two should not be here.
Quoted 6 lines
Thanks.
But, I don't know I should move these two macro to which file. Inasm-generic/unistd.h, these two are used to decide whether relative syscall number is defined or not.
Therefore, I put these two macros here in order that these two definitions are available in user space.
What I meant is that they should not be available to user space.
The C libraries implement the user space interfaces based on the replacement system calls, e.g. an application calling the glibc stat() function will end up in the sys_stat64() system call entry point, not the older sys_newstat().
Arnd
PATCH v2 15/35 nds32: VDSO support
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
This patch adds VDSO support. The VDSO code is currently used for sys_rt_sigreturn() and optimised gettimeofday() (using the SoC timer counter).
--- arch/nds32/include/asm/vdso.h | 35 ++++ arch/nds32/include/asm/vdso_datapage.h | 51 ++++++ arch/nds32/kernel/vdso.c | 245 +++++++++++++++++++++++++ arch/nds32/kernel/vdso/Makefile | 82 +++++++++ arch/nds32/kernel/vdso/datapage.S | 34 ++++ arch/nds32/kernel/vdso/gen_vdso_offsets.sh | 15 ++ arch/nds32/kernel/vdso/gettimeofday.c | 266 ++++++++++++++++++++++++++++ arch/nds32/kernel/vdso/note.S | 29 +++ arch/nds32/kernel/vdso/sigreturn.S | 33 ++++ arch/nds32/kernel/vdso/vdso.S | 33 ++++ arch/nds32/kernel/vdso/vdso.lds.S | 87 +++++++++ 11 files changed, 910 insertions(+) create mode 100644 arch/nds32/include/asm/vdso.h create mode 100644 arch/nds32/include/asm/vdso_datapage.h create mode 100644 arch/nds32/kernel/vdso.c create mode 100644 arch/nds32/kernel/vdso/Makefile create mode 100644 arch/nds32/kernel/vdso/datapage.S create mode 100755 arch/nds32/kernel/vdso/gen_vdso_offsets.sh create mode 100644 arch/nds32/kernel/vdso/gettimeofday.c create mode 100644 arch/nds32/kernel/vdso/note.S create mode 100644 arch/nds32/kernel/vdso/sigreturn.S create mode 100644 arch/nds32/kernel/vdso/vdso.S create mode 100644 arch/nds32/kernel/vdso/vdso.lds.S
arch/nds32/include/asm/vdso.h new file +35 -0
@@ -0,0 +1,35 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef __ASM_VDSO_H +#define __ASM_VDSO_H + +#ifdef __KERNEL__ + +#ifndef __ASSEMBLY__ + +#include <generated/vdso-offsets.h> + +#define VDSO_SYMBOL (base, name) \ +({ \ + (unsigned long)(vdso_offset_##name + (unsigned long)(base)); \ +}) + +#endif /* !__ASSEMBLY__ */ + +#endif /* __KERNEL__ */ + +#endif /* __ASM_VDSO_H */
arch/nds32/include/asm/vdso_datapage.h new file +51 -0
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arch/nds32/kernel/vdso.c new file +245 -0
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arch/nds32/kernel/vdso/Makefile new file +82 -0
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arch/nds32/kernel/vdso/datapage.S new file +34 -0
@@ -0,0 +1,34 @@ +/* + * Copyright (C) 2005-2017 Andes Technology Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/linkage.h> +#include <asm/page.h> + +ENTRY(__get_timerpage) + sethi $r0, hi20(. + PAGE_SIZE + 8) + ori $r0, $r0, lo12(. + PAGE_SIZE + 4) + mfusr $r1, $pc + sub $r0, $r1, $r0 + ret +ENDPROC(__get_timerpage) + +ENTRY(__get_datapage) + sethi $r0, hi20(. + 2*PAGE_SIZE + 8) + ori $r0, $r0, lo12(. + 2*PAGE_SIZE + 4) + mfusr $r1, $pc + sub $r0, $r1, $r0 + ret +ENDPROC(__get_datapage)
arch/nds32/kernel/vdso/gen_vdso_offsets.sh new file +15 -0
@@ -0,0 +1,15 @@ +#!/bin/sh + +# +# Match symbols in the DSO that look like VDSO_*; produce a header file +# of constant offsets into the shared object. +# +# Doing this inside the Makefile will break the $(filter-out) function, +# causing Kbuild to rebuild the vdso-offsets header file every time. +# +# Author: Will Deacon <[email protected] +# + +LC_ALL=C +sed -n -e 's/^00*/0/' -e \ +'s/^\([0-9a-fA-F]*\) . VDSO_\([a-zA-Z0-9_]*\)$/\#define vdso_offset_\2\t0x\1/p'
arch/nds32/kernel/vdso/gettimeofday.c new file +266 -0
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arch/nds32/kernel/vdso/note.S new file +29 -0
@@ -0,0 +1,29 @@ +/* + * Copyright (C) 2012 ARM Limited + * Copyright (C) 2005-2017 Andes Technology Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + * Author: Will Deacon <[email protected]> + * + * This supplies .note.* sections to go into the PT_NOTE inside the vDSO text. + * Here we can supply some information useful to userland. + */ + +#include <linux/uts.h> +#include <linux/version.h> +#include <linux/elfnote.h> + +ELFNOTE_START(Linux, 0, "a") + .long LINUX_VERSION_CODE +ELFNOTE_END
arch/nds32/kernel/vdso/sigreturn.S new file +33 -0
@@ -0,0 +1,33 @@ +/* + * Sigreturn trampoline for returning from a signal when the SA_RESTORER + * flag is not set. + * + * Copyright (C) 2012 ARM Limited + * Copyright (C) 2005-2017 Andes Technology Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + * Author: Will Deacon <[email protected]> + */ + +#include <linux/linkage.h> +#include <asm/unistd.h> + + .text + +ENTRY(__kernel_rt_sigreturn) + .cfi_startproc + movi $r15, __NR_rt_sigreturn + syscall 0x0 + .cfi_endproc +ENDPROC(__kernel_rt_sigreturn)
arch/nds32/kernel/vdso/vdso.S new file +33 -0
@@ -0,0 +1,33 @@ +/* + * Copyright (C) 2012 ARM Limited + * Copyright (C) 2005-2017 Andes Technology Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + * Author: Will Deacon <[email protected]> + */ + +#include <linux/init.h> +#include <linux/linkage.h> +#include <linux/const.h> +#include <asm/page.h> + + .globl vdso_start, vdso_end + .section .rodata + .balign PAGE_SIZE +vdso_start: + .incbin "arch/nds32/kernel/vdso/vdso.so" + .balign PAGE_SIZE +vdso_end: + + .previous
arch/nds32/kernel/vdso/vdso.lds.S new file +87 -0
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Signature · 1 line
1.7.9.5
PATCH v2 16/35 nds32: Signal handling support
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
This patch adds support for signal handling.
--- arch/nds32/include/uapi/asm/sigcontext.h | 73 ++++++ arch/nds32/include/uapi/asm/signal.h | 23 ++ arch/nds32/kernel/signal.c | 354 ++++++++++++++++++++++++++++++ 3 files changed, 450 insertions(+) create mode 100644 arch/nds32/include/uapi/asm/sigcontext.h create mode 100644 arch/nds32/include/uapi/asm/signal.h create mode 100644 arch/nds32/kernel/signal.c
arch/nds32/include/uapi/asm/sigcontext.h new file +73 -0
@@ -0,0 +1,73 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef _ASMNDS32_SIGCONTEXT_H +#define _ASMNDS32_SIGCONTEXT_H + +/* +* Signal context structure - contains all info to do with the state +* before the signal handler was invoked. Note: only add new entries +* to the end of the structure. +*/ + +struct zol_struct { +unsigned long nds32_lc;/* $LC */ +unsigned long nds32_le;/* $LE */ +unsigned long nds32_lb;/* $LB */ +}; + +struct sigcontext { +unsigned long trap_no; +unsigned long error_code; +unsigned long oldmask; +unsigned long nds32_r0; +unsigned long nds32_r1; +unsigned long nds32_r2; +unsigned long nds32_r3; +unsigned long nds32_r4; +unsigned long nds32_r5; +unsigned long nds32_r6; +unsigned long nds32_r7; +unsigned long nds32_r8; +unsigned long nds32_r9; +unsigned long nds32_r10; +unsigned long nds32_r11; +unsigned long nds32_r12; +unsigned long nds32_r13; +unsigned long nds32_r14; +unsigned long nds32_r15; +unsigned long nds32_r16; +unsigned long nds32_r17; +unsigned long nds32_r18; +unsigned long nds32_r19; +unsigned long nds32_r20; +unsigned long nds32_r21; +unsigned long nds32_r22; +unsigned long nds32_r23; +unsigned long nds32_r24; +unsigned long nds32_r25; +unsigned long nds32_fp;/* $r28 */ +unsigned long nds32_gp;/* $r29 */ +unsigned long nds32_lp;/* $r30 */ +unsigned long nds32_sp;/* $r31 */ +unsigned long nds32_ipc; +unsigned long fault_address; +unsigned long used_math_flag; +/* FPU Registers */ +struct zol_struct zol; +}; + +#endif
arch/nds32/include/uapi/asm/signal.h new file +23 -0
@@ -0,0 +1,23 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef _ASMNDS32_SIGNAL_H +#define _ASMNDS32_SIGNAL_H + +#define SA_RESTORER 0x04000000 + +#include <asm-generic/signal.h> +#endif
arch/nds32/kernel/signal.c new file +354 -0
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Signature · 1 line
1.7.9.5
Arnd Bergmann
maintainerRe: [PATCH v2 16/35] nds32: Signal handling support
arch/nds32/include/uapi/asm/signal.h line 23
Quoted 7 lines · Greentime Hu
arch/nds32/include/uapi/asm/signal.h new file +7
-0+#ifndef _ASMNDS32_SIGNAL_H +#define _ASMNDS32_SIGNAL_H + +#define SA_RESTORER 0x04000000 + +#include <asm-generic/signal.h> +#endif
As documented in asm-generic/signal.h, new architectures should not define SA_RESTORER.
Arnd
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Re: [PATCH v2 16/35] nds32: Signal handling support
2017-11-27 22:37 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 13 lines · Greentime Hu
arch/nds32/include/uapi/asm/signal.h line 23
Quoted 8 lines
arch/nds32/include/uapi/asm/signal.h new file +7
-0+#ifndef _ASMNDS32_SIGNAL_H +#define _ASMNDS32_SIGNAL_H + +#define SA_RESTORER 0x04000000 + +#include <asm-generic/signal.h> +#endif As documented in
asm-generic/signal.h, new architectures should not defineSA_RESTORER.
Thanks.
I will remove it in the next version patch.
Quoted 1 line
Arnd
Vincent
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PATCH v2 17/35 nds32: Library functions
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
This patch add support for various library functions.
--- arch/nds32/include/asm/string.h | 30 ++++ arch/nds32/include/asm/swab.h | 48 +++++++ arch/nds32/include/asm/uaccess.h | 296 ++++++++++++++++++++++++++++++++++++++ arch/nds32/kernel/nds32_ksyms.c | 44 ++++++ arch/nds32/lib/Makefile | 3 + arch/nds32/lib/clear_user.S | 55 +++++++ arch/nds32/lib/copy_from_user.S | 58 ++++++++ arch/nds32/lib/copy_template.S | 83 +++++++++++ arch/nds32/lib/copy_to_user.S | 58 ++++++++ arch/nds32/lib/memcpy.S | 43 ++++++ arch/nds32/lib/memmove.S | 83 +++++++++++ arch/nds32/lib/memset.S | 46 ++++++ arch/nds32/lib/memzero.S | 31 ++++ 13 files changed, 878 insertions(+) create mode 100644 arch/nds32/include/asm/string.h create mode 100644 arch/nds32/include/asm/swab.h create mode 100644 arch/nds32/include/asm/uaccess.h create mode 100644 arch/nds32/kernel/nds32_ksyms.c create mode 100644 arch/nds32/lib/Makefile create mode 100644 arch/nds32/lib/clear_user.S create mode 100644 arch/nds32/lib/copy_from_user.S create mode 100644 arch/nds32/lib/copy_template.S create mode 100644 arch/nds32/lib/copy_to_user.S create mode 100644 arch/nds32/lib/memcpy.S create mode 100644 arch/nds32/lib/memmove.S create mode 100644 arch/nds32/lib/memset.S create mode 100644 arch/nds32/lib/memzero.S
arch/nds32/include/asm/string.h new file +30 -0
@@ -0,0 +1,30 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef __ASM_NDS32_STRING_H +#define __ASM_NDS32_STRING_H + +#define __HAVE_ARCH_MEMCPY +extern void *memcpy (void *,const void *,__kernel_size_t ); + +#define __HAVE_ARCH_MEMMOVE +extern void *memmove (void *,const void *,__kernel_size_t ); + +#define __HAVE_ARCH_MEMSET +extern void *memset (void *,int ,__kernel_size_t ); + +extern void *memzero (void *ptr,__kernel_size_t n); +#endif
arch/nds32/include/asm/swab.h new file +48 -0
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arch/nds32/include/asm/uaccess.h new file +296 -0
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arch/nds32/kernel/nds32_ksyms.c new file +44 -0
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arch/nds32/lib/Makefile new file +3 -0
@@ -0,0 +1,3 @@ +lib-y := copy_page.o memcpy.o memmove.o \ + memset.o memzero.o \ + copy_from_user.o copy_to_user.o clear_user.o
arch/nds32/lib/clear_user.S new file +55 -0
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arch/nds32/lib/copy_from_user.S new file +58 -0
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arch/nds32/lib/copy_template.S new file +83 -0
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arch/nds32/lib/copy_to_user.S new file +58 -0
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arch/nds32/lib/memcpy.S new file +43 -0
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arch/nds32/lib/memmove.S new file +83 -0
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arch/nds32/lib/memset.S new file +46 -0
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arch/nds32/lib/memzero.S new file +31 -0
@@ -0,0 +1,31 @@ +/* + * Copyright (C) 2005-2017 Andes Technology Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/linkage.h> + + .text +ENTRY(memzero) + beqz $r1, 1f + push $lp + move $r2, $r1 + move $r1, #0 + push $r0 + bal memset + pop $r0 + pop $lp +1: + ret +ENDPROC(memzero)
Signature · 1 line
1.7.9.5
PATCH v2 18/35 nds32: Debugging support
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
This patch adds ptrace support.
--- arch/nds32/include/uapi/asm/ptrace.h | 42 +++++ arch/nds32/kernel/ptrace.c | 325 ++++++++++++++++++++++++++++++++++ 2 files changed, 367 insertions(+) create mode 100644 arch/nds32/include/uapi/asm/ptrace.h create mode 100644 arch/nds32/kernel/ptrace.c
arch/nds32/include/uapi/asm/ptrace.h new file +42 -0
@@ -0,0 +1,42 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef __UAPI_ASM_NDS32_PTRACE_H +#define __UAPI_ASM_NDS32_PTRACE_H + +#ifndef __ASSEMBLY__ + +/* +* User structures for general purpose register. +*/ +struct user_pt_regs { +long uregs[26 ]; +long fp; +long gp; +long lp; +long sp; +long ipc; +#if defined(CONFIG_HWZOL ) +long lb; +long le; +long lc; +#else +long dummy[3 ]; +#endif +long syscallno; +}; +#endif +#endif
arch/nds32/kernel/ptrace.c new file +325 -0
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Signature · 1 line
1.7.9.5
Arnd Bergmann
maintainerRe: [PATCH v2 18/35] nds32: Debugging support
Quoted 6 lines · Greentime Hu
arch/nds32/include/uapi/asm/ptrace.h new file +6
-0+struct user_pt_regs { +long uregs[26 ]; +long fp; +long gp; +long lp; +long sp;
arch/nds32/include/uapi/asm/ptrace.h line 40
Quoted 10 lines
arch/nds32/include/uapi/asm/ptrace.h new file +10
-0+long ipc; +#if defined(CONFIG_HWZOL ) +long lb; +long le; +long lc; +#else +long dummy[3 ]; +#endif +long syscallno; +};
You cannot reference CONFIG_ symbols in a uapi header, since the configuration headers
are not available.
Arnd
Re: [PATCH v2 18/35] nds32: Debugging support
2017-11-27 22:34 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 13 lines · Greentime Hu
Quoted 12 lines
arch/nds32/include/uapi/asm/ptrace.h new file +12
-0+struct user_pt_regs { +long uregs[26 ]; +long fp; +long gp; +long lp; +long sp; +long ipc; +#if defined(CONFIG_HWZOL ) +long lb; +long le; +long lc; +#else
Quoted 9 lines
arch/nds32/include/uapi/asm/ptrace.h line 40
Quoted 4 lines
arch/nds32/include/uapi/asm/ptrace.h new file +4
-0+long dummy[3 ]; +#endif +long syscallno; +};You cannot reference
CONFIG_symbols in a uapi header, since the configuration headers
are not available.
Thanks
I will modify it in the next version patch.
Quoted 1 line
Arnd
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PATCH v2 19/35 nds32: L2 cache support
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
This patch adds L2 cache support.
--- arch/nds32/include/asm/l2_cache.h | 155 +++++++++++++++++++++++++++++++++++++ arch/nds32/kernel/atl2c.c | 77 ++++++++++++++++++ 2 files changed, 232 insertions(+) create mode 100644 arch/nds32/include/asm/l2_cache.h create mode 100644 arch/nds32/kernel/atl2c.c
arch/nds32/include/asm/l2_cache.h new file +155 -0
@@ -0,0 +1,155 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef L2_CACHE_H +#define L2_CACHE_H + +/* CCTL_CMD_OP */ +#define L2_CA_CONF_OFF 0x0 +#define L2_IF_CONF_OFF 0x4 +#define L2CC_SETUP_OFF 0x8 +#define L2CC_PROT_OFF 0xC +#define L2CC_CTRL_OFF 0x10 +#define L2_INT_EN_OFF 0x20 +#define L2_STA_OFF 0x24 +#define RDERR_ADDR_OFF 0x28 +#define WRERR_ADDR_OFF 0x2c +#define EVDPTERR_ADDR_OFF 0x30 +#define IMPL3ERR_ADDR_OFF 0x34 +#define L2_CNT0_CTRL_OFF 0x40 +#define L2_EVNT_CNT0_OFF 0x44 +#define L2_CNT1_CTRL_OFF 0x48 +#define L2_EVNT_CNT1_OFF 0x4c +#define L2_CCTL_CMD_OFF 0x60 +#define L2_CCTL_STATUS_OFF 0x64 +#define L2_LINE_TAG_OFF 0x68 +#define L2_LINE_DPT_OFF 0x70 + +#define CCTL_CMD_L2_IX_INVAL 0x0 +#define CCTL_CMD_L2_PA_INVAL 0x1 +#define CCTL_CMD_L2_IX_WB 0x2 +#define CCTL_CMD_L2_PA_WB 0x3 +#define CCTL_CMD_L2_PA_WBINVAL 0x5 +#define CCTL_CMD_L2_SYNC 0xa + +/* CCTL_CMD_TYPE */ +#define CCTL_SINGLE_CMD 0 +#define CCTL_BLOCK_CMD 0x10 +#define CCTL_ALL_CMD 0x10 + +/****************************************************************************** +* L2_CA_CONF (Cache architecture configuration) +*****************************************************************************/ +#define L2_CA_CONF_offL2SET 0 +#define L2_CA_CONF_offL2WAY 4 +#define L2_CA_CONF_offL2CLSZ 8 +#define L2_CA_CONF_offL2DW 11 +#define L2_CA_CONF_offL2PT 14 +#define L2_CA_CONF_offL2VER 16 + +#define L2_CA_CONF_mskL2SET (0xFUL << L2_CA_CONF_offL2SET) +#define L2_CA_CONF_mskL2WAY (0xFUL << L2_CA_CONF_offL2WAY) +#define L2_CA_CONF_mskL2CLSZ (0x7UL << L2_CA_CONF_offL2CLSZ) +#define L2_CA_CONF_mskL2DW (0x7UL << L2_CA_CONF_offL2DW) +#define L2_CA_CONF_mskL2PT (0x3UL << L2_CA_CONF_offL2PT) +#define L2_CA_CONF_mskL2VER (0xFFFFUL << L2_CA_CONF_offL2VER) + +/****************************************************************************** +* L2CC_SETUP (L2CC Setup register) +*****************************************************************************/ +#define L2CC_SETUP_offPART 0 +#define L2CC_SETUP_mskPART (0x3UL << L2CC_SETUP_offPART) +#define L2CC_SETUP_offDDLATC 4 +#define L2CC_SETUP_mskDDLATC (0x3UL << L2CC_SETUP_offDDLATC) +#define L2CC_SETUP_offTDLATC 8 +#define L2CC_SETUP_mskTDLATC (0x3UL << L2CC_SETUP_offTDLATC) + +/****************************************************************************** +* L2CC_PROT (L2CC Protect register) +*****************************************************************************/ +#define L2CC_PROT_offMRWEN 31 +#define L2CC_PROT_mskMRWEN (0x1UL << L2CC_PROT_offMRWEN) + +/****************************************************************************** +* L2_CCTL_STATUS_Mn (The L2CCTL command working status for Master n) +*****************************************************************************/ +#define L2CC_CTRL_offEN 31 +#define L2CC_CTRL_mskEN (0x1UL << L2CC_CTRL_offEN) + +/****************************************************************************** +* L2_CCTL_STATUS_Mn (The L2CCTL command working status for Master n) +*****************************************************************************/ +#define L2_CCTL_STATUS_offCMD_COMP 31 +#define L2_CCTL_STATUS_mskCMD_COMP (0x1 << L2_CCTL_STATUS_offCMD_COMP) + +#ifndef __ASSEMBLY__ +extern void __iomem *atl2c_base; + +#include <linux/smp.h> +#include <asm/io.h> +#include <asm/bitfield.h> + +#define L2C_R_REG (offset) __raw_readl(atl2c_base + offset) +#define L2C_W_REG (offset, value) __raw_writel(value, atl2c_base + offset) + +#define L2_CMD_RDY () \ + do{;}while((L2C_R_REG(L2_CCTL_STATUS_OFF) & L2_CCTL_STATUS_mskCMD_COMP) == 0) + +static inline unsigned long L2_CACHE_SET (void ) +{ +return 64 << ((L2C_R_REG (L2_CA_CONF_OFF ) & L2_CA_CONF_mskL2SET) >> + L2_CA_CONF_offL2SET); +} + +static inline unsigned long L2_CACHE_WAY (void ) +{ +return 1 + + ((L2C_R_REG (L2_CA_CONF_OFF ) & L2_CA_CONF_mskL2WAY) >> + L2_CA_CONF_offL2WAY); +} + +static inline unsigned long L2_CACHE_LINE_SIZE (void ) +{ + +return 4 << ((L2C_R_REG (L2_CA_CONF_OFF ) & L2_CA_CONF_mskL2CLSZ) >> + L2_CA_CONF_offL2CLSZ); +} + +static inline unsigned long GET_L2CC_CTRL_CPU (unsigned long cpu) +{ +if (cpu ==smp_processor_id ()) +return L2C_R_REG (L2CC_CTRL_OFF ); +return L2C_R_REG (L2CC_CTRL_OFF + (cpu <<8 )); +} + +static inline void SET_L2CC_CTRL_CPU (unsigned long cpu,unsigned long val) +{ +if (cpu ==smp_processor_id ()) +L2C_W_REG (L2CC_CTRL_OFF , val); +else +L2C_W_REG (L2CC_CTRL_OFF + (cpu <<8 ), val); +} + +static inline unsigned long GET_L2CC_STATUS_CPU (unsigned long cpu) +{ +if (cpu ==smp_processor_id ()) +return L2C_R_REG (L2_CCTL_STATUS_OFF ); +return L2C_R_REG (L2_CCTL_STATUS_OFF + (cpu <<8 )); +} + +#endif + +#endif
arch/nds32/kernel/atl2c.c new file +77 -0
77 lines not on this page · raw message
Signature · 1 line
1.7.9.5
Arnd Bergmann
maintainerRe: [PATCH v2 19/35] nds32: L2 cache support
arch/nds32/include/asm/l2_cache.h line 106
Quoted 3 lines · Greentime Hu
arch/nds32/include/asm/l2_cache.h new file +3
-0+ +#define L2C_R_REG (offset) __raw_readl(atl2c_base + offset) +#define L2C_W_REG (offset, value) __raw_writel(value, atl2c_base + offset)
__raw_readl() is generally not endian-safe, and might not have the barriers you require here. Could you use readl/writel here, and only fall back to readl_relaxed()/writel_relaxed() when you absolutely must avoid the barriers?
arch/nds32/kernel/atl2c.c line 21
Quoted 10 lines
arch/nds32/kernel/atl2c.c new file +5
-0+#include <linux/compiler.h> +#include <linux/of_address.h> +#include <linux/of_fdt.h> +#include <linux/of_platform.h> +#include <asm/l2_cache.h>
If this is the only file that includes asm/l2_cache.h, then I'd simply move the entire
contents in here, rather than having a separate file in the global namespace.
Arnd
Re: [PATCH v2 19/35] nds32: L2 cache support
Hi, Arnd:
2017-11-27 22:33 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 8 lines · Greentime Hu
arch/nds32/include/asm/l2_cache.h line 106
Quoted 3 lines
arch/nds32/include/asm/l2_cache.h new file +3
-0+ +#define L2C_R_REG (offset) __raw_readl(atl2c_base + offset) +#define L2C_W_REG (offset, value) __raw_writel(value, atl2c_base + offset)
__raw_readl()is generally not endian-safe, and might not have the barriers you require here. Could you use readl/writel here, and only fall back to readl_relaxed()/writel_relaxed() when you absolutely must avoid the barriers?
Thanks for your suggestions.
We will changed it to readl/writel
Quoted 6 lines
Quoted 6 lines
arch/nds32/kernel/atl2c.c new file +1
-0+#include <linux/compiler.h>
Quoted 9 lines
arch/nds32/kernel/atl2c.c line 21
Quoted 4 lines
arch/nds32/kernel/atl2c.c new file +4
-0+#include <linux/of_address.h> +#include <linux/of_fdt.h> +#include <linux/of_platform.h> +#include <asm/l2_cache.h> If this is the only file that includes
asm/l2_cache.h, then I'd simply move the entire
contents in here, rather than having a separate file in the global namespace.
arch/nds32/mm/proc.c also includes this file so I will keep it.
PATCH v2 20/35 nds32: Loadable modules
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
This patch adds support for loadable modules.
--- arch/nds32/include/asm/module.h | 24 ++++ arch/nds32/kernel/module.c | 299 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 323 insertions(+) create mode 100644 arch/nds32/include/asm/module.h create mode 100644 arch/nds32/kernel/module.c
arch/nds32/include/asm/module.h new file +24 -0
@@ -0,0 +1,24 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef _ASM_NDS32_MODULE_H +#define _ASM_NDS32_MODULE_H + +#include <asm-generic/module.h> + +#define MODULE_ARCH_VERMAGIC "NDS32v3" + +#endif /* _ASM_NDS32_MODULE_H */
arch/nds32/kernel/module.c new file +299 -0
299 lines not on this page · raw message
Signature · 1 line
1.7.9.5
PATCH v2 21/35 nds32: Generic timers support
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
This patch adds support for timer.
--- arch/nds32/kernel/time.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 arch/nds32/kernel/time.c
arch/nds32/kernel/time.c new file +22 -0
@@ -0,0 +1,22 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <linux/clocksource.h> + +void __init time_init (void ) +{ +timer_probe (); +}
Signature · 1 line
1.7.9.5
PATCH v2 22/35 nds32: Device tree support
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
This patch adds support for device tree.
--- arch/nds32/boot/dts/Makefile | 8 ++++++ arch/nds32/boot/dts/ae3xx.dts | 55 ++++++++++++++++++++++++++++++++++++ arch/nds32/boot/dts/ag101p.dts | 60 ++++++++++++++++++++++++++++++++++++++++ arch/nds32/kernel/devtree.c | 45 ++++++++++++++++++++++++++++++ 4 files changed, 168 insertions(+) create mode 100644 arch/nds32/boot/dts/Makefile create mode 100644 arch/nds32/boot/dts/ae3xx.dts create mode 100644 arch/nds32/boot/dts/ag101p.dts create mode 100644 arch/nds32/kernel/devtree.c
arch/nds32/boot/dts/Makefile new file +8 -0
@@ -0,0 +1,8 @@ +ifneq '$(CONFIG_NDS32_BUILTIN_DTB)' '""' +BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_NDS32_BUILTIN_DTB)).dtb.o +else +BUILTIN_DTB := +endif +obj-$(CONFIG_OF) += $(BUILTIN_DTB) + +clean-files := *.dtb *.dtb.S
arch/nds32/boot/dts/ae3xx.dts new file +55 -0
55 lines not on this page · raw message
arch/nds32/boot/dts/ag101p.dts new file +60 -0
60 lines not on this page · raw message
arch/nds32/kernel/devtree.c new file +45 -0
45 lines not on this page · raw message
Signature · 1 line
1.7.9.5
Arnd Bergmann
maintainerRe: [PATCH v2 22/35] nds32: Device tree support
arch/nds32/boot/dts/ae3xx.dts line 3
Quoted 4 lines · Greentime Hu
arch/nds32/boot/dts/ae3xx.dts new file +3
-0@@ -0,0 +1,55 @@ +/dts-v1/; +/ { + compatible = "nds32 ae3xx";
The compatible string doesn't seem to match the binding, it should always have vendor prefix.
arch/nds32/boot/dts/ae3xx.dts line 11
Quoted 8 lines
arch/nds32/boot/dts/ae3xx.dts new file +8
-0+ #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + chosen { + bootargs = "earlycon console=ttyS0,38400n8 debug loglevel=7"; + stdout-path = &serial0; + };
I would drop the bootargs here, this is something that should be set by the bootloader and is up to the user.
Arnd
Re: [PATCH v2 22/35] nds32: Device tree support
2017-11-27 22:30 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 8 lines · Greentime Hu
arch/nds32/boot/dts/ae3xx.dts line 3
Quoted 4 lines
arch/nds32/boot/dts/ae3xx.dts new file +3
-0@@ -0,0 +1,55 @@ +/dts-v1/; +/ { + compatible = "nds32 ae3xx";The compatible string doesn't seem to match the binding, it should always have vendor prefix.
Sorry I forgot to check this.
I will provide a document in bindings like "Documentation/devicetree/bindings/nds32/andestech-boards".
Quoted 11 lines
arch/nds32/boot/dts/ae3xx.dts line 11
Quoted 8 lines
arch/nds32/boot/dts/ae3xx.dts new file +8
-0+ #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + chosen { + bootargs = "earlycon console=ttyS0,38400n8 debug loglevel=7"; + stdout-path = &serial0; + };I would drop the bootargs here, this is something that should be set by the bootloader and is up to the user.
Thanks
I will drop it in the next version patch.
--
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Re: [PATCH v2 22/35] nds32: Device tree support
In reply to Greentime HuQuoted 23 lines · Greentime Hu
From: Greentime Hu <[email protected]>
This patch adds support for device tree.
Signed-off-by Vincent Chen <[email protected]>Signed-off-by Greentime Hu <[email protected]>--- arch/nds32/boot/dts/Makefile | 8 ++++++ arch/nds32/boot/dts/ae3xx.dts | 55 ++++++++++++++++++++++++++++++++++++ arch/nds32/boot/dts/ag101p.dts | 60 ++++++++++++++++++++++++++++++++++++++++ arch/nds32/kernel/devtree.c | 45 ++++++++++++++++++++++++++++++ 4 files changed, 168 insertions(+) create mode 100644 arch/nds32/boot/dts/Makefile create mode 100644 arch/nds32/boot/dts/ae3xx.dts create mode 100644 arch/nds32/boot/dts/ag101p.dts create mode 100644 arch/nds32/kernel/devtree.carch/nds32/boot/dts/Makefile new file +0
-0
arch/nds32/boot/dts/Makefile line 1
Quoted 1 line
arch/nds32/boot/dts/Makefile new file +1
-0@@ -0,0 +1,8 @@ +ifneq '$(CONFIG_NDS32_BUILTIN_DTB)' '""'
Built-in dtb's are really for legacy bootloader cases where the bootloader doesn't understand dtbs. Do you have that here?
Plus, I don't see any code here to handle the built-in dtb.
Quoted 13 lines
arch/nds32/boot/dts/Makefile new file +7
-0+BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_NDS32_BUILTIN_DTB)).dtb.o +else +BUILTIN_DTB := +endif +obj-$(CONFIG_OF) += $(BUILTIN_DTB) + +clean-files := *.dtb *.dtb.Sarch/nds32/boot/dts/ae3xx.dts new file +0
-0
arch/nds32/boot/dts/ae3xx.dts line 3
Quoted 3 lines
arch/nds32/boot/dts/ae3xx.dts new file +3
-0@@ -0,0 +1,55 @@ +/dts-v1/; +/ { + compatible = "nds32 ae3xx";
This compatible needs to be documented and is not valid. Needs to be in the form "vendor,board-name" without spaces.
Quoted 36 lines
arch/nds32/boot/dts/ae3xx.dts new file +36
-0+ #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + chosen { + bootargs = "earlycon console=ttyS0,38400n8 debug loglevel=7"; + stdout-path = &serial0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + cpu { + device_type = "cpu"; + compatible = "andestech,n13", "andestech,nds32v3"; + clock-frequency = <60000000>; + }; + + intc: interrupt-controller { + compatible = "andestech,ativic32"; + #interrupt-cells = <1>; + interrupt-controller; + }; + + serial0: serial@f0300000 { + compatible = "andestech,uart16550", "ns16550a"; + reg = <0xf0300000 0x1000>; + interrupts = <8>; + clock-frequency = <14745600>; + reg-shift = <2>; + reg-offset = <32>; + no-loopback-test = <1>; + }; +
arch/nds32/boot/dts/ae3xx.dts line 49
Quoted 10 lines
arch/nds32/boot/dts/ae3xx.dts new file +10
-0+ timer0: timer@f0400000 { + compatible = "andestech,atcpit100"; + reg = <0xf0400000 0x1000>; + interrupts = <2>; + clock-frequency = <30000000>; + cycle-count-offset = <0x38>; + cycle-count-down; + }; + + mac0: mac@e0100000 {
ethernet@...
Quoted 12 lines
arch/nds32/boot/dts/ae3xx.dts new file +6
-0+ compatible = "andestech,atmac100"; + reg = <0xe0100000 0x1000>; + interrupts = <18>; + }; + +};arch/nds32/boot/dts/ag101p.dts new file +0
-0
arch/nds32/boot/dts/ag101p.dts line 3
Quoted 3 lines
arch/nds32/boot/dts/ag101p.dts new file +3
-0@@ -0,0 +1,60 @@ +/dts-v1/; +/ { + compatible = "nds32 ag101p";
Same here.
Quoted 83 lines
arch/nds32/boot/dts/ag101p.dts new file +57
-0+ #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + chosen { + bootargs = "earlycon console=ttyS0,38400n8 debug loglevel=7"; + stdout-path = &serial0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + cpu@0 { + device_type = "cpu"; + compatible = "andestech,n13"; + clock-frequency = <60000000>; + next-level-cache = <&L2>; + }; + + intc: interrupt-controller { + compatible = "andestech,ativic32"; + #interrupt-cells = <2>; + interrupt-controller; + }; + + serial0: serial@99600000 { + compatible = "andestech,uart16550", "ns16550a"; + reg = <0x99600000 0x1000>; + interrupts = <7 4>; + clock-frequency = <14745600>; + reg-shift = <2>; + no-loopback-test = <1>; + }; + + timer0: timer@98400000 { + compatible = "andestech,atftmr010"; + reg = <0x98400000 0x1000>; + interrupts = <19 4>; + clock-frequency = <15000000>; + cycle-count-offset = <0x20>; + }; + + mac0: mac@90900000 { + compatible = "andestech,atmac100"; + reg = <0x90900000 0x1000>; + interrupts = <25 4>; + }; + + L2: l2-cache { + compatible = "andestech,atl2c"; + reg = <0x90f00000 0x1000>; + cache-unified; + cache-level = <2>; + }; +};arch/nds32/kernel/devtree.c new file +20
-0@@ -0,0 +1,45 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <linux/memblock.h> +#include <linux/of_fdt.h> +#include <linux/bootmem.h> +
arch/nds32/kernel/devtree.c line 30
Quoted 10 lines
arch/nds32/kernel/devtree.c new file +10
-0+void __init early_init_dt_add_memory_arch (u64 base,u64 size) +{ + size &=PAGE_MASK ; +memblock_add_node (base, size,0 ); +} + +void *__init early_init_dt_alloc_memory_arch (u64 size,u64 align) +{ +return alloc_bootmem_align (size, align); +}
You should be able to use the default functions for these 2.
arch/nds32/kernel/devtree.c line 37
Quoted 7 lines
arch/nds32/kernel/devtree.c new file +7
-0+ +void __init early_init_devtree (void *params) +{ +if (!params || !early_init_dt_scan (params)) { +pr_crit ("\n" +"Error: invalid device tree blob at (virtual address 0x%p)\n" + "The dtb must be 8-byte aligned and must not exceed 8 KB in size\n"
Why the size limit? That's pretty small for a DT.
arch/nds32/kernel/devtree.c line 41
Quoted 4 lines
arch/nds32/kernel/devtree.c new file +4
-0+ "\nPlease check your bootloader.", params); + +while (true) +cpu_relax ();
Might as well use BUG_ON here if you're not going to continue. It's generally better to WARN and continue on otherwise the messages aren't visible until the console is up. However, if you have DT errors this early, there's not much you can really do here.
Quoted 7 lines
arch/nds32/kernel/devtree.c new file +4
-1+ } + +dump_stack_set_arch_desc ("%s (DT)" ,of_flat_dt_get_machine_name ()); +} --1.7.9.5
Re: [PATCH v2 22/35] nds32: Device tree support
Quoted 29 lines · Rob Herring
Quoted 23 lines · Greentime Hu
From: Greentime Hu <[email protected]>
This patch adds support for device tree.
Signed-off-by Vincent Chen <[email protected]>Signed-off-by Greentime Hu <[email protected]>--- arch/nds32/boot/dts/Makefile | 8 ++++++ arch/nds32/boot/dts/ae3xx.dts | 55 ++++++++++++++++++++++++++++++++++++ arch/nds32/boot/dts/ag101p.dts | 60 ++++++++++++++++++++++++++++++++++++++++ arch/nds32/kernel/devtree.c | 45 ++++++++++++++++++++++++++++++ 4 files changed, 168 insertions(+) create mode 100644 arch/nds32/boot/dts/Makefile create mode 100644 arch/nds32/boot/dts/ae3xx.dts create mode 100644 arch/nds32/boot/dts/ag101p.dts create mode 100644 arch/nds32/kernel/devtree.carch/nds32/boot/dts/Makefile new file +0
-0arch/nds32/boot/dts/Makefile line 1
Quoted 1 line
arch/nds32/boot/dts/Makefile new file +1
-0@@ -0,0 +1,8 @@ +ifneq '$(CONFIG_NDS32_BUILTIN_DTB)' '""'Built-in dtb's are really for legacy bootloader cases where the bootloader doesn't understand dtbs. Do you have that here?
Quoted 1 line
Plus, I don't see any code here to handle the built-in dtb.
I see it is in patch 2. That means patch 2 won't actually compile. You should move the devtree.c parts at least and maybe the Makefile infrastructure part too to patch 2. I don't think you need to split things up so much, but I'll defer to Arnd on that.
Rob
Re: [PATCH v2 22/35] nds32: Device tree support
In reply to Rob Herring2017-11-28 3:07 GMT+08:00 Rob Herring <[email protected]>:
Quoted 29 lines · Greentime Hu
Quoted 23 lines
From: Greentime Hu <greentime-MUIXKm3Oiri1Z/[email protected]>
This patch adds support for device tree.
Signed-off-by Vincent Chen <vincentc-MUIXKm3Oiri1Z/[email protected]>Signed-off-by Greentime Hu <greentime-MUIXKm3Oiri1Z/[email protected]>--- arch/nds32/boot/dts/Makefile | 8 ++++++ arch/nds32/boot/dts/ae3xx.dts | 55 ++++++++++++++++++++++++++++++++++++ arch/nds32/boot/dts/ag101p.dts | 60 ++++++++++++++++++++++++++++++++++++++++ arch/nds32/kernel/devtree.c | 45 ++++++++++++++++++++++++++++++ 4 files changed, 168 insertions(+) create mode 100644 arch/nds32/boot/dts/Makefile create mode 100644 arch/nds32/boot/dts/ae3xx.dts create mode 100644 arch/nds32/boot/dts/ag101p.dts create mode 100644 arch/nds32/kernel/devtree.carch/nds32/boot/dts/Makefile new file +0
-0arch/nds32/boot/dts/Makefile line 1
Quoted 1 line
arch/nds32/boot/dts/Makefile new file +1
-0@@ -0,0 +1,8 @@ +ifneq '$(CONFIG_NDS32_BUILTIN_DTB)' '""'Built-in dtb's are really for legacy bootloader cases where the bootloader doesn't understand dtbs. Do you have that here?
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Plus, I don't see any code here to handle the built-in dtb.
As you mentioned in the next thread, it is handled in head.S We would like to keep it because we debug kernel through gdb without bootloader very often.
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arch/nds32/boot/dts/Makefile new file +7
-0+BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_NDS32_BUILTIN_DTB)).dtb.o +else +BUILTIN_DTB := +endif +obj-$(CONFIG_OF) += $(BUILTIN_DTB) + +clean-files := *.dtb *.dtb.Sarch/nds32/boot/dts/ae3xx.dts new file +0
-1--- /dev/null
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arch/nds32/boot/dts/ae3xx.dts line 3
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+++
b/arch/nds32/boot/dts/ae3xx.dtsarch/nds32/boot/dts/ae3xx.dts new file +3
-0@@ -0,0 +1,55 @@ +/dts-v1/; +/ { + compatible = "nds32 ae3xx";This compatible needs to be documented and is not valid. Needs to be in the form "vendor,board-name" without spaces.
Sorry I forgot to check this.
I will provide a document in bindings like "Documentation/devicetree/bindings/nds32/andestech-boards".
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arch/nds32/boot/dts/ae3xx.dts new file +36
-0+ #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + chosen { + bootargs = "earlycon console=ttyS0,38400n8 debug loglevel=7"; + stdout-path = &serial0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + cpu { + device_type = "cpu"; + compatible = "andestech,n13", "andestech,nds32v3"; + clock-frequency = <60000000>; + }; + + intc: interrupt-controller { + compatible = "andestech,ativic32"; + #interrupt-cells = <1>; + interrupt-controller; + }; + + serial0: serial@f0300000 { + compatible = "andestech,uart16550", "ns16550a"; + reg = <0xf0300000 0x1000>; + interrupts = <8>; + clock-frequency = <14745600>; + reg-shift = <2>; + reg-offset = <32>; + no-loopback-test = <1>; + }; +arch/nds32/boot/dts/ae3xx.dts line 49
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arch/nds32/boot/dts/ae3xx.dts new file +10
-0+ timer0: timer@f0400000 { + compatible = "andestech,atcpit100"; + reg = <0xf0400000 0x1000>; + interrupts = <2>; + clock-frequency = <30000000>; + cycle-count-offset = <0x38>; + cycle-count-down; + }; + + mac0: mac@e0100000 {ethernet@...
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arch/nds32/boot/dts/ae3xx.dts new file +6
-0+ compatible = "andestech,atmac100"; + reg = <0xe0100000 0x1000>; + interrupts = <18>; + }; + +};arch/nds32/boot/dts/ag101p.dts new file +0
-0
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arch/nds32/boot/dts/ag101p.dts line 3
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arch/nds32/boot/dts/ag101p.dts new file +3
-0@@ -0,0 +1,60 @@ +/dts-v1/; +/ { + compatible = "nds32 ag101p";Same here.
Sorry I forgot to check this.
I will provide a document in bindings like "Documentation/devicetree/bindings/nds32/andestech-boards".
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arch/nds32/boot/dts/ag101p.dts new file +57
-0+ #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + chosen { + bootargs = "earlycon console=ttyS0,38400n8 debug loglevel=7"; + stdout-path = &serial0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + cpu@0 { + device_type = "cpu"; + compatible = "andestech,n13"; + clock-frequency = <60000000>; + next-level-cache = <&L2>; + }; + + intc: interrupt-controller { + compatible = "andestech,ativic32"; + #interrupt-cells = <2>; + interrupt-controller; + }; + + serial0: serial@99600000 { + compatible = "andestech,uart16550", "ns16550a"; + reg = <0x99600000 0x1000>; + interrupts = <7 4>; + clock-frequency = <14745600>; + reg-shift = <2>; + no-loopback-test = <1>; + }; + + timer0: timer@98400000 { + compatible = "andestech,atftmr010"; + reg = <0x98400000 0x1000>; + interrupts = <19 4>; + clock-frequency = <15000000>; + cycle-count-offset = <0x20>; + }; + + mac0: mac@90900000 { + compatible = "andestech,atmac100"; + reg = <0x90900000 0x1000>; + interrupts = <25 4>; + }; + + L2: l2-cache { + compatible = "andestech,atl2c"; + reg = <0x90f00000 0x1000>; + cache-unified; + cache-level = <2>; + }; +};arch/nds32/kernel/devtree.c new file +24
-0@@ -0,0 +1,45 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <linux/memblock.h> +#include <linux/of_fdt.h> +#include <linux/bootmem.h> + +void __init early_init_dt_add_memory_arch (u64 base,u64 size) +{ + size &=PAGE_MASK ; +memblock_add_node (base, size,0 );
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arch/nds32/kernel/devtree.c line 30
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arch/nds32/kernel/devtree.c new file +6
-0+} + +void *__init early_init_dt_alloc_memory_arch (u64 size,u64 align) +{ +return alloc_bootmem_align (size, align); +}You should be able to use the default functions for these 2.
Thanks. I will remove these 2 functions to use default ones.
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arch/nds32/kernel/devtree.c line 37
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arch/nds32/kernel/devtree.c new file +7
-0+ +void __init early_init_devtree (void *params) +{ +if (!params || !early_init_dt_scan (params)) { +pr_crit ("\n" +"Error: invalid device tree blob at (virtual address 0x%p)\n" + "The dtb must be 8-byte aligned and must not exceed 8 KB in size\n"Why the size limit? That's pretty small for a DT.
Thanks. I will update it in the next version patch.
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arch/nds32/kernel/devtree.c line 41
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arch/nds32/kernel/devtree.c new file +4
-0+ "\nPlease check your bootloader.", params); + +while (true) +cpu_relax ();Might as well use
BUG_ONhere if you're not going to continue. It's generally better to WARN and continue on otherwise the messages aren't visible until the console is up. However, if you have DT errors this early, there's not much you can really do here.
Yup. Maybe we shall hang in here for user to know he use a wrong DT. I will change it to BUG_ON(1).
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arch/nds32/kernel/devtree.c new file +4
-1+ } + +dump_stack_set_arch_desc ("%s (DT)" ,of_flat_dt_get_machine_name ()); +} --1.7.9.5
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PATCH v2 23/35 nds32: Miscellaneous header files
In reply to Greentime HuFrom: Greentime Hu <greentime-MUIXKm3Oiri1Z/[email protected]>
This patch introduces some miscellaneous header files.
--- arch/nds32/include/asm/delay.h | 51 +++++++++++++++++++++++++++++++ arch/nds32/include/asm/linkage.h | 24 +++++++++++++++ arch/nds32/include/uapi/asm/byteorder.h | 26 ++++++++++++++++ 3 files changed, 101 insertions(+) create mode 100644 arch/nds32/include/asm/delay.h create mode 100644 arch/nds32/include/asm/linkage.h create mode 100644 arch/nds32/include/uapi/asm/byteorder.h
arch/nds32/include/asm/delay.h new file +51 -0
@@ -0,0 +1,51 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef __NDS32_DELAY_H__ +#define __NDS32_DELAY_H__ + +#include <asm/param.h> + +static inline void __delay (unsigned long loops) +{ + __asm__ __volatile__(".align 2\n" +"1:\n" +"\taddi\t%0, %0, -1\n" +"\tbgtz\t%0, 1b\n" + :"=r" (loops) + :"0" (loops)); +} + +static inline void __udelay (unsigned long usecs,unsigned long lpj) +{ + usecs *= (unsigned long )(((0x8000000000000000ULL / (500000 /HZ )) + +0x80000000ULL ) >>32 ); + usecs = (unsigned long )(((unsigned long long )usecs * lpj) >>32 ); +__delay (usecs); +} + +#define udelay (usecs) __udelay((usecs), loops_per_jiffy) + +/* make sure "usecs *= ..." in udelay do not overflow. */ +#if HZ >=1000 +#define MAX_UDELAY_MS 1 +#elif HZ <=200 +#define MAX_UDELAY_MS 5 +#else +#define MAX_UDELAY_MS (1000 / HZ) +#endif + +#endif
arch/nds32/include/asm/linkage.h new file +24 -0
@@ -0,0 +1,24 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef __ASM_LINKAGE_H +#define __ASM_LINKAGE_H + +/* This file is required by include/linux/linkage.h */ +#define __ALIGN .align 2 +#define __ALIGN_STR ".align 2" + +#endif
arch/nds32/include/uapi/asm/byteorder.h new file +26 -0
@@ -0,0 +1,26 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef __NDS32_BYTEORDER_H__ +#define __NDS32_BYTEORDER_H__ + +#ifdef __NDS32_EB__ +#include <linux/byteorder/big_endian.h> +#else +#include <linux/byteorder/little_endian.h> +#endif + +#endif /* __NDS32_BYTEORDER_H__ */
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PATCH v2 24/35 nds32: defconfig
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
This patch adds nds32 defconfig.
--- arch/nds32/configs/defconfig | 111 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 111 insertions(+) create mode 100644 arch/nds32/configs/defconfig
arch/nds32/configs/defconfig new file +111 -0
@@ -0,0 +1,111 @@ +CONFIG_CROSS_COMPILE="nds32le-linux-" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +CONFIG_PROFILING=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_HWZOL is not set +CONFIG_ANDES_PAGE_SIZE_8KB=y +CONFIG_NDS32_BUILTIN_DTB="ae3xx" +CONFIG_PREEMPT=y +# CONFIG_COMPACTION is not set +CONFIG_HZ_100=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +CONFIG_BRIDGE=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_NETDEVICES=y +CONFIG_TUN=y +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +CONFIG_FTMAC100=y +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_SERIO is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +# CONFIG_VGA_CONSOLE is not set +CONFIG_SOUND=y +CONFIG_SND=y +# CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_VERBOSE_PROCFS is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_HCTOSYS is not set +CONFIG_CLKSRC_ATCPIT100=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_EXT4_ENCRYPTION=y +CONFIG_FUSE_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CONFIGFS_FS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_USE_LEGACY_DNS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_INFO_DWARF4=y +CONFIG_GDB_SCRIPTS=y +CONFIG_READABLE_ASM=y +CONFIG_HEADERS_CHECK=y +CONFIG_DEBUG_SECTION_MISMATCH=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_PANIC_ON_OOPS=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_STACKTRACE=y +CONFIG_RCU_CPU_STALL_TIMEOUT=300 +# CONFIG_CRYPTO_HW is not set
Signature · 1 line
1.7.9.5
Arnd Bergmann
maintainerRe: [PATCH v2 24/35] nds32: defconfig
Quoted 1 line · Greentime Hu
+CONFIG_EXPERT=y
You normally shouldn't need CONFIG_EXPERT in a defconfig file, by definition this is needed for unusual configurations only.
Quoted 1 line
+CONFIG_NDS32_BUILTIN_DTB="ae3xx"
Having a built-in DTB also makes no sense for a defconfig, when the idea is that it can run on as many machines as possible.
arch/nds32/configs/defconfig line 44
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arch/nds32/configs/defconfig new file +3
-0+CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192
Having ramdisk built-in is rather unusual, most users don't use ramdisks any more since we don't need it for booting with the initramfs.
arch/nds32/configs/defconfig line 46
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arch/nds32/configs/defconfig new file +2
-0+CONFIG_BRIDGE=y +CONFIG_TUN=y
These also look unusual. Would it make sense to have these as loadable modules, or do you require having everything built-in for your workflow?
arch/nds32/configs/defconfig line 76
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arch/nds32/configs/defconfig new file +4
-0+CONFIG_SOUND=y +CONFIG_SND=y +# CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_VERBOSE_PROCFS is not set
It seems the sound subsystem is enabled, but no drivers are selected, so it won't actually do anything.
arch/nds32/configs/defconfig line 78
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arch/nds32/configs/defconfig new file +2
-0+# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y
Same for MMC. If you are still trying to get the respective device drivers merged, that doesn't need to stop you from enabling the configurations here.
Arnd
PATCH v2 25/35 nds32: Build infrastructure
In reply to Greentime HuFrom: Greentime Hu <greentime-MUIXKm3Oiri1Z/[email protected]>
This patch adds Makefile, Kconfig and vmlinux.lds.S files required for building an nds32 kernel.
--- arch/nds32/Kconfig | 107 +++++++++++++++++++++++++++++ arch/nds32/Kconfig.cpu | 131 ++++++++++++++++++++++++++++++++++++ arch/nds32/Makefile | 66 ++++++++++++++++++ arch/nds32/boot/Makefile | 15 +++++ arch/nds32/include/asm/Kbuild | 54 +++++++++++++++ arch/nds32/include/uapi/asm/Kbuild | 27 ++++++++ arch/nds32/kernel/Makefile | 23 +++++++ arch/nds32/kernel/vmlinux.lds.S | 70 +++++++++++++++++++ arch/nds32/mm/Makefile | 7 ++ 9 files changed, 500 insertions(+) create mode 100644 arch/nds32/Kconfig create mode 100644 arch/nds32/Kconfig.cpu create mode 100644 arch/nds32/Makefile create mode 100644 arch/nds32/boot/Makefile create mode 100644 arch/nds32/include/asm/Kbuild create mode 100644 arch/nds32/include/uapi/asm/Kbuild create mode 100644 arch/nds32/kernel/Makefile create mode 100644 arch/nds32/kernel/vmlinux.lds.S create mode 100644 arch/nds32/mm/Makefile
arch/nds32/Kconfig new file +107 -0
@@ -0,0 +1,107 @@ +# +# For a description of the syntax of this configuration file, +# see Documentation/kbuild/kconfig-language.txt. +# + +config NDS32 + def_bool y + select ARCH_HAS_RAW_COPY_USER + select ARCH_WANT_FRAME_POINTERS if FTRACE + select ARCH_WANT_IPC_PARSE_VERSION + select CLKSRC_MMIO + select CLONE_BACKWARDS + select TIMER_OF + select FRAME_POINTER + select GENERIC_ATOMIC64 + select GENERIC_CPU_DEVICES + select GENERIC_CLOCKEVENTS + select GENERIC_IRQ_CHIP + select GENERIC_IRQ_PROBE + select GENERIC_IRQ_SHOW + select GENERIC_STRNCPY_FROM_USER + select GENERIC_STRNLEN_USER + select GENERIC_TIME_VSYSCALL + select HANDLE_DOMAIN_IRQ + select HAVE_ARCH_TRACEHOOK + select HAVE_DEBUG_KMEMLEAK + select HAVE_MEMBLOCK + select HAVE_MEMBLOCK_NODE_MAP + select HAVE_REGS_AND_STACK_ACCESS_API + select IRQ_DOMAIN + select LOCKDEP_SUPPORT + select MODULES_USE_ELF_RELA + select OF + select OF_EARLY_FLATTREE + select NO_IOPORT_MAP + select RTC_LIB + select THREAD_INFO_IN_TASK + help + Andes(nds32) Linux support. + +config GENERIC_CALIBRATE_DELAY + def_bool n + +config GENERIC_CSUM + def_bool y + +config GENERIC_HWEIGHT + def_bool y + +config GENERIC_LOCKBREAK + def_bool y + depends on PREEMPT + +config RWSEM_GENERIC_SPINLOCK + def_bool y + +config TRACE_IRQFLAGS_SUPPORT + def_bool y + +config STACKTRACE_SUPPORT + def_bool y + +config FIX_EARLYCON_MEM + def_bool y + +config PGTABLE_LEVELS + default 2 + +source "init/Kconfig" + +menu "System Type" +source "arch/nds32/Kconfig.cpu" +config NR_CPUS + int + default 1 + +config MMU + def_bool y + +config NDS32_BUILTIN_DTB + string "Builtin DTB" + default "" + help + User can use it to specify the dts of the SoC +endmenu + +menu "Kernel Features" +source "kernel/Kconfig.preempt" +source "mm/Kconfig" +source "kernel/Kconfig.hz" +endmenu + +menu "Executable file formats" +source "fs/Kconfig.binfmt" +endmenu + +source "net/Kconfig" +source "drivers/Kconfig" +source "fs/Kconfig" + +menu "Kernel hacking" +source "lib/Kconfig.debug" +endmenu + +source "security/Kconfig" +source "crypto/Kconfig" +source "lib/Kconfig"
arch/nds32/Kconfig.cpu new file +131 -0
131 lines not on this page · raw message
arch/nds32/Makefile new file +66 -0
66 lines not on this page · raw message
arch/nds32/boot/Makefile new file +15 -0
@@ -0,0 +1,15 @@ +targets := Image Image.gz + +$(obj)/Image: vmlinux FORCE + $(call if_changed,objcopy) + +$(obj)/Image.gz: $(obj)/Image FORCE + $(call if_changed,gzip) + +install: $(obj)/Image + $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \ + $(obj)/Image System.map "$(INSTALL_PATH)" + +zinstall: $(obj)/Image.gz + $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \ + $(obj)/Image.gz System.map "$(INSTALL_PATH)"
arch/nds32/include/asm/Kbuild new file +54 -0
54 lines not on this page · raw message
arch/nds32/include/uapi/asm/Kbuild new file +27 -0
@@ -0,0 +1,27 @@ +# UAPI Header export list +include include/uapi/asm-generic/Kbuild.asm + +generic-y += errno.h +generic-y += ioctl.h +generic-y += ioctls.h +generic-y += ipcbuf.h +generic-y += shmbuf.h +generic-y += bitsperlong.h +generic-y += fcntl.h +generic-y += stat.h +generic-y += mman.h +generic-y += msgbuf.h +generic-y += poll.h +generic-y += posix_types.h +generic-y += resource.h +generic-y += sembuf.h +generic-y += setup.h +generic-y += siginfo.h +generic-y += socket.h +generic-y += sockios.h +generic-y += swab.h +generic-y += statfs.h +generic-y += termbits.h +generic-y += termios.h +generic-y += types.h +generic-y += ucontext.h
arch/nds32/kernel/Makefile new file +23 -0
@@ -0,0 +1,23 @@ +# +# Makefile for the linux kernel. +# + +CPPFLAGS_vmlinux.lds := -DTEXTADDR=$(TEXTADDR) +AFLAGS_head.o := -DTEXTADDR=$(TEXTADDR) + +# Object file lists. + +obj-y := ex-entry.o ex-exit.o ex-scall.o irq.o \ + process.o ptrace.o setup.o signal.o \ + sys_nds32.o time.o traps.o cacheinfo.o \ + dma.o syscall_table.o vdso.o + +obj-$(CONFIG_MODULES) += nds32_ksyms.o module.o +obj-$(CONFIG_STACKTRACE) += stacktrace.o +obj-$(CONFIG_OF) += devtree.o +obj-$(CONFIG_CACHE_L2) += atl2c.o + +extra-y := head.o vmlinux.lds + + +obj-y += vdso/
arch/nds32/kernel/vmlinux.lds.S new file +70 -0
70 lines not on this page · raw message
arch/nds32/mm/Makefile new file +7 -0
@@ -0,0 +1,7 @@ +obj-y := extable.o tlb.o \ + fault.o init.o ioremap.o mmap.o \ + mm-nds32.o cacheflush.o proc.o + +obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o +obj-$(CONFIG_HIGHMEM) += highmem.o +CFLAGS_proc-n13.o += -fomit-frame-pointer
Signature · 6 lines
1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
Arnd Bergmann
maintainerRe: [PATCH v2 25/35] nds32: Build infrastructure
Quoted 6 lines · Greentime Hu
arch/nds32/Kconfig.cpu new file +0
-0
arch/nds32/Kconfig.cpu line 9
Quoted 9 lines
arch/nds32/Kconfig.cpu new file +9
-0@@ -0,0 +1,131 @@ +comment "Processor Features" + +config CPU_BIG_ENDIAN + bool "Big endian" + def_bool n + +config CPU_LITTLE_ENDIAN + bool "Little endian" + def_bool y
These must be mutually exclusive, you surely get some build error if you try to set both here.
You can either make it a 'choice' statement to pick between the two, or you can make CPU_LITTLE_ENDIAN a silent option like
config CPU_BIG_ENDIAN
bool "Big endian"
config CPU_LITTLE_ENDIAN
def_bool !CPU_BIG_ENDIAN
arch/nds32/Kconfig.cpu line 29
Quoted 7 lines
arch/nds32/Kconfig.cpu new file +7
-0+config CPU_CACHE_NONALIASING + bool "Non-aliasing cache" + help + If this CPU is using VIPT data cache and its cache way size is larger + than page size, say N. If it is using PIPT data cache, say Y. + + If unsure, say Y.
Can you determine this from the CPU type?
Quoted 9 lines
arch/nds32/Kconfig.cpu new file +9
-0+choice + prompt "Memory split" + depends on MMU + default VMSPLIT_3G + help + Select the desired split between kernel and user memory. + + If you are not absolutely sure what you are doing, leave this + option alone!
arch/nds32/Kconfig.cpu line 122
Quoted 10 lines
arch/nds32/Kconfig.cpu new file +10
-0+ + config VMSPLIT_3G + bool "3G/1G user/kernel split" + config VMSPLIT_3G_OPT + bool "3G/1G user/kernel split (for full 1G low memory)" + config VMSPLIT_2G + bool "2G/2G user/kernel split" + config VMSPLIT_1G + bool "1G/3G user/kernel split" +endchoice
I think you mentioned that the 1GB configuration is quite common, how about making VMSPLIT_3G_OPT the default here?
Arnd
Re: [PATCH v2 25/35] nds32: Build infrastructure
2017-11-27 22:21 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 21 lines · Greentime Hu
Quoted 7 lines
arch/nds32/Kconfig.cpu new file +0
-0arch/nds32/Kconfig.cpu line 9
Quoted 9 lines
arch/nds32/Kconfig.cpu new file +9
-0@@ -0,0 +1,131 @@ +comment "Processor Features" + +config CPU_BIG_ENDIAN + bool "Big endian" + def_bool n + +config CPU_LITTLE_ENDIAN + bool "Little endian" + def_bool yThese must be mutually exclusive, you surely get some build error if you try to set both here.
Quoted 9 lines
You can either make it a 'choice' statement to pick between the two, or you can make
CPU_LITTLE_ENDIANa silent option likeconfig
CPU_BIG_ENDIAN
bool "Big endian"config
CPU_LITTLE_ENDIAN
def_bool!CPU_BIG_ENDIAN
Thanks. I will fix it in the next version patch.
Quoted 9 lines
arch/nds32/Kconfig.cpu line 29
Quoted 7 lines
arch/nds32/Kconfig.cpu new file +7
-0+config CPU_CACHE_NONALIASING + bool "Non-aliasing cache" + help + If this CPU is using VIPT data cache and its cache way size is larger + than page size, say N. If it is using PIPT data cache, say Y. + + If unsure, say Y.Can you determine this from the CPU type?
There is no cpu register to determine it. It also depeneds on page size and way size however page size is configurable by software. These codes are determined at compile time will be benefit to code size and performance.
IMHO, I think it would be better to be determined here.
Quoted 14 lines
Quoted 14 lines
arch/nds32/Kconfig.cpu new file +14
-0+choice + prompt "Memory split" + depends on MMU + default VMSPLIT_3G + help + Select the desired split between kernel and user memory. + + If you are not absolutely sure what you are doing, leave this + option alone! + + config VMSPLIT_3G + bool "3G/1G user/kernel split" + config VMSPLIT_3G_OPT + bool "3G/1G user/kernel split (for full 1G low memory)"
Quoted 8 lines
arch/nds32/Kconfig.cpu line 122
Quoted 5 lines
arch/nds32/Kconfig.cpu new file +5
-0+ config VMSPLIT_2G + bool "2G/2G user/kernel split" + config VMSPLIT_1G + bool "1G/3G user/kernel split" +endchoiceI think you mentioned that the 1GB configuration is quite common, how about making
VMSPLIT_3G_OPTthe default here?
We use 1GB in our fpga platform, but I am not sure our customer's config and their user space program may use bigger memory space. Anyway, we will discuss it to decide the default value. Thanks for your suggestion.
Arnd Bergmann
maintainerRe: [PATCH v2 25/35] nds32: Build infrastructure
Quoted 13 lines · Greentime Hu
2017-11-27 22:21 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 11 lines · Greentime Hu
arch/nds32/Kconfig.cpu line 29
Quoted 8 lines
arch/nds32/Kconfig.cpu +7
-0+config CPU_CACHE_NONALIASING + bool "Non-aliasing cache" + help + If this CPU is using VIPT data cache and its cache way size is larger + than page size, say N. If it is using PIPT data cache, say Y. + + If unsure, say Y.Can you determine this from the CPU type?
Quoted 5 lines
There is no cpu register to determine it. It also depeneds on page size and way size however page size is configurable by software. These codes are determined at compile time will be benefit to code size and performance.
IMHO, I think it would be better to be determined here.
I meant determining it at compile time from other Kconfig symbols, if that's possible. Do the CPU cores each have a fixed way-size? If they do, it could be done like
menu "CPU selection"
config CPU_N15
bool "AndesCore N15"
select CPU_CACHE_NONALIASING
config CPU_N13
bool "AndesCore N15"
select CPU_CACHE_NONALIASING if PAGE_SIZE_16K
...
endmenu
and then you can use the same CPU_... symbols to make other decisions as well, e.g. CPU specific compiler optimizations.
Arnd
Re: [PATCH v2 25/35] nds32: Build infrastructure
Hi Arnd,
Quoted 34 lines · Arnd Bergmann
Quoted 13 lines · Greentime Hu
2017-11-27 22:21 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 11 lines · Greentime Hu
arch/nds32/Kconfig.cpu line 29
Quoted 8 lines
arch/nds32/Kconfig.cpu +7
-0+config CPU_CACHE_NONALIASING + bool "Non-aliasing cache" + help + If this CPU is using VIPT data cache and its cache way size is larger + than page size, say N. If it is using PIPT data cache, say Y. + + If unsure, say Y.Can you determine this from the CPU type?
Quoted 5 lines
There is no cpu register to determine it. It also depeneds on page size and way size however page size is configurable by software. These codes are determined at compile time will be benefit to code size and performance.
IMHO, I think it would be better to be determined here.I meant determining it at compile time from other
Kconfigsymbols, if that's possible. Do the CPU cores each have a fixed way-size? If they do, it could be done likemenu "CPU selection"
config
CPU_N15
bool "AndesCore N15"
selectCPU_CACHE_NONALIASINGconfig
CPU_N13
bool "AndesCore N15"
selectCPU_CACHE_NONALIASINGifPAGE_SIZE_16K
Quoted 6 lines
...
endmenu
and then you can use the same
CPU_... symbols to make other decisions as well, e.g. CPU specific compiler optimizations.
Do you want to support multiple CPU types in a single kernel image (I see no "choice" statement above)?
If yes, you may have a mix of aliasing and non-aliasing caches, so you may want to invert the logic, and select CPU_CACHE_ALIASING instead.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Arnd Bergmann
maintainerRe: [PATCH v2 25/35] nds32: Build infrastructure
Quoted 41 lines · Geert Uytterhoeven
Hi Arnd,
Quoted 38 lines · Arnd Bergmann
Quoted 13 lines · Greentime Hu
2017-11-27 22:21 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 11 lines · Greentime Hu
arch/nds32/Kconfig.cpu line 29
Quoted 8 lines
arch/nds32/Kconfig.cpu +7
-0+config CPU_CACHE_NONALIASING + bool "Non-aliasing cache" + help + If this CPU is using VIPT data cache and its cache way size is larger + than page size, say N. If it is using PIPT data cache, say Y. + + If unsure, say Y.Can you determine this from the CPU type?
Quoted 5 lines
There is no cpu register to determine it. It also depeneds on page size and way size however page size is configurable by software. These codes are determined at compile time will be benefit to code size and performance.
IMHO, I think it would be better to be determined here.I meant determining it at compile time from other
Kconfigsymbols, if that's possible. Do the CPU cores each have a fixed way-size? If they do, it could be done likemenu "CPU selection"
config
CPU_N15
bool "AndesCore N15"
selectCPU_CACHE_NONALIASINGconfig
CPU_N13
bool "AndesCore N15"
selectCPU_CACHE_NONALIASINGifPAGE_SIZE_16K...
endmenu
Quoted 8 lines
Quoted 2 lines
and then you can use the same
CPU_... symbols to make other decisions as well, e.g. CPU specific compiler optimizations.Do you want to support multiple CPU types in a single kernel image (I see no "choice" statement above)?
If yes, you may have a mix of aliasing and non-aliasing caches, so you may want to invert the logic, and selectCPU_CACHE_ALIASINGinstead.
Right, my mistake.
Arnd
Re: [PATCH v2 25/35] nds32: Build infrastructure
2017-11-29 17:25 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 46 lines
Quoted 44 lines · Geert Uytterhoeven
Hi Arnd,
Quoted 40 lines · Arnd Bergmann
Quoted 13 lines · Greentime Hu
2017-11-27 22:21 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 11 lines · Greentime Hu
arch/nds32/Kconfig.cpu line 29
Quoted 8 lines
arch/nds32/Kconfig.cpu +7
-0+config CPU_CACHE_NONALIASING + bool "Non-aliasing cache" + help + If this CPU is using VIPT data cache and its cache way size is larger + than page size, say N. If it is using PIPT data cache, say Y. + + If unsure, say Y.Can you determine this from the CPU type?
Quoted 5 lines
There is no cpu register to determine it. It also depeneds on page size and way size however page size is configurable by software. These codes are determined at compile time will be benefit to code size and performance.
IMHO, I think it would be better to be determined here.I meant determining it at compile time from other
Kconfigsymbols, if that's possible. Do the CPU cores each have a fixed way-size? If they do, it could be done likemenu "CPU selection"
config
CPU_N15
bool "AndesCore N15"
selectCPU_CACHE_NONALIASINGconfig
CPU_N13
bool "AndesCore N15"
selectCPU_CACHE_NONALIASINGifPAGE_SIZE_16K...
endmenu
and then you can use the same
CPU_... symbols to make other decisions as well, e.g. CPU specific compiler optimizations.
Quoted 8 lines
Quoted 5 lines
Do you want to support multiple CPU types in a single kernel image (I see no "choice" statement above)?
If yes, you may have a mix of aliasing and non-aliasing caches, so you may want to invert the logic, and selectCPU_CACHE_ALIASINGinstead.Right, my mistake.
Thanks to Arnd and Geert!
How about this?
choice
prompt "CPU type"
default CPU_N13
config CPU_N15
bool "AndesCore N15"
select CPU_CACHE_NONALIASING
config CPU_N13
bool "AndesCore N13"
select CPU_CACHE_NONALIASING if ANDES_PAGE_SIZE_8KB
config CPU_N10
bool "AndesCore N10"
select CPU_CACHE_NONALIASING if ANDES_PAGE_SIZE_8KB
config CPU_D15
bool "AndesCore D15"
select CPU_CACHE_NONALIASING
select HWZOL
config CPU_D10
bool "AndesCore D10"
select CPU_CACHE_NONALIASING if ANDES_PAGE_SIZE_8KB
endchoice
Arnd Bergmann
maintainerRe: [PATCH v2 25/35] nds32: Build infrastructure
Quoted 72 lines · Greentime Hu
2017-11-29 17:25 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 46 lines
Quoted 44 lines · Geert Uytterhoeven
Hi Arnd,
Quoted 40 lines · Arnd Bergmann
Quoted 13 lines · Greentime Hu
2017-11-27 22:21 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 11 lines · Greentime Hu
arch/nds32/Kconfig.cpu
Quoted 8 lines
arch/nds32/Kconfig.cpu +7
-0+config CPU_CACHE_NONALIASING + bool "Non-aliasing cache" + help + If this CPU is using VIPT data cache and its cache way size is larger + than page size, say N. If it is using PIPT data cache, say Y. + + If unsure, say Y.Can you determine this from the CPU type?
Quoted 5 lines
There is no cpu register to determine it. It also depeneds on page size and way size however page size is configurable by software. These codes are determined at compile time will be benefit to code size and performance.
IMHO, I think it would be better to be determined here.I meant determining it at compile time from other
Kconfigsymbols, if that's possible. Do the CPU cores each have a fixed way-size? If they do, it could be done likemenu "CPU selection"
config
CPU_N15
bool "AndesCore N15"
selectCPU_CACHE_NONALIASINGconfig
CPU_N13
bool "AndesCore N15"
selectCPU_CACHE_NONALIASINGifPAGE_SIZE_16K...
endmenu
and then you can use the same
CPU_... symbols to make other decisions as well, e.g. CPU specific compiler optimizations.Quoted 8 lines
Quoted 5 lines
Do you want to support multiple CPU types in a single kernel image (I see no "choice" statement above)?
If yes, you may have a mix of aliasing and non-aliasing caches, so you may want to invert the logic, and selectCPU_CACHE_ALIASINGinstead.Right, my mistake.
Thanks to Arnd and Geert!
How about this?
choice
prompt "CPU type"
defaultCPU_N13
configCPU_N15
bool "AndesCore N15"
selectCPU_CACHE_NONALIASING
configCPU_N13
bool "AndesCore N13"
selectCPU_CACHE_NONALIASINGifANDES_PAGE_SIZE_8KB
configCPU_N10
bool "AndesCore N10"
selectCPU_CACHE_NONALIASINGifANDES_PAGE_SIZE_8KB
Quoted 8 lines
config
CPU_D15
bool "AndesCore D15"
selectCPU_CACHE_NONALIASING
select HWZOL
configCPU_D10
bool "AndesCore D10"
selectCPU_CACHE_NONALIASINGifANDES_PAGE_SIZE_8KB
endchoice
With a 'choice' statement this works, but I would consider that suboptimal for another reason: now you cannot build a kernel that works on e.g. both N13 and N15.
This is what we had on ARM a long time ago and on MIPS not so long ago, but it's really a burden for testing and distribution once you get support for more than a handful of machines supported in the mainline
kernel: If each CPU core is mutually incompatible with the other ones, this means you likely end up having one defconfig per CPU core, or even one defconfig per SoC or board.
I would always try to get the largest amount of hardware to work in the same kernel concurrently.
One way of of this would be to define the "CPU type" as the minimum supported CPU, e.g. selecting D15 would result in a kernel that only works on D15, while selecting N15 would work on both N15 and D15, and selecting D10 would work on both D10 and D15.
Arnd
Re: [PATCH v2 25/35] nds32: Build infrastructure
2017-11-29 19:57 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 93 lines · Greentime Hu
Quoted 72 lines
2017-11-29 17:25 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 46 lines
Quoted 44 lines · Geert Uytterhoeven
Hi Arnd,
Quoted 40 lines · Arnd Bergmann
Quoted 13 lines · Greentime Hu
2017-11-27 22:21 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 11 lines · Greentime Hu
arch/nds32/Kconfig.cpu
Quoted 8 lines
arch/nds32/Kconfig.cpu +7
-0+config CPU_CACHE_NONALIASING + bool "Non-aliasing cache" + help + If this CPU is using VIPT data cache and its cache way size is larger + than page size, say N. If it is using PIPT data cache, say Y. + + If unsure, say Y.Can you determine this from the CPU type?
Quoted 5 lines
There is no cpu register to determine it. It also depeneds on page size and way size however page size is configurable by software. These codes are determined at compile time will be benefit to code size and performance.
IMHO, I think it would be better to be determined here.I meant determining it at compile time from other
Kconfigsymbols, if that's possible. Do the CPU cores each have a fixed way-size? If they do, it could be done likemenu "CPU selection"
config
CPU_N15
bool "AndesCore N15"
selectCPU_CACHE_NONALIASINGconfig
CPU_N13
bool "AndesCore N15"
selectCPU_CACHE_NONALIASINGifPAGE_SIZE_16K...
endmenu
and then you can use the same
CPU_... symbols to make other decisions as well, e.g. CPU specific compiler optimizations.Quoted 8 lines
Quoted 5 lines
Do you want to support multiple CPU types in a single kernel image (I see no "choice" statement above)?
If yes, you may have a mix of aliasing and non-aliasing caches, so you may want to invert the logic, and selectCPU_CACHE_ALIASINGinstead.Right, my mistake.
Thanks to Arnd and Geert!
How about this?
choice
prompt "CPU type"
defaultCPU_N13
configCPU_N15
bool "AndesCore N15"
selectCPU_CACHE_NONALIASING
configCPU_N13
bool "AndesCore N13"
selectCPU_CACHE_NONALIASINGifANDES_PAGE_SIZE_8KB
configCPU_N10
bool "AndesCore N10"
selectCPU_CACHE_NONALIASINGifANDES_PAGE_SIZE_8KBQuoted 8 lines
config
CPU_D15
bool "AndesCore D15"
selectCPU_CACHE_NONALIASING
select HWZOL
configCPU_D10
bool "AndesCore D10"
selectCPU_CACHE_NONALIASINGifANDES_PAGE_SIZE_8KB
endchoiceWith a 'choice' statement this works, but I would consider that suboptimal for another reason: now you cannot build a kernel that works on e.g. both N13 and N15.
This is what we had on ARM a long time ago and on MIPS not so long ago, but it's really a burden for testing and distribution once you get support for more than a handful of machines supported in the mainline
kernel: If each CPU core is mutually incompatible with the other ones, this means you likely end up having one defconfig per CPU core, or even one defconfig per SoC or board.
Quoted 8 lines
I would always try to get the largest amount of hardware to work in the same kernel concurrently.
One way of of this would be to define the "CPU type" as the minimum supported CPU, e.g. selecting D15 would result in a kernel that only works on D15, while selecting N15 would work on both N15 and D15, and selecting D10 would work on both D10 and D15.
Hi, Arnd:
Maybe we should keep the original implementation for this reason. The default value of CPU_CACHE_NONALIASING and ANDES_PAGE_SIZE_8KB is available for all CPU types for now.
User can use these configs built kernel to boot on almost all nds32 CPUs.
It might be a little bit weird if we config CPU_N10 but run on a N13 CPU. This might confuse our users.
Arnd Bergmann
maintainerRe: [PATCH v2 25/35] nds32: Build infrastructure
Quoted 48 lines · Greentime Hu
2017-11-29 19:57 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 36 lines · Greentime Hu
Quoted 15 lines
How about this?
choice
prompt "CPU type"
defaultCPU_N13
configCPU_N15
bool "AndesCore N15"
selectCPU_CACHE_NONALIASING
configCPU_N13
bool "AndesCore N13"
selectCPU_CACHE_NONALIASINGifANDES_PAGE_SIZE_8KB
configCPU_N10
bool "AndesCore N10"
selectCPU_CACHE_NONALIASINGifANDES_PAGE_SIZE_8KBQuoted 8 lines
config
CPU_D15
bool "AndesCore D15"
selectCPU_CACHE_NONALIASING
select HWZOL
configCPU_D10
bool "AndesCore D10"
selectCPU_CACHE_NONALIASINGifANDES_PAGE_SIZE_8KB
endchoiceWith a 'choice' statement this works, but I would consider that suboptimal for another reason: now you cannot build a kernel that works on e.g. both N13 and N15.
This is what we had on ARM a long time ago and on MIPS not so long ago, but it's really a burden for testing and distribution once you get support for more than a handful of machines supported in the mainline
kernel: If each CPU core is mutually incompatible with the other ones, this means you likely end up having one defconfig per CPU core, or even one defconfig per SoC or board.Quoted 8 lines
I would always try to get the largest amount of hardware to work in the same kernel concurrently.
One way of of this would be to define the "CPU type" as the minimum supported CPU, e.g. selecting D15 would result in a kernel that only works on D15, while selecting N15 would work on both N15 and D15, and selecting D10 would work on both D10 and D15.
Hi, Arnd:
Quoted 7 lines
Maybe we should keep the original implementation for this reason. The default value of
CPU_CACHE_NONALIASINGandANDES_PAGE_SIZE_8KBis available for all CPU types for now.
User can use these configs built kernel to boot on almost all nds32 CPUs.It might be a little bit weird if we config
CPU_N10but run on a N13 CPU. This might confuse our users.
I think it really depends on how much flexibility you want to give to users. The way I suggested first was to allow selecting an arbitrary combination of CPUs, and then let Kconfig derive the correct set of optimization flags and other options that work with those. That is probably the easiest for the users, but can be tricky to get right for all combinations.
When you put them in a sorted list like I mentioned for simplicity, you could reduce the confusion by naming them differently, e.g. CONFIG_CPU_N10_OR_NEWER.
Having only the CPU_CACHE_NONALIASING option is fine if you never need to make any other decisions based on the CPU core type, but then the help text should describe specifically which cases are affected (N10/N13/D13 with 4K page size), and you can decide to hide the option and make it always-on when using 8K page size.
Arnd
Re: [PATCH v2 25/35] nds32: Build infrastructure
2017-11-30 4:27 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 67 lines · Greentime Hu
Quoted 48 lines
2017-11-29 19:57 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 36 lines · Greentime Hu
Quoted 15 lines
How about this?
choice
prompt "CPU type"
defaultCPU_N13
configCPU_N15
bool "AndesCore N15"
selectCPU_CACHE_NONALIASING
configCPU_N13
bool "AndesCore N13"
selectCPU_CACHE_NONALIASINGifANDES_PAGE_SIZE_8KB
configCPU_N10
bool "AndesCore N10"
selectCPU_CACHE_NONALIASINGifANDES_PAGE_SIZE_8KBQuoted 8 lines
config
CPU_D15
bool "AndesCore D15"
selectCPU_CACHE_NONALIASING
select HWZOL
configCPU_D10
bool "AndesCore D10"
selectCPU_CACHE_NONALIASINGifANDES_PAGE_SIZE_8KB
endchoiceWith a 'choice' statement this works, but I would consider that suboptimal for another reason: now you cannot build a kernel that works on e.g. both N13 and N15.
This is what we had on ARM a long time ago and on MIPS not so long ago, but it's really a burden for testing and distribution once you get support for more than a handful of machines supported in the mainline
kernel: If each CPU core is mutually incompatible with the other ones, this means you likely end up having one defconfig per CPU core, or even one defconfig per SoC or board.Quoted 8 lines
I would always try to get the largest amount of hardware to work in the same kernel concurrently.
One way of of this would be to define the "CPU type" as the minimum supported CPU, e.g. selecting D15 would result in a kernel that only works on D15, while selecting N15 would work on both N15 and D15, and selecting D10 would work on both D10 and D15.
Hi, Arnd:
Quoted 7 lines
Maybe we should keep the original implementation for this reason. The default value of
CPU_CACHE_NONALIASINGandANDES_PAGE_SIZE_8KBis available for all CPU types for now.
User can use these configs built kernel to boot on almost all nds32 CPUs.It might be a little bit weird if we config
CPU_N10but run on a N13 CPU. This might confuse our users.I think it really depends on how much flexibility you want to give to users. The way I suggested first was to allow selecting an arbitrary combination of CPUs, and then let
Kconfigderive the correct set of optimization flags and other options that work with those. That is probably the easiest for the users, but can be tricky to get right for all combinations.When you put them in a sorted list like I mentioned for simplicity, you could reduce the confusion by naming them differently, e.g.
CONFIG_CPU_N10_OR_NEWER.
Quoted 7 lines
Having only the
CPU_CACHE_NONALIASINGoption is fine if you never need to make any other decisions based on the CPU core type, but then the help text should describe specifically which cases are affected (N10/N13/D13 with 4K page size), and you can decide to hide the option and make it always-on when using 8K page size.Arnd
Hi, Arnd:
I think I can use this name "CPU_V3" for all nds32 v3 compatible cpu. It will be implemented like this.
config HWZOL
bool "hardware zero overhead loop support"
depends on CPU_D10 || CPU_D15
default n
help
A set of Zero-Overhead Loop mechanism is provided to reduce the instruction fetch and execution overhead of loop-control instructions. It will save 3 registers($LB, $LC, $LE) for context saving if say Y. You don't need to save these registers if you can make sure your user program doesn't use these registers.
If unsure, say N.
config CPU_CACHE_NONALIASING
bool "Non-aliasing cache"
depends on !CPU_N10 && !CPU_D10
default n
help
If this CPU is using VIPT data cache and its cache way size is larger than page size, say N. If it is using PIPT data cache, say Y.
If unsure, say N.
choice
prompt "CPU type"
default CPU_V3
config CPU_N15
bool "AndesCore N15"
select CPU_CACHE_NONALIASING
config CPU_N13
bool "AndesCore N13"
select CPU_CACHE_NONALIASING if ANDES_PAGE_SIZE_8KB
config CPU_N10
bool "AndesCore N10"
config CPU_D15
bool "AndesCore D15"
select CPU_CACHE_NONALIASING
config CPU_D10
bool "AndesCore D10"
config CPU_V3
bool "AndesCore v3 compatible"
select ANDES_PAGE_SIZE_4KB
endchoice
Re: [PATCH v2 25/35] nds32: Build infrastructure
Quoted 28 lines · Greentime Hu
2017-11-30 4:27 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 3 lines · Greentime Hu
Quoted 2 lines
2017-11-29 19:57 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 1 line · Greentime Hu
I think I can use this name "
CPU_V3" for all nds32 v3 compatible cpu. It will be implemented like this.config HWZOL
bool "hardware zero overhead loop support"
depends onCPU_D10||CPU_D15
default n
help
A set of Zero-Overhead Loop mechanism is provided to reduce the instruction fetch and execution overhead of loop-control instructions. It will save 3registers($LB, $LC, $LE)for context saving if say Y. You don't need to save these registers if you can make sure your user program doesn't use these registers.If unsure, say N.
config
CPU_CACHE_NONALIASING
bool "Non-aliasing cache"
depends on !CPU_N10 && !CPU_D10
default n
help
If this CPU is using VIPT data cache and its cache way size is larger than page size, say N. If it is using PIPT data cache, say Y.
Quoted 1 line
If unsure, say N.
I still think it will be easier to revert the logic, and have CPU_CACHE_ALIASING.
Gr{oetje,eeting}s,
Geert
Re: [PATCH v2 25/35] nds32: Build infrastructure
2017-11-30 15:52 GMT+08:00 Geert Uytterhoeven <[email protected]>:
Quoted 29 lines · Greentime Hu
Quoted 28 lines
2017-11-30 4:27 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 3 lines · Greentime Hu
Quoted 2 lines
2017-11-29 19:57 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 1 line · Greentime Hu
I think I can use this name "
CPU_V3" for all nds32 v3 compatible cpu. It will be implemented like this.config HWZOL
bool "hardware zero overhead loop support"
depends onCPU_D10||CPU_D15
default n
help
A set of Zero-Overhead Loop mechanism is provided to reduce the instruction fetch and execution overhead of loop-control instructions. It will save 3registers($LB, $LC, $LE)for context saving if say Y. You don't need to save these registers if you can make sure your user program doesn't use these registers.If unsure, say N.
config
CPU_CACHE_NONALIASING
bool "Non-aliasing cache"
depends on !CPU_N10 && !CPU_D10
default n
help
If this CPU is using VIPT data cache and its cache way size is larger than page size, say N. If it is using PIPT data cache, say Y.
Quoted 5 lines
Quoted 1 line
If unsure, say N.
I still think it will be easier to revert the logic, and have
CPU_CACHE_ALIASING.
Thanks Geert
I will implement it like this.
config HWZOL
bool "hardware zero overhead loop support"
depends on CPU_D10 || CPU_D15
default n
help
A set of Zero-Overhead Loop mechanism is provided to reduce the instruction fetch and execution overhead of loop-control instructions. It will save 3 registers($LB, $LC, $LE) for context saving if say Y. You don't need to save these registers if you can make sure your user program doesn't use these registers.
If unsure, say N.
config CPU_CACHE_ALIASING
bool "Aliasing cache"
depends on CPU_N10 || CPU_D10 || CPU_N13 || CPU_V3
default y
help
If this CPU is using VIPT data cache and its cache way size is larger than page size, say Y. If it is using PIPT data cache, say N.
If unsure, say Y.
choice
prompt "CPU type"
default CPU_V3
config CPU_N15
bool "AndesCore N15"
config CPU_N13
bool "AndesCore N13"
select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB
config CPU_N10
bool "AndesCore N10"
select CPU_CACHE_ALIASING
config CPU_D15
bool "AndesCore D15"
config CPU_D10
bool "AndesCore D10"
select CPU_CACHE_ALIASING
config CPU_V3
bool "AndesCore v3 compatible"
select ANDES_PAGE_SIZE_8KB
endchoice
Arnd Bergmann
maintainerRe: [PATCH v2 25/35] nds32: Build infrastructure
In reply to Greentime HuQuoted 14 lines · Greentime Hu
2017-11-30 4:27 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 13 lines · Greentime Hu
Quoted 1 line
2017-11-29 19:57 GMT+08:00 Arnd Bergmann <[email protected]>:
When you put them in a sorted list like I mentioned for simplicity, you could reduce the confusion by naming them differently, e.g.
CONFIG_CPU_N10_OR_NEWER.Having only the
CPU_CACHE_NONALIASINGoption is fine if you never need to make any other decisions based on the CPU core type, but then the help text should describe specifically which cases are affected (N10/N13/D13 with 4K page size), and you can decide to hide the option and make it always-on when using 8K page size.
Quoted 7 lines
Quoted 1 line
Arnd
Hi, Arnd:
I think I can use this name "
CPU_V3" for all nds32 v3 compatible cpu. It will be implemented like this.
I think I'm still a bit confused about the relation between CPU cores and architecture levels. Is it correct to say that there are orthogonal, and that you can have e.g. an N10 core implementing either nds32v2 or nds32v3?
There is nothing wrong with that of course, it's just not what I expected from having worked with other architectures.
I also see that GCC has no pipeline specific optimizations for specific cores, it just understands the differences between the architecture levels, so at least today there is way to pass e.g. "-march=nds32v2 -mtune=d15" to generate code that would work on both v2 and v3 but be optimized for d15.
Quoted 21 lines
config HWZOL
bool "hardware zero overhead loop support"
depends onCPU_D10||CPU_D15
default n
help
A set of Zero-Overhead Loop mechanism is provided to reduce the instruction fetch and execution overhead of loop-control instructions. It will save 3registers($LB, $LC, $LE)for context saving if say Y. You don't need to save these registers if you can make sure your user program doesn't use these registers.If unsure, say N.
config
CPU_CACHE_NONALIASING
bool "Non-aliasing cache"
depends on !CPU_N10 && !CPU_D10
default n
help
If this CPU is using VIPT data cache and its cache way size is larger than page size, say N. If it is using PIPT data cache, say Y.
Quoted 1 line
If unsure, say N.
This looks ok, yes, but as Geert said, it would seem more intuitive to write it as
config CPU_CACHE_ALIASING
bool "Aliasing VIPT cache"
depends on CPU_N10 || CPU_D10
Quoted 12 lines
choice
prompt "CPU type"
defaultCPU_V3
configCPU_N15
bool "AndesCore N15"
selectCPU_CACHE_NONALIASING
configCPU_N13
bool "AndesCore N13"
selectCPU_CACHE_NONALIASINGifANDES_PAGE_SIZE_8KB
configCPU_N10
bool "AndesCore N10"
configCPU_D15
Quoted 8 lines
bool "AndesCore D15"
selectCPU_CACHE_NONALIASING
configCPU_D10
bool "AndesCore D10"
configCPU_V3
bool "AndesCore v3 compatible"
selectANDES_PAGE_SIZE_4KB
endchoice
Two points here:
- Generally you should not mix 'select' and 'depends on' like this. Either you make the cache aliasing a user visible option that uses 'depends on' with a combination of CPU cores, or you make it a hidden option (with no string after the "bool" keyword) that always gets selected from the per-cpu options.
- There is a little-known trick with choice statements that allows you to use 'tristate' instead of 'bool' in the choice. In that case, you can enable multiple options together as long as all of them are 'm'.
Arnd
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Re: [PATCH v2 25/35] nds32: Build infrastructure
2017-11-30 17:30 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 20 lines · Greentime Hu
Quoted 19 lines
2017-11-30 4:27 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 7 lines · Greentime Hu
Quoted 1 line
2017-11-29 19:57 GMT+08:00 Arnd Bergmann <[email protected]>:
When you put them in a sorted list like I mentioned for simplicity, you could reduce the confusion by naming them differently, e.g.
CONFIG_CPU_N10_OR_NEWER.Quoted 7 lines
Having only the
CPU_CACHE_NONALIASINGoption is fine if you never need to make any other decisions based on the CPU core type, but then the help text should describe specifically which cases are affected (N10/N13/D13 with 4K page size), and you can decide to hide the option and make it always-on when using 8K page size.Arnd
Hi, Arnd:
Quoted 8 lines
Quoted 2 lines
I think I can use this name "
CPU_V3" for all nds32 v3 compatible cpu. It will be implemented like this.I think I'm still a bit confused about the relation between CPU cores and architecture levels. Is it correct to say that there are orthogonal, and that you can have e.g. an N10 core implementing either nds32v2 or nds32v3?
Yup, we did having N10 cores are implementing either nds32v3 or nds32v2, but nds32v2 are not used anymore.
We can assume every nds32 cores are v3.
Quoted 8 lines
There is nothing wrong with that of course, it's just not what I expected from having worked with other architectures.
I also see that GCC has no pipeline specific optimizations for specific cores, it just understands the differences between the architecture levels, so at least today there is way to pass e.g. "-march=nds32v2 -mtune=d15" to generate code that would work on both v2 and v3 but be optimized for d15.
Thanks. We will work on that.
Quoted 59 lines
Quoted 21 lines
config HWZOL
bool "hardware zero overhead loop support"
depends onCPU_D10||CPU_D15
default n
help
A set of Zero-Overhead Loop mechanism is provided to reduce the instruction fetch and execution overhead of loop-control instructions. It will save 3registers($LB, $LC, $LE)for context saving if say Y. You don't need to save these registers if you can make sure your user program doesn't use these registers.If unsure, say N.
config
CPU_CACHE_NONALIASING
bool "Non-aliasing cache"
depends on !CPU_N10 && !CPU_D10
default n
help
If this CPU is using VIPT data cache and its cache way size is larger than page size, say N. If it is using PIPT data cache, say Y.Quoted 1 line
If unsure, say N.
This looks ok, yes, but as Geert said, it would seem more intuitive to write it as
config
CPU_CACHE_ALIASING
bool "Aliasing VIPT cache"
depends onCPU_N10||CPU_D10Quoted 12 lines
choice
prompt "CPU type"
defaultCPU_V3
configCPU_N15
bool "AndesCore N15"
selectCPU_CACHE_NONALIASING
configCPU_N13
bool "AndesCore N13"
selectCPU_CACHE_NONALIASINGifANDES_PAGE_SIZE_8KB
configCPU_N10
bool "AndesCore N10"
configCPU_D15Quoted 8 lines
bool "AndesCore D15"
selectCPU_CACHE_NONALIASING
configCPU_D10
bool "AndesCore D10"
configCPU_V3
bool "AndesCore v3 compatible"
selectANDES_PAGE_SIZE_4KB
endchoiceTwo points here:
- Generally you should not mix 'select' and 'depends on' like this. Either you make the cache aliasing a user visible option that uses 'depends on' with a combination of CPU cores, or you make it a hidden option (with no string after the "bool" keyword) that always gets selected from the per-cpu options.
Quoted 6 lines
- There is a little-known trick with choice statements that allows you to use 'tristate' instead of 'bool' in the choice. In that case, you can enable multiple options together as long as all of them are 'm'.
Arnd
Thanks.CPU_CACHE_ALIASING is more intuitive. I will apply it.
PATCH v2 26/35 dt-bindings: interrupt-controller: Andestech Internal Vector Interrupt Controller
In reply to Greentime HuFrom: Greentime Hu <greentime-MUIXKm3Oiri1Z/[email protected]>
This patch adds an irqchip driver document for the Andestech Internal Vector Interrupt Controller.
--- .../interrupt-controller/andestech,ativic32.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt
Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt new file +19 -0
@@ -0,0 +1,19 @@ +* Andestech Internal Vector Interrupt Controller + +The Internal Vector Interrupt Controller (IVIC) is a basic interrupt controller +suitable for a simpler SoC platform not requiring a more sophisticated and +bigger External Vector Interrupt Controller. + + +Main node required properties: + +- compatible : should at least contain "andestech,ativic32". +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells: 1 cells and refer to interrupt-controller/interrupts + +Examples: + intc: interrupt-controller { + compatible = "andestech,ativic32"; + #interrupt-cells = <1>; + interrupt-controller; + };
Signature · 6 lines
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Re: [PATCH v2 26/35] dt-bindings: interrupt-controller: Andestech Internal Vector Interrupt Controller
Quoted 11 lines · Greentime Hu
From: Greentime Hu <[email protected]>
This patch adds an irqchip driver document for the Andestech Internal Vector Interrupt Controller.
Signed-off-by Rick Chen <[email protected]>Signed-off-by Greentime Hu <[email protected]>--- .../interrupt-controller/andestech,ativic32.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt
PATCH v2 27/35 irqchip: Andestech Internal Vector Interrupt Controller driver
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
This patch adds the Andestech Internal Vector Interrupt Controller driver. You can find the spec here. Ch4.9 of AndeStar SPA V3 Manual.
http://www.andestech.com/product.php?cls=9
--- drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-ativic32.c | 119 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 120 insertions(+) create mode 100644 drivers/irqchip/irq-ativic32.c
drivers/irqchip/Makefile +1 -0
@@ -80,3 +80,4 @@ obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o obj-$(CONFIG_IRQ_UNIPHIER_AIDET) += irq-uniphier-aidet.o +obj-$(CONFIG_NDS32) += irq-ativic32.o
drivers/irqchip/irq-ativic32.c new file +119 -0
119 lines not on this page · raw message
Signature · 1 line
1.7.9.5
Re: [PATCH v2 27/35] irqchip: Andestech Internal Vector Interrupt Controller driver
Quoted 47 lines · Greentime Hu
From: Greentime Hu <greentime-MUIXKm3Oiri1Z/[email protected]>
This patch adds the Andestech Internal Vector Interrupt Controller driver. You can find the spec here. Ch4.9 of AndeStar SPA V3 Manual.
http://www.andestech.com/product.php?cls=9Signed-off-by Rick Chen <rick-MUIXKm3Oiri1Z/[email protected]>Signed-off-by Greentime Hu <greentime-MUIXKm3Oiri1Z/[email protected]>--- drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-ativic32.c | 119 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 120 insertions(+) create mode 100644 drivers/irqchip/irq-ativic32.cdrivers/irqchip/Makefile +1
-0@@ -80,3 +80,4 @@ obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o obj-$(CONFIG_IRQ_UNIPHIER_AIDET) += irq-uniphier-aidet.o +obj-$(CONFIG_NDS32) += irq-ativic32.odrivers/irqchip/irq-ativic32.c new file +18
-0@@ -0,0 +1,119 @@ +/* +* Copyright (C) 2005-2017 Andes Technology Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <linux/irq.h> +#include <linux/of.h>
drivers/irqchip/irq-ativic32.c line 28
Quoted 10 lines
drivers/irqchip/irq-ativic32.c new file +10
-0+#include <linux/of_irq.h> +#include <linux/of_address.h> +#include <linux/interrupt.h> +#include <linux/irqdomain.h> +#include <linux/irqchip.h> +#include <nds32_intrinsic.h> + +static void ativic32_ack_irq (struct irq_data *data) +{ +__nds32__mtsr_dsb (1 << data->hwirq,NDS32_SR_INT_PEND2 );
Consider writing (1 << data->hwirq) as BIT(data->hwirq).
drivers/irqchip/irq-ativic32.c line 34
Quoted 6 lines
drivers/irqchip/irq-ativic32.c new file +6
-0+} + +static void ativic32_mask_irq (struct irq_data *data) +{ +unsigned long int_mask2 =__nds32__mfsr (NDS32_SR_INT_MASK2 ); +__nds32__mtsr_dsb (int_mask2 & (~(1 << data->hwirq)),NDS32_SR_INT_MASK2 );
Same here.
drivers/irqchip/irq-ativic32.c line 41
Quoted 7 lines
drivers/irqchip/irq-ativic32.c new file +7
-0+} + +static void ativic32_mask_ack_irq (struct irq_data *data) +{ +unsigned long int_mask2 =__nds32__mfsr (NDS32_SR_INT_MASK2 ); +__nds32__mtsr_dsb (int_mask2 & (~(1 << data->hwirq)),NDS32_SR_INT_MASK2 ); +__nds32__mtsr_dsb ((1 << data->hwirq),NDS32_SR_INT_PEND2 );
This is effectively MASK+ACK, so you're better off just writing it as such. And since there is no advantage in your implementation in having MASK_ACK over MASK+ACK, I suggest you remove this function completely, and rely on the core code which will call them in sequence.
drivers/irqchip/irq-ativic32.c line 48
Quoted 7 lines
drivers/irqchip/irq-ativic32.c new file +7
-0+ +} + +static void ativic32_unmask_irq (struct irq_data *data) +{ +unsigned long int_mask2 =__nds32__mfsr (NDS32_SR_INT_MASK2 ); +__nds32__mtsr_dsb (int_mask2 | (1 << data->hwirq),NDS32_SR_INT_MASK2 );
Same BIT() here.
Quoted 10 lines
drivers/irqchip/irq-ativic32.c new file +10
-0+} + +static struct irq_chip ativic32_chip = { + .name ="ativic32" , + .irq_ack = ativic32_ack_irq, + .irq_mask = ativic32_mask_irq, + .irq_mask_ack = ativic32_mask_ack_irq, + .irq_unmask = ativic32_unmask_irq, +}; +
drivers/irqchip/irq-ativic32.c line 68
Quoted 10 lines
drivers/irqchip/irq-ativic32.c new file +10
-0+static unsigned int __initdata nivic_map[6 ] = {6 ,2 ,10 ,16 ,24 ,32 }; + +static struct irq_domain *root_domain; +static int ativic32_irq_domain_map (struct irq_domain *id,unsigned int virq, +irq_hw_number_t hw) +{ + +unsigned long int_trigger_type; + int_trigger_type =__nds32__mfsr (NDS32_SR_INT_TRIGGER ); +if (int_trigger_type & (1 << hw))
And here.
drivers/irqchip/irq-ativic32.c line 71
Quoted 3 lines
drivers/irqchip/irq-ativic32.c new file +3
-0+irq_set_chip_and_handler (virq, &ativic32_chip, handle_edge_irq); + else + irq_set_chip_and_handler(virq, &ativic32_chip, handle_level_irq);
Since you do not express the trigger in DT, you need to tell the core about it by calling irqd_set_trigger_type() with the right setting.
drivers/irqchip/irq-ativic32.c line 81
Quoted 10 lines
drivers/irqchip/irq-ativic32.c new file +10
-0+ +return 0 ; +} + +static struct irq_domain_ops ativic32_ops = { + .map = ativic32_irq_domain_map, + .xlate = irq_domain_xlate_onecell +}; + +static int get_intr_src (void )
I'm not sure "int" is the best return type here. I suspect something unsigned would be preferable, or even the irq_hw_number_t type.
drivers/irqchip/irq-ativic32.c line 83
Quoted 2 lines
drivers/irqchip/irq-ativic32.c new file +2
-0+{ +return ((__nds32__mfsr (NDS32_SR_ITYPE )&ITYPE_mskVECTOR) >> ITYPE_offVECTOR)
Spaces around '&'.
drivers/irqchip/irq-ativic32.c line 89
Quoted 6 lines
drivers/irqchip/irq-ativic32.c new file +6
-0+ - NDS32_VECTOR_offINTERRUPT; +} + +asmlinkage void asm_do_IRQ(struct pt_regs *regs) +{ +int hwirq =get_intr_src ();
irq_hw_number_t.
Quoted 7 lines
drivers/irqchip/irq-ativic32.c new file +7
-0+handle_domain_irq (root_domain, hwirq, regs); +} + +int __init ativic32_init_irq (struct device_node *node,struct device_node *parent) +{ +unsigned long int_vec_base, nivic; +
drivers/irqchip/irq-ativic32.c line 106
Quoted 10 lines
drivers/irqchip/irq-ativic32.c new file +10
-0+if (WARN (parent,"non-root ativic32 are not supported" )) +return -EINVAL ; + + int_vec_base =__nds32__mfsr (NDS32_SR_IVB ); + +if (((int_vec_base & IVB_mskIVIC_VER) >> IVB_offIVIC_VER) ==0 ) +panic ("Unable to use atcivic32 for this cpu.\n" ); + + nivic = (int_vec_base & IVB_mskNIVIC) >> IVB_offNIVIC; +if (nivic >= (sizeof nivic_map /sizeof nivic_map[0 ]))
This should be:
if (nivic >= ARRAY_SIZE(NIVIC_MAP))
drivers/irqchip/irq-ativic32.c line 109
Quoted 3 lines
drivers/irqchip/irq-ativic32.c new file +3
-0+panic ("The number of input for ativic32 is not supported.\n" ); + + nivic = nivic_map[nivic];
I'd rather you use another variable (nr_ints?).
drivers/irqchip/irq-ativic32.c line 119
Quoted 11 lines
drivers/irqchip/irq-ativic32.c new file +10
-0+ + root_domain =irq_domain_add_linear (node, nivic, + &ativic32_ops,NULL ); + +if (!root_domain) +panic ("%s: unable to create IRQ domain\n" , node->full_name); + +return 0 ; +} +IRQCHIP_DECLARE (ativic32,"andestech,ativic32" , ativic32_init_irq);
Thanks,
M.
Signature · 5 lines
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Re: [PATCH v2 27/35] irqchip: Andestech Internal Vector Interrupt Controller driver
Hi, Marc:
2017-11-28 17:37 GMT+08:00 Marc Zyngier <[email protected]>:
Quoted 6 lines · Greentime Hu
drivers/irqchip/irq-ativic32.c line 28
Quoted 3 lines
drivers/irqchip/irq-ativic32.c new file +3
-0+static void ativic32_ack_irq (struct irq_data *data) +{ +__nds32__mtsr_dsb (1 << data->hwirq,NDS32_SR_INT_PEND2 );Consider writing (1 <<
data->hwirq) asBIT(data->hwirq).
Thanks for this suggestion. I will modify it in the next version patch.
Quoted 8 lines
drivers/irqchip/irq-ativic32.c line 34
Quoted 6 lines
drivers/irqchip/irq-ativic32.c new file +6
-0+} + +static void ativic32_mask_irq (struct irq_data *data) +{ +unsigned long int_mask2 =__nds32__mfsr (NDS32_SR_INT_MASK2 ); +__nds32__mtsr_dsb (int_mask2 & (~(1 << data->hwirq)),NDS32_SR_INT_MASK2 );Same here.
Thanks for this suggestion. I will modify it in the next version patch.
Quoted 4 lines
Quoted 4 lines
drivers/irqchip/irq-ativic32.c new file +4
-0+} + +static void ativic32_mask_ack_irq (struct irq_data *data) +{
Quoted 8 lines
drivers/irqchip/irq-ativic32.c line 41
Quoted 3 lines
drivers/irqchip/irq-ativic32.c new file +3
-0+unsigned long int_mask2 =__nds32__mfsr (NDS32_SR_INT_MASK2 ); +__nds32__mtsr_dsb (int_mask2 & (~(1 << data->hwirq)),NDS32_SR_INT_MASK2 ); +__nds32__mtsr_dsb ((1 << data->hwirq),NDS32_SR_INT_PEND2 );This is effectively MASK+ACK, so you're better off just writing it as such. And since there is no advantage in your implementation in having
MASK_ACKover MASK+ACK, I suggest you remove this function completely, and rely on the core code which will call them in sequence.
I think mask_ack is still better than mask + ack because we don't need to do two function call.
We can save a prologue and a epilogue. It will benefit interrupt latency.
Quoted 10 lines
drivers/irqchip/irq-ativic32.c line 48
Quoted 7 lines
drivers/irqchip/irq-ativic32.c new file +7
-0+ +} + +static void ativic32_unmask_irq (struct irq_data *data) +{ +unsigned long int_mask2 =__nds32__mfsr (NDS32_SR_INT_MASK2 ); +__nds32__mtsr_dsb (int_mask2 | (1 << data->hwirq),NDS32_SR_INT_MASK2 );Same
BIT()here.
Thanks for this suggestion. I will modify it in the next version patch.
Quoted 14 lines
Quoted 14 lines
drivers/irqchip/irq-ativic32.c new file +14
-0+} + +static struct irq_chip ativic32_chip = { + .name ="ativic32" , + .irq_ack = ativic32_ack_irq, + .irq_mask = ativic32_mask_irq, + .irq_mask_ack = ativic32_mask_ack_irq, + .irq_unmask = ativic32_unmask_irq, +}; + +static unsigned int __initdata nivic_map[6 ] = {6 ,2 ,10 ,16 ,24 ,32 }; + +static struct irq_domain *root_domain; +static int ativic32_irq_domain_map(struct irq_domain *id, unsigned int virq,
Quoted 9 lines
drivers/irqchip/irq-ativic32.c line 68
Quoted 6 lines
drivers/irqchip/irq-ativic32.c new file +6
-0+ irq_hw_number_t hw) +{ + +unsigned long int_trigger_type; + int_trigger_type =__nds32__mfsr (NDS32_SR_INT_TRIGGER ); +if (int_trigger_type & (1 << hw))And here.
Thanks for this suggestion. I will modify it in the next version patch.
Quoted 7 lines
drivers/irqchip/irq-ativic32.c line 71
Quoted 3 lines
drivers/irqchip/irq-ativic32.c new file +3
-0+irq_set_chip_and_handler (virq, &ativic32_chip, handle_edge_irq); + else + irq_set_chip_and_handler(virq, &ativic32_chip, handle_level_irq);Since you do not express the trigger in DT, you need to tell the core about it by calling
irqd_set_trigger_type()with the right setting.
Since the comments say so, I will add ativic32_set_type() for irq_set_type() in the next version patch.
/*
* Must only be called inside irq_chip.irq_set_type() functions. */
static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
{
__irqd_to_state(d) &= ~IRQD_TRIGGER_MASK;
__irqd_to_state(d) |= type & IRQD_TRIGGER_MASK;
}It will be like this.
static int ativic32_set_type(struct irq_data *data, unsigned int flow_type)
{
irqd_set_trigger_type(data, flow_type);
return IRQ_SET_MASK_OK;
}Quoted 5 lines
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drivers/irqchip/irq-ativic32.c new file +5
-0+ +return 0 ; +} + +static struct irq_domain_ops ativic32_ops = {
Quoted 8 lines
drivers/irqchip/irq-ativic32.c line 81
Quoted 5 lines
drivers/irqchip/irq-ativic32.c new file +5
-0+ .map = ativic32_irq_domain_map, + .xlate = irq_domain_xlate_onecell +}; + +static int get_intr_src (void )I'm not sure "int" is the best return type here. I suspect something unsigned would be preferable, or even the
irq_hw_number_ttype.
Thanks for this suggestion. I will modify it in the next version patch.
Quoted 5 lines
Review
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(quoted diff) +2
-0+{ + return ((__nds32__mfsr(NDS32_SR_ITYPE)&ITYPE_mskVECTOR) >> ITYPE_offVECTOR)Spaces around '&'.
Thanks for this suggestion. I will modify it in the next version patch.
Quoted 9 lines
drivers/irqchip/irq-ativic32.c line 89
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drivers/irqchip/irq-ativic32.c new file +6
-0+ - NDS32_VECTOR_offINTERRUPT; +} + +asmlinkage void asm_do_IRQ(struct pt_regs *regs) +{ +int hwirq =get_intr_src ();
irq_hw_number_t.
Thanks for this suggestion. I will modify it in the next version patch.
Quoted 12 lines
Quoted 12 lines
drivers/irqchip/irq-ativic32.c new file +12
-0+handle_domain_irq (root_domain, hwirq, regs); +} + +int __init ativic32_init_irq (struct device_node *node,struct device_node *parent) +{ +unsigned long int_vec_base, nivic; + +if (WARN (parent,"non-root ativic32 are not supported" )) +return -EINVAL ; + + int_vec_base =__nds32__mfsr (NDS32_SR_IVB ); +
Quoted 9 lines
drivers/irqchip/irq-ativic32.c line 106
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drivers/irqchip/irq-ativic32.c new file +5
-0+if (((int_vec_base & IVB_mskIVIC_VER) >> IVB_offIVIC_VER) ==0 ) +panic ("Unable to use atcivic32 for this cpu.\n" ); + + nivic = (int_vec_base & IVB_mskNIVIC) >> IVB_offNIVIC; +if (nivic >= (sizeof nivic_map /sizeof nivic_map[0 ]))This should be:
if (nivic >=ARRAY_SIZE(NIVIC_MAP))
Thanks for this suggestion. I will modify it in the next version patch.
Quoted 6 lines
drivers/irqchip/irq-ativic32.c line 109
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drivers/irqchip/irq-ativic32.c new file +3
-0+panic ("The number of input for ativic32 is not supported.\n" ); + + nivic = nivic_map[nivic];I'd rather you use another variable (
nr_ints?).
Thanks for this suggestion. I will modify it in the next version patch.
Quoted 14 lines
drivers/irqchip/irq-ativic32.c line 119
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drivers/irqchip/irq-ativic32.c new file +10
-0+ + root_domain =irq_domain_add_linear (node, nivic, + &ativic32_ops,NULL ); + +if (!root_domain) +panic ("%s: unable to create IRQ domain\n" , node->full_name); + +return 0 ; +} +IRQCHIP_DECLARE (ativic32,"andestech,ativic32" , ativic32_init_irq);Thanks,
Quoted 3 lines
M.--
Jazz is not dead. It just smells funny...
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Re: [PATCH v2 27/35] irqchip: Andestech Internal Vector Interrupt Controller driver
On Wed, Nov 29 2017 at 11:23:34 pm GMT, Greentime Hu <[email protected]> wrote:
Hi Greentime,
Quoted 14 lines
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drivers/irqchip/irq-ativic32.c new file +5
-0+} + +static void ativic32_mask_ack_irq (struct irq_data *data) +{ +unsigned long int_mask2 =__nds32__mfsr (NDS32_SR_INT_MASK2 );Quoted 8 lines
Quoted 3 lines
+
__nds32__mtsr_dsb(int_mask2 & (~(1 << data->hwirq)), NDS32_SR_INT_MASK2);
+__nds32__mtsr_dsb((1 << data->hwirq), NDS32_SR_INT_PEND2);This is effectively MASK+ACK, so you're better off just writing it as such. And since there is no advantage in your implementation in having
MASK_ACKover MASK+ACK, I suggest you remove this function completely, and rely on the core code which will call them in sequence.
Quoted 3 lines
I think
mask_ackis still better than mask + ack because we don't need to do two function call.
We can save a prologue and a epilogue. It will benefit interrupt latency.
Can you actually measure this? Your CPU would have to be extremely slow if you could see the impact of an extra function call on interrupt latency. From a maintenance perspective, this isn't very nice (it is effectively code duplication).
I suggest you start with the simplest version of the code, and provide an optimisation once you can measurably demonstrate that mask_ack is better.
[...]
Quoted 20 lines
Quoted 7 lines
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+
irq_set_chip_and_handler(virq, &ativic32_chip, handle_edge_irq);
+ else
+irq_set_chip_and_handler(virq, &ativic32_chip, handle_level_irq);Since you do not express the trigger in DT, you need to tell the core about it by calling
irqd_set_trigger_type()with the right setting.Since the comments say so, I will add
ativic32_set_type()forirq_set_type()in the next version patch./*
* Must only be called insideirq_chip.irq_set_type()functions. */
static inline voidirqd_set_trigger_type(struct irq_data *d, u32 type){ __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK; __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK; }
Quoted 6 lines
It will be like this.
static intativic32_set_type(struct irq_data *data, unsigned int flow_type){ irqd_set_trigger_type(data, flow_type); return IRQ_SET_MASK_OK; }
This feels wrong. Your interrupt controller doesn't seem to support the trigger being changed, so irq_set_type would be a bit pointless. A driver trying to set a level trigger on an edge interrupt would succeed, and that is as bad as it gets. All you need is to expose the capability of the HW when you register the flow handler instead of adding a rather misleading callback.
Thanks,
M.
Signature · 1 line
Jazz is not dead, it just smell funny.
PATCH v2 28/35 MAINTAINERS: Add nds32
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
--- MAINTAINERS | 11 +++++++++++ 1 file changed, 11 insertions(+)
MAINTAINERS +11 -0
@@ -857,6 +857,17 @@ X: drivers/iio/*/adjd* F: drivers/staging/iio/*/ad* F: drivers/staging/iio/trigger/iio-trig-bfin-timer.c +ANDES ARCHITECTURE +M: Greentime Hu <[email protected]> +M: Vincent Chen <[email protected]> +T: git https://github.com/andestech/linux.git +S: Supported +F: arch/nds32 +F: Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt +F: Documentation/devicetree/bindings/nds32 +K: nds32 +N: nds32 + ANDROID CONFIG FRAGMENTS M: Rob Herring <[email protected]> S: Supported
Signature · 1 line
1.7.9.5
PATCH v2 29/35 dt-bindings: nds32 CPU Bindings
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
This patch adds nds32 CPU binding documents.
--- Documentation/devicetree/bindings/nds32/cpus.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/nds32/cpus.txt
Documentation/devicetree/bindings/nds32/cpus.txt new file +32 -0
@@ -0,0 +1,32 @@ +* Andestech Processor Binding + +This binding specifies what properties must be available in the device tree +representation of a Andestech Processor Core, which is the root node in the +tree. + +Required properties: + + - compatible: + Usage: required + Value type: <string> + Definition: should be one of: + "andestech,n13" + "andestech,n15" + "andestech,d15" + "andestech,n10" + "andestech,d10" + "andestech,nds32v3" + - device_type + Usage: required + Value type: <string> + Definition: must be "cpu" + - clock-frequency: Contains the clock frequency for CPU, in Hz. + +* Examples + +/ { + cpu { + device_type = "cpu"; + compatible = "andestech,n13", "andestech,nds32v3"; + }; +};
Signature · 1 line
1.7.9.5
Re: [PATCH v2 29/35] dt-bindings: nds32 CPU Bindings
Him
Quoted 27 lines · Greentime Hu
From: Greentime Hu <[email protected]>
This patch adds nds32 CPU binding documents.
Signed-off-by Vincent Chen <[email protected]>Signed-off-by Rick Chen <[email protected]>Signed-off-by Zong Li <[email protected]>Signed-off-by Greentime Hu <[email protected]>--- Documentation/devicetree/bindings/nds32/cpus.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/nds32/cpus.txtDocumentation/devicetree/bindings/nds32/cpus.txt new file +8
-0@@ -0,0 +1,32 @@ +* Andestech Processor Binding + +This binding specifies what properties must be available in the device tree +representation of a Andestech Processor Core, which is the root node in the +tree. + +Required properties: +
Documentation/devicetree/bindings/nds32/cpus.txt line 18
Quoted 10 lines
Documentation/devicetree/bindings/nds32/cpus.txt new file +10
-0+ - compatible: + Usage: required + Value type: <string> + Definition: should be one of: + "andestech,n13" + "andestech,n15" + "andestech,d15" + "andestech,n10" + "andestech,d10" + "andestech,nds32v3"
Are these specific parts, or architecture versions?
I guess "andestech,nds32v3" is an architecture version, and the rest are specific parts?
Documentation/devicetree/bindings/nds32/cpus.txt line 31
Quoted 13 lines
Documentation/devicetree/bindings/nds32/cpus.txt new file +13
-0+ - device_type + Usage: required + Value type: <string> + Definition: must be "cpu" + - clock-frequency: Contains the clock frequency for CPU, in Hz. + +* Examples + +/ { + cpu { + device_type = "cpu"; + compatible = "andestech,n13", "andestech,nds32v3"; + };
This is missing the required clock-frequency property.
There should be a /cpus node, with each CPU listed under that, to align with the devicetree spec. Even if you never support SMP, there's no reason to be different from other architectures.
You should have something like:
/ {
cpus {
cpu {
device_type = "cpu";
compatible = "andestech,n13";
clock-frequency = <...>;
};
};
};Thanks,
Mark.
Re: [PATCH v2 29/35] dt-bindings: nds32 CPU Bindings
2017-11-27 21:42 GMT+08:00 Mark Rutland <[email protected]>:
Quoted 43 lines
Him
Quoted 27 lines · Greentime Hu
From: Greentime Hu <greentime-MUIXKm3Oiri1Z/[email protected]>
This patch adds nds32 CPU binding documents.
Signed-off-by Vincent Chen <vincentc-MUIXKm3Oiri1Z/[email protected]>Signed-off-by Rick Chen <rick-MUIXKm3Oiri1Z/[email protected]>Signed-off-by Zong Li <zong-MUIXKm3Oiri1Z/[email protected]>Signed-off-by Greentime Hu <greentime-MUIXKm3Oiri1Z/[email protected]>--- Documentation/devicetree/bindings/nds32/cpus.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/nds32/cpus.txtDocumentation/devicetree/bindings/nds32/cpus.txt new file +8
-0@@ -0,0 +1,32 @@ +* Andestech Processor Binding + +This binding specifies what properties must be available in the device tree +representation of a Andestech Processor Core, which is the root node in the +tree. + +Required properties: +Documentation/devicetree/bindings/nds32/cpus.txt line 18
Quoted 10 lines
Documentation/devicetree/bindings/nds32/cpus.txt new file +10
-0+ - compatible: + Usage: required + Value type: <string> + Definition: should be one of: + "andestech,n13" + "andestech,n15" + "andestech,d15" + "andestech,n10" + "andestech,d10" + "andestech,nds32v3"Are these specific parts, or architecture versions?
Quoted 2 lines
I guess "andestech,nds32v3" is an architecture version, and the rest are specific parts?
Yes, nds32v3 is an architecture version and the rest are nds32v3 compatible processor's name.
Quoted 32 lines
Documentation/devicetree/bindings/nds32/cpus.txt line 31
Quoted 13 lines
Documentation/devicetree/bindings/nds32/cpus.txt new file +13
-0+ - device_type + Usage: required + Value type: <string> + Definition: must be "cpu" + - clock-frequency: Contains the clock frequency for CPU, in Hz. + +* Examples + +/ { + cpu { + device_type = "cpu"; + compatible = "andestech,n13", "andestech,nds32v3"; + };This is missing the required clock-frequency property.
There should be a /cpus node, with each CPU listed under that, to align with the devicetree spec. Even if you never support SMP, there's no reason to be different from other architectures.
You should have something like:
/ { cpus { cpu { device_type = "cpu"; compatible = "andestech,n13"; clock-frequency = <...>; }; }; };
Quoted 2 lines
Thanks,
Mark.
Thanks.
I will modify it in the next version patch.
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PATCH v2 30/35 net: faraday add nds32 support.
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
--- drivers/net/ethernet/faraday/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/net/ethernet/faraday/Kconfig +3 -3
@@ -5,7 +5,7 @@ config NET_VENDOR_FARADAY bool "Faraday devices" default y - depends on ARM + depends on ARM || NDS32 ---help--- If you have a network (Ethernet) card belonging to this class, say Y.
@@ -18,7 +18,7 @@ if NET_VENDOR_FARADAY config FTMAC100 tristate "Faraday FTMAC100 10/100 Ethernet support" - depends on ARM + depends on ARM || NDS32 select MII ---help--- This driver supports the FTMAC100 10/100 Ethernet controller
@@ -27,7 +27,7 @@ config FTMAC100 config FTGMAC100 tristate "Faraday FTGMAC100 Gigabit Ethernet support" - depends on ARM + depends on ARM || NDS32 select PHYLIB ---help--- This driver supports the FTGMAC100 Gigabit Ethernet controller
Signature · 1 line
1.7.9.5
Arnd Bergmann
maintainerRe: [PATCH v2 30/35] net: faraday add nds32 support.
Quoted 3 lines · Greentime Hu
From: Greentime Hu <[email protected]>
Signed-off-by Greentime Hu <[email protected]>
This is missing a patch description.
drivers/net/ethernet/faraday/Kconfig line 11
Quoted 13 lines
drivers/net/ethernet/faraday/Kconfig +1
-1@@ -5,7 +5,7 @@ config NET_VENDOR_FARADAY bool "Faraday devices" default y - depends on ARM + depends on ARM || NDS32 ---help--- If you have a network (Ethernet) card belonging to this class, say Y.
We probably want to make all three here
depends on ARM || NDS32 || COMPILE_TEST
Arnd
Re: [PATCH v2 30/35] net: faraday add nds32 support.
2017-11-27 22:15 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 7 lines · Greentime Hu
Quoted 3 lines
From: Greentime Hu <greentime-MUIXKm3Oiri1Z/[email protected]>
Signed-off-by Greentime Hu <greentime-MUIXKm3Oiri1Z/[email protected]>This is missing a patch description.
Thanks.
Sorry. I miss it. I will add the commit messages in the next version patch.
Quoted 16 lines
drivers/net/ethernet/faraday/Kconfig line 11
Quoted 13 lines
drivers/net/ethernet/faraday/Kconfig +1
-1@@ -5,7 +5,7 @@ config NET_VENDOR_FARADAY bool "Faraday devices" default y - depends on ARM + depends on ARM || NDS32 ---help--- If you have a network (Ethernet) card belonging to this class, say Y.We probably want to make all three here
Quoted 2 lines
depends on ARM || NDS32 ||
COMPILE_TEST
Thanks.
I will modify it in the next version patch.
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PATCH v2 31/35 earlycon: add reg-offset to physical address before mapping
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
It will get the wrong virtual address because port->mapbase is not added the correct reg-offset yet. We have to update it before earlycon_map() is called
--- drivers/tty/serial/earlycon.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
drivers/tty/serial/earlycon.c +2 -1
@@ -253,11 +253,12 @@ int __init of_setup_earlycon(const struct earlycon_id *match, } port->mapbase = addr; port->uartclk =BASE_BAUD *16 ; - port->membase =earlycon_map (port->mapbase,SZ_4K ); val =of_get_flat_dt_prop (node,"reg-offset" ,NULL );if (val) port->mapbase +=be32_to_cpu (*val); + port->membase =earlycon_map (port->mapbase,SZ_4K ); + val =of_get_flat_dt_prop (node,"reg-shift" ,NULL );if (val) port->regshift =be32_to_cpu (*val);
Signature · 1 line
1.7.9.5
Re: [PATCH v2 31/35] earlycon: add reg-offset to physical address before mapping
Quoted 8 lines · Greentime Hu
From: Greentime Hu <[email protected]>
It will get the wrong virtual address because
port->mapbaseis not added the correct reg-offset yet. We have to update it beforeearlycon_map()is called--- drivers/tty/serial/earlycon.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
No signed-off-by line?
Re: [PATCH v2 31/35] earlycon: add reg-offset to physical address before mapping
2017-11-28 22:25 GMT+08:00 Greg KH <[email protected]>:
Quoted 11 lines · Greentime Hu
Quoted 8 lines
From: Greentime Hu <[email protected]>
It will get the wrong virtual address because
port->mapbaseis not added the correct reg-offset yet. We have to update it beforeearlycon_map()is called--- drivers/tty/serial/earlycon.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)No signed-off-by line?
Sorry I forget it.
I will add it in the next version patch.
PATCH v2 32/35 asm-generic/io.h: move ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef CONFIG_MMU
In reply to Greentime HuFrom: Greentime Hu <[email protected]>
It allows some architectures to use this generic macro instead of defining theirs.
--- include/asm-generic/io.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)
include/asm-generic/io.h +9 -9
@@ -852,7 +852,16 @@ static inline void __iomem *__ioremap(phys_addr_t offset, size_t size, }#endif +#ifndef iounmap +#define iounmap iounmap + +static inline void iounmap (void __iomem *addr) +{ +} +#endif +#endif /* CONFIG_MMU */ #ifndef ioremap_nocache +void __iomem *ioremap (phys_addr_t phys_addr,size_t size);#define ioremap_nocache ioremap_nocachestatic inline void __iomem *ioremap_nocache (phys_addr_t offset,size_t size) {
@@ -884,15 +893,6 @@ static inline void __iomem *ioremap_wt(phys_addr_t offset, size_t size) }#endif -#ifndef iounmap -#define iounmap iounmap - -static inline void iounmap (void __iomem *addr) -{ -} -#endif -#endif /* CONFIG_MMU */ -#ifdef CONFIG_HAS_IOPORT_MAP #ifndef CONFIG_GENERIC_IOMAP #ifndef ioport_map
Signature · 1 line
1.7.9.5
Re: [PATCH v2 32/35] asm-generic/io.h: move ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef CONFIG_MMU
Quoted 10 lines · Greentime Hu
From: Greentime Hu <[email protected]>
It allows some architectures to use this generic macro instead of defining theirs.
Signed-off-by Vincent Chen <[email protected]>Signed-off-by Greentime Hu <[email protected]>--- include/asm-generic/io.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)
This looks good, but you probably want to do this earlier in the series, so you can build on top of this change.
Please keep this patch as part of your series,
PATCH v2 33/35 clocksource/drivers/atcpit100: Add andestech atcpit100 timer
In reply to Greentime HuFrom: Rick Chen <[email protected]>
ATCPIT100 is often used on the Andes architecture, This timer provide 4 PIT channels. Each PIT channel is a multi-function timer, can be configured as 32,16,8 bit timers or PWM as well.
For system timer it will set channel 1 32-bit timer0 as clock source and count downwards until underflow and restart again.
It also set channel 0 32-bit timer0 as clock event and count downwards until condition match. It will generate an interrupt for handling periodically.
--- drivers/clocksource/timer-atcpit100.c | 247 +++++++++++++++++++++++++++++++++ 1 file changed, 247 insertions(+) create mode 100644 drivers/clocksource/timer-atcpit100.c
drivers/clocksource/timer-atcpit100.c new file +247 -0
@@ -0,0 +1,247 @@ +/* +* Andestech ATCPIT100 Timer Device Driver Implementation +* +* Copyright (C) 2017 Andes Technology Corporation +* Rick Chen, Andes Technology Corporation <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* +*/ + +#include <linux/irq.h> +#include <linux/clocksource.h> +#include <linux/clockchips.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/cpufreq.h> +#include <linux/sched.h> +#include <linux/sched_clock.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/of_platform.h> +#include "timer-of.h" + +/* +* Definition of register offsets +*/ + +/* ID and Revision Register */ +#define ID_REV 0x0 + +/* Configuration Register */ +#define CFG 0x10 + +/* Interrupt Enable Register */ +#define INT_EN 0x14 +#define CH_INT_EN (c, i) ((1<<i)<<(4*c)) +#define CH0INT0EN 0x01 + +/* Interrupt Status Register */ +#define INT_STA 0x18 +#define CH0INT0 0x01 + +/* Channel Enable Register */ +#define CH_EN 0x1C +#define CH0TMR0EN 0x1 +#define CH1TMR0EN 0x10 + +/* Channel 0 , 1 Control Register */ +#define CH0_CTL (0x20) +#define CH1_CTL (0x20 + 0x10) + +/* Channel clock source , bit 3 , 0:External clock , 1:APB clock */ +#define APB_CLK BIT(3) + +/* Channel mode , bit 0~2 */ +#define TMR_32 0x1 +#define TMR_16 0x2 +#define TMR_8 0x3 + +/* Channel 0 , 1 Reload Register */ +#define CH0_REL (0x24) +#define CH1_REL (0x24 + 0x10) + +/* Channel 0 , 1 Counter Register */ +#define CH0_CNT (0x28) +#define CH1_CNT (0x28 + 0x10) + +#define TIMER_SYNC_TICKS 3 + +static void atcpit100_ch1_tmr0_en (void __iomem *base) +{ +writel (~0 , base +CH1_REL ); +writel (APB_CLK |TMR_32 , base +CH1_CTL ); +} + +static void atcpit100_ch0_tmr0_en (void __iomem *base) +{ +writel (APB_CLK |TMR_32 , base +CH0_CTL ); +} + +static void atcpit100_clkevt_time_setup (void __iomem *base,unsigned long delay) +{ +writel (delay, base +CH0_CNT ); +writel (delay, base +CH0_REL ); +} + +static void atcpit100_timer_clear_interrupt (void __iomem *base) +{ +u32 val; + + val =readl (base +INT_STA ); +writel (val |CH0INT0 , base +INT_STA ); +} + +static void atcpit100_clocksource_start (void __iomem *base) +{ +u32 val; + + val =readl (base +CH_EN ); +writel (val |CH1TMR0EN , base +CH_EN ); +} + +static void atcpit100_clkevt_time_start (void __iomem *base) +{ +u32 val; + + val =readl (base +CH_EN ); +writel (val |CH0TMR0EN , base +CH_EN ); +} + +static void atcpit100_clkevt_time_stop (void __iomem *base) +{ +u32 val; + +atcpit100_timer_clear_interrupt (base); + val =readl (base +CH_EN ); +writel (val & ~CH0TMR0EN , base +CH_EN ); +} + +static int atcpit100_clkevt_next_event (unsigned long evt, +struct clock_event_device *clkevt) +{ +struct timer_of *to =to_timer_of (clkevt); + +writel (evt,timer_of_base (to) +CH0_REL ); + +return 0 ; +} + +static int atcpit100_clkevt_set_periodic (struct clock_event_device *evt) +{ +struct timer_of *to =to_timer_of (evt); + +atcpit100_clkevt_time_setup (timer_of_base (to),timer_of_period (to)); +atcpit100_clkevt_time_start (timer_of_base (to)); + +return 0 ; +} +static int atcpit100_clkevt_shutdown (struct clock_event_device *evt) +{ +struct timer_of *to =to_timer_of (evt); + +atcpit100_clkevt_time_stop (timer_of_base (to)); + +return 0 ; +} +static int atcpit100_clkevt_set_oneshot (struct clock_event_device *evt) +{ +struct timer_of *to =to_timer_of (evt); +u32 val; + +writel (~0x0 ,timer_of_base (to) +CH0_REL ); + val =readl (timer_of_base (to) +CH_EN ); +writel (val |CH0TMR0EN ,timer_of_base (to) +CH_EN ); + +return 0 ; +} + +static irqreturn_t atcpit100_timer_interrupt (int irq,void *dev_id) +{ +struct clock_event_device *evt = (struct clock_event_device *)dev_id; +struct timer_of *to =to_timer_of (evt); + +atcpit100_timer_clear_interrupt (timer_of_base (to)); + + evt->event_handler (evt); + +return IRQ_HANDLED ; +} + +static struct timer_of to = { + .flags =TIMER_OF_IRQ |TIMER_OF_CLOCK |TIMER_OF_BASE , + + .clkevt = { + .name ="atcpit100_tick" , + .rating =300 , + .features =CLOCK_EVT_FEAT_PERIODIC |CLOCK_EVT_FEAT_ONESHOT , + .set_state_shutdown = atcpit100_clkevt_shutdown, + .set_state_periodic = atcpit100_clkevt_set_periodic, + .set_state_oneshot = atcpit100_clkevt_set_oneshot, + .tick_resume = atcpit100_clkevt_shutdown, + .set_next_event = atcpit100_clkevt_next_event, + .cpumask = cpu_all_mask, + }, + + .of_irq = { + .handler = atcpit100_timer_interrupt, + .flags =IRQF_TIMER |IRQF_IRQPOLL , + }, +}; + +static u64 notrace atcpit100_timer_sched_read(void) +{ +return ~readl (timer_of_base (&to) +CH1_CNT ); +} + +static int __init atcpit100_timer_init (struct device_node *node) +{ +int ret; +u32 val; +void __iomem *base; + + ret =timer_of_init (node, &to); +if (ret) +return ret; + + base =timer_of_base (&to); + +sched_clock_register (atcpit100_timer_sched_read,32 , +timer_of_rate (&to)); + + ret =clocksource_mmio_init (base +CH1_CNT , + node->name,timer_of_rate (&to),300 ,32 , + clocksource_mmio_readl_down); + +if (ret) { +pr_err ("Failed to register clocksource\n" ); +return ret; + } + +/* clear channel 0 timer0 interrupt */ +atcpit100_timer_clear_interrupt (base); + +clockevents_config_and_register (&to.clkevt,timer_of_rate (&to), +TIMER_SYNC_TICKS ,0xffffffff ); +atcpit100_ch0_tmr0_en (base); +atcpit100_ch1_tmr0_en (base); +atcpit100_clocksource_start (base); +atcpit100_clkevt_time_start (base); + +/* Enable channel 0 timer0 interrupt */ + val =readl (base +INT_EN ); +writel (val |CH0INT0EN , base +INT_EN ); + +return ret; +} + +TIMER_OF_DECLARE (atcpit100,"andestech,atcpit100" , atcpit100_timer_init);
Signature · 1 line
1.7.9.5
Re: [PATCH v2 33/35] clocksource/drivers/atcpit100: Add andestech atcpit100 timer
Quoted 10 lines · Greentime Hu
From: Rick Chen <[email protected]>
ATCPIT100 is often used on the Andes architecture, This timer provide 4 PIT channels. Each PIT channel is a multi-function timer, can be configured as 32,16,8 bit timers or PWM as well.
For system timer it will set channel 1 32-bit timer0 as clock source and count downwards until underflow and restart again.
Quoted 6 lines
It also set channel 0 32-bit timer0 as clock event and count downwards until condition match. It will generate an interrupt for handling periodically.
Signed-off-by Rick Chen <[email protected]>Signed-off-by Greentime Hu <[email protected]>
The driver looks nice overall.
Quoted 9 lines
drivers/clocksource/timer-atcpit100.c new file +9
-0+static struct timer_of to = { + .flags =TIMER_OF_IRQ |TIMER_OF_CLOCK |TIMER_OF_BASE , + + .clkevt = { + .name ="atcpit100_tick" , + .rating =300 , + .features =CLOCK_EVT_FEAT_PERIODIC |CLOCK_EVT_FEAT_ONESHOT , + .set_state_shutdown = atcpit100_clkevt_shutdown, + .set_state_periodic = atcpit100_clkevt_set_periodic,
drivers/clocksource/timer-atcpit100.c line 198
Quoted 10 lines
drivers/clocksource/timer-atcpit100.c new file +10
-0+ .set_state_oneshot = atcpit100_clkevt_set_oneshot, + .tick_resume = atcpit100_clkevt_shutdown, + .set_next_event = atcpit100_clkevt_next_event, + .cpumask = cpu_all_mask, + }, + + .of_irq = { + .handler = atcpit100_timer_interrupt, + .flags = IRQF_TIMER | IRQF_IRQPOLL, + },
I would add:
.of_clk = {
.name = "PCLK",
};To be explicit on what we use.
(I hope I understand this OF timer right.)
Otherwise it looks good!
Yours,
Linus Walleij
Re: [PATCH v2 33/35] clocksource/drivers/atcpit100: Add andestech atcpit100 timer
In reply to Greentime HuQuoted 10 lines · Greentime Hu
From: Rick Chen <[email protected]>
ATCPIT100 is often used on the Andes architecture, This timer provide 4 PIT channels. Each PIT channel is a multi-function timer, can be configured as 32,16,8 bit timers or PWM as well.
For system timer it will set channel 1 32-bit timer0 as clock source and count downwards until underflow and restart again.
Quoted 7 lines
It also set channel 0 32-bit timer0 as clock event and count downwards until condition match. It will generate an interrupt for handling periodically.
Signed-off-by Rick Chen <[email protected]>Signed-off-by Greentime Hu <[email protected]>---
Looks good.
Please resend this patch folded with the Makefile change and the DT binding (fixed) as suggested by Arnd. I will merge them.
Thanks
-- Daniel
Signature · 5 lines
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog
PATCH v2 34/35 clocksource/drivers/Kconfig: Support andestech atcpit100 timer
In reply to Greentime HuFrom: Rick Chen <[email protected]>
Add CLKSRC_ATCPIT100 for Andestech atcpit100 timer selection. It often be used in Andestech AE3XX platform.
--- drivers/clocksource/Kconfig | 6 ++++++ drivers/clocksource/Makefile | 1 + 2 files changed, 7 insertions(+)
drivers/clocksource/Kconfig +6 -0
@@ -615,4 +615,10 @@ config CLKSRC_ST_LPC Enable this option to use the Low Power controller timer as clocksource. +config CLKSRC_ATCPIT100 + bool "Clocksource for AE3XX platform" if COMPILE_TEST + depends on GENERIC_CLOCKEVENTS && HAS_IOMEM + help + This option enables support for the Andestech AE3XX platform timers. + endmenu
drivers/clocksource/Makefile +1 -0
@@ -75,3 +75,4 @@ obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o obj-$(CONFIG_H8300_TPU) += h8300_tpu.o obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o obj-$(CONFIG_X86_NUMACHIP) += numachip.o +obj-$(CONFIG_CLKSRC_ATCPIT100) += timer-atcpit100.o
Signature · 1 line
1.7.9.5
Arnd Bergmann
maintainerRe: [PATCH v2 34/35] clocksource/drivers/Kconfig: Support andestech atcpit100 timer
Quoted 7 lines · Greentime Hu
From: Rick Chen <[email protected]>
Add
CLKSRC_ATCPIT100for Andestech atcpit100 timer selection. It often be used in Andestech AE3XX platform.Signed-off-by Rick Chen <[email protected]>Signed-off-by Greentime Hu <[email protected]>
No need to split out the Makefile patch from the actual driver, they clearly belong together.
The binding change should be a separate patch, as you did.
It's probably best to separate the driver patches from the architecture submission
in the future, they can simply get merged by the respective subsystem maintainers,
with a smaller Cc list.
Arnd
Re: [PATCH v2 34/35] clocksource/drivers/Kconfig: Support andestech atcpit100 timer
2017-11-27 22:11 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 13 lines · Greentime Hu
Quoted 7 lines
From: Rick Chen <[email protected]>
Add
CLKSRC_ATCPIT100for Andestech atcpit100 timer selection. It often be used in Andestech AE3XX platform.Signed-off-by Rick Chen <[email protected]>Signed-off-by Greentime Hu <[email protected]>No need to split out the
Makefilepatch from the actual driver, they clearly belong together.
The binding change should be a separate patch, as you did.
Quoted 6 lines
It's probably best to separate the driver patches from the architecture submission
in the future, they can simply get merged by the respective subsystem maintainers,
with a smaller Cc list.
Hi, Arnd:
Thanks.
We will merge these 2 patches together in the next version patch. We will sent to clocksource subsystem with a seperate patchset. --
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Re: [PATCH v2 34/35] clocksource/drivers/Kconfig: Support andestech atcpit100 timer
Quoted 21 lines · Greentime Hu
2017-11-27 22:11 GMT+08:00 Arnd Bergmann <[email protected]>:
Quoted 13 lines · Greentime Hu
Quoted 7 lines
From: Rick Chen <[email protected]>
Add
CLKSRC_ATCPIT100for Andestech atcpit100 timer selection. It often be used in Andestech AE3XX platform.Signed-off-by Rick Chen <[email protected]>Signed-off-by Greentime Hu <[email protected]>No need to split out the
Makefilepatch from the actual driver, they clearly belong together.
The binding change should be a separate patch, as you did.Quoted 6 lines
It's probably best to separate the driver patches from the architecture submission
in the future, they can simply get merged by the respective subsystem maintainers,
with a smaller Cc list.
Quoted 5 lines
Hi, Arnd:
Thanks.
We will merge these 2 patches together in the next version patch. We will sent to clocksource subsystem with a seperate patchset.
Sounds good.
Signature · 5 lines
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog
Re: [PATCH v2 34/35] clocksource/drivers/Kconfig: Support andestech atcpit100 timer
In reply to Greentime HuQuoted 17 lines · Greentime Hu
From: Rick Chen <[email protected]>
Add
CLKSRC_ATCPIT100for Andestech atcpit100 timer selection. It often be used in Andestech AE3XX platform.Signed-off-by Rick Chen <[email protected]>Signed-off-by Greentime Hu <[email protected]>--- drivers/clocksource/Kconfig | 6 ++++++ drivers/clocksource/Makefile | 1 + 2 files changed, 7 insertions(+)drivers/clocksource/Kconfig +0
-0
drivers/clocksource/Kconfig config CLKSRC_ST_LPC · line 620
Quoted 6 lines
drivers/clocksource/Kconfig +3
-0@@ -615,4 +615,10 @@ config CLKSRC_ST_LPC Enable this option to use the Low Power controller timer as clocksource. +config CLKSRC_ATCPIT100 + bool "Clocksource for AE3XX platform" if COMPILE_TEST + depends on GENERIC_CLOCKEVENTS && HAS_IOMEM
You can remove the GENERIC_CLOCKEVENTS as now it is factored out in the higher menuconfig option.
Signature · 10 lines
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
PATCH v2 35/35 dt-bindings: timer: Add andestech atcpit100 timer binding doc
In reply to Greentime HuFrom: Rick Chen <[email protected]>
Add a document to describe Andestech atcpit100 timer and binding information.
--- .../bindings/timer/andestech,atcpit100-timer.txt | 33 ++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt
Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt new file +33 -0
@@ -0,0 +1,33 @@ +Andestech ATCPIT100 timer +------------------------------------------------------------------ +ATCPIT100 is a generic IP block from Andes Technology, embedded in +Andestech AE3XX platforms and other designs. + +This timer is a set of compact multi-function timers, which can be +used as pulse width modulators (PWM) as well as simple timers. + +It supports up to 4 PIT channels. Each PIT channel is a +multi-function timer and provide the following usage scenarios: +One 32-bit timer +Two 16-bit timers +Four 8-bit timers +One 16-bit PWM +One 16-bit timer and one 8-bit PWM +Two 8-bit timer and one 8-bit PWM + +Required properties: +- compatible : Should be "andestech,atcpit100" +- reg : Address and length of the register set +- interrupts : Reference to the timer interrupt +- clocks : a clock to provide the tick rate for "andestech,atcpit100" +- clock-names : should be "PCLK" for the external tick timer. + +Examples: + +timer0: timer@f0400000 { + compatible = "andestech,atcpit100"; + reg = <0xf0400000 0x1000>; + interrupts = <2 4>; + clocks = <&clk_pll>; + clock-names = "PCLK"; +};
Signature · 1 line
1.7.9.5
Re: [PATCH v2 35/35] dt-bindings: timer: Add andestech atcpit100 timer binding doc
Quoted 8 lines · Greentime Hu
From: Rick Chen <[email protected]>
Add a document to describe Andestech atcpit100 timer and binding information.
Signed-off-by Rick Chen <[email protected]>Acked-by Rob Herring <[email protected]>Signed-off-by Greentime Hu <[email protected]>
Thanks for submitting this interesting architecture!
(...)
Quoted 6 lines
+Required properties:
+- compatible : Should be "andestech,atcpit100" +- reg : Address and length of the register set +- interrupts : Reference to the timer interrupt +- clocks : a clock to provide the tick rate for "andestech,atcpit100" +- clock-names : should be "PCLK" for the external tick timer.
This text seem wrong. PCLK is the internal timer, right? "PCLK" is "peripheral clock" (I hope) and that comes from the bus.
Consider also adding an optional "EXTCLK" already now, since it is evident from the driver that this is also supported.
Yours,
Linus Walleij
Re: [PATCH v2 35/35] dt-bindings: timer: Add andestech atcpit100 timer binding doc
2017-12-01 20:19 GMT+08:00 Linus Walleij <[email protected]>:
Quoted 22 lines · Greentime Hu
Quoted 9 lines
From: Rick Chen <[email protected]>
Add a document to describe Andestech atcpit100 timer and binding information.
Signed-off-by Rick Chen <[email protected]>Acked-by Rob Herring <[email protected]>Signed-off-by Greentime Hu <[email protected]>Thanks for submitting this interesting architecture!
(...)
Quoted 6 lines
+Required properties:
+- compatible : Should be "andestech,atcpit100" +- reg : Address and length of the register set +- interrupts : Reference to the timer interrupt +- clocks : a clock to provide the tick rate for "andestech,atcpit100" +- clock-names : should be "PCLK" for the external tick timer.
Quoted 6 lines
This text seem wrong. PCLK is the internal timer, right? "PCLK" is "peripheral clock" (I hope) and that comes from the bus.
Consider also adding an optional "EXTCLK" already now, since it is evident from the driver that this is also supported.
Thank you for reviewing !
I will modify it in the next patch.
Rick
Quoted 2 lines
Yours,
Linus Walleij