irqchip: qcom: add support for PDC interrupt controller
Subsystems (3)
v6 cover irqchip: qcom: add support for PDC interrupt controller
Changes since v5:
- Fixed comment style of SPDX
Changes since v4:
- Code clean up as suggested by Marc
On newer Qualcomm Techonologies Inc's SoCs like the SDM845, the GIC is in a power domain that can be powered off when not needed. Interrupts that need to be sensed even when the GIC is powered off, are routed through an interrupt controller in an always-on domain called the Power Domain Controller a.k.a PDC. This series adds support for the PDC's interrupt controller.
Please consider reviewing these patches.
RFC v1: https://patchwork.kernel.org/patch/10180857/
RFC v2: https://www.mail-archive.com/[email protected]/msg1600634.html
v3: https://lkml.org/lkml/2018/2/6/595
v4: https://www.spinics.net/lists/linux-arm-msm/msg32906.html
Lina Iyer (2):
drivers: irqchip: pdc: Add PDC interrupt controller for QCOM SoCs dt-bindings/interrupt-controller: pdc: descibe PDC device binding
.../bindings/interrupt-controller/qcom,pdc.txt | 78 +++++ drivers/irqchip/Kconfig | 9 + drivers/irqchip/Makefile | 1 + drivers/irqchip/qcom-pdc.c | 314 +++++++++++++++++++++ 4 files changed, 402 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt create mode 100644 drivers/irqchip/qcom-pdc.c
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v6 1/2 drivers: irqchip: pdc: Add PDC interrupt controller for QCOM SoCs
Quoted 1 line
From : Archana Sathyakumar <[email protected]>
The Power Domain Controller (PDC) on QTI SoCs like SDM845 houses an interrupt controller along with other domain control functions to handle interrupt related functions like handle falling edge or active low which are not detected at the GIC and handle wakeup interrupts.
The interrupt controller is on an always-on domain for the purpose of waking up the processor. Only a subset of the processor's interrupts are routed through the PDC to the GIC. The PDC powers on the processors' domain, when in low power mode and replays pending interrupts so the GIC may wake up the processor.
--- drivers/irqchip/Kconfig | 9 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/qcom-pdc.c | 314 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 324 insertions(+) create mode 100644 drivers/irqchip/qcom-pdc.c
drivers/irqchip/Kconfig +9 -0
@@ -343,4 +343,13 @@ config MESON_IRQ_GPIO help Support Meson SoC Family GPIO Interrupt Multiplexer +config QCOM_PDC + bool "QCOM PDC" + depends on ARCH_QCOM + select IRQ_DOMAIN + select IRQ_DOMAIN_HIERARCHY + help + Power Domain Controller driver to manage and configure wakeup + IRQs for Qualcomm Technologies Inc (QTI) mobile chips. + endmenu
drivers/irqchip/Makefile +1 -0
@@ -84,3 +84,4 @@ obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o obj-$(CONFIG_IRQ_UNIPHIER_AIDET) += irq-uniphier-aidet.o obj-$(CONFIG_ARCH_SYNQUACER) += irq-sni-exiu.o obj-$(CONFIG_MESON_IRQ_GPIO) += irq-meson-gpio.o +obj-$(CONFIG_QCOM_PDC) += qcom-pdc.o
drivers/irqchip/qcom-pdc.c new file +314 -0
314 lines not on this page · raw message
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH v6 1/2] drivers: irqchip: pdc: Add PDC interrupt controller for QCOM SoCs
Quoted 12 lines · Lina Iyer
drivers/irqchip/qcom-pdc.c new file +12
-0+/* +* GIC does not handle falling edge or active low. To allow falling edge and +* active low interrupts to be handled at GIC, PDC has an inverter that inverts +* falling edge into a rising edge and active low into an active high. +* For the inverter to work, the polarity bit in the IRQ_CONFIG register has to +* set as per the table below. +* (polarity, falling edge, rising edge ) POLARITY +* 3'b0 00 Level sensitive active low LOW +* 3'b0 01 Rising edge sensitive NOT USED +* 3'b0 10 Falling edge sensitive LOW +* 3'b0 11 Dual Edge sensitive NOT USED +* 3'b1 00 Level sensitive active High HIGH
drivers/irqchip/qcom-pdc.c line 99
Quoted 10 lines
drivers/irqchip/qcom-pdc.c new file +10
-0+* 3'b1 01 Falling Edge sensitive NOT USED +* 3'b1 10 Rising edge sensitive HIGH +* 3'b1 11 Dual Edge sensitive HIGH +*/ +enum pdc_irq_config_bits { +PDC_POLARITY_LOW =0 , +PDC_FALLING_EDGE =2 , +PDC_POLARITY_HIGH =4 , +PDC_RISING_EDGE =6 , +PDC_DUAL_EDGE =7 ,
My previous comment about using binary constants still stands. Please either address review comments or reply at least. Ignoring reviews is not an option.
Aside of that I really have to ask about the naming of these constants. Are these names hardware register nomenclature? If yes, they are disgusting. If no, they are still disgusting, but should be changed to sensible ones, which just match the IRQ_TYPE naming convention.
PDC_LEVEL_LOW = 000b,
PDC_EDGE_FALLING = 010b,
....drivers/irqchip/qcom-pdc.c line 121
Quoted 4 lines
drivers/irqchip/qcom-pdc.c new file +4
-0+switch (type) { +case IRQ_TYPE_EDGE_RISING : + pdc_type =PDC_RISING_EDGE ; + type =IRQ_TYPE_EDGE_RISING ;
Whats the point of assigning the same value again?
drivers/irqchip/qcom-pdc.c line 132
Quoted 11 lines
drivers/irqchip/qcom-pdc.c new file +11
-0+break ; +case IRQ_TYPE_EDGE_FALLING : + pdc_type =PDC_FALLING_EDGE ; + type =IRQ_TYPE_EDGE_RISING ; +break ; +case IRQ_TYPE_EDGE_BOTH : + pdc_type =PDC_DUAL_EDGE ; +break ; +case IRQ_TYPE_LEVEL_HIGH : + pdc_type =PDC_POLARITY_HIGH ; + type =IRQ_TYPE_LEVEL_HIGH ;
Ditto
Thanks,
tglx
Re: [PATCH v6 1/2] drivers: irqchip: pdc: Add PDC interrupt controller for QCOM SoCs
Quoted 19 lines · Thomas Gleixner
Quoted 18 lines · Lina Iyer
drivers/irqchip/qcom-pdc.c new file +18
-0+/* +* GIC does not handle falling edge or active low. To allow falling edge and +* active low interrupts to be handled at GIC, PDC has an inverter that inverts +* falling edge into a rising edge and active low into an active high. +* For the inverter to work, the polarity bit in the IRQ_CONFIG register has to +* set as per the table below. +* (polarity, falling edge, rising edge ) POLARITY +* 3'b0 00 Level sensitive active low LOW +* 3'b0 01 Rising edge sensitive NOT USED +* 3'b0 10 Falling edge sensitive LOW +* 3'b0 11 Dual Edge sensitive NOT USED +* 3'b1 00 Level sensitive active High HIGH +* 3'b1 01 Falling Edge sensitive NOT USED +* 3'b1 10 Rising edge sensitive HIGH +* 3'b1 11 Dual Edge sensitive HIGH +*/ +enum pdc_irq_config_bits { +PDC_POLARITY_LOW =0 ,
Quoted 9 lines
drivers/irqchip/qcom-pdc.c line 99
Quoted 4 lines
drivers/irqchip/qcom-pdc.c new file +4
-0+PDC_FALLING_EDGE =2 , +PDC_POLARITY_HIGH =4 , +PDC_RISING_EDGE =6 , + PDC_DUAL_EDGE = 7,My previous comment about using binary constants still stands. Please either address review comments or reply at least. Ignoring reviews is not an option.
I removed them from the enum definitions. Will remove them from the comments as well. Sorry. It was not my intention to ignore any review comments.
Quoted 10 lines
Aside of that I really have to ask about the naming of these constants. Are these names hardware register nomenclature? If yes, they are disgusting. If no, they are still disgusting, but should be changed to sensible ones, which just match the
IRQ_TYPEnaming convention.PDC_LEVEL_LOW = 000b, PDC_EDGE_FALLING = 010b, ....
They are named that way in spec :) Will change.
Quoted 7 lines
drivers/irqchip/qcom-pdc.c line 121
Quoted 4 lines
drivers/irqchip/qcom-pdc.c new file +4
-0+switch (type) { +case IRQ_TYPE_EDGE_RISING : + pdc_type =PDC_RISING_EDGE ; + type =IRQ_TYPE_EDGE_RISING ;Whats the point of assigning the same value again?
Failed to notice. Will fix.
Thanks,
Lina
Quoted 17 lines
drivers/irqchip/qcom-pdc.c line 132
Quoted 11 lines
drivers/irqchip/qcom-pdc.c new file +11
-0+break ; +case IRQ_TYPE_EDGE_FALLING : + pdc_type =PDC_FALLING_EDGE ; + type =IRQ_TYPE_EDGE_RISING ; +break ; +case IRQ_TYPE_EDGE_BOTH : + pdc_type =PDC_DUAL_EDGE ; +break ; +case IRQ_TYPE_LEVEL_HIGH : + pdc_type =PDC_POLARITY_HIGH ; + type =IRQ_TYPE_LEVEL_HIGH ;Ditto
Thanks,
tglx
Re: [PATCH v6 1/2] drivers: irqchip: pdc: Add PDC interrupt controller for QCOM SoCs
In reply to Thomas GleixnerQuoted 12 lines · Thomas Gleixner
drivers/irqchip/qcom-pdc.c line 99
Quoted 6 lines · Lina Iyer
drivers/irqchip/qcom-pdc.c new file +6
-0+enum pdc_irq_config_bits { +PDC_POLARITY_LOW =0 , +PDC_FALLING_EDGE =2 , +PDC_POLARITY_HIGH =4 , +PDC_RISING_EDGE =6 , +PDC_DUAL_EDGE =7 ,My previous comment about using binary constants still stands. Please either address review comments or reply at least. Ignoring reviews is not an option.
Quoted 10 lines
Aside of that I really have to ask about the naming of these constants. Are these names hardware register nomenclature? If yes, they are disgusting. If no, they are still disgusting, but should be changed to sensible ones, which just match the
IRQ_TYPEnaming convention.PDC_LEVEL_LOW = 000b, PDC_EDGE_FALLING = 010b, ....
Checkpatch doesn't like binary constants. I guess I will need to keep the enum definitions in hex or decimal. I will remove the binary from the comments though.
commit 95e2c6023b0e4c8499fb521697f79215f69135fe
Author: Joe Perches <[email protected]> Date: Wed Jul 3 15:05:20 2013 -0700
checkpatch: warn when using gcc's binary constant ("0b") extension
The gcc extension for binary constants that start with 0b is only supported with gcc version 4.3 or higher.
The kernel can still be compiled with earlier versions of gcc, so have checkpatch emit a warning for these constants.
Restructure checkpatch's constant finding code a bit to support finding these binary constants.
Thanks,
Lina
Re: [PATCH v6 1/2] drivers: irqchip: pdc: Add PDC interrupt controller for QCOM SoCs
Quoted 18 lines · Lina Iyer
Quoted 17 lines · Thomas Gleixner
drivers/irqchip/qcom-pdc.c line 99
Quoted 6 lines · Lina Iyer
drivers/irqchip/qcom-pdc.c new file +6
-0+enum pdc_irq_config_bits { +PDC_POLARITY_LOW =0 , +PDC_FALLING_EDGE =2 , +PDC_POLARITY_HIGH =4 , +PDC_RISING_EDGE =6 , +PDC_DUAL_EDGE =7 ,My previous comment about using binary constants still stands. Please either address review comments or reply at least. Ignoring reviews is not an option.
Aside of that I really have to ask about the naming of these constants. Are these names hardware register nomenclature? If yes, they are disgusting. If no, they are still disgusting, but should be changed to sensible ones, which just match the
IRQ_TYPEnaming convention.
Quoted 8 lines
Quoted 5 lines
PDC_LEVEL_LOW = 000b, PDC_EDGE_FALLING = 010b, ....Checkpatch doesn't like binary constants. I guess I will need to keep the enum definitions in hex or decimal. I will remove the binary from the comments though.
Well checkpatch is not always right.
Quoted 9 lines
commit
95e2c6023b0e4c8499fb521697f79215f69135feAuthor: Joe Perches <[email protected]> Date: Wed Jul 3 15:05:20 2013 -0700checkpatch: warn when using gcc's binary constant ("0b") extension
The gcc extension for binary constants that start with 0b is only supported with gcc version 4.3 or higher.
Can anything of this be compiled with gcc < 4.3?
Thanks,
tglx
Re: [PATCH v6 1/2] drivers: irqchip: pdc: Add PDC interrupt controller for QCOM SoCs
Quoted 35 lines · Thomas Gleixner
Quoted 18 lines · Lina Iyer
Quoted 17 lines · Thomas Gleixner
drivers/irqchip/qcom-pdc.c line 99
Quoted 6 lines · Lina Iyer
drivers/irqchip/qcom-pdc.c new file +6
-0+enum pdc_irq_config_bits { +PDC_POLARITY_LOW =0 , +PDC_FALLING_EDGE =2 , +PDC_POLARITY_HIGH =4 , +PDC_RISING_EDGE =6 , +PDC_DUAL_EDGE =7 ,My previous comment about using binary constants still stands. Please either address review comments or reply at least. Ignoring reviews is not an option.
Aside of that I really have to ask about the naming of these constants. Are these names hardware register nomenclature? If yes, they are disgusting. If no, they are still disgusting, but should be changed to sensible ones, which just match the
IRQ_TYPEnaming convention.Quoted 8 lines
Quoted 5 lines
PDC_LEVEL_LOW = 000b, PDC_EDGE_FALLING = 010b, ....Checkpatch doesn't like binary constants. I guess I will need to keep the enum definitions in hex or decimal. I will remove the binary from the comments though.
Well checkpatch is not always right.
Quoted 5 lines
commit
95e2c6023b0e4c8499fb521697f79215f69135feAuthor: Joe Perches <[email protected]> Date: Wed Jul 3 15:05:20 2013 -0700
Quoted 7 lines
Quoted 4 lines
checkpatch: warn when using gcc's binary constant ("0b") extension
The gcc extension for binary constants that start with 0b is only supported with gcc version 4.3 or higher.
Can anything of this be compiled with gcc < 4.3?
I don't see a reason why this would be compiled with a older GCC. I am okay with ignoring the checkpatch errors. I was just not sure if I should.
Thanks,
Lina
PATCH v6 2/2 dt-bindings/interrupt-controller: pdc: descibe PDC device binding
In reply to Lina IyerFrom: Archana Sathyakumar <[email protected]>
Add device binding documentation for the PDC Interrupt controller on QCOM SoC's like the SDM845. The interrupt-controller can be used to sense edge low interrupts and wakeup interrupts when the GIC is non-operational.
--- .../bindings/interrupt-controller/qcom,pdc.txt | 78 ++++++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt new file +78 -0
@@ -0,0 +1,78 @@ +PDC interrupt controller + +Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a +Power Domain Controller (PDC) that is on always-on domain. In addition to +providing power control for the power domains, the hardware also has an +interrupt controller that can be used to help detect edge low interrupts as +well detect interrupts when the GIC is non-operational. + +GIC is parent interrupt controller at the highest level. Platform interrupt +controller PDC is next in hierarchy, followed by others. Drivers requiring +wakeup capabilities of their device interrupts routed through the PDC, must +specify PDC as their interrupt controller and request the PDC port associated +with the GIC interrupt. See example below. + +Properties: + +- compatible: + Usage: required + Value type: <string> + Definition: Should contain "qcom,<soc>-pdc" + - "qcom,sdm845-pdc": For SDM845 + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: Specifies the base physical address for PDC hardware. + +- interrupt-cells: + Usage: required + Value type: <u32> + Definition: Specifies the number of cells needed to encode an interrupt + source. + Must be 2. + The first element of the tuple is the PDC pin for the + interrupt. + The second element is the trigger type. + +- interrupt-parent: + Usage: required + Value type: <phandle> + Definition: Specifies the interrupt parent necessary for hierarchical + domain to operate. + +- interrupt-controller: + Usage: required + Value type: <bool> + Definition: Identifies the node as an interrupt controller. + +- qcom,pdc-ranges: + Usage: required + Value type: <u32 array> + Definition: Specifies the PDC pin offset and the number of PDC ports. + The tuples indicates the valid mapping of valid PDC ports + and their hwirq mapping. + The first element of the tuple is the starting PDC port. + The second element is the GIC hwirq number for the PDC port. + The third element is the number of interrupts in sequence. + +Example: + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sdm845-pdc"; + reg = <0xb220000 0x30000>; + qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + +DT binding of a device that wants to use the GIC SPI 514 as a wakeup +interrupt, must do - + + wake-device { + interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>; + }; + +In this case interrupt 514 would be mapped to port 2 on the PDC as defined by +the qcom,pdc-ranges property.
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH v6 2/2] dt-bindings/interrupt-controller: pdc: descibe PDC device binding
Quoted 7 lines · Lina Iyer
From: Archana Sathyakumar <[email protected]>
Add device binding documentation for the PDC Interrupt controller on QCOM SoC's like the SDM845. The interrupt-controller can be used to sense edge low interrupts and wakeup interrupts when the GIC is non-operational.
Quoted 7 lines
Signed-off-by Archana Sathyakumar <[email protected]>Signed-off-by Lina Iyer <[email protected]>--- .../bindings/interrupt-controller/qcom,pdc.txt | 78 ++++++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt