Restore ULPI USB on Tegra20

Muxing of pins MCLK1/2 determine the muxing of the corresponding clocks. Make pinctrl driver to provide clock muxes for the CDEV1/2 pingroups, so that main clk-controller driver could get an actual parent clock for the CDEV1/2 clocks.

Signed-off-by Dmitry Osipenko <[email protected]>

Reviewed-by Marcel Ziswiler <[email protected]>

Tested-by Marcel Ziswiler <[email protected]>

Tested-by Marc Dietrich <[email protected]>

Acked-by Peter De Schrijver <[email protected]>

---

v2: This patch is factored out from the v1 clk/DT series so that it could be
applied separately.

Quoted 12 lines · Dmitry Osipenko

Muxing of pins MCLK1/2 determine the muxing of the corresponding clocks. Make pinctrl driver to provide clock muxes for the CDEV1/2 pingroups, so that main clk-controller driver could get an actual parent clock for the CDEV1/2 clocks.

Signed-off-by Dmitry Osipenko <[email protected]>

Reviewed-by Marcel Ziswiler <[email protected]>

Tested-by Marcel Ziswiler <[email protected]>

Tested-by Marc Dietrich <[email protected]>

Acked-by Peter De Schrijver <[email protected]>

---

Quoted 2 lines

v2: This patch is factored out from the v1 clk/DT series so that it could be
applied separately.

Patch applied unless Stephen W protests.
Please include swarren on future patches to this driver.

CDEV1 and CDEV2 clocks are a bit special case, their parent clock is created by the pinctrl driver. It should be possible for clk user to request these clocks before pinctrl driver got probed and hence user will get an orphaned clock. That might be undesirable because user expects parent clock to be enabled by the child, so let's return EPROBE_DEFER until parent clock appear.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 drivers/clk/tegra/clk.c | 34 +++++++++++++++++++++++++++++++++-
 1 file changed, 33 insertions(+), 1 deletion(-)

drivers/clk/tegra/clk.c +22 -0

index ba923f0d5953..04cbe7e9eff3 100644
@@ -298,6 +298,38 @@ static struct reset_controller_dev rst_ctlr = {
 	.of_reset_n_cells = 1,
 };
 
+static struct clk *tegra_of_clk_src_onecell_get(struct of_phandle_args *clkspec,
+						void *data)
+{
+	struct clk_hw *parent_hw;
+	struct clk_hw *hw;
+	struct clk *clk;
+	const char *name;
+
+	clk = of_clk_src_onecell_get(clkspec, data);
+	if (IS_ERR(clk))
+		return clk;
+
+	name = __clk_get_name(clk);
+
+	/*
+	 * Tegra20 CDEV1 and CDEV2 clocks are a bit special case, their parent
+	 * clock is created by the pinctrl driver. It is possible for clk user
+	 * to request these clocks before pinctrl driver got probed and hence
+	 * user will get an orphaned clock. That might be undesirable because
+	 * user may expect parent clock to be enabled by the child.
+	 */
+	if (!strcmp(name, "cdev1") || !strcmp(name, "cdev2")) {

drivers/clk/tegra/clk.c +1 -1

 void __init tegra_add_of_provider(struct device_node *np)
 {
 	int i;

@@ -314,7 +346,7 @@ void __init tegra_add_of_provider(struct device_node *np)
 
 	clk_data.clks = clks;
 	clk_data.clk_num = clk_num;
-	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+	of_clk_add_provider(np, tegra_of_clk_src_onecell_get, &clk_data);
 
 	rst_ctlr.of_node = np;
 	rst_ctlr.nr_resets = periph_banks * 32 + num_special_reset;

Signature · 1 line

2.17.0

Commit 4c9a27a6c66d ("ARM: tegra: Fix ULPI regression on Tegra20") changed "ulpi-link" clock from CDEV2 to PLL_P_OUT4. Turned out that PLL_P_OUT4 is the parent of CDEV2 clock and original clock setup of "ulpi-link" was correct. The reverted patch was fixing USB for one board and broke the other, now Tegra's clk driver correctly sets parent for the CDEV2 clock and hence patch could be reverted safely, restoring USB for all of the boards.

Signed-off-by Dmitry Osipenko <[email protected]>

Reviewed-by Marcel Ziswiler <[email protected]>

Tested-by Marcel Ziswiler <[email protected]>

Tested-by Marc Dietrich <[email protected]>

---
 arch/arm/boot/dts/tegra20.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Quoted 8 lines · Dmitry Osipenko

Commit 4c9a27a6c66d ("ARM: tegra: Fix ULPI regression on Tegra20") changed "ulpi-link" clock from CDEV2 to PLL_P_OUT4. Turned out that PLL_P_OUT4 is the parent of CDEV2 clock and original clock setup of "ulpi-link" was correct. The reverted patch was fixing USB for one board and broke the other, now Tegra's clk driver correctly sets parent for the CDEV2 clock and hence patch could be reverted safely, restoring USB for all of the boards.

Quoted 7 lines

Signed-off-by Dmitry Osipenko <[email protected]>

Reviewed-by Marcel Ziswiler <[email protected]>

Tested-by Marcel Ziswiler <[email protected]>

Tested-by Marc Dietrich <[email protected]>

---
 arch/arm/boot/dts/tegra20.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Is it still true that this patch alone fixes the known regression? I'm just asking because the remainder of the series, even though it sounds to be the right thing to do, is fairly big for a fix against v4.17.

So if this alone fixes the regression I think it'd be best to queue it up for v4.17 and get the rest of the patches into v4.18.

Hello,

This series of patches fixes ULPI USB on Tegra20. The original problem
was reported by Marcel Ziswiler, he found that "ulpi-link" clock was incorrectly set to CDEV2 instead of PLL_P_OUT4. Marcel made a patch that changed the "ulpi-link" clock to PLL_P_OUT4 and that fixed issue with the USB for the devices that have CDEV2 being enabled by bootloader.
The patch got into the kernel and later Marc Dietrich found that USB stopped working on the "paz00" Tegra20 board. After a bit of discussion
was revealed that PLL_P_OUT4 is the parent clock of the CDEV2 and clock
driver was setting CDEV2's parent incorrectly. The parent clock is actually
determined by the pinmuxing config of CDEV2 pingroup. This patchset fixes
the parent of CDEV2 clock by making Tegra's pinctrl driver a clock provider,
providing CDEV1/2 clock muxes (thanks to Peter De Schrijver for the suggestion), and then setting these clock muxes as parents for the CDEV1/2
clocks. In the end Marcel's CDEV2->PLL_P_OUT4 change is reverted since CDEV2
(aka MCLK2) is the actual clock source for "ulpi-link".

Changelog:

v2:
- Added new patch "Add quirk for getting CDEV1/2 clocks",
assuring
that clk user won't get CDEV1/2 clocks until parent clk muxes are available, i.e. resolves potential issue with CDEV-user
driver
vs pinctrl driver probe order.

- Factored out "pinctrl" patch from the patchset as was
requested by
Linus Walleij.

- Addressed v1 review comments: fixed swapped DEV1/2 clk div
bits,
made DEV1/2 divs read-only, etc minor changes.

Dmitry Osipenko (4):
clk: tegra20: Add DEV1/DEV2 OSC dividers
clk: tegra20: Correct parents of CDEV1/2 clocks
clk: tegra: Add quirk for getting CDEV1/2 clocks
ARM: dts: tegra20: Revert "Fix ULPI regression on Tegra20"

 arch/arm/boot/dts/tegra20.dtsi  |  2 +-
 drivers/clk/tegra/clk-tegra20.c | 20 +++++++++++++++----
 drivers/clk/tegra/clk.c         | 34
++++++++++++++++++++++++++++++++-
 3 files changed, 50 insertions(+), 6 deletions(-)

Hi Dmitry

Quoted 51 lines · Dmitry Osipenko

Hello,

This series of patches fixes ULPI USB on Tegra20. The original problem
was reported by Marcel Ziswiler, he found that "ulpi-link" clock was incorrectly set to CDEV2 instead of PLL_P_OUT4. Marcel made a patch that changed the "ulpi-link" clock to PLL_P_OUT4 and that fixed issue with the USB for the devices that have CDEV2 being enabled by bootloader.
The patch got into the kernel and later Marc Dietrich found that USB stopped working on the "paz00" Tegra20 board. After a bit of discussion
was revealed that PLL_P_OUT4 is the parent clock of the CDEV2 and clock
driver was setting CDEV2's parent incorrectly. The parent clock is actually
determined by the pinmuxing config of CDEV2 pingroup. This patchset fixes
the parent of CDEV2 clock by making Tegra's pinctrl driver a clock provider,
providing CDEV1/2 clock muxes (thanks to Peter De Schrijver for the suggestion), and then setting these clock muxes as parents for the CDEV1/2
clocks. In the end Marcel's CDEV2->PLL_P_OUT4 change is reverted since CDEV2
(aka MCLK2) is the actual clock source for "ulpi-link".

Changelog:

v2:
- Added new patch "Add quirk for getting CDEV1/2 clocks",
assuring
that clk user won't get CDEV1/2 clocks until parent clk muxes are available, i.e. resolves potential issue with CDEV-user
driver
vs pinctrl driver probe order.

- Factored out "pinctrl" patch from the patchset as was
requested by
Linus Walleij.

- Addressed v1 review comments: fixed swapped DEV1/2 clk div
bits,
made DEV1/2 divs read-only, etc minor changes.

Dmitry Osipenko (4):
clk: tegra20: Add DEV1/DEV2 OSC dividers
clk: tegra20: Correct parents of CDEV1/2 clocks
clk: tegra: Add quirk for getting CDEV1/2 clocks
ARM: dts: tegra20: Revert "Fix ULPI regression on Tegra20"

Quoted 5 lines

 arch/arm/boot/dts/tegra20.dtsi  |  2 +-
 drivers/clk/tegra/clk-tegra20.c | 20 +++++++++++++++----
 drivers/clk/tegra/clk.c         | 34
++++++++++++++++++++++++++++++++-
 3 files changed, 50 insertions(+), 6 deletions(-)

Beautiful (;-p).

root@colibri-t20:~# cat /sys/kernel/debug/clk/clk_summary | grep -E
'pll_p_out4|cdev2'
          pll_p_out4_div              1        1        0    24000000  
        0 0  
             pll_p_out4               2        2        0    24000000  
        0 0  
                cdev2_mux             1        1        0    24000000  
        0 0  
                   cdev2              1        1        0    24000000  
        0 0  

You may add my reviewed and tested bys to the remaining patches as well.

Thanks!