Restore ULPI USB on Tegra20
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b4 am [email protected]Versions newest first · linked by author and title
- v3 Latest4 patches 2 repliesIn review
- v24 patches 5 repliesSuperseded
- v14 patches 17 repliesSuperseded
Changes in v3 from the cover letter
- Use clk DT ID's instead of comparing clk names and make custom of_src_onecell_get specific to Tegra20 clk provider in the "Add quirk for getting CDEV1/2 clocks on Tegra20" patch as was suggested by Peter De Schrijver for v2.
Patches in v3 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/4 | clk: tegra20: Add DEV1/DEV2 OSC dividersdrivers/ | +14 | 0 replies | |
| 2/4 | clk: tegra20: Correct parents of CDEV1/2 clocksdrivers/ | +2 | 0 replies | |
| 3/4 | clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20drivers/ drivers/ drivers/ +4 more | +39 | 1 reply | |
| 4/4 | ARM: dts: tegra20: Revert "Fix ULPI regression on Tegra20"arch/ | +1 | 0 replies |
Reviews trailers per patch
All 4 patches have a Reviewed-by or Acked-by of their own; the series has one for all of them.
| Patch | Marcel Ziswiler | Marc Dietrich | Peter De Schrijver | Stephen Boyd | Thierry Reding |
|---|---|---|---|---|---|
| Series | R-b T-b | T-b | A-b | A-b | |
| 1/4 | R-b T-b | T-b | A-b | A-b | |
| 2/4 | R-b T-b | T-b | A-b | A-b | |
| 3/4 | A-b | ||||
| 4/4 | R-b T-b | T-b |
Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes. Scroll the table sideways for all 5 reviewers.
Cover letter [PATCH v3 0/4] Restore ULPI USB on Tegra20
Hello,
This series of patches fixes ULPI USB on Tegra20. The original problem was reported by Marcel Ziswiler, he found that "ulpi-link" clock was incorrectly set to CDEV2 instead of PLL_P_OUT4. Marcel made a patch that changed the "ulpi-link" clock to PLL_P_OUT4 and that fixed issue with the USB for the devices that have CDEV2 being enabled by bootloader. The patch got into the kernel and later Marc Dietrich found that USB stopped working on the "paz00" Tegra20 board. After a bit of discussion was revealed that PLL_P_OUT4 is the parent clock of the CDEV2 and clock driver was setting CDEV2's parent incorrectly. The parent clock is actually determined by the pinmuxing config of CDEV2 pingroup. This patchset fixes the parent of CDEV2 clock by making Tegra's pinctrl driver a clock provider, providing CDEV1/2 clock muxes (thanks to Peter De Schrijver for the suggestion), and then setting these clock muxes as parents for the CDEV1/2 clocks. In the end Marcel's CDEV2->PLL_P_OUT4 change is reverted since CDEV2 (aka MCLK2) is the actual clock source for "ulpi-link".
Changelog:
v3:
- Use clk DT ID's instead of comparing clk names and make custom of_src_onecell_get specific to Tegra20 clk provider in the "Add quirk for getting CDEV1/2 clocks on Tegra20" patch as was suggested by Peter De Schrijver for v2.
v2:
- Added new patch "Add quirk for getting CDEV1/2 clocks", assuring that clk user won't get CDEV1/2 clocks until parent clk muxes are available, i.e. resolves potential issue with CDEV-user driver vs pinctrl driver probe order.
- Factored out "pinctrl" patch from the patchset as was requested by Linus Walleij.
- Addressed v1 review comments: fixed swapped DEV1/2 clk div bits, made DEV1/2 divs read-only, etc minor changes.
Dmitry Osipenko (4):
clk: tegra20: Add DEV1/DEV2 OSC dividers
clk: tegra20: Correct parents of CDEV1/2 clocks
clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20
ARM: dts: tegra20: Revert "Fix ULPI regression on Tegra20"
arch/arm/boot/dts/tegra20.dtsi | 2 +- drivers/clk/tegra/clk-tegra114.c | 2 +- drivers/clk/tegra/clk-tegra124.c | 2 +- drivers/clk/tegra/clk-tegra20.c | 52 +++++++++++++++++++++++++++++--- drivers/clk/tegra/clk-tegra210.c | 2 +- drivers/clk/tegra/clk-tegra30.c | 2 +- drivers/clk/tegra/clk.c | 5 +-- drivers/clk/tegra/clk.h | 2 +- 8 files changed, 56 insertions(+), 13 deletions(-)
Signature · 1 line
2.17.0