Skip to contentSkip to conversation

clk: davinci: pll-dm355: fix SYSCLKn parent names

PATCH In review David Lechner 2 participants 5 messages May 9, 2018 – May 10, 2018

Subsystems (2)
Common clk TI DaVinci series clock driver
lore
Share & tools
lore

David Lechner

author maintainer
#0 lore raw

v3 cover clk: davinci: pll-dm355: fix SYSCLKn parent names

v3 changes:
* swap order of patches

v2 changes:
* add new patch to remove non-existent PLL2 SYSCLK2

David Lechner (2):
clk: davinci: pll-dm355: drop pll2_sysclk2
clk: davinci: pll-dm355: fix SYSCLKn parent names

 drivers/clk/davinci/pll-dm355.c | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)
Signature · 1 line
2.17.0
author maintainer
#1 lore raw

PATCH v3 1/2 clk: davinci: pll-dm355: drop pll2_sysclk2

This removes pll2_sysclk2 from the TI DM355 clock driver. This SoC doesn't have such a clock. Also, SYSCLK_ALWAYS_ENABLED is transferred to pll2_sysclk1 since it drives the DDR and doesn't have another mechanism to keep it on.

Reported-by Sekhar Nori <[email protected]>
Signed-off-by David Lechner <[email protected]>
---
 drivers/clk/davinci/pll-dm355.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)
drivers/clk/davinci/pll-dm355.c +1 -4
index 5345f8286c50..718d9bbbf30d 100644
@@ -62,8 +62,7 @@ static const struct davinci_pll_clk_info dm355_pll2_info = {
 		 PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
 };
 
-SYSCLK(1, pll2_sysclk1, pll2, 5, SYSCLK_FIXED_DIV);
-SYSCLK(2, pll2_sysclk2, pll2, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
+SYSCLK(1, pll2_sysclk1, pll2, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
 
 int dm355_pll2_init(struct device *dev, void __iomem *base)
 {

@@ -71,8 +70,6 @@ int dm355_pll2_init(struct device *dev, void __iomem *base)
 
 	davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
 
-	davinci_pll_sysclk_register(dev, &pll2_sysclk2, base);
-
 	davinci_pll_sysclkbp_clk_register(dev, "pll2_sysclkbp", base);
 
 	return 0;
Signature · 1 line
2.17.0
Acked-by on v3 1/2
#2 lore raw

Re: [PATCH v3 1/2] clk: davinci: pll-dm355: drop pll2_sysclk2

Quoted 7 lines · David Lechner

This removes pll2_sysclk2 from the TI DM355 clock driver. This SoC doesn't have such a clock. Also, SYSCLK_ALWAYS_ENABLED is transferred to pll2_sysclk1 since it drives the DDR and doesn't have another mechanism to keep it on.

Reported-by Sekhar Nori <[email protected]>
Signed-off-by David Lechner <[email protected]>

I would not have minded the SYSCLK_ALWAYS_ENABLED change to be a separate patch too, but:

Acked-by Sekhar Nori <[email protected]>

Thanks,
Sekhar

author maintainer
#3 lore raw

PATCH v3 2/2 clk: davinci: pll-dm355: fix SYSCLKn parent names

In reply to David Lechner

This fixes the parent clock names of the SYSCLKn clocks for the DM355 SoC in the TI DaVinici PLL clock driver.

It appears that this name just didn't get updated to the correct name like the other SoCs during the driver's development.

Reported-by Sekhar Nori <[email protected]>
Signed-off-by David Lechner <[email protected]>
---
 drivers/clk/davinci/pll-dm355.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)
drivers/clk/davinci/pll-dm355.c +5 -5
index 718d9bbbf30d..93f4a53d6b44 100644
@@ -22,10 +22,10 @@ static const struct davinci_pll_clk_info dm355_pll1_info = {
 		 PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
 };
 
-SYSCLK(1, pll1_sysclk1, pll1, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
-SYSCLK(2, pll1_sysclk2, pll1, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
-SYSCLK(3, pll1_sysclk3, pll1, 5, SYSCLK_ALWAYS_ENABLED);
-SYSCLK(4, pll1_sysclk4, pll1, 5, SYSCLK_ALWAYS_ENABLED);
+SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
+SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
+SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
+SYSCLK(4, pll1_sysclk4, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
 
 int dm355_pll1_init(struct device *dev, void __iomem *base)
 {

@@ -62,7 +62,7 @@ static const struct davinci_pll_clk_info dm355_pll2_info = {
 		 PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
 };
 
-SYSCLK(1, pll2_sysclk1, pll2, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
+SYSCLK(1, pll2_sysclk1, pll2_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
 
 int dm355_pll2_init(struct device *dev, void __iomem *base)
 {
Signature · 1 line
2.17.0