Patch #6
PATCH 6/6 Patch #6
Right before we do an VMENTER we need to flush the L1 data cache to thwart against untrusted guests reading the host memory that is cached in L1 data cache.
Signed-off-by Konrad Rzeszutek Wilk <[email protected]>
--- arch/x86/kvm/x86.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)
arch/x86/kvm/x86.c +9 -1
@@ -58,6 +58,7 @@#include <trace/events/kvm.h> +#include <asm/cpu.h> #include <asm/debugreg.h> #include <asm/msr.h> #include <asm/desc.h>
@@ -6550,8 +6551,15 @@ static void *__read_mostly empty_zero_pages;void kvm_l1d_flush (void ) { +int size; + +if (static_cpu_has (X86_FEATURE_FLUSH_L1D )) { +x86_flush_l1d (); +return ; + } +/* FIXME: could this be boot_cpu_data.x86_cache_size * 2? */ -int size =PAGE_SIZE <<L1D_CACHE_ORDER ; + size =PAGE_SIZE <<L1D_CACHE_ORDER ; asmvolatile (/* First ensure the pages are in the TLB */ "xorl %%eax, %%eax\n\t"
Signature · 1 line
2.14.3
Paolo Bonzini
maintainerQuoted 5 lines · speck for konrad.wilk_at_oracle.com
x86/KVM: Use L1 cache flush before VMENTER if available.
Right before we do an VMENTER we need to flush the L1 data cache to thwart against untrusted guests reading the host memory that is cached in L1 data cache.
This is not what the patch does. The patch adds the usage of the MSR. You should add something like "If provided by the processor, use MSR_IA32_FLUSH_CMD instead of a loop" to the commit message.
Paolo
Quoted 28 lines
Signed-off-by Konrad Rzeszutek Wilk <[email protected]>--- arch/x86/kvm/x86.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)arch/x86/kvm/x86.c +8
-0@@ -58,6 +58,7 @@#include <trace/events/kvm.h> +#include <asm/cpu.h> #include <asm/debugreg.h> #include <asm/msr.h> #include <asm/desc.h> @@ -6550,8 +6551,15 @@ static void *__read_mostly empty_zero_pages;void kvm_l1d_flush (void ) { +int size; + +if (static_cpu_has (X86_FEATURE_FLUSH_L1D )) { +x86_flush_l1d (); +return ; + } +