Skip to contentSkip to conversation

sunxi: Enable DM_MMC for U-Boot proper

PATCH New Jagan Teki 6 participants 59 messages Jul 16, 2018 – Jul 20, 2018

Subsystems (8)
lore
Share & tools
lore

Jagan Teki

author
#0 lore raw

cover sunxi: Enable DM_MMC for U-Boot proper

Enabling DM_MMC is not straight forward for Allwinner SoC's to make proper compatibility in mmc driver vs DT nodes.

Existing dm code for ahb gate clock will be suitable to handle sun4i,5i,6i and 7i U-Boot specific mmc dt nodes, which are different from Linux in terms of clocks phandle notation.

U-Boot DT clocks phandle follow direct ahb and clock address on node definition with specific bit position, but Linux clocks phandle follow macros to define AHB and MMC clocks so-that the ccu driver will set the bits accordingly.

Clocks phandle notations in U-Boot for higher Allwinner SoC start from sun8i, sun50i are following Linux notation so-that both Linux and U-Boot can have common node definition.

This series will address the ahb gate, clock setup to handle all type of Allwinner SoCs. and sync mmc node definitions from Linux for sun4i and sun5i.

Note:
- sun6i, A23, A33, V3S were untested these need to have a closer look on dt nodes along with default ENV_FAT device.

All these changes available at u-boot-sunxi/next

Let me know if any questions or missings,
Jagan.

Jagan Teki (25):
ARM: dts: sun4i: Sync A10 MMC nodes from Linux
ARM: dts: sun4i: Sync A10 board dts mmc0 node from Linux
ARM: dts: sun4i: Add mmc0 node for iNet 3F
ARM: dts: sun4i: Add mmc0 node for iNet 3W
dm: mmc: sunxi: Refactor ahb gate and clock setup
dm: mmc: sunxi: Add ahb reset0 register write
ARM: dts: sun7i: Sync A20 MMC nodes from Linux
ARM: dts: sun7i: Add mmc0 node for Primo73 tablet
ARM: dts: sun7i: Add mmc0 node for Ainol AW1
ARM: dts: sun7i: Add mmc0 node for Mele M5
ARM: dts: sun7i: Add mmc0 node for Toptech BD1078
sunxi: A20: Enable DM_MMC
mmc: sunxi: Add mmc, emmc H5/A64 compatible
sunxi: H3_H5: Enable DM_MMC
sunxi: A64: Enable DM_MMC
ARM: dts: sun8i: Update A83T dts(i) files from Linux
mmc: sunxi: Add A83T emmc compatible
sunxi: A83T: Enable DM_MMC
ARM: dts: sun8i: Update R40 dts(i) files from Linux
sunxi: V40: Enable DM_MMC
fastboot: sunxi: Update fastboot mmc default device
env: sunxi: Update default env fat device
sunxi: Use mmc_bootdev=2 for MMC2 boot
[DO NOT MERGE] sunxi: A13/A31: Enable DM_MMC [DO NOT MERGE] sunxi: A23/A33/V3S: Enable DM_MMC

 arch/arm/dts/axp81x.dtsi                      | 169 ++++
 arch/arm/dts/sun4i-a10-a1000.dts              |   5 +-
 arch/arm/dts/sun4i-a10-ba10-tvbox.dts         |   5 +-
 arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts    |   5 +-
 arch/arm/dts/sun4i-a10-cubieboard.dts         |   5 +-
 arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts   |   5 +-
 arch/arm/dts/sun4i-a10-gemei-g9.dts           |   5 +-
 arch/arm/dts/sun4i-a10-hackberry.dts          |   5 +-
 arch/arm/dts/sun4i-a10-hyundai-a7hd.dts       |   5 +-
 arch/arm/dts/sun4i-a10-inet-3f.dts            |   9 +
 arch/arm/dts/sun4i-a10-inet-3w.dts            |   9 +
 arch/arm/dts/sun4i-a10-inet1.dts              |   5 +-
 arch/arm/dts/sun4i-a10-inet97fv2.dts          |   5 +-
 arch/arm/dts/sun4i-a10-inet9f-rev03.dts       |   5 +-
 .../dts/sun4i-a10-itead-iteaduino-plus.dts    |   5 +-
 arch/arm/dts/sun4i-a10-jesurun-q5.dts         |   5 +-
 arch/arm/dts/sun4i-a10-marsboard.dts          |   5 +-
 arch/arm/dts/sun4i-a10-mini-xplus.dts         |   5 +-
 arch/arm/dts/sun4i-a10-mk802.dts              |   5 +-
 arch/arm/dts/sun4i-a10-mk802ii.dts            |   5 +-
 arch/arm/dts/sun4i-a10-olinuxino-lime.dts     |   5 +-
 arch/arm/dts/sun4i-a10-pcduino.dts            |   5 +-
 arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts   |   5 +-
 arch/arm/dts/sun4i-a10.dtsi                   | 112 +--
 arch/arm/dts/sun7i-a20-ainol-aw1.dts          |  13 +
 arch/arm/dts/sun7i-a20-m5.dts                 |  12 +
 arch/arm/dts/sun7i-a20-primo73.dts            |  20 +-
 .../dts/sun7i-a20-yones-toptech-bd1078.dts    |  13 +
 arch/arm/dts/sun7i-a20.dtsi                   | 102 +-
 .../dts/sun8i-a83t-allwinner-h8homlet-v2.dts  | 195 +++-
 arch/arm/dts/sun8i-a83t-bananapi-m3.dts       | 298 +++++-
 arch/arm/dts/sun8i-a83t-cubietruck-plus.dts   | 322 ++++++-
 arch/arm/dts/sun8i-a83t-tbs-a711.dts          | 355 ++++++-
 arch/arm/dts/sun8i-a83t.dtsi                  | 885 ++++++++++++++++--
 arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts  | 197 +++-
 arch/arm/dts/sun8i-r40.dtsi                   | 616 +++++++++++-
 arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts  |  50 +
 arch/arm/mach-sunxi/Kconfig                   |  10 +
 board/sunxi/board.c                           |   2 +-
 configs/A20-OLinuXino-Lime2-eMMC_defconfig    |   2 +
 configs/A20-OLinuXino_MICRO-eMMC_defconfig    |   1 +
 configs/A20-OLinuXino_MICRO_defconfig         |   1 +
 configs/A20-Olimex-SOM-EVB_defconfig          |   1 +
 configs/A20-Olimex-SOM204-EVB-eMMC_defconfig  |   1 +
 configs/Mele_M3_defconfig                     |   1 +
 configs/Orangepi_mini_defconfig               |   1 +
 configs/Sinlinx_SinA33_defconfig              |   2 +
 configs/Yones_Toptech_BD1078_defconfig        |   1 +
 configs/amarula_a64_relic_defconfig           |   2 +
 drivers/fastboot/Kconfig                      |   3 +-
 drivers/mmc/sunxi_mmc.c                       |  81 +-
 env/Kconfig                                   |   3 +-
 include/configs/sunxi-common.h                |   4 +-
 include/dt-bindings/clock/sun4i-a10-ccu.h     | 202 ++++
 include/dt-bindings/clock/sun7i-a20-ccu.h     |  53 ++
 include/dt-bindings/clock/sun8i-a83t-ccu.h    | 140 +++
 include/dt-bindings/reset/sun8i-a83t-ccu.h    |  98 ++
 57 files changed, 3715 insertions(+), 371 deletions(-)
 create mode 100644 arch/arm/dts/axp81x.dtsi
 create mode 100644 include/dt-bindings/clock/sun4i-a10-ccu.h
 create mode 100644 include/dt-bindings/clock/sun7i-a20-ccu.h
 create mode 100644 include/dt-bindings/clock/sun8i-a83t-ccu.h
 create mode 100644 include/dt-bindings/reset/sun8i-a83t-ccu.h
Signature · 1 line
2.17.1
author
#1 lore raw

PATCH 1/25 ARM: dts: sun4i: Sync A10 MMC nodes from Linux

DM_MMC need MMC nodes in dtsi need to update and follow Linux notation to support dm driven mmc driver. So sync mmc nodes for sun4i-a10 from Linux. This will also useful for CLK driver handling in future.

Last linux commit for sun4i-a10.dtsi:
commit 590b0c0cfc6162aeebbf43eaafb9753b56df1532

Author: Pascal Roeleven <[email protected]>
Date:   Fri Apr 20 12:21:12 2018 +0200

ARM: dts: sun4i: Fix incorrect clocks for displays

Last linux commit for sun4i-a10-ccu.h:
commit 4328a2186e5120cfd34c4f04c6e4b7e74fb8b7b4

Author: Jonathan Liu <[email protected]>
Date:   Tue Oct 17 20:18:03 2017 +0800

clk: sunxi-ng: sun4i: Export video PLLs

---
 arch/arm/dts/sun4i-a10.dtsi               | 112 ++++--------
 include/dt-bindings/clock/sun4i-a10-ccu.h | 202 ++++++++++++++++++++++
 2 files changed, 232 insertions(+), 82 deletions(-)
 create mode 100644 include/dt-bindings/clock/sun4i-a10-ccu.h
arch/arm/dts/sun4i-a10.dtsi +30 -82
index 7e7dfc2b43..b58252934b 100644
@@ -47,6 +47,7 @@
 
 #include <dt-bindings/clock/sun4i-a10-pll2.h>
 #include <dt-bindings/dma/sun4i-a10.h>
+#include <dt-bindings/clock/sun4i-a10-ccu.h>
 #include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
@@ -420,46 +421,6 @@
 			clock-output-names = "ms";
 		};
 
-		mmc0_clk: clk at 01c20088 {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun4i-a10-mmc-clk";
-			reg = <0x01c20088 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-			clock-output-names = "mmc0",
-					     "mmc0_output",
-					     "mmc0_sample";
-		};
-
-		mmc1_clk: clk at 01c2008c {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun4i-a10-mmc-clk";
-			reg = <0x01c2008c 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-			clock-output-names = "mmc1",
-					     "mmc1_output",
-					     "mmc1_sample";
-		};
-
-		mmc2_clk: clk at 01c20090 {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun4i-a10-mmc-clk";
-			reg = <0x01c20090 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-			clock-output-names = "mmc2",
-					     "mmc2_output",
-					     "mmc2_sample";
-		};
-
-		mmc3_clk: clk at 01c20094 {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun4i-a10-mmc-clk";
-			reg = <0x01c20094 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-			clock-output-names = "mmc3",
-					     "mmc3_output",
-					     "mmc3_sample";
-		};
-
 		ts_clk: clk at 01c20098 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-mod0-clk";
@@ -779,68 +740,46 @@
 			#size-cells = <0>;
 		};
 
-		mmc0: mmc at 01c0f000 {
+		mmc0: mmc at 1c0f000 {
 			compatible = "allwinner,sun4i-a10-mmc";
 			reg = <0x01c0f000 0x1000>;
-			clocks = <&ahb_gates 8>,
-				 <&mmc0_clk 0>,
-				 <&mmc0_clk 1>,
-				 <&mmc0_clk 2>;
-			clock-names = "ahb",
-				      "mmc",
-				      "output",
-				      "sample";
+			clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
+			clock-names = "ahb", "mmc";
 			interrupts = <32>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc0_pins>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
 
-		mmc1: mmc at 01c10000 {
+		mmc1: mmc at 1c10000 {
 			compatible = "allwinner,sun4i-a10-mmc";
 			reg = <0x01c10000 0x1000>;
-			clocks = <&ahb_gates 9>,
-				 <&mmc1_clk 0>,
-				 <&mmc1_clk 1>,
-				 <&mmc1_clk 2>;
-			clock-names = "ahb",
-				      "mmc",
-				      "output",
-				      "sample";
+			clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
+			clock-names = "ahb", "mmc";
 			interrupts = <33>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
 
-		mmc2: mmc at 01c11000 {
+		mmc2: mmc at 1c11000 {
 			compatible = "allwinner,sun4i-a10-mmc";
 			reg = <0x01c11000 0x1000>;
-			clocks = <&ahb_gates 10>,
-				 <&mmc2_clk 0>,
-				 <&mmc2_clk 1>,
-				 <&mmc2_clk 2>;
-			clock-names = "ahb",
-				      "mmc",
-				      "output",
-				      "sample";
+			clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
+			clock-names = "ahb", "mmc";
 			interrupts = <34>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
 
-		mmc3: mmc at 01c12000 {
+		mmc3: mmc at 1c12000 {
 			compatible = "allwinner,sun4i-a10-mmc";
 			reg = <0x01c12000 0x1000>;
-			clocks = <&ahb_gates 11>,
-				 <&mmc3_clk 0>,
-				 <&mmc3_clk 1>,
-				 <&mmc3_clk 2>;
-			clock-names = "ahb",
-				      "mmc",
-				      "output",
-				      "sample";
+			clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>;
+			clock-names = "ahb", "mmc";
 			interrupts = <35>;
 			status = "disabled";
 			#address-cells = <1>;
@@ -956,6 +895,15 @@
 			#size-cells = <0>;
 		};
 
+		ccu: clock at 1c20000 {
+			compatible = "allwinner,sun4i-a10-ccu";
+			reg = <0x01c20000 0x400>;
+			clocks = <&osc24M>, <&osc32k>;
+			clock-names = "hosc", "losc";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
 		intc: interrupt-controller at 01c20400 {
 			compatible = "allwinner,sun4i-a10-ic";
 			reg = <0x01c20400 0x400>;
@@ -1033,12 +981,12 @@
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
 
-			mmc0_pins_a: mmc0 at 0 {
-				allwinner,pins = "PF0", "PF1", "PF2",
-						 "PF3", "PF4", "PF5";
-				allwinner,function = "mmc0";
-				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			mmc0_pins: mmc0-pins {
+				pins = "PF0", "PF1", "PF2",
+				       "PF3", "PF4", "PF5";
+				function = "mmc0";
+				drive-strength = <30>;
+				bias-pull-up;
 			};
 
 			mmc0_cd_pin_reference_design: mmc0_cd_pin at 0 {
include/dt-bindings/clock/sun4i-a10-ccu.h new file +202 -0

202 lines not on this page · raw message

Signature · 1 line
2.17.1
#2 lore raw

PATCH 1/25 ARM: dts: sun4i: Sync A10 MMC nodes from Linux

Quoted 10 lines · Jagan Teki

DM_MMC need MMC nodes in dtsi need to update and follow Linux notation to support dm driven mmc driver. So sync mmc nodes for sun4i-a10 from Linux. This will also useful for CLK driver handling in future.

Last linux commit for sun4i-a10.dtsi:
commit 590b0c0cfc6162aeebbf43eaafb9753b56df1532

Author: Pascal Roeleven <[email protected]>
Date:   Fri Apr 20 12:21:12 2018 +0200
Quoted 8 lines

ARM: dts: sun4i: Fix incorrect clocks for displays

Last linux commit for sun4i-a10-ccu.h:
commit 4328a2186e5120cfd34c4f04c6e4b7e74fb8b7b4

Author: Jonathan Liu <[email protected]>
Date:   Tue Oct 17 20:18:03 2017 +0800

clk: sunxi-ng: sun4i: Export video PLLs

Can't we just sync all the A10 DTs in one go to the latest kernel release, instead of half doing the work with a random commit?

Maxime

Signature · 10 lines
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180716/6d877e8c/attachment.sig>
#3 lore raw

PATCH 1/25 ARM: dts: sun4i: Sync A10 MMC nodes from Linux

Quoted 18 lines · Maxime Ripard
Quoted 17 lines · Jagan Teki

DM_MMC need MMC nodes in dtsi need to update and follow Linux notation to support dm driven mmc driver. So sync mmc nodes for sun4i-a10 from Linux. This will also useful for CLK driver handling in future.

Last linux commit for sun4i-a10.dtsi:
commit 590b0c0cfc6162aeebbf43eaafb9753b56df1532

Author: Pascal Roeleven <[email protected]>
Date:   Fri Apr 20 12:21:12 2018 +0200

ARM: dts: sun4i: Fix incorrect clocks for displays

Last linux commit for sun4i-a10-ccu.h:
commit 4328a2186e5120cfd34c4f04c6e4b7e74fb8b7b4

Author: Jonathan Liu <[email protected]>
Date:   Tue Oct 17 20:18:03 2017 +0800
Quoted 4 lines
Quoted 1 line

clk: sunxi-ng: sun4i: Export video PLLs

Can't we just sync all the A10 DTs in one go to the latest kernel release, instead of half doing the work with a random commit?

Now we need only minimal changes in dtsi, no need for board dts files to update for sun4i. All DT sync from Linux not require here at this point of time. even the subsequent patches will add only mmc0 node in dts files which are not available in Linux.

#4 lore raw

PATCH 1/25 ARM: dts: sun4i: Sync A10 MMC nodes from Linux

Quoted 20 lines · Jagan Teki
Quoted 18 lines · Maxime Ripard
Quoted 17 lines · Jagan Teki

DM_MMC need MMC nodes in dtsi need to update and follow Linux notation to support dm driven mmc driver. So sync mmc nodes for sun4i-a10 from Linux. This will also useful for CLK driver handling in future.

Last linux commit for sun4i-a10.dtsi:
commit 590b0c0cfc6162aeebbf43eaafb9753b56df1532

Author: Pascal Roeleven <[email protected]>
Date:   Fri Apr 20 12:21:12 2018 +0200

ARM: dts: sun4i: Fix incorrect clocks for displays

Last linux commit for sun4i-a10-ccu.h:
commit 4328a2186e5120cfd34c4f04c6e4b7e74fb8b7b4

Author: Jonathan Liu <[email protected]>
Date:   Tue Oct 17 20:18:03 2017 +0800
Quoted 8 lines
Quoted 4 lines
Quoted 1 line

clk: sunxi-ng: sun4i: Export video PLLs

Can't we just sync all the A10 DTs in one go to the latest kernel release, instead of half doing the work with a random commit?

Now we need only minimal changes in dtsi, no need for board dts files to update for sun4i. All DT sync from Linux not require here at this point of time.

Why? A DT is an hardware description, the hardware doesn't change between U-Boot and Linux.

Maxime

Signature · 10 lines
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180716/d5b32a9f/attachment.sig>
author
#5 lore raw

PATCH 2/25 ARM: dts: sun4i: Sync A10 board dts mmc0 node from Linux

In reply to Jagan Teki

Since sun4i-a10.dtsi synced from Linux, for compatibility sync sun4i-a10 board mmc0 nodes from Linux.

Last linux commit for sun4i-a10*.dts
commit 190e3138f9577885691540dca59c2f07540bde04
Merge: cafc87023b0d a7affb13b271
Author: Arnd Bergmann <[email protected]>
Date: Tue Mar 27 14:58:00 2018 +0200

Merge tag 'sunxi-h3-h5-for-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt

---
 arch/arm/dts/sun4i-a10-a1000.dts                | 5 +----
 arch/arm/dts/sun4i-a10-ba10-tvbox.dts           | 5 +----
 arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts      | 5 +----
 arch/arm/dts/sun4i-a10-cubieboard.dts           | 5 +----
 arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts     | 5 +----
 arch/arm/dts/sun4i-a10-gemei-g9.dts             | 5 +----
 arch/arm/dts/sun4i-a10-hackberry.dts            | 5 +----
 arch/arm/dts/sun4i-a10-hyundai-a7hd.dts         | 5 +----
 arch/arm/dts/sun4i-a10-inet1.dts                | 5 +----
 arch/arm/dts/sun4i-a10-inet97fv2.dts            | 5 +----
 arch/arm/dts/sun4i-a10-inet9f-rev03.dts         | 5 +----
 arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts | 5 +----
 arch/arm/dts/sun4i-a10-jesurun-q5.dts           | 5 +----
 arch/arm/dts/sun4i-a10-marsboard.dts            | 5 +----
 arch/arm/dts/sun4i-a10-mini-xplus.dts           | 5 +----
 arch/arm/dts/sun4i-a10-mk802.dts                | 5 +----
 arch/arm/dts/sun4i-a10-mk802ii.dts              | 5 +----
 arch/arm/dts/sun4i-a10-olinuxino-lime.dts       | 5 +----
 arch/arm/dts/sun4i-a10-pcduino.dts              | 5 +----
 arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts     | 5 +----
 20 files changed, 20 insertions(+), 80 deletions(-)
arch/arm/dts/sun4i-a10-a1000.dts +1 -4
index 39e368ec34..52ce35508f 100644
@@ -167,12 +167,9 @@
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
-	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-	cd-inverted;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
 	status = "okay";
 };
 
arch/arm/dts/sun4i-a10-ba10-tvbox.dts +1 -4
index f3cb297fd1..414db62310 100644
@@ -108,12 +108,9 @@
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
-	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-	cd-inverted;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
 	status = "okay";
 };
 
arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts +1 -4
index 023b03efa5..14ad14bfbe 100644
@@ -127,12 +127,9 @@
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
-	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-	cd-inverted;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
 	status = "okay";
 };
 
arch/arm/dts/sun4i-a10-cubieboard.dts +1 -4
index 710e2ef516..713157d967 100644
@@ -142,12 +142,9 @@
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
-	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-	cd-inverted;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
 	status = "okay";
 };
 
arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts +1 -4
index 893497e397..f5334056ca 100644
@@ -163,12 +163,9 @@
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
-	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-	cd-inverted;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
 	status = "okay";
 };
 
arch/arm/dts/sun4i-a10-gemei-g9.dts +1 -4
index ac64781a0a..a4e2d45249 100644
@@ -145,12 +145,9 @@
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
-	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH01 */
-	cd-inverted;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH01 */
 	status = "okay";
 };
 
arch/arm/dts/sun4i-a10-hackberry.dts +1 -4
index 6de83a6187..ac8939f985 100644
@@ -107,12 +107,9 @@
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
-	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-	cd-inverted;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
 	status = "okay";
 };
 
arch/arm/dts/sun4i-a10-hyundai-a7hd.dts +1 -4
index 9103864fef..6904c55e74 100644
@@ -78,12 +78,9 @@
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
-	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-	cd-inverted;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
 	status = "okay";
 };
 
arch/arm/dts/sun4i-a10-inet1.dts +1 -4
index e09053bf5e..542816a8dc 100644
@@ -161,12 +161,9 @@
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
-	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-	cd-inverted;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
 	status = "okay";
 };
 
arch/arm/dts/sun4i-a10-inet97fv2.dts +1 -4
index 04b0d2d1ae..8624fe1fa3 100644
@@ -146,12 +146,9 @@
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
-	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-	cd-inverted;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
 	status = "okay";
 };
 
arch/arm/dts/sun4i-a10-inet9f-rev03.dts +1 -4
index bba4f9cf9b..3d36c0e060 100644
@@ -305,12 +305,9 @@
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
-	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-	cd-inverted;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
 	status = "okay";
 };
 
arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts +1 -4
index 4e798f014c..0336333908 100644
@@ -99,12 +99,9 @@
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
-	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-	cd-inverted;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
 	status = "okay";
 };
 
arch/arm/dts/sun4i-a10-jesurun-q5.dts +1 -4
index e28f080b1f..3218a45e81 100644
@@ -140,12 +140,9 @@
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
-	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-	cd-inverted;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
 	status = "okay";
 };
 
arch/arm/dts/sun4i-a10-marsboard.dts +1 -4
index 8e50723dbe..5c82b639c3 100644
@@ -141,12 +141,9 @@
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
-	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-	cd-inverted;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
 	status = "okay";
 };
 
arch/arm/dts/sun4i-a10-mini-xplus.dts +1 -4
index a7dd86d30f..958b6b984e 100644
@@ -97,12 +97,9 @@
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
-	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-	cd-inverted;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
 	status = "okay";
 };
 
arch/arm/dts/sun4i-a10-mk802.dts +1 -4
index ee46ea8548..beac451356 100644
@@ -72,12 +72,9 @@
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
-	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-	cd-inverted;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
 	status = "okay";
 };
 
arch/arm/dts/sun4i-a10-mk802ii.dts +1 -4
index c861fa7e35..857384ad78 100644
@@ -82,12 +82,9 @@
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
-	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-	cd-inverted;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
 	status = "okay";
 };
 
arch/arm/dts/sun4i-a10-olinuxino-lime.dts +1 -4
index b350448c72..3e93ebc93e 100644
@@ -145,12 +145,9 @@
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
-	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-	cd-inverted;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
 	status = "okay";
 };
 
arch/arm/dts/sun4i-a10-pcduino.dts +1 -4
index 39034aa8e1..aa3ffb2b2b 100644
@@ -147,12 +147,9 @@
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
-	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-	cd-inverted;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
 	status = "okay";
 };
 
arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts +1 -4
index ea90634e48..6bd3bc0863 100644
@@ -156,12 +156,9 @@
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
-	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-	cd-inverted;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
 	status = "okay";
 };
 
Signature · 1 line
2.17.1
author
#6 lore raw

PATCH 3/25 ARM: dts: sun4i: Add mmc0 node for iNet 3F

In reply to Jagan Teki

Since SUN4I moved to DM_MMC, we need to have mmc node in iNet 3F DT otherwise it will not probe.

Cc Paul Kocialkowski <[email protected]>
---
 arch/arm/dts/sun4i-a10-inet-3f.dts | 9 +++++++++
 1 file changed, 9 insertions(+)
arch/arm/dts/sun4i-a10-inet-3f.dts +9 -0
index f815b83157..4ebf206c4a 100644
@@ -7,6 +7,8 @@
 
 /dts-v1/;
 #include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "iNet 3F";
@@ -21,6 +23,13 @@
 	};
 };
 
+&mmc0 {
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
+	status = "okay";
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pins_a>;
Signature · 1 line
2.17.1
author
#7 lore raw

PATCH 4/25 ARM: dts: sun4i: Add mmc0 node for iNet 3W

In reply to Jagan Teki

Since SUN4I moved to DM_MMC, we need to have mmc node in iNet 3W DT otherwise it will not probe.

Cc Paul Kocialkowski <[email protected]>
---
 arch/arm/dts/sun4i-a10-inet-3w.dts | 9 +++++++++
 1 file changed, 9 insertions(+)
arch/arm/dts/sun4i-a10-inet-3w.dts +9 -0
index d0267ceee9..4168e2c0d0 100644
@@ -7,6 +7,8 @@
 
 /dts-v1/;
 #include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "iNet 3W";
@@ -21,6 +23,13 @@
 	};
 };
 
+&mmc0 {
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	cd-gpios = <&pio 7 20 GPIO_ACTIVE_LOW>; /* PH20 */
+	status = "okay";
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pins_a>;
Signature · 1 line
2.17.1
author
#8 lore raw

PATCH 5/25 dm: mmc: sunxi: Refactor ahb gate and clock setup

In reply to Jagan Teki

Existing dm code for ahb gate clock will be suitable to handle sun4i,5i,6i and 7i U-Boot specific mmc dt nodes, which are different from Linux in terms of clocks phandle notation.

U-Boot DT clocks phandle follow direct ahb and clock address on node definition with specific bit position, but Linux clocks phandle follow macros to define AHB and MMC clocks so-that the ccu driver will set the bits accordingly.

Clocks phandle notations in U-Boot for higher Allwinner SoC start from sun8i, sun50i are following Linux notation to sync with common node definition along with proper clock driver handling.

So refactor the ahb gate, clock setup to handle all type of Allwinner SoCs. Since we don't have proper CLK driver yet, this code using driver data to differentiate require SoC specific data.

This require existing U-Boot mmc DT nodes need to sync with Linux and the subsequent patches are doing the same.

Cc Simon Glass <[email protected]>
Cc Jaehoon Chung <[email protected]>
---
 drivers/mmc/sunxi_mmc.c | 39 ++++++++++++++++++++++++++++-----------
 1 file changed, 28 insertions(+), 11 deletions(-)
drivers/mmc/sunxi_mmc.c +28 -11
index 7fa1ae8b16..38171b81f3 100644
@@ -569,8 +569,8 @@ static int sunxi_mmc_probe(struct udevice *dev)
 	struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
 	struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 	struct mmc_config *cfg = &plat->cfg;
+	struct sunxi_ccm_reg *ccm;
 	struct ofnode_phandle_args args;
-	u32 *gate_reg;
 	int bus_width, ret;
 
 	cfg->name = dev->name;
@@ -589,21 +589,38 @@ static int sunxi_mmc_probe(struct udevice *dev)
 	cfg->f_max = 52000000;
 
 	priv->reg = (void *)dev_read_addr(dev);
+	priv->mmc_no = (((uintptr_t)priv->reg / 0x1000) - 0x1C0F);
 
-	/* We don't have a sunxi clock driver so find the clock address here */
 	ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
-					  1, &args);
+					 0, &args);
 	if (ret)
 		return ret;
-	priv->mclkreg = (u32 *)ofnode_get_addr(args.node);
 
-	ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
-					  0, &args);
-	if (ret)
-		return ret;
-	gate_reg = (u32 *)ofnode_get_addr(args.node);
-	setbits_le32(gate_reg, 1 << args.args[0]);
-	priv->mmc_no = args.args[0] - 8;
+	ccm = (struct sunxi_ccm_reg *)ofnode_get_addr(args.node);
+	if (IS_ERR(ccm))
+		return PTR_ERR(ccm);
+
+	/* enable ahb gate */
+	setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));
+
+	/* find clock reg */
+	switch (priv->mmc_no) {
+	case 0:
+		priv->mclkreg = &ccm->sd0_clk_cfg;
+		break;
+	case 1:
+		priv->mclkreg = &ccm->sd1_clk_cfg;
+		break;
+	case 2:
+		priv->mclkreg = &ccm->sd2_clk_cfg;
+		break;
+	case 3:
+		priv->mclkreg = &ccm->sd3_clk_cfg;
+		break;
+	default:
+		printf("Wrong mmc number %d\n", priv->mmc_no);
+		return -EINVAL;
+	}
 
 	ret = mmc_set_mod_clk(priv, 24000000);
 	if (ret)
Signature · 1 line
2.17.1
author
#9 lore raw

PATCH 6/25 dm: mmc: sunxi: Add ahb reset0 register write

In reply to Jagan Teki

AHB reset0 is needed for Allwinner start from sun6i, so add driver data configuration for ahb reset0 and update the register bits during probe.

Cc Jaehoon Chung <[email protected]>
---
 drivers/mmc/sunxi_mmc.c | 36 +++++++++++++++++++++++++++++++++---
 1 file changed, 33 insertions(+), 3 deletions(-)
drivers/mmc/sunxi_mmc.c +33 -3
index 38171b81f3..beeded50af 100644
@@ -30,6 +30,7 @@ struct sunxi_mmc_priv {
 	unsigned fatal_err;
 	struct gpio_desc cd_gpio;	/* Change Detect GPIO */
 	int cd_inverted;		/* Inverted Card Detect */
+	u32 *reg_reset0;
 	struct sunxi_mmc *reg;
 	struct mmc_config cfg;
 };
@@ -528,6 +529,14 @@ struct mmc *sunxi_mmc_init(int sdc_no)
 }
 #else
 
+#define OFF_SUN6I_AHB_RESET0	0x2c0
+
+struct sunxi_mmc_config {
+	bool has_reset0;
+	u8 pos_reset0;
+	u32 off_reset0;
+};
+
 static int sunxi_mmc_set_ios(struct udevice *dev)
 {
 	struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
@@ -569,6 +578,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
 	struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
 	struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 	struct mmc_config *cfg = &plat->cfg;
+	const struct sunxi_mmc_config *data;
 	struct sunxi_ccm_reg *ccm;
 	struct ofnode_phandle_args args;
 	int bus_width, ret;
@@ -588,6 +598,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
 	cfg->f_min = 400000;
 	cfg->f_max = 52000000;
 
+	data = (struct sunxi_mmc_config *)dev_get_driver_data(dev);
 	priv->reg = (void *)dev_read_addr(dev);
 	priv->mmc_no = (((uintptr_t)priv->reg / 0x1000) - 0x1C0F);
 
@@ -600,9 +611,15 @@ static int sunxi_mmc_probe(struct udevice *dev)
 	if (IS_ERR(ccm))
 		return PTR_ERR(ccm);
 
+	priv->reg_reset0 = (void *)ccm + data->off_reset0;
+
 	/* enable ahb gate */
 	setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));
 
+	/* unassert reset */
+	if (data->has_reset0)
+		setbits_le32(priv->reg_reset0, BIT(data->pos_reset0 + priv->mmc_no));
+
 	/* find clock reg */
 	switch (priv->mmc_no) {
 	case 0:
@@ -653,10 +670,23 @@ static int sunxi_mmc_bind(struct udevice *dev)
 	return mmc_bind(dev, &plat->mmc, &plat->cfg);
 }
 
+static const struct sunxi_mmc_config sun4i_a10_cfg = {
+	.has_reset0 = false,
+};
+
+static const struct sunxi_mmc_config sun7i_a20_cfg = {
+	.has_reset0 = true,
+	.pos_reset0 = 8,
+	.off_reset0 = OFF_SUN6I_AHB_RESET0,
+};
+
 static const struct udevice_id sunxi_mmc_ids[] = {
-	{ .compatible = "allwinner,sun4i-a10-mmc" },
-	{ .compatible = "allwinner,sun5i-a13-mmc" },
-	{ .compatible = "allwinner,sun7i-a20-mmc" },
+	{ .compatible = "allwinner,sun4i-a10-mmc",
+			.data = (ulong)&sun4i_a10_cfg },
+	{ .compatible = "allwinner,sun5i-a13-mmc",
+			.data = (ulong)&sun4i_a10_cfg },
+	{ .compatible = "allwinner,sun7i-a20-mmc",
+			.data = (ulong)&sun7i_a20_cfg },
 	{ }
 };
 
Signature · 1 line
2.17.1
#10 lore raw

PATCH 6/25 dm: mmc: sunxi: Add ahb reset0 register write

Quoted 72 lines · Jagan Teki

AHB reset0 is needed for Allwinner start from sun6i, so add driver data configuration for ahb reset0 and update the register bits during probe.

Cc Jaehoon Chung <[email protected]>
---
 drivers/mmc/sunxi_mmc.c | 36 +++++++++++++++++++++++++++++++++---
 1 file changed, 33 insertions(+), 3 deletions(-)
drivers/mmc/sunxi_mmc.c +17 -0
index 38171b81f3..beeded50af 100644
@@ -30,6 +30,7 @@ struct sunxi_mmc_priv {
 	unsigned fatal_err;
 	struct gpio_desc cd_gpio;	/* Change Detect GPIO */
 	int cd_inverted;		/* Inverted Card Detect */
+	u32 *reg_reset0;
 	struct sunxi_mmc *reg;
 	struct mmc_config cfg;
 };
@@ -528,6 +529,14 @@ struct mmc *sunxi_mmc_init(int sdc_no)
 }
 #else
 
+#define OFF_SUN6I_AHB_RESET0	0x2c0
+
+struct sunxi_mmc_config {
+	bool has_reset0;
+	u8 pos_reset0;
+	u32 off_reset0;
+};
+
 static int sunxi_mmc_set_ios(struct udevice *dev)
 {
 	struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
@@ -569,6 +578,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
 	struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
 	struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 	struct mmc_config *cfg = &plat->cfg;
+	const struct sunxi_mmc_config *data;
 	struct sunxi_ccm_reg *ccm;
 	struct ofnode_phandle_args args;
 	int bus_width, ret;
@@ -588,6 +598,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
 	cfg->f_min = 400000;
 	cfg->f_max = 52000000;
 
+	data = (struct sunxi_mmc_config *)dev_get_driver_data(dev);
 	priv->reg = (void *)dev_read_addr(dev);
 	priv->mmc_no = (((uintptr_t)priv->reg / 0x1000) - 0x1C0F);
 
@@ -600,9 +611,15 @@ static int sunxi_mmc_probe(struct udevice *dev)
 	if (IS_ERR(ccm))
 		return PTR_ERR(ccm);
 
+	priv->reg_reset0 = (void *)ccm + data->off_reset0;
+
 	/* enable ahb gate */
 	setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));
 
+	/* unassert reset */
+	if (data->has_reset0)
+		setbits_le32(priv->reg_reset0, BIT(data->pos_reset0 + priv->mmc_no));
+
 	/* find clock reg */
 	switch (priv->mmc_no) {
 	case 0:
@@ -653,10 +670,23 @@ static int sunxi_mmc_bind(struct udevice *dev)
 	return mmc_bind(dev, &plat->mmc, &plat->cfg);
 }

drivers/mmc/sunxi_mmc.c static int sunxi_mmc_bind(struct udevice *dev) · line 681

Quoted 10 lines
drivers/mmc/sunxi_mmc.c +9 -0
 
+static const struct sunxi_mmc_config sun4i_a10_cfg = {
+	.has_reset0 = false,
+};
+
+static const struct sunxi_mmc_config sun7i_a20_cfg = {
+	.has_reset0 = true,
+	.pos_reset0 = 8,
+	.off_reset0 = OFF_SUN6I_AHB_RESET0,
+};

Nope. The A20 doesn't have any reset line.

Maxime

Signature · 10 lines
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180716/ed9488bf/attachment.sig>
#11 lore raw

PATCH 6/25 dm: mmc: sunxi: Add ahb reset0 register write

Quoted 74 lines · Maxime Ripard
Quoted 73 lines · Jagan Teki

AHB reset0 is needed for Allwinner start from sun6i, so add driver data configuration for ahb reset0 and update the register bits during probe.

Cc Jaehoon Chung <[email protected]>
---
 drivers/mmc/sunxi_mmc.c | 36 +++++++++++++++++++++++++++++++++---
 1 file changed, 33 insertions(+), 3 deletions(-)
drivers/mmc/sunxi_mmc.c +17 -0
index 38171b81f3..beeded50af 100644
@@ -30,6 +30,7 @@ struct sunxi_mmc_priv {
      unsigned fatal_err;
      struct gpio_desc cd_gpio;       /* Change Detect GPIO */
      int cd_inverted;                /* Inverted Card Detect */
+     u32 *reg_reset0;
      struct sunxi_mmc *reg;
      struct mmc_config cfg;
 };
@@ -528,6 +529,14 @@ struct mmc *sunxi_mmc_init(int sdc_no)
 }
 #else
 
+#define OFF_SUN6I_AHB_RESET0 0x2c0
+
+struct sunxi_mmc_config {
+     bool has_reset0;
+     u8 pos_reset0;
+     u32 off_reset0;
+};
+
 static int sunxi_mmc_set_ios(struct udevice *dev)
 {
      struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
@@ -569,6 +578,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
      struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
      struct sunxi_mmc_priv *priv = dev_get_priv(dev);
      struct mmc_config *cfg = &plat->cfg;
+     const struct sunxi_mmc_config *data;
      struct sunxi_ccm_reg *ccm;
      struct ofnode_phandle_args args;
      int bus_width, ret;
@@ -588,6 +598,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
      cfg->f_min = 400000;
      cfg->f_max = 52000000;
 
+     data = (struct sunxi_mmc_config *)dev_get_driver_data(dev);
      priv->reg = (void *)dev_read_addr(dev);
      priv->mmc_no = (((uintptr_t)priv->reg / 0x1000) - 0x1C0F);
 
@@ -600,9 +611,15 @@ static int sunxi_mmc_probe(struct udevice *dev)
      if (IS_ERR(ccm))
              return PTR_ERR(ccm);
 
+     priv->reg_reset0 = (void *)ccm + data->off_reset0;
+
      /* enable ahb gate */
      setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));
 
+     /* unassert reset */
+     if (data->has_reset0)
+             setbits_le32(priv->reg_reset0, BIT(data->pos_reset0 + priv->mmc_no));
+
      /* find clock reg */
      switch (priv->mmc_no) {
      case 0:
@@ -653,10 +670,23 @@ static int sunxi_mmc_bind(struct udevice *dev)
      return mmc_bind(dev, &plat->mmc, &plat->cfg);
 }
 
Quoted 11 lines

drivers/mmc/sunxi_mmc.c static int sunxi_mmc_bind(struct udevice *dev) · line 681

Quoted 9 lines
drivers/mmc/sunxi_mmc.c +9 -0
+static const struct sunxi_mmc_config sun4i_a10_cfg = {
+     .has_reset0 = false,
+};
+
+static const struct sunxi_mmc_config sun7i_a20_cfg = {
+     .has_reset0 = true,
+     .pos_reset0 = 8,
+     .off_reset0 = OFF_SUN6I_AHB_RESET0,
+};

Nope. The A20 doesn't have any reset line.

Yes, I know. but sun6i-a31 has it and share same compatible allwinner,sun7i-a20-mmc ie reason I've attached driver data.

#12 lore raw

PATCH 6/25 dm: mmc: sunxi: Add ahb reset0 register write

Quoted 88 lines · Jagan Teki
Quoted 74 lines · Maxime Ripard
Quoted 73 lines · Jagan Teki

AHB reset0 is needed for Allwinner start from sun6i, so add driver data configuration for ahb reset0 and update the register bits during probe.

Cc Jaehoon Chung <[email protected]>
---
 drivers/mmc/sunxi_mmc.c | 36 +++++++++++++++++++++++++++++++++---
 1 file changed, 33 insertions(+), 3 deletions(-)
drivers/mmc/sunxi_mmc.c +17 -0
index 38171b81f3..beeded50af 100644
@@ -30,6 +30,7 @@ struct sunxi_mmc_priv {
      unsigned fatal_err;
      struct gpio_desc cd_gpio;       /* Change Detect GPIO */
      int cd_inverted;                /* Inverted Card Detect */
+     u32 *reg_reset0;
      struct sunxi_mmc *reg;
      struct mmc_config cfg;
 };
@@ -528,6 +529,14 @@ struct mmc *sunxi_mmc_init(int sdc_no)
 }
 #else
 
+#define OFF_SUN6I_AHB_RESET0 0x2c0
+
+struct sunxi_mmc_config {
+     bool has_reset0;
+     u8 pos_reset0;
+     u32 off_reset0;
+};
+
 static int sunxi_mmc_set_ios(struct udevice *dev)
 {
      struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
@@ -569,6 +578,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
      struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
      struct sunxi_mmc_priv *priv = dev_get_priv(dev);
      struct mmc_config *cfg = &plat->cfg;
+     const struct sunxi_mmc_config *data;
      struct sunxi_ccm_reg *ccm;
      struct ofnode_phandle_args args;
      int bus_width, ret;
@@ -588,6 +598,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
      cfg->f_min = 400000;
      cfg->f_max = 52000000;
 
+     data = (struct sunxi_mmc_config *)dev_get_driver_data(dev);
      priv->reg = (void *)dev_read_addr(dev);
      priv->mmc_no = (((uintptr_t)priv->reg / 0x1000) - 0x1C0F);
 
@@ -600,9 +611,15 @@ static int sunxi_mmc_probe(struct udevice *dev)
      if (IS_ERR(ccm))
              return PTR_ERR(ccm);
 
+     priv->reg_reset0 = (void *)ccm + data->off_reset0;
+
      /* enable ahb gate */
      setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));
 
+     /* unassert reset */
+     if (data->has_reset0)
+             setbits_le32(priv->reg_reset0, BIT(data->pos_reset0 + priv->mmc_no));
+
      /* find clock reg */
      switch (priv->mmc_no) {
      case 0:
@@ -653,10 +670,23 @@ static int sunxi_mmc_bind(struct udevice *dev)
      return mmc_bind(dev, &plat->mmc, &plat->cfg);
 }
 
Quoted 11 lines

drivers/mmc/sunxi_mmc.c static int sunxi_mmc_bind(struct udevice *dev) · line 681

Quoted 9 lines
drivers/mmc/sunxi_mmc.c +9 -0
+static const struct sunxi_mmc_config sun4i_a10_cfg = {
+     .has_reset0 = false,
+};
+
+static const struct sunxi_mmc_config sun7i_a20_cfg = {
+     .has_reset0 = true,
+     .pos_reset0 = 8,
+     .off_reset0 = OFF_SUN6I_AHB_RESET0,
+};

Nope. The A20 doesn't have any reset line.

Quoted 2 lines

Yes, I know. but sun6i-a31 has it and share same compatible allwinner,sun7i-a20-mmc ie reason I've attached driver data.

That doesn't make it more correct. The A20 doesn't have a reset line, I don't see any good reason to imply this.

Maxime

Signature · 10 lines
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180716/50871cd7/attachment.sig>
#13 lore raw

PATCH 6/25 dm: mmc: sunxi: Add ahb reset0 register write

Quoted 89 lines · Maxime Ripard
Quoted 88 lines · Jagan Teki
Quoted 85 lines · Maxime Ripard
Quoted 72 lines · Jagan Teki

AHB reset0 is needed for Allwinner start from sun6i, so add driver data configuration for ahb reset0 and update the register bits during probe.

Cc Jaehoon Chung <[email protected]>
---
 drivers/mmc/sunxi_mmc.c | 36 +++++++++++++++++++++++++++++++++---
 1 file changed, 33 insertions(+), 3 deletions(-)
drivers/mmc/sunxi_mmc.c +17 -0
index 38171b81f3..beeded50af 100644
@@ -30,6 +30,7 @@ struct sunxi_mmc_priv {
      unsigned fatal_err;
      struct gpio_desc cd_gpio;       /* Change Detect GPIO */
      int cd_inverted;                /* Inverted Card Detect */
+     u32 *reg_reset0;
      struct sunxi_mmc *reg;
      struct mmc_config cfg;
 };
@@ -528,6 +529,14 @@ struct mmc *sunxi_mmc_init(int sdc_no)
 }
 #else
 
+#define OFF_SUN6I_AHB_RESET0 0x2c0
+
+struct sunxi_mmc_config {
+     bool has_reset0;
+     u8 pos_reset0;
+     u32 off_reset0;
+};
+
 static int sunxi_mmc_set_ios(struct udevice *dev)
 {
      struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
@@ -569,6 +578,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
      struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
      struct sunxi_mmc_priv *priv = dev_get_priv(dev);
      struct mmc_config *cfg = &plat->cfg;
+     const struct sunxi_mmc_config *data;
      struct sunxi_ccm_reg *ccm;
      struct ofnode_phandle_args args;
      int bus_width, ret;
@@ -588,6 +598,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
      cfg->f_min = 400000;
      cfg->f_max = 52000000;
 
+     data = (struct sunxi_mmc_config *)dev_get_driver_data(dev);
      priv->reg = (void *)dev_read_addr(dev);
      priv->mmc_no = (((uintptr_t)priv->reg / 0x1000) - 0x1C0F);
 
@@ -600,9 +611,15 @@ static int sunxi_mmc_probe(struct udevice *dev)
      if (IS_ERR(ccm))
              return PTR_ERR(ccm);
 
+     priv->reg_reset0 = (void *)ccm + data->off_reset0;
+
      /* enable ahb gate */
      setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));
 
+     /* unassert reset */
+     if (data->has_reset0)
+             setbits_le32(priv->reg_reset0, BIT(data->pos_reset0 + priv->mmc_no));
+
      /* find clock reg */
      switch (priv->mmc_no) {
      case 0:
@@ -653,10 +670,23 @@ static int sunxi_mmc_bind(struct udevice *dev)
      return mmc_bind(dev, &plat->mmc, &plat->cfg);
 }

drivers/mmc/sunxi_mmc.c static int sunxi_mmc_bind(struct udevice *dev) · line 681

Quoted 10 lines
drivers/mmc/sunxi_mmc.c +9 -0
 
+static const struct sunxi_mmc_config sun4i_a10_cfg = {
+     .has_reset0 = false,
+};
+
+static const struct sunxi_mmc_config sun7i_a20_cfg = {
+     .has_reset0 = true,
+     .pos_reset0 = 8,
+     .off_reset0 = OFF_SUN6I_AHB_RESET0,
+};

Nope. The A20 doesn't have any reset line.

Quoted 5 lines
Quoted 2 lines

Yes, I know. but sun6i-a31 has it and share same compatible allwinner,sun7i-a20-mmc ie reason I've attached driver data.

That doesn't make it more correct. The A20 doesn't have a reset line, I don't see any good reason to imply this.

OK, let me know if you have any suggestion on this I will remove this for A20.

#14 lore raw

PATCH 6/25 dm: mmc: sunxi: Add ahb reset0 register write

Quoted 91 lines · Jagan Teki
Quoted 89 lines · Maxime Ripard
Quoted 88 lines · Jagan Teki
Quoted 85 lines · Maxime Ripard
Quoted 72 lines · Jagan Teki

AHB reset0 is needed for Allwinner start from sun6i, so add driver data configuration for ahb reset0 and update the register bits during probe.

Cc Jaehoon Chung <[email protected]>
---
 drivers/mmc/sunxi_mmc.c | 36 +++++++++++++++++++++++++++++++++---
 1 file changed, 33 insertions(+), 3 deletions(-)
drivers/mmc/sunxi_mmc.c +17 -0
index 38171b81f3..beeded50af 100644
@@ -30,6 +30,7 @@ struct sunxi_mmc_priv {
      unsigned fatal_err;
      struct gpio_desc cd_gpio;       /* Change Detect GPIO */
      int cd_inverted;                /* Inverted Card Detect */
+     u32 *reg_reset0;
      struct sunxi_mmc *reg;
      struct mmc_config cfg;
 };
@@ -528,6 +529,14 @@ struct mmc *sunxi_mmc_init(int sdc_no)
 }
 #else
 
+#define OFF_SUN6I_AHB_RESET0 0x2c0
+
+struct sunxi_mmc_config {
+     bool has_reset0;
+     u8 pos_reset0;
+     u32 off_reset0;
+};
+
 static int sunxi_mmc_set_ios(struct udevice *dev)
 {
      struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
@@ -569,6 +578,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
      struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
      struct sunxi_mmc_priv *priv = dev_get_priv(dev);
      struct mmc_config *cfg = &plat->cfg;
+     const struct sunxi_mmc_config *data;
      struct sunxi_ccm_reg *ccm;
      struct ofnode_phandle_args args;
      int bus_width, ret;
@@ -588,6 +598,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
      cfg->f_min = 400000;
      cfg->f_max = 52000000;
 
+     data = (struct sunxi_mmc_config *)dev_get_driver_data(dev);
      priv->reg = (void *)dev_read_addr(dev);
      priv->mmc_no = (((uintptr_t)priv->reg / 0x1000) - 0x1C0F);
 
@@ -600,9 +611,15 @@ static int sunxi_mmc_probe(struct udevice *dev)
      if (IS_ERR(ccm))
              return PTR_ERR(ccm);
 
+     priv->reg_reset0 = (void *)ccm + data->off_reset0;
+
      /* enable ahb gate */
      setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));
 
+     /* unassert reset */
+     if (data->has_reset0)
+             setbits_le32(priv->reg_reset0, BIT(data->pos_reset0 + priv->mmc_no));
+
      /* find clock reg */
      switch (priv->mmc_no) {
      case 0:
@@ -653,10 +670,23 @@ static int sunxi_mmc_bind(struct udevice *dev)
      return mmc_bind(dev, &plat->mmc, &plat->cfg);
 }

drivers/mmc/sunxi_mmc.c static int sunxi_mmc_bind(struct udevice *dev) · line 681

Quoted 10 lines
drivers/mmc/sunxi_mmc.c +9 -0
 
+static const struct sunxi_mmc_config sun4i_a10_cfg = {
+     .has_reset0 = false,
+};
+
+static const struct sunxi_mmc_config sun7i_a20_cfg = {
+     .has_reset0 = true,
+     .pos_reset0 = 8,
+     .off_reset0 = OFF_SUN6I_AHB_RESET0,
+};

Nope. The A20 doesn't have any reset line.

Quoted 8 lines
Quoted 5 lines
Quoted 2 lines

Yes, I know. but sun6i-a31 has it and share same compatible allwinner,sun7i-a20-mmc ie reason I've attached driver data.

That doesn't make it more correct. The A20 doesn't have a reset line, I don't see any good reason to imply this.

OK, let me know if you have any suggestion on this I will remove this for A20.

Use the A31 name and tie it to the matching compatible instead?

Signature · 10 lines
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180716/ac4d3283/attachment.sig>
author
#15 lore raw

PATCH 7/25 ARM: dts: sun7i: Sync A20 MMC nodes from Linux

In reply to Jagan Teki

DM_MMC need MMC nodes in dtsi need to update and follow Linux notation to support dm driven mmc driver. So sync mmc nodes for sun7i-a20 from Linux. This will also useful for CLK driver handling in future.

Last linux commit for sun7i-a20.dtsi:
commit e3b742026b92a141b43560858b089921953a63de

Author: Viresh Kumar <[email protected]>
Date:   Tue Jun 5 10:17:49 2018 +0530

ARM: dts: sunxi: Add missing cooling device properties for CPUs

Last linux commit for sun7i-a20-ccu.h:
commit c84f5683f6e9fee78e054431d89121225ccb7464

Author: Priit Laes <[email protected]>
Date:   Wed Aug 23 20:23:29 2017 +0300

clk: sunxi-ng: Add sun4i/sun7i CCU driver

Cc Stefan Mavrodiev <[email protected]>
---
 arch/arm/dts/sun7i-a20.dtsi               | 102 ++++++++--------------
 include/dt-bindings/clock/sun7i-a20-ccu.h |  53 +++++++++++
 2 files changed, 87 insertions(+), 68 deletions(-)
 create mode 100644 include/dt-bindings/clock/sun7i-a20-ccu.h
arch/arm/dts/sun7i-a20.dtsi +34 -68
index 4394711e5a..620e4d5a21 100644
@@ -49,6 +49,7 @@
 
 #include <dt-bindings/clock/sun4i-a10-pll2.h>
 #include <dt-bindings/dma/sun4i-a10.h>
+#include <dt-bindings/clock/sun7i-a20-ccu.h>
 #include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
@@ -419,46 +420,6 @@
 			clock-output-names = "ms";
 		};
 
-		mmc0_clk: clk at 01c20088 {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun4i-a10-mmc-clk";
-			reg = <0x01c20088 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-			clock-output-names = "mmc0",
-					     "mmc0_output",
-					     "mmc0_sample";
-		};
-
-		mmc1_clk: clk at 01c2008c {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun4i-a10-mmc-clk";
-			reg = <0x01c2008c 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-			clock-output-names = "mmc1",
-					     "mmc1_output",
-					     "mmc1_sample";
-		};
-
-		mmc2_clk: clk at 01c20090 {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun4i-a10-mmc-clk";
-			reg = <0x01c20090 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-			clock-output-names = "mmc2",
-					     "mmc2_output",
-					     "mmc2_sample";
-		};
-
-		mmc3_clk: clk at 01c20094 {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun4i-a10-mmc-clk";
-			reg = <0x01c20094 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-			clock-output-names = "mmc3",
-					     "mmc3_output",
-					     "mmc3_sample";
-		};
-
 		ts_clk: clk at 01c20098 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-mod0-clk";
@@ -904,14 +865,13 @@
 			#size-cells = <0>;
 		};
 
-		mmc0: mmc at 01c0f000 {
-			compatible = "allwinner,sun7i-a20-mmc",
-				     "allwinner,sun5i-a13-mmc";
+		mmc0: mmc at 1c0f000 {
+			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c0f000 0x1000>;
-			clocks = <&ahb_gates 8>,
-				 <&mmc0_clk 0>,
-				 <&mmc0_clk 1>,
-				 <&mmc0_clk 2>;
+			clocks = <&ccu CLK_AHB_MMC0>,
+				 <&ccu CLK_MMC0>,
+				 <&ccu CLK_MMC0_OUTPUT>,
+				 <&ccu CLK_MMC0_SAMPLE>;
 			clock-names = "ahb",
 				      "mmc",
 				      "output",
@@ -922,14 +882,13 @@
 			#size-cells = <0>;
 		};
 
-		mmc1: mmc at 01c10000 {
-			compatible = "allwinner,sun7i-a20-mmc",
-				     "allwinner,sun5i-a13-mmc";
+		mmc1: mmc at 1c10000 {
+			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c10000 0x1000>;
-			clocks = <&ahb_gates 9>,
-				 <&mmc1_clk 0>,
-				 <&mmc1_clk 1>,
-				 <&mmc1_clk 2>;
+			clocks = <&ccu CLK_AHB_MMC1>,
+				 <&ccu CLK_MMC1>,
+				 <&ccu CLK_MMC1_OUTPUT>,
+				 <&ccu CLK_MMC1_SAMPLE>;
 			clock-names = "ahb",
 				      "mmc",
 				      "output",
@@ -940,14 +899,13 @@
 			#size-cells = <0>;
 		};
 
-		mmc2: mmc at 01c11000 {
-			compatible = "allwinner,sun7i-a20-mmc",
-				     "allwinner,sun5i-a13-mmc";
+		mmc2: mmc at 1c11000 {
+			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c11000 0x1000>;
-			clocks = <&ahb_gates 10>,
-				 <&mmc2_clk 0>,
-				 <&mmc2_clk 1>,
-				 <&mmc2_clk 2>;
+			clocks = <&ccu CLK_AHB_MMC2>,
+				 <&ccu CLK_MMC2>,
+				 <&ccu CLK_MMC2_OUTPUT>,
+				 <&ccu CLK_MMC2_SAMPLE>;
 			clock-names = "ahb",
 				      "mmc",
 				      "output",
@@ -958,14 +916,13 @@
 			#size-cells = <0>;
 		};
 
-		mmc3: mmc at 01c12000 {
-			compatible = "allwinner,sun7i-a20-mmc",
-				     "allwinner,sun5i-a13-mmc";
+		mmc3: mmc at 1c12000 {
+			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c12000 0x1000>;
-			clocks = <&ahb_gates 11>,
-				 <&mmc3_clk 0>,
-				 <&mmc3_clk 1>,
-				 <&mmc3_clk 2>;
+			clocks = <&ccu CLK_AHB_MMC3>,
+				 <&ccu CLK_MMC3>,
+				 <&ccu CLK_MMC3_OUTPUT>,
+				 <&ccu CLK_MMC3_SAMPLE>;
 			clock-names = "ahb",
 				      "mmc",
 				      "output",
@@ -1085,6 +1042,15 @@
 			#size-cells = <0>;
 		};
 
+		ccu: clock at 1c20000 {
+			compatible = "allwinner,sun7i-a20-ccu";
+			reg = <0x01c20000 0x400>;
+			clocks = <&osc24M>, <&osc32k>;
+			clock-names = "hosc", "losc";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
 		pio: pinctrl at 01c20800 {
 			compatible = "allwinner,sun7i-a20-pinctrl";
 			reg = <0x01c20800 0x400>;
include/dt-bindings/clock/sun7i-a20-ccu.h new file +53 -0

53 lines not on this page · raw message

Signature · 1 line
2.17.1
author
#16 lore raw

PATCH 8/25 ARM: dts: sun7i: Add mmc0 node for Primo73 tablet

In reply to Jagan Teki

Reuse mmc0 node from sun7i-a20.dtsi like other board dts files for Primo73 tablet dts file, and drop in dts mmc0 definition.

Cc Siarhei Siamashka <[email protected]>
---
 arch/arm/dts/sun7i-a20-primo73.dts | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)
arch/arm/dts/sun7i-a20-primo73.dts +10 -10
index 0658f82675..942a955309 100644
@@ -62,16 +62,6 @@
 	};
 
 	soc at 01c00000 {
-		mmc0: mmc at 01c0f000 {
-			pinctrl-names = "default";
-			pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
-			vmmc-supply = <&reg_vcc3v3>;
-			bus-width = <4>;
-			cd-gpios = <&pio 7 1 0>; /* PH1 */
-			cd-inverted;
-			status = "okay";
-		};
-
 		usbphy: phy at 01c13400 {
 			usb2_vbus-supply = <&reg_usb2_vbus>;
 			status = "okay";
@@ -100,3 +90,13 @@
 		status = "okay";
 	};
 };
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+	cd-inverted;
+	status = "okay";
+};
Signature · 1 line
2.17.1
#17 lore raw

PATCH 8/25 ARM: dts: sun7i: Add mmc0 node for Primo73 tablet

Quoted 35 lines · Jagan Teki

Reuse mmc0 node from sun7i-a20.dtsi like other board dts files for Primo73 tablet dts file, and drop in dts mmc0 definition.

Cc Siarhei Siamashka <[email protected]>
---
 arch/arm/dts/sun7i-a20-primo73.dts | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)
arch/arm/dts/sun7i-a20-primo73.dts +0 -10
index 0658f82675..942a955309 100644
@@ -62,16 +62,6 @@
 	};
 
 	soc at 01c00000 {
-		mmc0: mmc at 01c0f000 {
-			pinctrl-names = "default";
-			pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
-			vmmc-supply = <&reg_vcc3v3>;
-			bus-width = <4>;
-			cd-gpios = <&pio 7 1 0>; /* PH1 */
-			cd-inverted;
-			status = "okay";
-		};
-
 		usbphy: phy at 01c13400 {
 			usb2_vbus-supply = <&reg_usb2_vbus>;
 			status = "okay";
@@ -100,3 +90,13 @@
 		status = "okay";
 	};
 };

arch/arm/dts/sun7i-a20-primo73.dts line 102

Quoted 10 lines
arch/arm/dts/sun7i-a20-primo73.dts +10 -0
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+	cd-inverted;
+	status = "okay";
+};

You're not adding the node, you're just moving it around.

Maxime

Signature · 10 lines
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180716/350caa28/attachment.sig>
#18 lore raw

PATCH 8/25 ARM: dts: sun7i: Add mmc0 node for Primo73 tablet

Quoted 40 lines · Maxime Ripard
Quoted 39 lines · Jagan Teki

Reuse mmc0 node from sun7i-a20.dtsi like other board dts files for Primo73 tablet dts file, and drop in dts mmc0 definition.

Cc Siarhei Siamashka <[email protected]>
---
 arch/arm/dts/sun7i-a20-primo73.dts | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)
arch/arm/dts/sun7i-a20-primo73.dts +4 -10
index 0658f82675..942a955309 100644
@@ -62,16 +62,6 @@
      };
 
      soc at 01c00000 {
-             mmc0: mmc at 01c0f000 {
-                     pinctrl-names = "default";
-                     pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
-                     vmmc-supply = <&reg_vcc3v3>;
-                     bus-width = <4>;
-                     cd-gpios = <&pio 7 1 0>; /* PH1 */
-                     cd-inverted;
-                     status = "okay";
-             };
-
              usbphy: phy at 01c13400 {
                      usb2_vbus-supply = <&reg_usb2_vbus>;
                      status = "okay";
@@ -100,3 +90,13 @@
              status = "okay";
      };
 };
+
+&mmc0 {
+     pinctrl-names = "default";
+     pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
Quoted 8 lines

arch/arm/dts/sun7i-a20-primo73.dts line 102

Quoted 6 lines
arch/arm/dts/sun7i-a20-primo73.dts +6 -0
+     vmmc-supply = <&reg_vcc3v3>;
+     bus-width = <4>;
+     cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+     cd-inverted;
+     status = "okay";
+};

You're not adding the node, you're just moving it around.

ie what I mentioned on the commit message. adding mmc0 node like other board dts files and removing in dts mmc0 node definition.

#19 lore raw

PATCH 8/25 ARM: dts: sun7i: Add mmc0 node for Primo73 tablet

Quoted 51 lines · Jagan Teki
Quoted 40 lines · Maxime Ripard
Quoted 39 lines · Jagan Teki

Reuse mmc0 node from sun7i-a20.dtsi like other board dts files for Primo73 tablet dts file, and drop in dts mmc0 definition.

Cc Siarhei Siamashka <[email protected]>
---
 arch/arm/dts/sun7i-a20-primo73.dts | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)
arch/arm/dts/sun7i-a20-primo73.dts +4 -10
index 0658f82675..942a955309 100644
@@ -62,16 +62,6 @@
      };
 
      soc at 01c00000 {
-             mmc0: mmc at 01c0f000 {
-                     pinctrl-names = "default";
-                     pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
-                     vmmc-supply = <&reg_vcc3v3>;
-                     bus-width = <4>;
-                     cd-gpios = <&pio 7 1 0>; /* PH1 */
-                     cd-inverted;
-                     status = "okay";
-             };
-
              usbphy: phy at 01c13400 {
                      usb2_vbus-supply = <&reg_usb2_vbus>;
                      status = "okay";
@@ -100,3 +90,13 @@
              status = "okay";
      };
 };
+
+&mmc0 {
+     pinctrl-names = "default";
+     pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
Quoted 8 lines

arch/arm/dts/sun7i-a20-primo73.dts line 102

Quoted 6 lines
arch/arm/dts/sun7i-a20-primo73.dts +6 -0
+     vmmc-supply = <&reg_vcc3v3>;
+     bus-width = <4>;
+     cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+     cd-inverted;
+     status = "okay";
+};

You're not adding the node, you're just moving it around.

Quoted 2 lines

ie what I mentioned on the commit message. adding mmc0 node like other board dts files and removing in dts mmc0 node definition.

If you understand the device tree, you'll know that they are one and the same. They compile down to the same node. Otherwise the original pattern wouldn't work.

The commit message should read something more like:

xxx: Convert to DT label based syntax

In order to lessen the amount of duplication of the DT tree, ease the new and follow the trend that prefers to use label based references when overriding DTSI nodes, convert the board to this syntax

This was the commit message in a whole slew of patches that Maxime did to convert all the sunxi device tree files in the kernel.

Better yet, just drop all these conversion patches and just sync up to Linux 4.18-rc1.

ChenYu

author
#20 lore raw

PATCH 9/25 ARM: dts: sun7i: Add mmc0 node for Ainol AW1

In reply to Jagan Teki

Since SUN7I moved to DM_MMC, we need to have mmc node in Ainol AW1 DT otherwise it will not probe.

Cc Paul Kocialkowski <[email protected]>
---
 arch/arm/dts/sun7i-a20-ainol-aw1.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)
arch/arm/dts/sun7i-a20-ainol-aw1.dts +13 -0
index 57fe0066cb..3831adc88d 100644
@@ -7,6 +7,9 @@
 
 /dts-v1/;
 #include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "Ainol AW1";
@@ -21,6 +24,16 @@
 	};
 };
 
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+	cd-inverted;
+	status = "okay";
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pins_a>;
Signature · 1 line
2.17.1
author
#21 lore raw

PATCH 10/25 ARM: dts: sun7i: Add mmc0 node for Mele M5

In reply to Jagan Teki

Since SUN7I moved to DM_MMC, we need to have mmc node in Mele M5 DT otherwise it will not probe.

---
 arch/arm/dts/sun7i-a20-m5.dts | 12 ++++++++++++
 1 file changed, 12 insertions(+)
arch/arm/dts/sun7i-a20-m5.dts +12 -0
index 00c3ffd323..8014ebc310 100644
@@ -7,6 +7,8 @@
 
 /dts-v1/;
 #include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "Mele M5";
@@ -41,6 +43,16 @@
 	};
 };
 
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+	cd-inverted;
+	status = "okay";
+};
+
 &ohci0 {
 	status = "okay";
 };
Signature · 1 line
2.17.1
author
#22 lore raw

PATCH 11/25 ARM: dts: sun7i: Add mmc0 node for Toptech BD1078

In reply to Jagan Teki

Since SUN7I moved to DM_MMC, we need to have mmc node in Toptech BD1078 DT otherwise it will not probe.

Cc Paul Kocialkowski <[email protected]>
---
 arch/arm/dts/sun7i-a20-yones-toptech-bd1078.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)
arch/arm/dts/sun7i-a20-yones-toptech-bd1078.dts +13 -0
index f1fb97d3fb..89c8cf60b1 100644
@@ -7,6 +7,9 @@
 
 /dts-v1/;
 #include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
 	model = "Yones Toptech BD1078";
@@ -21,6 +24,16 @@
 	};
 };
 
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+	cd-inverted;
+	status = "okay";
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pins_a>;
Signature · 1 line
2.17.1
author
#23 lore raw

PATCH 12/25 sunxi: A20: Enable DM_MMC

In reply to Jagan Teki

Enable DM_MMC for Allwinner A20 SoC.

Tested on A20-OLinuXino-LIME2.

Cc Stefan Mavrodiev <[email protected]>
---
 arch/arm/mach-sunxi/Kconfig | 1 +
 1 file changed, 1 insertion(+)
arch/arm/mach-sunxi/Kconfig +1 -0
index 678e33dd40..7d1184306f 100644
@@ -180,6 +180,7 @@ config MACH_SUN7I
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
 	select DRAM_SUN4I
+	select DM_MMC if MMC
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL
Signature · 1 line
2.17.1
author
#24 lore raw

PATCH 13/25 mmc: sunxi: Add mmc, emmc H5/A64 compatible

In reply to Jagan Teki

Added H5, A64 compatible for mmc and emmc.

---
 drivers/mmc/sunxi_mmc.c | 4 ++++
 1 file changed, 4 insertions(+)
drivers/mmc/sunxi_mmc.c +4 -0
index beeded50af..16e94cf4b7 100644
@@ -687,6 +687,10 @@ static const struct udevice_id sunxi_mmc_ids[] = {
 			.data = (ulong)&sun4i_a10_cfg },
 	{ .compatible = "allwinner,sun7i-a20-mmc",
 			.data = (ulong)&sun7i_a20_cfg },
+	{ .compatible = "allwinner,sun50i-a64-mmc",
+			.data = (ulong)&sun7i_a20_cfg },
+	{ .compatible = "allwinner,sun50i-a64-emmc",
+			.data = (ulong)&sun7i_a20_cfg },
 	{ }
 };
 
Signature · 1 line
2.17.1
author
#25 lore raw

PATCH 14/25 sunxi: H3_H5: Enable DM_MMC

In reply to Jagan Teki

Enable DM_MMC for Allwinner H3/H5 SoCs.

Tested on
H3: BPI-M2+
H5: Orangepi pc2, prime, zero+2

---
 arch/arm/mach-sunxi/Kconfig | 1 +
 1 file changed, 1 insertion(+)
arch/arm/mach-sunxi/Kconfig +1 -0
index 7d1184306f..a1ee431700 100644
@@ -127,6 +127,7 @@ endif
 config MACH_SUNXI_H3_H5
 	bool
 	select DM_I2C
+	select DM_MMC if MMC
 	select PHY_SUN4I_USB
 	select SUNXI_DE2
 	select SUNXI_DRAM_DW
Signature · 1 line
2.17.1
author
#26 lore raw

PATCH 15/25 sunxi: A64: Enable DM_MMC

In reply to Jagan Teki

Enable DM_MMC for Allwinner A64 SoCs.

Tested on BPI-M64, Amarula A64-Relic

---
 arch/arm/mach-sunxi/Kconfig | 1 +
 1 file changed, 1 insertion(+)
arch/arm/mach-sunxi/Kconfig +1 -0
index a1ee431700..3b790e39dd 100644
@@ -268,6 +268,7 @@ config MACH_SUN50I
 	bool "sun50i (Allwinner A64)"
 	select ARM64
 	select DM_I2C
+	select DM_MMC if MMC
 	select PHY_SUN4I_USB
 	select SUNXI_DE2
 	select SUNXI_GEN_SUN6I
Signature · 1 line
2.17.1
author
#27 lore raw

PATCH 16/25 ARM: dts: sun8i: Update A83T dts(i) files from Linux

In reply to Jagan Teki

Update all A83T devicetree dtsi and dtsi files from Linux with below commit:
commit 221cb9fd2ee3042689fe0e6613d0f34eb46a5af6

Author: Mylène Josserand <[email protected]>
Date:   Fri May 4 21:05:44 2018 +0200

ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC

Note: bananapi-m3 and cubietruck-plus board dts files has usb_otg enabled in U-Boot which were not present in Linux.

---
 arch/arm/dts/axp81x.dtsi                      | 169 ++++
 .../dts/sun8i-a83t-allwinner-h8homlet-v2.dts  | 195 +++-
 arch/arm/dts/sun8i-a83t-bananapi-m3.dts       | 298 +++++-
 arch/arm/dts/sun8i-a83t-cubietruck-plus.dts   | 322 ++++++-
 arch/arm/dts/sun8i-a83t-tbs-a711.dts          | 355 ++++++-
 arch/arm/dts/sun8i-a83t.dtsi                  | 885 ++++++++++++++++--
 include/dt-bindings/clock/sun8i-a83t-ccu.h    | 140 +++
 include/dt-bindings/reset/sun8i-a83t-ccu.h    |  98 ++
 8 files changed, 2382 insertions(+), 80 deletions(-)
 create mode 100644 arch/arm/dts/axp81x.dtsi
 create mode 100644 include/dt-bindings/clock/sun8i-a83t-ccu.h
 create mode 100644 include/dt-bindings/reset/sun8i-a83t-ccu.h
arch/arm/dts/axp81x.dtsi new file +169 -0
new file mode 100644
index 0000000000..043c717dce
@@ -0,0 +1,169 @@
+/*
+ * Copyright 2017 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <[email protected]>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/* AXP813/818 Integrated Power Management Chip */
+
+&axp81x {
+	interrupt-controller;
+	#interrupt-cells = <1>;
+
+	axp_adc: adc {
+		compatible = "x-powers,axp813-adc";
+		#io-channel-cells = <1>;
+	};
+
+	axp_gpio: gpio {
+		compatible = "x-powers,axp813-gpio";
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		gpio0_ldo: gpio0-ldo {
+			pins = "GPIO0";
+			function = "ldo";
+		};
+
+		gpio1_ldo: gpio1-ldo {
+			pins = "GPIO1";
+			function = "ldo";
+		};
+	};
+
+	battery_power_supply: battery-power-supply {
+		compatible = "x-powers,axp813-battery-power-supply";
+		status = "disabled";
+	};
+
+	regulators {
+		/* Default work frequency for buck regulators */
+		x-powers,dcdc-freq = <3000>;
+
+		reg_dcdc1: dcdc1 {
+		};
+
+		reg_dcdc2: dcdc2 {
+		};
+
+		reg_dcdc3: dcdc3 {
+		};
+
+		reg_dcdc4: dcdc4 {
+		};
+
+		reg_dcdc5: dcdc5 {
+		};
+
+		reg_dcdc6: dcdc6 {
+		};
+
+		reg_dcdc7: dcdc7 {
+		};
+
+		reg_aldo1: aldo1 {
+		};
+
+		reg_aldo2: aldo2 {
+		};
+
+		reg_aldo3: aldo3 {
+		};
+
+		reg_dldo1: dldo1 {
+		};
+
+		reg_dldo2: dldo2 {
+		};
+
+		reg_dldo3: dldo3 {
+		};
+
+		reg_dldo4: dldo4 {
+		};
+
+		reg_eldo1: eldo1 {
+		};
+
+		reg_eldo2: eldo2 {
+		};
+
+		reg_eldo3: eldo3 {
+		};
+
+		reg_fldo1: fldo1 {
+		};
+
+		reg_fldo2: fldo2 {
+		};
+
+		reg_fldo3: fldo3 {
+		};
+
+		reg_ldo_io0: ldo-io0 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&gpio0_ldo>;
+			/* Disable by default to avoid conflicts with GPIO */
+			status = "disabled";
+		};
+
+		reg_ldo_io1: ldo-io1 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&gpio1_ldo>;
+			/* Disable by default to avoid conflicts with GPIO */
+			status = "disabled";
+		};
+
+		reg_rtc_ldo: rtc-ldo {
+			/* RTC_LDO is a fixed, always-on regulator */
+			regulator-always-on;
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		reg_sw: sw {
+		};
+
+		reg_drivevbus: drivevbus {
+			status = "disabled";
+		};
+	};
+};
arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts +194 -1

222 lines not on this page · raw message

arch/arm/dts/sun8i-a83t-bananapi-m3.dts +293 -5

328 lines not on this page · raw message

arch/arm/dts/sun8i-a83t-cubietruck-plus.dts +321 -1

354 lines not on this page · raw message

arch/arm/dts/sun8i-a83t-tbs-a711.dts +351 -4

390 lines not on this page · raw message

arch/arm/dts/sun8i-a83t.dtsi +816 -69

1,023 lines not on this page · raw message

include/dt-bindings/clock/sun8i-a83t-ccu.h new file +140 -0

140 lines not on this page · raw message

include/dt-bindings/reset/sun8i-a83t-ccu.h new file +98 -0

98 lines not on this page · raw message

Signature · 1 line
2.17.1
author
#28 lore raw

PATCH 17/25 mmc: sunxi: Add A83T emmc compatible

In reply to Jagan Teki

Add emmc compatible for A83T SoC.

Cc VishnuPatekar <[email protected]>
---
 drivers/mmc/sunxi_mmc.c | 2 ++
 1 file changed, 2 insertions(+)
drivers/mmc/sunxi_mmc.c +2 -0
index 16e94cf4b7..1e7bea4d5a 100644
@@ -687,6 +687,8 @@ static const struct udevice_id sunxi_mmc_ids[] = {
 			.data = (ulong)&sun4i_a10_cfg },
 	{ .compatible = "allwinner,sun7i-a20-mmc",
 			.data = (ulong)&sun7i_a20_cfg },
+	{ .compatible = "allwinner,sun8i-a83t-emmc",
+			.data = (ulong)&sun7i_a20_cfg },
 	{ .compatible = "allwinner,sun50i-a64-mmc",
 			.data = (ulong)&sun7i_a20_cfg },
 	{ .compatible = "allwinner,sun50i-a64-emmc",
Signature · 1 line
2.17.1
author
#29 lore raw

PATCH 18/25 sunxi: A83T: Enable DM_MMC

In reply to Jagan Teki

Enable DM_MMC for Allwinner A83T SoC.

Tested on BPI-M3.

Cc VishnuPatekar <[email protected]>
---
 arch/arm/mach-sunxi/Kconfig | 1 +
 1 file changed, 1 insertion(+)
arch/arm/mach-sunxi/Kconfig +1 -0
index 3b790e39dd..d5b0700e13 100644
@@ -216,6 +216,7 @@ config MACH_SUN8I_A33
 config MACH_SUN8I_A83T
 	bool "sun8i (Allwinner A83T)"
 	select CPU_V7A
+	select DM_MMC if MMC
 	select DRAM_SUN8I_A83T
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN6I
Signature · 1 line
2.17.1
author
#30 lore raw

PATCH 19/25 ARM: dts: sun8i: Update R40 dts(i) files from Linux

In reply to Jagan Teki

Update all R40 devicetree dtsi and dtsi files from Linux with below commit:
commit 6a7556f604f94461ca802ab69a6dad317c014d30

Author: Jernej Skrabec <[email protected]>
Date:   Tue Jul 10 22:35:09 2018 +0200

ARM: dts: sun8i: r40: Disable TCONs by default.

and BPI-M2 berry
commit c5f0bb472795170ab5c33be12e29ce7465fb31ed

Author: Icenowy Zheng <[email protected]>
Date:   Fri Apr 6 22:03:44 2018 +0800

ARM: sun8i: v40: enable USB host ports for Banana Pi M2 Berry

Cc Lothar Felten <[email protected]>
---
 arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts | 197 +++++-
 arch/arm/dts/sun8i-r40.dtsi                  | 616 ++++++++++++++++++-
 arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts |  50 ++
 3 files changed, 830 insertions(+), 33 deletions(-)
arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts +190 -7
index 28c9158302..c39b9169ea 100644
@@ -1,5 +1,6 @@
 /*
- * Copyright (C) 2016 Chen-Yu Tsai <[email protected]>
+ * Copyright (C) 2017 Chen-Yu Tsai <[email protected]>
+ * Copyright (C) 2017 Icenowy Zheng <[email protected]>
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
@@ -43,6 +44,8 @@
 /dts-v1/;
 #include "sun8i-r40.dtsi"
 
+#include <dt-bindings/gpio/gpio.h>
+
 / {
 	model = "Banana Pi BPI-M2-Ultra";
 	compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40";
@@ -55,17 +58,62 @@
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
+
+	connector {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		pwr-led {
+			label = "bananapi:red:pwr";
+			gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		user-led-green {
+			label = "bananapi:green:user";
+			gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
+		};
+
+		user-led-blue {
+			label = "bananapi:blue:user";
+			gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	reg_vcc5v0: vcc5v0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
+		enable-active-high;
+	};
+
+	wifi_pwrseq: wifi_pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
+	};
 };
 
-&i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins>;
+&de {
 	status = "okay";
 };
 
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pb_pins>;
+&ehci1 {
+	status = "okay";
+};
+
+&ehci2 {
 	status = "okay";
 };
 
@@ -74,6 +122,7 @@
 	pinctrl-0 = <&gmac_rgmii_pins>;
 	phy-handle = <&phy1>;
 	phy-mode = "rgmii";
+	phy-supply = <&reg_dc1sw>;
 	status = "okay";
 };
 
@@ -83,3 +132,137 @@
 		reg = <1>;
 	};
 };
+
+&hdmi {
+	status = "okay";
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+
+	axp22x: pmic at 34 {
+		compatible = "x-powers,axp221";
+		reg = <0x34>;
+		interrupt-parent = <&nmi_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+#include "axp22x.dtsi"
+
+&mmc0 {
+	vmmc-supply = <&reg_dcdc1>;
+	bus-width = <4>;
+	cd-gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */
+	cd-inverted;
+	status = "okay";
+};
+
+&mmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pg_pins>;
+	vmmc-supply = <&reg_dldo2>;
+	vqmmc-supply = <&reg_dldo1>;
+	mmc-pwrseq = <&wifi_pwrseq>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+};
+
+&mmc2 {
+	vmmc-supply = <&reg_dcdc1>;
+	vqmmc-supply = <&reg_dcdc1>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&ohci2 {
+	status = "okay";
+};
+
+&reg_aldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <2500000>;
+	regulator-max-microvolt = <2500000>;
+	regulator-name = "vcc-pa";
+};
+
+&reg_aldo3 {
+	regulator-always-on;
+	regulator-min-microvolt = <2700000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "avcc";
+};
+
+&reg_dc1sw {
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-gmac-phy";
+};
+
+&reg_dcdc1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-3v0";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1000000>;
+	regulator-max-microvolt = <1300000>;
+	regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc3 {
+	regulator-always-on;
+	regulator-min-microvolt = <1000000>;
+	regulator-max-microvolt = <1300000>;
+	regulator-name = "vdd-sys";
+};
+
+&reg_dcdc5 {
+	regulator-always-on;
+	regulator-min-microvolt = <1500000>;
+	regulator-max-microvolt = <1500000>;
+	regulator-name = "vcc-dram";
+};
+
+&reg_dldo1 {
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi-io";
+};
+
+&reg_dldo2 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi";
+};
+
+&tcon_tv0 {
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pb_pins>;
+	status = "okay";
+};
+
+&usbphy {
+	usb1_vbus-supply = <&reg_vcc5v0>;
+	usb2_vbus-supply = <&reg_vcc5v0>;
+	status = "okay";
+};
arch/arm/dts/sun8i-r40.dtsi +590 -26

723 lines not on this page · raw message

arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts +50 -0

64 lines not on this page · raw message

Signature · 1 line
2.17.1
author
#31 lore raw

PATCH 20/25 sunxi: V40: Enable DM_MMC

In reply to Jagan Teki

Enable DM_MMC for Allwinner V40 SoC.

Tested on BPI-M2 Ultra, BPI-M2 Berry.

Cc Lothar Felten <[email protected]>
---
 arch/arm/mach-sunxi/Kconfig | 1 +
 1 file changed, 1 insertion(+)
arch/arm/mach-sunxi/Kconfig +1 -0
index d5b0700e13..f3d7c8b67d 100644
@@ -238,6 +238,7 @@ config MACH_SUN8I_R40
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
+	select DM_MMC if MMC
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
 	select SUNXI_DRAM_DW
Signature · 1 line
2.17.1
author
#32 lore raw

PATCH 21/25 fastboot: sunxi: Update fastboot mmc default device

In reply to Jagan Teki

Usually eMMC is default env fat device for environment, if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc device as 1. but with DM_MMC it can be more possible to probe eMMC as device 2 since for most of the sunxi platforms eMMC is configured mmc2.

So update the fastboot mmc default device as 2 if DM_MMC and MMC_SUNXI_SLOT_EXTRA != 1 slot is 2 defined but some boards may not use all possible mmc devices or partly disabled in DT, for those update the device in board specific defconfig.

Cc Olliver Schinagl <[email protected]>
Cc Chen-Yu Tsai <[email protected]>
---
 configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
 configs/Sinlinx_SinA33_defconfig           | 1 +
 configs/amarula_a64_relic_defconfig        | 1 +
 drivers/fastboot/Kconfig                   | 3 ++-
 4 files changed, 5 insertions(+), 1 deletion(-)
configs/A20-OLinuXino-Lime2-eMMC_defconfig +1 -0
index 5657fc2594..20ea254191 100644
@@ -29,4 +29,5 @@ CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
configs/Sinlinx_SinA33_defconfig +1 -0
index 394534b8b5..7841219a65 100644
@@ -21,5 +21,6 @@ CONFIG_DFU_RAM=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
 CONFIG_USB_FUNCTION_MASS_STORAGE=y
configs/amarula_a64_relic_defconfig +1 -0
index b72cbfabc6..caeb3f6008 100644
@@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
drivers/fastboot/Kconfig +2 -1
index bc25ea1d9c..4a1bfd119c 100644
@@ -88,7 +88,8 @@ config FASTBOOT_FLASH_MMC_DEV
 	int "Define FASTBOOT MMC FLASH default device"
 	depends on FASTBOOT_FLASH_MMC
 	default 0 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
-	default 1 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
+	default 1 if ARCH_SUNXI && !DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
+	default 2 if ARCH_SUNXI && DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
 	help
 	  The fastboot "flash" command requires additional information
 	  regarding the non-volatile storage device. Define this to
Signature · 1 line
2.17.1
#33 lore raw

PATCH 21/25 fastboot: sunxi: Update fastboot mmc default device

Quoted 36 lines · Jagan Teki

Usually eMMC is default env fat device for environment, if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc device as 1. but with DM_MMC it can be more possible to probe eMMC as device 2 since for most of the sunxi platforms eMMC is configured mmc2.

So update the fastboot mmc default device as 2 if DM_MMC and MMC_SUNXI_SLOT_EXTRA != 1 slot is 2 defined but some boards may not use all possible mmc devices or partly disabled in DT, for those update the device in board specific defconfig.

Cc Olliver Schinagl <[email protected]>
Cc Chen-Yu Tsai <[email protected]>
---
 configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
 configs/Sinlinx_SinA33_defconfig           | 1 +
 configs/amarula_a64_relic_defconfig        | 1 +
 drivers/fastboot/Kconfig                   | 3 ++-
 4 files changed, 5 insertions(+), 1 deletion(-)
configs/A20-OLinuXino-Lime2-eMMC_defconfig +1 -0
index 5657fc2594..20ea254191 100644
@@ -29,4 +29,5 @@ CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
configs/Sinlinx_SinA33_defconfig +0 -0
index 394534b8b5..7841219a65 100644

configs/Sinlinx_SinA33_defconfig CONFIG_DFU_RAM=y · line 24

Quoted 4 lines
configs/Sinlinx_SinA33_defconfig +1 -0
@@ -21,5 +21,6 @@ CONFIG_DFU_RAM=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1

Your commit doesn't make any sense: the SinaA33 and the Lime2 both have the eMMC on MMC2, and you claim you want to update the default to point to MMC2, but you're changing both these boards to point to MMC1 instead?

Quoted 17 lines
configs/Sinlinx_SinA33_defconfig +0 -0
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
 CONFIG_USB_FUNCTION_MASS_STORAGE=y
configs/amarula_a64_relic_defconfig +1 -0
index b72cbfabc6..caeb3f6008 100644
@@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
drivers/fastboot/Kconfig +0 -0
index bc25ea1d9c..4a1bfd119c 100644

drivers/fastboot/Kconfig config FASTBOOT_FLASH_MMC_DEV · line 92

Quoted 6 lines
drivers/fastboot/Kconfig +2 -1
@@ -88,7 +88,8 @@ config FASTBOOT_FLASH_MMC_DEV
 	int "Define FASTBOOT MMC FLASH default device"
 	depends on FASTBOOT_FLASH_MMC
 	default 0 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
-	default 1 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
+	default 1 if ARCH_SUNXI && !DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
+	default 2 if ARCH_SUNXI && DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1

It'd be better to be fixed properly, instead of just relying on a broken index.

Maxime

Signature · 10 lines
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180716/dcbc6242/attachment.sig>
#34 lore raw

PATCH 21/25 fastboot: sunxi: Update fastboot mmc default device

Quoted 38 lines · Maxime Ripard
Quoted 37 lines · Jagan Teki

Usually eMMC is default env fat device for environment, if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc device as 1. but with DM_MMC it can be more possible to probe eMMC as device 2 since for most of the sunxi platforms eMMC is configured mmc2.

So update the fastboot mmc default device as 2 if DM_MMC and MMC_SUNXI_SLOT_EXTRA != 1 slot is 2 defined but some boards may not use all possible mmc devices or partly disabled in DT, for those update the device in board specific defconfig.

Cc Olliver Schinagl <[email protected]>
Cc Chen-Yu Tsai <[email protected]>
---
 configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
 configs/Sinlinx_SinA33_defconfig           | 1 +
 configs/amarula_a64_relic_defconfig        | 1 +
 drivers/fastboot/Kconfig                   | 3 ++-
 4 files changed, 5 insertions(+), 1 deletion(-)
configs/A20-OLinuXino-Lime2-eMMC_defconfig +1 -0
index 5657fc2594..20ea254191 100644
@@ -29,4 +29,5 @@ CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
configs/Sinlinx_SinA33_defconfig +0 -0
index 394534b8b5..7841219a65 100644
@@ -21,5 +21,6 @@ CONFIG_DFU_RAM=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
Quoted 8 lines

configs/Sinlinx_SinA33_defconfig CONFIG_DFU_RAM=y · line 24

Quoted 3 lines
configs/Sinlinx_SinA33_defconfig +1 -0
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1

Your commit doesn't make any sense: the SinaA33 and the Lime2 both have the eMMC on MMC2, and you claim you want to update the default to point to MMC2, but you're changing both these boards to point to MMC1 instead?

If DM_MMC and SLOT != 1 => default device 2 which is updated by kconfig, this is with all relevant mmc nodes are enabled
but these two boards mmc1 is not enabled so emmc will detected in device 1

Quoted 19 lines
Quoted 19 lines
configs/Sinlinx_SinA33_defconfig +0 -0
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
 CONFIG_USB_FUNCTION_MASS_STORAGE=y
configs/amarula_a64_relic_defconfig +1 -0
index b72cbfabc6..caeb3f6008 100644
@@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
drivers/fastboot/Kconfig +0 -0
index bc25ea1d9c..4a1bfd119c 100644
@@ -88,7 +88,8 @@ config FASTBOOT_FLASH_MMC_DEV
      int "Define FASTBOOT MMC FLASH default device"
Quoted 8 lines

drivers/fastboot/Kconfig config FASTBOOT_FLASH_MMC_DEV · line 92

Quoted 5 lines
drivers/fastboot/Kconfig +2 -1
      depends on FASTBOOT_FLASH_MMC
      default 0 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
-     default 1 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
+     default 1 if ARCH_SUNXI && !DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
+     default 2 if ARCH_SUNXI && DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1

It'd be better to be fixed properly, instead of just relying on a broken index.

I don't think we can't do anything with this now, since this INDEX more rely on SPL for pinctrl enablement. if you have any suggestion please share.

#35 lore raw

PATCH 21/25 fastboot: sunxi: Update fastboot mmc default device

Quoted 82 lines · Jagan Teki
Quoted 38 lines · Maxime Ripard
Quoted 37 lines · Jagan Teki

Usually eMMC is default env fat device for environment, if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc device as 1. but with DM_MMC it can be more possible to probe eMMC as device 2 since for most of the sunxi platforms eMMC is configured mmc2.

So update the fastboot mmc default device as 2 if DM_MMC and MMC_SUNXI_SLOT_EXTRA != 1 slot is 2 defined but some boards may not use all possible mmc devices or partly disabled in DT, for those update the device in board specific defconfig.

Cc Olliver Schinagl <[email protected]>
Cc Chen-Yu Tsai <[email protected]>
---
 configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
 configs/Sinlinx_SinA33_defconfig           | 1 +
 configs/amarula_a64_relic_defconfig        | 1 +
 drivers/fastboot/Kconfig                   | 3 ++-
 4 files changed, 5 insertions(+), 1 deletion(-)
configs/A20-OLinuXino-Lime2-eMMC_defconfig +1 -0
index 5657fc2594..20ea254191 100644
@@ -29,4 +29,5 @@ CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
configs/Sinlinx_SinA33_defconfig +0 -0
index 394534b8b5..7841219a65 100644
@@ -21,5 +21,6 @@ CONFIG_DFU_RAM=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
Quoted 8 lines

configs/Sinlinx_SinA33_defconfig CONFIG_DFU_RAM=y · line 24

Quoted 3 lines
configs/Sinlinx_SinA33_defconfig +1 -0
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1

Your commit doesn't make any sense: the SinaA33 and the Lime2 both have the eMMC on MMC2, and you claim you want to update the default to point to MMC2, but you're changing both these boards to point to MMC1 instead?

If DM_MMC and SLOT != 1 => default device 2 which is updated by kconfig, this is with all relevant mmc nodes are enabled
but these two boards mmc1 is not enabled so emmc will detected in device 1

Quoted 19 lines
Quoted 19 lines
configs/Sinlinx_SinA33_defconfig +0 -0
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
 CONFIG_USB_FUNCTION_MASS_STORAGE=y
configs/amarula_a64_relic_defconfig +1 -0
index b72cbfabc6..caeb3f6008 100644
@@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
drivers/fastboot/Kconfig +0 -0
index bc25ea1d9c..4a1bfd119c 100644
@@ -88,7 +88,8 @@ config FASTBOOT_FLASH_MMC_DEV
      int "Define FASTBOOT MMC FLASH default device"
Quoted 8 lines

drivers/fastboot/Kconfig config FASTBOOT_FLASH_MMC_DEV · line 92

Quoted 5 lines
drivers/fastboot/Kconfig +2 -1
      depends on FASTBOOT_FLASH_MMC
      default 0 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
-     default 1 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
+     default 1 if ARCH_SUNXI && !DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
+     default 2 if ARCH_SUNXI && DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1

It'd be better to be fixed properly, instead of just relying on a broken index.

Quoted 3 lines

I don't think we can't do anything with this now, since this INDEX more rely on SPL for pinctrl enablement. if you have any suggestion please share.

Would another answer (at least for this specific case) to change the fastboot code so it doesn't need the device number in advance? Given we get device names along the lines of 'mmcsda1', we could parse out the 'a' to figure out the device number (and then use the alias code so your board can expose a portable name).

Signature · 1 line
Alex Kiernan
#36 lore raw

PATCH 21/25 fastboot: sunxi: Update fastboot mmc default device

Quoted 87 lines · Alex Kiernan
Quoted 82 lines · Jagan Teki
Quoted 38 lines · Maxime Ripard
Quoted 37 lines · Jagan Teki

Usually eMMC is default env fat device for environment, if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc device as 1. but with DM_MMC it can be more possible to probe eMMC as device 2 since for most of the sunxi platforms eMMC is configured mmc2.

So update the fastboot mmc default device as 2 if DM_MMC and MMC_SUNXI_SLOT_EXTRA != 1 slot is 2 defined but some boards may not use all possible mmc devices or partly disabled in DT, for those update the device in board specific defconfig.

Cc Olliver Schinagl <[email protected]>
Cc Chen-Yu Tsai <[email protected]>
---
 configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
 configs/Sinlinx_SinA33_defconfig           | 1 +
 configs/amarula_a64_relic_defconfig        | 1 +
 drivers/fastboot/Kconfig                   | 3 ++-
 4 files changed, 5 insertions(+), 1 deletion(-)
configs/A20-OLinuXino-Lime2-eMMC_defconfig +1 -0
index 5657fc2594..20ea254191 100644
@@ -29,4 +29,5 @@ CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
configs/Sinlinx_SinA33_defconfig +0 -0
index 394534b8b5..7841219a65 100644
@@ -21,5 +21,6 @@ CONFIG_DFU_RAM=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
Quoted 8 lines

configs/Sinlinx_SinA33_defconfig CONFIG_DFU_RAM=y · line 24

Quoted 3 lines
configs/Sinlinx_SinA33_defconfig +1 -0
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1

Your commit doesn't make any sense: the SinaA33 and the Lime2 both have the eMMC on MMC2, and you claim you want to update the default to point to MMC2, but you're changing both these boards to point to MMC1 instead?

If DM_MMC and SLOT != 1 => default device 2 which is updated by kconfig, this is with all relevant mmc nodes are enabled
but these two boards mmc1 is not enabled so emmc will detected in device 1

Quoted 19 lines
Quoted 19 lines
configs/Sinlinx_SinA33_defconfig +0 -0
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
 CONFIG_USB_FUNCTION_MASS_STORAGE=y
configs/amarula_a64_relic_defconfig +1 -0
index b72cbfabc6..caeb3f6008 100644
@@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
drivers/fastboot/Kconfig +0 -0
index bc25ea1d9c..4a1bfd119c 100644
@@ -88,7 +88,8 @@ config FASTBOOT_FLASH_MMC_DEV
      int "Define FASTBOOT MMC FLASH default device"
Quoted 8 lines

drivers/fastboot/Kconfig config FASTBOOT_FLASH_MMC_DEV · line 92

Quoted 5 lines
drivers/fastboot/Kconfig +2 -1
      depends on FASTBOOT_FLASH_MMC
      default 0 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
-     default 1 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
+     default 1 if ARCH_SUNXI && !DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
+     default 2 if ARCH_SUNXI && DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1

It'd be better to be fixed properly, instead of just relying on a broken index.

Quoted 3 lines

I don't think we can't do anything with this now, since this INDEX more rely on SPL for pinctrl enablement. if you have any suggestion please share.

Quoted 5 lines

Would another answer (at least for this specific case) to change the fastboot code so it doesn't need the device number in advance? Given we get device names along the lines of 'mmcsda1', we could parse out the 'a' to figure out the device number (and then use the alias code so your board can expose a portable name).

That sounds like a pretty good solution. I guess we would have some corner cases when we have a NAND and an MMC card for example that can be flashed using fastboot, but I'm not sure we have boards in that setup at the moment (for Allwinner SoCs at least).

Maxime

Signature · 10 lines
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180717/3f36de85/attachment.sig>
#37 lore raw

PATCH 21/25 fastboot: sunxi: Update fastboot mmc default device

Quoted 95 lines · Maxime Ripard
Quoted 87 lines · Alex Kiernan
Quoted 82 lines · Jagan Teki
Quoted 38 lines · Maxime Ripard
Quoted 37 lines · Jagan Teki

Usually eMMC is default env fat device for environment, if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc device as 1. but with DM_MMC it can be more possible to probe eMMC as device 2 since for most of the sunxi platforms eMMC is configured mmc2.

So update the fastboot mmc default device as 2 if DM_MMC and MMC_SUNXI_SLOT_EXTRA != 1 slot is 2 defined but some boards may not use all possible mmc devices or partly disabled in DT, for those update the device in board specific defconfig.

Cc Olliver Schinagl <[email protected]>
Cc Chen-Yu Tsai <[email protected]>
---
 configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
 configs/Sinlinx_SinA33_defconfig           | 1 +
 configs/amarula_a64_relic_defconfig        | 1 +
 drivers/fastboot/Kconfig                   | 3 ++-
 4 files changed, 5 insertions(+), 1 deletion(-)
configs/A20-OLinuXino-Lime2-eMMC_defconfig +1 -0
index 5657fc2594..20ea254191 100644
@@ -29,4 +29,5 @@ CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
configs/Sinlinx_SinA33_defconfig +0 -0
index 394534b8b5..7841219a65 100644
@@ -21,5 +21,6 @@ CONFIG_DFU_RAM=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
Quoted 8 lines

configs/Sinlinx_SinA33_defconfig CONFIG_DFU_RAM=y · line 24

Quoted 3 lines
configs/Sinlinx_SinA33_defconfig +1 -0
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1

Your commit doesn't make any sense: the SinaA33 and the Lime2 both have the eMMC on MMC2, and you claim you want to update the default to point to MMC2, but you're changing both these boards to point to MMC1 instead?

If DM_MMC and SLOT != 1 => default device 2 which is updated by kconfig, this is with all relevant mmc nodes are enabled
but these two boards mmc1 is not enabled so emmc will detected in device 1

Quoted 19 lines
Quoted 19 lines
configs/Sinlinx_SinA33_defconfig +0 -0
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
 CONFIG_USB_FUNCTION_MASS_STORAGE=y
configs/amarula_a64_relic_defconfig +1 -0
index b72cbfabc6..caeb3f6008 100644
@@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
drivers/fastboot/Kconfig +0 -0
index bc25ea1d9c..4a1bfd119c 100644
@@ -88,7 +88,8 @@ config FASTBOOT_FLASH_MMC_DEV
      int "Define FASTBOOT MMC FLASH default device"
Quoted 8 lines

drivers/fastboot/Kconfig config FASTBOOT_FLASH_MMC_DEV · line 92

Quoted 5 lines
drivers/fastboot/Kconfig +2 -1
      depends on FASTBOOT_FLASH_MMC
      default 0 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
-     default 1 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
+     default 1 if ARCH_SUNXI && !DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
+     default 2 if ARCH_SUNXI && DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1

It'd be better to be fixed properly, instead of just relying on a broken index.

Quoted 3 lines

I don't think we can't do anything with this now, since this INDEX more rely on SPL for pinctrl enablement. if you have any suggestion please share.

Quoted 5 lines

Would another answer (at least for this specific case) to change the fastboot code so it doesn't need the device number in advance? Given we get device names along the lines of 'mmcsda1', we could parse out the 'a' to figure out the device number (and then use the alias code so your board can expose a portable name).

Quoted 5 lines

That sounds like a pretty good solution. I guess we would have some corner cases when we have a NAND and an MMC card for example that can be flashed using fastboot, but I'm not sure we have boards in that setup at the moment (for Allwinner SoCs at least).

It's not something I need right now, but having spent so much time refactoring the fastboot code I'd like to get to this! Support for getvar all is also on my todo list.

The NAND stuff is a good call, I'm not sure how that fits in (not least not having a board which has a NAND part).

Signature · 1 line
Alex Kiernan
#38 lore raw

PATCH 21/25 fastboot: sunxi: Update fastboot mmc default device

Quoted 103 lines · Alex Kiernan
Quoted 95 lines · Maxime Ripard
Quoted 87 lines · Alex Kiernan
Quoted 82 lines · Jagan Teki
Quoted 38 lines · Maxime Ripard
Quoted 37 lines · Jagan Teki

Usually eMMC is default env fat device for environment, if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc device as 1. but with DM_MMC it can be more possible to probe eMMC as device 2 since for most of the sunxi platforms eMMC is configured mmc2.

So update the fastboot mmc default device as 2 if DM_MMC and MMC_SUNXI_SLOT_EXTRA != 1 slot is 2 defined but some boards may not use all possible mmc devices or partly disabled in DT, for those update the device in board specific defconfig.

Cc Olliver Schinagl <[email protected]>
Cc Chen-Yu Tsai <[email protected]>
---
 configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
 configs/Sinlinx_SinA33_defconfig           | 1 +
 configs/amarula_a64_relic_defconfig        | 1 +
 drivers/fastboot/Kconfig                   | 3 ++-
 4 files changed, 5 insertions(+), 1 deletion(-)
configs/A20-OLinuXino-Lime2-eMMC_defconfig +1 -0
index 5657fc2594..20ea254191 100644
@@ -29,4 +29,5 @@ CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
configs/Sinlinx_SinA33_defconfig +0 -0
index 394534b8b5..7841219a65 100644
@@ -21,5 +21,6 @@ CONFIG_DFU_RAM=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
Quoted 8 lines

configs/Sinlinx_SinA33_defconfig CONFIG_DFU_RAM=y · line 24

Quoted 3 lines
configs/Sinlinx_SinA33_defconfig +1 -0
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1

Your commit doesn't make any sense: the SinaA33 and the Lime2 both have the eMMC on MMC2, and you claim you want to update the default to point to MMC2, but you're changing both these boards to point to MMC1 instead?

If DM_MMC and SLOT != 1 => default device 2 which is updated by kconfig, this is with all relevant mmc nodes are enabled
but these two boards mmc1 is not enabled so emmc will detected in device 1

Quoted 19 lines
Quoted 19 lines
configs/Sinlinx_SinA33_defconfig +0 -0
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
 CONFIG_USB_FUNCTION_MASS_STORAGE=y
configs/amarula_a64_relic_defconfig +1 -0
index b72cbfabc6..caeb3f6008 100644
@@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
drivers/fastboot/Kconfig +0 -0
index bc25ea1d9c..4a1bfd119c 100644
@@ -88,7 +88,8 @@ config FASTBOOT_FLASH_MMC_DEV
      int "Define FASTBOOT MMC FLASH default device"
Quoted 8 lines

drivers/fastboot/Kconfig config FASTBOOT_FLASH_MMC_DEV · line 92

Quoted 5 lines
drivers/fastboot/Kconfig +2 -1
      depends on FASTBOOT_FLASH_MMC
      default 0 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
-     default 1 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
+     default 1 if ARCH_SUNXI && !DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
+     default 2 if ARCH_SUNXI && DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1

It'd be better to be fixed properly, instead of just relying on a broken index.

Quoted 3 lines

I don't think we can't do anything with this now, since this INDEX more rely on SPL for pinctrl enablement. if you have any suggestion please share.

Quoted 5 lines

Would another answer (at least for this specific case) to change the fastboot code so it doesn't need the device number in advance? Given we get device names along the lines of 'mmcsda1', we could parse out the 'a' to figure out the device number (and then use the alias code so your board can expose a portable name).

Quoted 5 lines

That sounds like a pretty good solution. I guess we would have some corner cases when we have a NAND and an MMC card for example that can be flashed using fastboot, but I'm not sure we have boards in that setup at the moment (for Allwinner SoCs at least).

Quoted 6 lines

It's not something I need right now, but having spent so much time refactoring the fastboot code I'd like to get to this! Support for getvar all is also on my todo list.

The NAND stuff is a good call, I'm not sure how that fits in (not least not having a board which has a NAND part).

Maybe we can hack something at the partition level though: instead of having the partition name itself, what about prefixing it by the device name? ie having something like mmc1:rootfs and nand0:rootfs, as partition name.

maxime

Signature · 10 lines
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180719/6de9ec16/attachment.sig>
author
#39 lore raw

PATCH 21/25 fastboot: sunxi: Update fastboot mmc default device

Quoted 108 lines · Maxime Ripard
Quoted 107 lines · Alex Kiernan
Quoted 95 lines · Maxime Ripard
Quoted 87 lines · Alex Kiernan
Quoted 82 lines · Jagan Teki
Quoted 38 lines · Maxime Ripard
Quoted 37 lines · Jagan Teki

Usually eMMC is default env fat device for environment, if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc device as 1. but with DM_MMC it can be more possible to probe eMMC as device 2 since for most of the sunxi platforms eMMC is configured mmc2.

So update the fastboot mmc default device as 2 if DM_MMC and MMC_SUNXI_SLOT_EXTRA != 1 slot is 2 defined but some boards may not use all possible mmc devices or partly disabled in DT, for those update the device in board specific defconfig.

Cc Olliver Schinagl <[email protected]>
Cc Chen-Yu Tsai <[email protected]>
---
 configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
 configs/Sinlinx_SinA33_defconfig           | 1 +
 configs/amarula_a64_relic_defconfig        | 1 +
 drivers/fastboot/Kconfig                   | 3 ++-
 4 files changed, 5 insertions(+), 1 deletion(-)
configs/A20-OLinuXino-Lime2-eMMC_defconfig +1 -0
index 5657fc2594..20ea254191 100644
@@ -29,4 +29,5 @@ CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
configs/Sinlinx_SinA33_defconfig +0 -0
index 394534b8b5..7841219a65 100644
@@ -21,5 +21,6 @@ CONFIG_DFU_RAM=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
Quoted 8 lines

configs/Sinlinx_SinA33_defconfig CONFIG_DFU_RAM=y · line 24

Quoted 3 lines
configs/Sinlinx_SinA33_defconfig +1 -0
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1

Your commit doesn't make any sense: the SinaA33 and the Lime2 both have the eMMC on MMC2, and you claim you want to update the default to point to MMC2, but you're changing both these boards to point to MMC1 instead?

If DM_MMC and SLOT != 1 => default device 2 which is updated by kconfig, this is with all relevant mmc nodes are enabled
but these two boards mmc1 is not enabled so emmc will detected in device 1

Quoted 19 lines
Quoted 19 lines
configs/Sinlinx_SinA33_defconfig +0 -0
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
 CONFIG_USB_FUNCTION_MASS_STORAGE=y
configs/amarula_a64_relic_defconfig +1 -0
index b72cbfabc6..caeb3f6008 100644
@@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
drivers/fastboot/Kconfig +0 -0
index bc25ea1d9c..4a1bfd119c 100644
@@ -88,7 +88,8 @@ config FASTBOOT_FLASH_MMC_DEV
      int "Define FASTBOOT MMC FLASH default device"
Quoted 8 lines

drivers/fastboot/Kconfig config FASTBOOT_FLASH_MMC_DEV · line 92

Quoted 5 lines
drivers/fastboot/Kconfig +2 -1
      depends on FASTBOOT_FLASH_MMC
      default 0 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
-     default 1 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
+     default 1 if ARCH_SUNXI && !DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
+     default 2 if ARCH_SUNXI && DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1

It'd be better to be fixed properly, instead of just relying on a broken index.

Quoted 3 lines

I don't think we can't do anything with this now, since this INDEX more rely on SPL for pinctrl enablement. if you have any suggestion please share.

Quoted 5 lines

Would another answer (at least for this specific case) to change the fastboot code so it doesn't need the device number in advance? Given we get device names along the lines of 'mmcsda1', we could parse out the 'a' to figure out the device number (and then use the alias code so your board can expose a portable name).

Quoted 5 lines

That sounds like a pretty good solution. I guess we would have some corner cases when we have a NAND and an MMC card for example that can be flashed using fastboot, but I'm not sure we have boards in that setup at the moment (for Allwinner SoCs at least).

It's not something I need right now, but having spent so much time refactoring the fastboot code I'd like to get to this! Support for getvar all is also on my todo list.

Quoted 7 lines
Quoted 2 lines

The NAND stuff is a good call, I'm not sure how that fits in (not least not having a board which has a NAND part).

Maybe we can hack something at the partition level though: instead of having the partition name itself, what about prefixing it by the device name? ie having something like mmc1:rootfs and nand0:rootfs, as partition name.

How about giving an input during command 'fastboot <controller> [dev_type] <dev[:part]>' it can be fastboot 0 mmc 1 similar like ums did 'ums 0 mmc 1'

#40 lore raw

PATCH 21/25 fastboot: sunxi: Update fastboot mmc default device

Quoted 113 lines · Jagan Teki
Quoted 111 lines · Maxime Ripard
Quoted 109 lines · Alex Kiernan
Quoted 95 lines · Maxime Ripard
Quoted 87 lines · Alex Kiernan
Quoted 82 lines · Jagan Teki
Quoted 38 lines · Maxime Ripard
Quoted 37 lines · Jagan Teki

Usually eMMC is default env fat device for environment, if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc device as 1. but with DM_MMC it can be more possible to probe eMMC as device 2 since for most of the sunxi platforms eMMC is configured mmc2.

So update the fastboot mmc default device as 2 if DM_MMC and MMC_SUNXI_SLOT_EXTRA != 1 slot is 2 defined but some boards may not use all possible mmc devices or partly disabled in DT, for those update the device in board specific defconfig.

Cc Olliver Schinagl <[email protected]>
Cc Chen-Yu Tsai <[email protected]>
---
 configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
 configs/Sinlinx_SinA33_defconfig           | 1 +
 configs/amarula_a64_relic_defconfig        | 1 +
 drivers/fastboot/Kconfig                   | 3 ++-
 4 files changed, 5 insertions(+), 1 deletion(-)
configs/A20-OLinuXino-Lime2-eMMC_defconfig +1 -0
index 5657fc2594..20ea254191 100644
@@ -29,4 +29,5 @@ CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
configs/Sinlinx_SinA33_defconfig +0 -0
index 394534b8b5..7841219a65 100644
@@ -21,5 +21,6 @@ CONFIG_DFU_RAM=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
Quoted 8 lines

configs/Sinlinx_SinA33_defconfig CONFIG_DFU_RAM=y · line 24

Quoted 3 lines
configs/Sinlinx_SinA33_defconfig +1 -0
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1

Your commit doesn't make any sense: the SinaA33 and the Lime2 both have the eMMC on MMC2, and you claim you want to update the default to point to MMC2, but you're changing both these boards to point to MMC1 instead?

If DM_MMC and SLOT != 1 => default device 2 which is updated by kconfig, this is with all relevant mmc nodes are enabled
but these two boards mmc1 is not enabled so emmc will detected in device 1

Quoted 19 lines
Quoted 19 lines
configs/Sinlinx_SinA33_defconfig +0 -0
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
 CONFIG_USB_FUNCTION_MASS_STORAGE=y
configs/amarula_a64_relic_defconfig +1 -0
index b72cbfabc6..caeb3f6008 100644
@@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
drivers/fastboot/Kconfig +0 -0
index bc25ea1d9c..4a1bfd119c 100644
@@ -88,7 +88,8 @@ config FASTBOOT_FLASH_MMC_DEV
      int "Define FASTBOOT MMC FLASH default device"
Quoted 8 lines

drivers/fastboot/Kconfig config FASTBOOT_FLASH_MMC_DEV · line 92

Quoted 5 lines
drivers/fastboot/Kconfig +2 -1
      depends on FASTBOOT_FLASH_MMC
      default 0 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
-     default 1 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
+     default 1 if ARCH_SUNXI && !DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
+     default 2 if ARCH_SUNXI && DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1

It'd be better to be fixed properly, instead of just relying on a broken index.

Quoted 3 lines

I don't think we can't do anything with this now, since this INDEX more rely on SPL for pinctrl enablement. if you have any suggestion please share.

Quoted 5 lines

Would another answer (at least for this specific case) to change the fastboot code so it doesn't need the device number in advance? Given we get device names along the lines of 'mmcsda1', we could parse out the 'a' to figure out the device number (and then use the alias code so your board can expose a portable name).

Quoted 5 lines

That sounds like a pretty good solution. I guess we would have some corner cases when we have a NAND and an MMC card for example that can be flashed using fastboot, but I'm not sure we have boards in that setup at the moment (for Allwinner SoCs at least).

It's not something I need right now, but having spent so much time refactoring the fastboot code I'd like to get to this! Support for getvar all is also on my todo list.

The NAND stuff is a good call, I'm not sure how that fits in (not least not having a board which has a NAND part).

Quoted 8 lines
Quoted 4 lines

Maybe we can hack something at the partition level though: instead of having the partition name itself, what about prefixing it by the device name? ie having something like mmc1:rootfs and nand0:rootfs, as partition name.

How about giving an input during command 'fastboot <controller> [dev_type] <dev[:part]>' it can be fastboot 0 mmc 1 similar like ums did 'ums 0 mmc 1'

The dev ID doesn't have much sense with the DM either though.

Maxime

Signature · 10 lines
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180720/4e6919ec/attachment.sig>
#41 lore raw

PATCH 21/25 fastboot: sunxi: Update fastboot mmc default device

In reply to Maxime Ripard
Quoted 109 lines · Maxime Ripard
Quoted 107 lines · Alex Kiernan
Quoted 95 lines · Maxime Ripard
Quoted 87 lines · Alex Kiernan
Quoted 82 lines · Jagan Teki
Quoted 38 lines · Maxime Ripard
Quoted 37 lines · Jagan Teki

Usually eMMC is default env fat device for environment, if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc device as 1. but with DM_MMC it can be more possible to probe eMMC as device 2 since for most of the sunxi platforms eMMC is configured mmc2.

So update the fastboot mmc default device as 2 if DM_MMC and MMC_SUNXI_SLOT_EXTRA != 1 slot is 2 defined but some boards may not use all possible mmc devices or partly disabled in DT, for those update the device in board specific defconfig.

Cc Olliver Schinagl <[email protected]>
Cc Chen-Yu Tsai <[email protected]>
---
 configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
 configs/Sinlinx_SinA33_defconfig           | 1 +
 configs/amarula_a64_relic_defconfig        | 1 +
 drivers/fastboot/Kconfig                   | 3 ++-
 4 files changed, 5 insertions(+), 1 deletion(-)
configs/A20-OLinuXino-Lime2-eMMC_defconfig +1 -0
index 5657fc2594..20ea254191 100644
@@ -29,4 +29,5 @@ CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
configs/Sinlinx_SinA33_defconfig +0 -0
index 394534b8b5..7841219a65 100644
@@ -21,5 +21,6 @@ CONFIG_DFU_RAM=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
Quoted 8 lines

configs/Sinlinx_SinA33_defconfig CONFIG_DFU_RAM=y · line 24

Quoted 3 lines
configs/Sinlinx_SinA33_defconfig +1 -0
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1

Your commit doesn't make any sense: the SinaA33 and the Lime2 both have the eMMC on MMC2, and you claim you want to update the default to point to MMC2, but you're changing both these boards to point to MMC1 instead?

If DM_MMC and SLOT != 1 => default device 2 which is updated by kconfig, this is with all relevant mmc nodes are enabled
but these two boards mmc1 is not enabled so emmc will detected in device 1

Quoted 19 lines
Quoted 19 lines
configs/Sinlinx_SinA33_defconfig +0 -0
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
 CONFIG_USB_FUNCTION_MASS_STORAGE=y
configs/amarula_a64_relic_defconfig +1 -0
index b72cbfabc6..caeb3f6008 100644
@@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
drivers/fastboot/Kconfig +0 -0
index bc25ea1d9c..4a1bfd119c 100644
@@ -88,7 +88,8 @@ config FASTBOOT_FLASH_MMC_DEV
      int "Define FASTBOOT MMC FLASH default device"
Quoted 8 lines

drivers/fastboot/Kconfig config FASTBOOT_FLASH_MMC_DEV · line 92

Quoted 5 lines
drivers/fastboot/Kconfig +2 -1
      depends on FASTBOOT_FLASH_MMC
      default 0 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
-     default 1 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
+     default 1 if ARCH_SUNXI && !DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
+     default 2 if ARCH_SUNXI && DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1

It'd be better to be fixed properly, instead of just relying on a broken index.

Quoted 3 lines

I don't think we can't do anything with this now, since this INDEX more rely on SPL for pinctrl enablement. if you have any suggestion please share.

Quoted 5 lines

Would another answer (at least for this specific case) to change the fastboot code so it doesn't need the device number in advance? Given we get device names along the lines of 'mmcsda1', we could parse out the 'a' to figure out the device number (and then use the alias code so your board can expose a portable name).

Quoted 5 lines

That sounds like a pretty good solution. I guess we would have some corner cases when we have a NAND and an MMC card for example that can be flashed using fastboot, but I'm not sure we have boards in that setup at the moment (for Allwinner SoCs at least).

It's not something I need right now, but having spent so much time refactoring the fastboot code I'd like to get to this! Support for getvar all is also on my todo list.

Quoted 8 lines
Quoted 2 lines

The NAND stuff is a good call, I'm not sure how that fits in (not least not having a board which has a NAND part).

Maybe we can hack something at the partition level though: instead of having the partition name itself, what about prefixing it by the device name? ie having something like mmc1:rootfs and nand0:rootfs, as partition name.

Just looking at the code, I suspect NAND already works, just use the name that mtd knows. And mmc looks trivial to implement.

I guess one question is if you want to be able to filter out which devices you can address from the fastboot client.

Signature · 1 line
Alex Kiernan
#42 lore raw

PATCH 21/25 fastboot: sunxi: Update fastboot mmc default device

Quoted 119 lines · Alex Kiernan
Quoted 109 lines · Maxime Ripard
Quoted 107 lines · Alex Kiernan
Quoted 95 lines · Maxime Ripard
Quoted 87 lines · Alex Kiernan
Quoted 82 lines · Jagan Teki
Quoted 38 lines · Maxime Ripard
Quoted 37 lines · Jagan Teki

Usually eMMC is default env fat device for environment, if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc device as 1. but with DM_MMC it can be more possible to probe eMMC as device 2 since for most of the sunxi platforms eMMC is configured mmc2.

So update the fastboot mmc default device as 2 if DM_MMC and MMC_SUNXI_SLOT_EXTRA != 1 slot is 2 defined but some boards may not use all possible mmc devices or partly disabled in DT, for those update the device in board specific defconfig.

Cc Olliver Schinagl <[email protected]>
Cc Chen-Yu Tsai <[email protected]>
---
 configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
 configs/Sinlinx_SinA33_defconfig           | 1 +
 configs/amarula_a64_relic_defconfig        | 1 +
 drivers/fastboot/Kconfig                   | 3 ++-
 4 files changed, 5 insertions(+), 1 deletion(-)
configs/A20-OLinuXino-Lime2-eMMC_defconfig +1 -0
index 5657fc2594..20ea254191 100644
@@ -29,4 +29,5 @@ CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
configs/Sinlinx_SinA33_defconfig +0 -0
index 394534b8b5..7841219a65 100644
@@ -21,5 +21,6 @@ CONFIG_DFU_RAM=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
Quoted 8 lines

configs/Sinlinx_SinA33_defconfig CONFIG_DFU_RAM=y · line 24

Quoted 3 lines
configs/Sinlinx_SinA33_defconfig +1 -0
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1

Your commit doesn't make any sense: the SinaA33 and the Lime2 both have the eMMC on MMC2, and you claim you want to update the default to point to MMC2, but you're changing both these boards to point to MMC1 instead?

If DM_MMC and SLOT != 1 => default device 2 which is updated by kconfig, this is with all relevant mmc nodes are enabled
but these two boards mmc1 is not enabled so emmc will detected in device 1

Quoted 19 lines
Quoted 19 lines
configs/Sinlinx_SinA33_defconfig +0 -0
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
 CONFIG_USB_FUNCTION_MASS_STORAGE=y
configs/amarula_a64_relic_defconfig +1 -0
index b72cbfabc6..caeb3f6008 100644
@@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
drivers/fastboot/Kconfig +0 -0
index bc25ea1d9c..4a1bfd119c 100644
@@ -88,7 +88,8 @@ config FASTBOOT_FLASH_MMC_DEV
      int "Define FASTBOOT MMC FLASH default device"
Quoted 8 lines

drivers/fastboot/Kconfig config FASTBOOT_FLASH_MMC_DEV · line 92

Quoted 5 lines
drivers/fastboot/Kconfig +2 -1
      depends on FASTBOOT_FLASH_MMC
      default 0 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
-     default 1 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
+     default 1 if ARCH_SUNXI && !DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
+     default 2 if ARCH_SUNXI && DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1

It'd be better to be fixed properly, instead of just relying on a broken index.

Quoted 3 lines

I don't think we can't do anything with this now, since this INDEX more rely on SPL for pinctrl enablement. if you have any suggestion please share.

Quoted 5 lines

Would another answer (at least for this specific case) to change the fastboot code so it doesn't need the device number in advance? Given we get device names along the lines of 'mmcsda1', we could parse out the 'a' to figure out the device number (and then use the alias code so your board can expose a portable name).

Quoted 5 lines

That sounds like a pretty good solution. I guess we would have some corner cases when we have a NAND and an MMC card for example that can be flashed using fastboot, but I'm not sure we have boards in that setup at the moment (for Allwinner SoCs at least).

It's not something I need right now, but having spent so much time refactoring the fastboot code I'd like to get to this! Support for getvar all is also on my todo list.

Quoted 8 lines
Quoted 2 lines

The NAND stuff is a good call, I'm not sure how that fits in (not least not having a board which has a NAND part).

Maybe we can hack something at the partition level though: instead of having the partition name itself, what about prefixing it by the device name? ie having something like mmc1:rootfs and nand0:rootfs, as partition name.

Quoted 5 lines

Just looking at the code, I suspect NAND already works, just use the name that mtd knows. And mmc looks trivial to implement.

I guess one question is if you want to be able to filter out which devices you can address from the fastboot client.

Yeah, that's what I meant. NAND definitely works as long as you stick to partitions defined in mtdparts

Signature · 10 lines
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180720/4cff86c6/attachment.sig>
#43 lore raw

PATCH 21/25 fastboot: sunxi: Update fastboot mmc default device

In reply to Jagan Teki
Quoted 49 lines · Jagan Teki
Quoted 38 lines · Maxime Ripard
Quoted 37 lines · Jagan Teki

Usually eMMC is default env fat device for environment, if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc device as 1. but with DM_MMC it can be more possible to probe eMMC as device 2 since for most of the sunxi platforms eMMC is configured mmc2.

So update the fastboot mmc default device as 2 if DM_MMC and MMC_SUNXI_SLOT_EXTRA != 1 slot is 2 defined but some boards may not use all possible mmc devices or partly disabled in DT, for those update the device in board specific defconfig.

Cc Olliver Schinagl <[email protected]>
Cc Chen-Yu Tsai <[email protected]>
---
 configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 +
 configs/Sinlinx_SinA33_defconfig           | 1 +
 configs/amarula_a64_relic_defconfig        | 1 +
 drivers/fastboot/Kconfig                   | 3 ++-
 4 files changed, 5 insertions(+), 1 deletion(-)
configs/A20-OLinuXino-Lime2-eMMC_defconfig +1 -0
index 5657fc2594..20ea254191 100644
@@ -29,4 +29,5 @@ CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
configs/Sinlinx_SinA33_defconfig +0 -0
index 394534b8b5..7841219a65 100644
@@ -21,5 +21,6 @@ CONFIG_DFU_RAM=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
Quoted 8 lines

configs/Sinlinx_SinA33_defconfig CONFIG_DFU_RAM=y · line 24

Quoted 3 lines
configs/Sinlinx_SinA33_defconfig +1 -0
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1

Your commit doesn't make any sense: the SinaA33 and the Lime2 both have the eMMC on MMC2, and you claim you want to update the default to point to MMC2, but you're changing both these boards to point to MMC1 instead?

Quoted 3 lines

If DM_MMC and SLOT != 1 => default device 2 which is updated by kconfig, this is with all relevant mmc nodes are enabled but these two boards mmc1 is not enabled so emmc will detected in device 1

So it purely relies on luck and the fact that we don't have a wifi device enabled yet? It seems pretty fragile, doesn't it?

Maxime

Signature · 10 lines
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180717/151232b8/attachment.sig>
author
#44 lore raw

PATCH 22/25 env: sunxi: Update default env fat device

In reply to Jagan Teki

Usually eMMC is default env fat device for environment, if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc device as 1. but with DM_MMC it can be more possible to probe eMMC as device 2 since for most of the sunxi platforms eMMC is configured mmc2.

So update the env default device as 2 if DM_MMC and MMC_SUNXI_SLOT_EXTRA != 1 but some boards may not use all possible mmc devices or partly disabled in DT, for those update the device in board specific defconfig.

Cc Olliver Schinagl <[email protected]>
Cc Hans de Goede <[email protected]>
Cc Marcus Cooper <[email protected]>
Cc Stefan Mavrodiev <[email protected]>
Cc Paul Kocialkowski <[email protected]>
Cc Chen-Yu Tsai <[email protected]>
---
 configs/A20-OLinuXino-Lime2-eMMC_defconfig   | 1 +
 configs/A20-OLinuXino_MICRO-eMMC_defconfig   | 1 +
 configs/A20-OLinuXino_MICRO_defconfig        | 1 +
 configs/A20-Olimex-SOM-EVB_defconfig         | 1 +
 configs/A20-Olimex-SOM204-EVB-eMMC_defconfig | 1 +
 configs/Mele_M3_defconfig                    | 1 +
 configs/Orangepi_mini_defconfig              | 1 +
 configs/Sinlinx_SinA33_defconfig             | 1 +
 configs/Yones_Toptech_BD1078_defconfig       | 1 +
 configs/amarula_a64_relic_defconfig          | 1 +
 env/Kconfig                                  | 3 ++-
 11 files changed, 12 insertions(+), 1 deletion(-)
configs/A20-OLinuXino-Lime2-eMMC_defconfig +1 -0
index 20ea254191..98a8ceb178 100644
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_USB0_VBUS_PIN="PC17"
 CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_I2C1_ENABLE=y
configs/A20-OLinuXino_MICRO-eMMC_defconfig +1 -0
index f7e7cbab0a..1552960d88 100644
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_I2C1_ENABLE=y
 CONFIG_VIDEO_VGA=y
 CONFIG_SATAPWR="PB8"
configs/A20-OLinuXino_MICRO_defconfig +1 -0
index 8dcbdc08f9..b5f1b7efe2 100644
@@ -6,6 +6,7 @@ CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC3_CD_PIN="PH11"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_I2C1_ENABLE=y
 CONFIG_VIDEO_VGA=y
 CONFIG_SATAPWR="PB8"
configs/A20-Olimex-SOM-EVB_defconfig +1 -0
index a06499e2d0..58f6fbad91 100644
@@ -7,6 +7,7 @@ CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC3_CD_PIN="PH0"
 CONFIG_MMC3_PINS="PH"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_USB0_VBUS_PIN="PB9"
 CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_SATAPWR="PC3"
configs/A20-Olimex-SOM204-EVB-eMMC_defconfig +1 -0
index 3bb8c4c7e6..ac4f841c4e 100644
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_USB0_VBUS_PIN="PC17"
 CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_I2C1_ENABLE=y
configs/Mele_M3_defconfig +1 -0
index 9f48bd91e0..93a2395aee 100644
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_VIDEO_VGA=y
 CONFIG_VIDEO_COMPOSITE=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3"
configs/Orangepi_mini_defconfig +1 -0
index 46f27be254..d562273bef 100644
@@ -7,6 +7,7 @@ CONFIG_MACPWR="PH23"
 CONFIG_MMC0_CD_PIN="PH10"
 CONFIG_MMC3_CD_PIN="PH11"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_USB1_VBUS_PIN="PH26"
 CONFIG_USB2_VBUS_PIN="PH22"
 CONFIG_VIDEO_COMPOSITE=y
configs/Sinlinx_SinA33_defconfig +1 -0
index 7841219a65..061f27c9db 100644
@@ -6,6 +6,7 @@ CONFIG_DRAM_CLK=552
 CONFIG_DRAM_ZQ=15291
 CONFIG_MMC0_CD_PIN="PB4"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_USB0_ID_DET="PH8"
 CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0"
 CONFIG_VIDEO_LCD_DCLK_PHASE=0
configs/Yones_Toptech_BD1078_defconfig +1 -0
index c49cbcbc3c..cad5618d54 100644
@@ -7,6 +7,7 @@ CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC1_CD_PIN="PH2"
 CONFIG_MMC1_PINS="PH"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=1
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_USB0_VBUS_PIN="PB9"
 CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_AXP_GPIO=y
configs/amarula_a64_relic_defconfig +1 -0
index caeb3f6008..bb5c0ff7b2 100644
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN50I=y
 CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
 CONFIG_DRAM_ODT_EN=y
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:auto"
 # CONFIG_VIDEO_DE2 is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
env/Kconfig +2 -1
index 8618376f25..2be16893b6 100644
@@ -374,7 +374,8 @@ config ENV_FAT_DEVICE_AND_PART
 	default "0:1" if TI_COMMON_CMD_OPTIONS
 	default "0:auto" if ARCH_ZYNQMP
 	default "0:auto" if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
-	default "1:auto" if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
+	default "1:auto" if ARCH_SUNXI && !DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
+	default "2:auto" if ARCH_SUNXI && DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1
 	default "0" if ARCH_AT91
 	help
 	  Define this to a string to specify the partition of the device. It can
Signature · 1 line
2.17.1
#45 lore raw

PATCH 22/25 env: sunxi: Update default env fat device

Quoted 133 lines · Jagan Teki

Usually eMMC is default env fat device for environment, if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc device as 1. but with DM_MMC it can be more possible to probe eMMC as device 2 since for most of the sunxi platforms eMMC is configured mmc2.

So update the env default device as 2 if DM_MMC and MMC_SUNXI_SLOT_EXTRA != 1 but some boards may not use all possible mmc devices or partly disabled in DT, for those update the device in board specific defconfig.

Cc Olliver Schinagl <[email protected]>
Cc Hans de Goede <[email protected]>
Cc Marcus Cooper <[email protected]>
Cc Stefan Mavrodiev <[email protected]>
Cc Paul Kocialkowski <[email protected]>
Cc Chen-Yu Tsai <[email protected]>
---
 configs/A20-OLinuXino-Lime2-eMMC_defconfig   | 1 +
 configs/A20-OLinuXino_MICRO-eMMC_defconfig   | 1 +
 configs/A20-OLinuXino_MICRO_defconfig        | 1 +
 configs/A20-Olimex-SOM-EVB_defconfig         | 1 +
 configs/A20-Olimex-SOM204-EVB-eMMC_defconfig | 1 +
 configs/Mele_M3_defconfig                    | 1 +
 configs/Orangepi_mini_defconfig              | 1 +
 configs/Sinlinx_SinA33_defconfig             | 1 +
 configs/Yones_Toptech_BD1078_defconfig       | 1 +
 configs/amarula_a64_relic_defconfig          | 1 +
 env/Kconfig                                  | 3 ++-
 11 files changed, 12 insertions(+), 1 deletion(-)
configs/A20-OLinuXino-Lime2-eMMC_defconfig +1 -0
index 20ea254191..98a8ceb178 100644
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_USB0_VBUS_PIN="PC17"
 CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_I2C1_ENABLE=y
configs/A20-OLinuXino_MICRO-eMMC_defconfig +1 -0
index f7e7cbab0a..1552960d88 100644
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_I2C1_ENABLE=y
 CONFIG_VIDEO_VGA=y
 CONFIG_SATAPWR="PB8"
configs/A20-OLinuXino_MICRO_defconfig +1 -0
index 8dcbdc08f9..b5f1b7efe2 100644
@@ -6,6 +6,7 @@ CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC3_CD_PIN="PH11"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_I2C1_ENABLE=y
 CONFIG_VIDEO_VGA=y
 CONFIG_SATAPWR="PB8"
configs/A20-Olimex-SOM-EVB_defconfig +1 -0
index a06499e2d0..58f6fbad91 100644
@@ -7,6 +7,7 @@ CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC3_CD_PIN="PH0"
 CONFIG_MMC3_PINS="PH"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_USB0_VBUS_PIN="PB9"
 CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_SATAPWR="PC3"
configs/A20-Olimex-SOM204-EVB-eMMC_defconfig +1 -0
index 3bb8c4c7e6..ac4f841c4e 100644
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_USB0_VBUS_PIN="PC17"
 CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_I2C1_ENABLE=y
configs/Mele_M3_defconfig +1 -0
index 9f48bd91e0..93a2395aee 100644
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_VIDEO_VGA=y
 CONFIG_VIDEO_COMPOSITE=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3"
configs/Orangepi_mini_defconfig +1 -0
index 46f27be254..d562273bef 100644
@@ -7,6 +7,7 @@ CONFIG_MACPWR="PH23"
 CONFIG_MMC0_CD_PIN="PH10"
 CONFIG_MMC3_CD_PIN="PH11"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_USB1_VBUS_PIN="PH26"
 CONFIG_USB2_VBUS_PIN="PH22"
 CONFIG_VIDEO_COMPOSITE=y
configs/Sinlinx_SinA33_defconfig +1 -0
index 7841219a65..061f27c9db 100644
@@ -6,6 +6,7 @@ CONFIG_DRAM_CLK=552
 CONFIG_DRAM_ZQ=15291
 CONFIG_MMC0_CD_PIN="PB4"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_USB0_ID_DET="PH8"
 CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0"
 CONFIG_VIDEO_LCD_DCLK_PHASE=0
configs/Yones_Toptech_BD1078_defconfig +0 -0
index c49cbcbc3c..cad5618d54 100644

configs/Yones_Toptech_BD1078_defconfig CONFIG_MMC0_CD_PIN="PH1" · line 10

Quoted 4 lines
configs/Yones_Toptech_BD1078_defconfig +1 -0
@@ -7,6 +7,7 @@ CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC1_CD_PIN="PH2"
 CONFIG_MMC1_PINS="PH"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=1
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"

Again, you're breaking all these boards while saying you want to fix them.

Maxime

Signature · 10 lines
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180716/2ecb5e9b/attachment.sig>
#46 lore raw

PATCH 22/25 env: sunxi: Update default env fat device

Quoted 133 lines · Maxime Ripard
Quoted 132 lines · Jagan Teki

Usually eMMC is default env fat device for environment, if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc device as 1. but with DM_MMC it can be more possible to probe eMMC as device 2 since for most of the sunxi platforms eMMC is configured mmc2.

So update the env default device as 2 if DM_MMC and MMC_SUNXI_SLOT_EXTRA != 1 but some boards may not use all possible mmc devices or partly disabled in DT, for those update the device in board specific defconfig.

Cc Olliver Schinagl <[email protected]>
Cc Hans de Goede <[email protected]>
Cc Marcus Cooper <[email protected]>
Cc Stefan Mavrodiev <[email protected]>
Cc Paul Kocialkowski <[email protected]>
Cc Chen-Yu Tsai <[email protected]>
---
 configs/A20-OLinuXino-Lime2-eMMC_defconfig   | 1 +
 configs/A20-OLinuXino_MICRO-eMMC_defconfig   | 1 +
 configs/A20-OLinuXino_MICRO_defconfig        | 1 +
 configs/A20-Olimex-SOM-EVB_defconfig         | 1 +
 configs/A20-Olimex-SOM204-EVB-eMMC_defconfig | 1 +
 configs/Mele_M3_defconfig                    | 1 +
 configs/Orangepi_mini_defconfig              | 1 +
 configs/Sinlinx_SinA33_defconfig             | 1 +
 configs/Yones_Toptech_BD1078_defconfig       | 1 +
 configs/amarula_a64_relic_defconfig          | 1 +
 env/Kconfig                                  | 3 ++-
 11 files changed, 12 insertions(+), 1 deletion(-)
configs/A20-OLinuXino-Lime2-eMMC_defconfig +1 -0
index 20ea254191..98a8ceb178 100644
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_USB0_VBUS_PIN="PC17"
 CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_I2C1_ENABLE=y
configs/A20-OLinuXino_MICRO-eMMC_defconfig +1 -0
index f7e7cbab0a..1552960d88 100644
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_I2C1_ENABLE=y
 CONFIG_VIDEO_VGA=y
 CONFIG_SATAPWR="PB8"
configs/A20-OLinuXino_MICRO_defconfig +1 -0
index 8dcbdc08f9..b5f1b7efe2 100644
@@ -6,6 +6,7 @@ CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC3_CD_PIN="PH11"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_I2C1_ENABLE=y
 CONFIG_VIDEO_VGA=y
 CONFIG_SATAPWR="PB8"
configs/A20-Olimex-SOM-EVB_defconfig +1 -0
index a06499e2d0..58f6fbad91 100644
@@ -7,6 +7,7 @@ CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC3_CD_PIN="PH0"
 CONFIG_MMC3_PINS="PH"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_USB0_VBUS_PIN="PB9"
 CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_SATAPWR="PC3"
configs/A20-Olimex-SOM204-EVB-eMMC_defconfig +1 -0
index 3bb8c4c7e6..ac4f841c4e 100644
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_USB0_VBUS_PIN="PC17"
 CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_I2C1_ENABLE=y
configs/Mele_M3_defconfig +1 -0
index 9f48bd91e0..93a2395aee 100644
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_VIDEO_VGA=y
 CONFIG_VIDEO_COMPOSITE=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3"
configs/Orangepi_mini_defconfig +1 -0
index 46f27be254..d562273bef 100644
@@ -7,6 +7,7 @@ CONFIG_MACPWR="PH23"
 CONFIG_MMC0_CD_PIN="PH10"
 CONFIG_MMC3_CD_PIN="PH11"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_USB1_VBUS_PIN="PH26"
 CONFIG_USB2_VBUS_PIN="PH22"
 CONFIG_VIDEO_COMPOSITE=y
configs/Sinlinx_SinA33_defconfig +1 -0
index 7841219a65..061f27c9db 100644
@@ -6,6 +6,7 @@ CONFIG_DRAM_CLK=552
 CONFIG_DRAM_ZQ=15291
 CONFIG_MMC0_CD_PIN="PB4"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_USB0_ID_DET="PH8"
 CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0"
 CONFIG_VIDEO_LCD_DCLK_PHASE=0
configs/Yones_Toptech_BD1078_defconfig +0 -0
index c49cbcbc3c..cad5618d54 100644
Quoted 8 lines

configs/Yones_Toptech_BD1078_defconfig CONFIG_MMC0_CD_PIN="PH1" · line 10

Quoted 5 lines
configs/Yones_Toptech_BD1078_defconfig +1 -0
@@ -7,6 +7,7 @@ CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC1_CD_PIN="PH2"
 CONFIG_MMC1_PINS="PH"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=1
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"

Again, you're breaking all these boards while saying you want to fix them.

Let me know what is breaking here, I'm trying to update the env device like before even if the order or detection follow as per DT.

#47 lore raw

PATCH 22/25 env: sunxi: Update default env fat device

Quoted 144 lines · Jagan Teki
Quoted 133 lines · Maxime Ripard
Quoted 132 lines · Jagan Teki

Usually eMMC is default env fat device for environment, if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc device as 1. but with DM_MMC it can be more possible to probe eMMC as device 2 since for most of the sunxi platforms eMMC is configured mmc2.

So update the env default device as 2 if DM_MMC and MMC_SUNXI_SLOT_EXTRA != 1 but some boards may not use all possible mmc devices or partly disabled in DT, for those update the device in board specific defconfig.

Cc Olliver Schinagl <[email protected]>
Cc Hans de Goede <[email protected]>
Cc Marcus Cooper <[email protected]>
Cc Stefan Mavrodiev <[email protected]>
Cc Paul Kocialkowski <[email protected]>
Cc Chen-Yu Tsai <[email protected]>
---
 configs/A20-OLinuXino-Lime2-eMMC_defconfig   | 1 +
 configs/A20-OLinuXino_MICRO-eMMC_defconfig   | 1 +
 configs/A20-OLinuXino_MICRO_defconfig        | 1 +
 configs/A20-Olimex-SOM-EVB_defconfig         | 1 +
 configs/A20-Olimex-SOM204-EVB-eMMC_defconfig | 1 +
 configs/Mele_M3_defconfig                    | 1 +
 configs/Orangepi_mini_defconfig              | 1 +
 configs/Sinlinx_SinA33_defconfig             | 1 +
 configs/Yones_Toptech_BD1078_defconfig       | 1 +
 configs/amarula_a64_relic_defconfig          | 1 +
 env/Kconfig                                  | 3 ++-
 11 files changed, 12 insertions(+), 1 deletion(-)
configs/A20-OLinuXino-Lime2-eMMC_defconfig +1 -0
index 20ea254191..98a8ceb178 100644
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_USB0_VBUS_PIN="PC17"
 CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_I2C1_ENABLE=y
configs/A20-OLinuXino_MICRO-eMMC_defconfig +1 -0
index f7e7cbab0a..1552960d88 100644
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_I2C1_ENABLE=y
 CONFIG_VIDEO_VGA=y
 CONFIG_SATAPWR="PB8"
configs/A20-OLinuXino_MICRO_defconfig +1 -0
index 8dcbdc08f9..b5f1b7efe2 100644
@@ -6,6 +6,7 @@ CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC3_CD_PIN="PH11"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_I2C1_ENABLE=y
 CONFIG_VIDEO_VGA=y
 CONFIG_SATAPWR="PB8"
configs/A20-Olimex-SOM-EVB_defconfig +1 -0
index a06499e2d0..58f6fbad91 100644
@@ -7,6 +7,7 @@ CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC3_CD_PIN="PH0"
 CONFIG_MMC3_PINS="PH"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_USB0_VBUS_PIN="PB9"
 CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_SATAPWR="PC3"
configs/A20-Olimex-SOM204-EVB-eMMC_defconfig +1 -0
index 3bb8c4c7e6..ac4f841c4e 100644
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_USB0_VBUS_PIN="PC17"
 CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_I2C1_ENABLE=y
configs/Mele_M3_defconfig +1 -0
index 9f48bd91e0..93a2395aee 100644
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_VIDEO_VGA=y
 CONFIG_VIDEO_COMPOSITE=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3"
configs/Orangepi_mini_defconfig +1 -0
index 46f27be254..d562273bef 100644
@@ -7,6 +7,7 @@ CONFIG_MACPWR="PH23"
 CONFIG_MMC0_CD_PIN="PH10"
 CONFIG_MMC3_CD_PIN="PH11"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_USB1_VBUS_PIN="PH26"
 CONFIG_USB2_VBUS_PIN="PH22"
 CONFIG_VIDEO_COMPOSITE=y
configs/Sinlinx_SinA33_defconfig +1 -0
index 7841219a65..061f27c9db 100644
@@ -6,6 +6,7 @@ CONFIG_DRAM_CLK=552
 CONFIG_DRAM_ZQ=15291
 CONFIG_MMC0_CD_PIN="PB4"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_USB0_ID_DET="PH8"
 CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0"
 CONFIG_VIDEO_LCD_DCLK_PHASE=0
configs/Yones_Toptech_BD1078_defconfig +0 -0
index c49cbcbc3c..cad5618d54 100644
Quoted 8 lines

configs/Yones_Toptech_BD1078_defconfig CONFIG_MMC0_CD_PIN="PH1" · line 10

Quoted 5 lines
configs/Yones_Toptech_BD1078_defconfig +1 -0
@@ -7,6 +7,7 @@ CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC1_CD_PIN="PH2"
 CONFIG_MMC1_PINS="PH"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=1
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"

Again, you're breaking all these boards while saying you want to fix them.

Quoted 2 lines

Let me know what is breaking here, I'm trying to update the env device like before even if the order or detection follow as per DT.

If the number is the one coming from the DT, then with DM_MMC, the ID will change for them as well and they will have the FAT device become 2 if they have an eMMC. Which is why you're changing the default.

However, you're also changing the defconfig so that the number remain the same, so you'll end up with the previous id being used, 1, which is not the eMMC one.

A proper fix would be to simply changing the default.

Maxime

Signature · 10 lines
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180717/a11e1644/attachment-0001.sig>
author
#48 lore raw

PATCH 22/25 env: sunxi: Update default env fat device

Quoted 148 lines · Maxime Ripard
Quoted 144 lines · Jagan Teki
Quoted 133 lines · Maxime Ripard
Quoted 132 lines · Jagan Teki

Usually eMMC is default env fat device for environment, if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc device as 1. but with DM_MMC it can be more possible to probe eMMC as device 2 since for most of the sunxi platforms eMMC is configured mmc2.

So update the env default device as 2 if DM_MMC and MMC_SUNXI_SLOT_EXTRA != 1 but some boards may not use all possible mmc devices or partly disabled in DT, for those update the device in board specific defconfig.

Cc Olliver Schinagl <[email protected]>
Cc Hans de Goede <[email protected]>
Cc Marcus Cooper <[email protected]>
Cc Stefan Mavrodiev <[email protected]>
Cc Paul Kocialkowski <[email protected]>
Cc Chen-Yu Tsai <[email protected]>
---
 configs/A20-OLinuXino-Lime2-eMMC_defconfig   | 1 +
 configs/A20-OLinuXino_MICRO-eMMC_defconfig   | 1 +
 configs/A20-OLinuXino_MICRO_defconfig        | 1 +
 configs/A20-Olimex-SOM-EVB_defconfig         | 1 +
 configs/A20-Olimex-SOM204-EVB-eMMC_defconfig | 1 +
 configs/Mele_M3_defconfig                    | 1 +
 configs/Orangepi_mini_defconfig              | 1 +
 configs/Sinlinx_SinA33_defconfig             | 1 +
 configs/Yones_Toptech_BD1078_defconfig       | 1 +
 configs/amarula_a64_relic_defconfig          | 1 +
 env/Kconfig                                  | 3 ++-
 11 files changed, 12 insertions(+), 1 deletion(-)
configs/A20-OLinuXino-Lime2-eMMC_defconfig +1 -0
index 20ea254191..98a8ceb178 100644
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_USB0_VBUS_PIN="PC17"
 CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_I2C1_ENABLE=y
configs/A20-OLinuXino_MICRO-eMMC_defconfig +1 -0
index f7e7cbab0a..1552960d88 100644
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_I2C1_ENABLE=y
 CONFIG_VIDEO_VGA=y
 CONFIG_SATAPWR="PB8"
configs/A20-OLinuXino_MICRO_defconfig +1 -0
index 8dcbdc08f9..b5f1b7efe2 100644
@@ -6,6 +6,7 @@ CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC3_CD_PIN="PH11"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_I2C1_ENABLE=y
 CONFIG_VIDEO_VGA=y
 CONFIG_SATAPWR="PB8"
configs/A20-Olimex-SOM-EVB_defconfig +1 -0
index a06499e2d0..58f6fbad91 100644
@@ -7,6 +7,7 @@ CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC3_CD_PIN="PH0"
 CONFIG_MMC3_PINS="PH"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_USB0_VBUS_PIN="PB9"
 CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_SATAPWR="PC3"
configs/A20-Olimex-SOM204-EVB-eMMC_defconfig +1 -0
index 3bb8c4c7e6..ac4f841c4e 100644
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_USB0_VBUS_PIN="PC17"
 CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_I2C1_ENABLE=y
configs/Mele_M3_defconfig +1 -0
index 9f48bd91e0..93a2395aee 100644
@@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_VIDEO_VGA=y
 CONFIG_VIDEO_COMPOSITE=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3"
configs/Orangepi_mini_defconfig +1 -0
index 46f27be254..d562273bef 100644
@@ -7,6 +7,7 @@ CONFIG_MACPWR="PH23"
 CONFIG_MMC0_CD_PIN="PH10"
 CONFIG_MMC3_CD_PIN="PH11"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_USB1_VBUS_PIN="PH26"
 CONFIG_USB2_VBUS_PIN="PH22"
 CONFIG_VIDEO_COMPOSITE=y
configs/Sinlinx_SinA33_defconfig +1 -0
index 7841219a65..061f27c9db 100644
@@ -6,6 +6,7 @@ CONFIG_DRAM_CLK=552
 CONFIG_DRAM_ZQ=15291
 CONFIG_MMC0_CD_PIN="PB4"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"
 CONFIG_USB0_ID_DET="PH8"
 CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0"
 CONFIG_VIDEO_LCD_DCLK_PHASE=0
configs/Yones_Toptech_BD1078_defconfig +0 -0
index c49cbcbc3c..cad5618d54 100644
Quoted 8 lines

configs/Yones_Toptech_BD1078_defconfig CONFIG_MMC0_CD_PIN="PH1" · line 10

Quoted 5 lines
configs/Yones_Toptech_BD1078_defconfig +1 -0
@@ -7,6 +7,7 @@ CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC1_CD_PIN="PH2"
 CONFIG_MMC1_PINS="PH"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=1
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto"

Again, you're breaking all these boards while saying you want to fix them.

Quoted 2 lines

Let me know what is breaking here, I'm trying to update the env device like before even if the order or detection follow as per DT.

Quoted 7 lines

If the number is the one coming from the DT, then with DM_MMC, the ID will change for them as well and they will have the FAT device become 2 if they have an eMMC. Which is why you're changing the default.

However, you're also changing the defconfig so that the number remain the same, so you'll end up with the previous id being used, 1, which is not the eMMC one.

ie what I'm trying here. Say for example A20-OLinuXino-LIME2-eMMC board based on the kconfig with 2 SLOTS and DM_MMC defined the default fat device is 2 but since the sun7i-a20-olinuxino-lime2-emmc.dts has only mmc0 and mmc2 (which is eMMC) due to missing mmc1 the eMMC will probed on device 1 ie what I'm trying to update in defconfig.

Quoted 1 line

A proper fix would be to simply changing the default.

No idea how can we support this, how about give device input to saveenv command.

author
#49 lore raw

PATCH 23/25 sunxi: Use mmc_bootdev=2 for MMC2 boot

In reply to Jagan Teki

With DM_MMC the mmc devices are probed as per dt status and eMMC can probed maximum device of 2, if all nodes like mmc0, mmc1 and mmc2 status are 'okay'.

So update mmc_bootdev to 2 and add boot order as 2, 1, 0 devices. so-that it can to boot any identified device even if the respective device status disabled or unsupported.

---
 board/sunxi/board.c            | 2 +-
 include/configs/sunxi-common.h | 4 +++-
 2 files changed, 4 insertions(+), 2 deletions(-)
board/sunxi/board.c +1 -1
index 5ed1b8bae1..7edc468185 100644
@@ -768,7 +768,7 @@ int misc_init_r(void)
 	} else if (boot == BOOT_DEVICE_MMC1) {
 		env_set("mmc_bootdev", "0");
 	} else if (boot == BOOT_DEVICE_MMC2) {
-		env_set("mmc_bootdev", "1");
+		env_set("mmc_bootdev", "2");
 	}
 
 	setup_environment(gd->fdt_blob);
include/configs/sunxi-common.h +3 -1
index 21371f4919..abf10f6dcf 100644
@@ -373,8 +373,10 @@ extern int soft_i2c_gpio_scl;
 #define BOOTENV_DEV_MMC_AUTO(devtypeu, devtypel, instance)		\
 	BOOTENV_DEV_MMC(MMC, mmc, 0)					\
 	BOOTENV_DEV_MMC(MMC, mmc, 1)					\
+	BOOTENV_DEV_MMC(MMC, mmc, 2)					\
 	"bootcmd_mmc_auto="						\
-		"if test ${mmc_bootdev} -eq 1; then "			\
+		"if test ${mmc_bootdev} -eq 2; then "			\
+			"run bootcmd_mmc2; "				\
 			"run bootcmd_mmc1; "				\
 			"run bootcmd_mmc0; "				\
 		"elif test ${mmc_bootdev} -eq 0; then "			\
Signature · 1 line
2.17.1
#50 lore raw

PATCH 23/25 sunxi: Use mmc_bootdev=2 for MMC2 boot

Quoted 19 lines · Jagan Teki

With DM_MMC the mmc devices are probed as per dt status and eMMC can probed maximum device of 2, if all nodes like mmc0, mmc1 and mmc2 status are 'okay'.

So update mmc_bootdev to 2 and add boot order as 2, 1, 0 devices. so-that it can to boot any identified device even if the respective device status disabled or unsupported.

---
 board/sunxi/board.c            | 2 +-
 include/configs/sunxi-common.h | 4 +++-
 2 files changed, 4 insertions(+), 2 deletions(-)
board/sunxi/board.c +0 -0
index 5ed1b8bae1..7edc468185 100644

board/sunxi/board.c int misc_init_r(void) · line 771

Quoted 5 lines
board/sunxi/board.c +1 -1
@@ -768,7 +768,7 @@ int misc_init_r(void)
 	} else if (boot == BOOT_DEVICE_MMC1) {
 		env_set("mmc_bootdev", "0");
 	} else if (boot == BOOT_DEVICE_MMC2) {
-		env_set("mmc_bootdev", "1");
+		env_set("mmc_bootdev", "2");

Isn't that broken too? I guess we should return MMC3 in that case.

Also, what about bisectability?

Maxime

Signature · 10 lines
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180716/32189e2a/attachment.sig>
#51 lore raw

PATCH 23/25 sunxi: Use mmc_bootdev=2 for MMC2 boot

Quoted 15 lines · Maxime Ripard
Quoted 14 lines · Jagan Teki

With DM_MMC the mmc devices are probed as per dt status and eMMC can probed maximum device of 2, if all nodes like mmc0, mmc1 and mmc2 status are 'okay'.

So update mmc_bootdev to 2 and add boot order as 2, 1, 0 devices. so-that it can to boot any identified device even if the respective device status disabled or unsupported.

---
 board/sunxi/board.c            | 2 +-
 include/configs/sunxi-common.h | 4 +++-
 2 files changed, 4 insertions(+), 2 deletions(-)
Quoted 12 lines

board/sunxi/board.c int misc_init_r(void) · line 771

Quoted 10 lines
board/sunxi/board.c +1 -1
index 5ed1b8bae1..7edc468185 100644
@@ -768,7 +768,7 @@ int misc_init_r(void)
      } else if (boot == BOOT_DEVICE_MMC1) {
              env_set("mmc_bootdev", "0");
      } else if (boot == BOOT_DEVICE_MMC2) {
-             env_set("mmc_bootdev", "1");
+             env_set("mmc_bootdev", "2");

Isn't that broken too? I guess we should return MMC3 in that case.

Yes, A10 has maximum of mmc3 will fix.

Quoted 2 lines

Also, what about bisectability?

are you referring order check while booting, ie reason I've update the ordering with device 2, 1, 0

#52 lore raw

PATCH 23/25 sunxi: Use mmc_bootdev=2 for MMC2 boot

Quoted 30 lines · Jagan Teki
Quoted 15 lines · Maxime Ripard
Quoted 14 lines · Jagan Teki

With DM_MMC the mmc devices are probed as per dt status and eMMC can probed maximum device of 2, if all nodes like mmc0, mmc1 and mmc2 status are 'okay'.

So update mmc_bootdev to 2 and add boot order as 2, 1, 0 devices. so-that it can to boot any identified device even if the respective device status disabled or unsupported.

---
 board/sunxi/board.c            | 2 +-
 include/configs/sunxi-common.h | 4 +++-
 2 files changed, 4 insertions(+), 2 deletions(-)
Quoted 12 lines

board/sunxi/board.c int misc_init_r(void) · line 771

Quoted 10 lines
board/sunxi/board.c +1 -1
index 5ed1b8bae1..7edc468185 100644
@@ -768,7 +768,7 @@ int misc_init_r(void)
      } else if (boot == BOOT_DEVICE_MMC1) {
              env_set("mmc_bootdev", "0");
      } else if (boot == BOOT_DEVICE_MMC2) {
-             env_set("mmc_bootdev", "1");
+             env_set("mmc_bootdev", "2");

Isn't that broken too? I guess we should return MMC3 in that case.

Quoted 7 lines

Yes, A10 has maximum of mmc3 will fix.

Quoted 2 lines

Also, what about bisectability?

are you referring order check while booting, ie reason I've update the ordering with device 2, 1, 0

No, I'm referring to the fact that each and every commit of your serie should be bootable and fully working without any regression. Selecting DM_MMC and then fixing the IDs in that case breaks that assumption.

Maxime

Signature · 10 lines
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180717/53d1cee1/attachment.sig>
author
#53 lore raw

PATCH 24/25 sunxi: A13/A31: Enable DM_MMC

In reply to Jagan Teki

Enable DM_MMC for Allwinner A13/A31 SoC.

---
 arch/arm/mach-sunxi/Kconfig | 2 ++
 1 file changed, 2 insertions(+)
arch/arm/mach-sunxi/Kconfig +2 -0
index f3d7c8b67d..0d277f9e2b 100644
@@ -155,6 +155,7 @@ config MACH_SUN5I
 	select CPU_V7A
 	select ARM_CORTEX_CPU_IS_UP
 	select DRAM_SUN4I
+	select DM_MMC if MMC
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL
@@ -167,6 +168,7 @@ config MACH_SUN6I
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
 	select DRAM_SUN6I
+	select DM_MMC if MMC
 	select PHY_SUN4I_USB
 	select SUN6I_P2WI
 	select SUN6I_PRCM
Signature · 1 line
2.17.1
author
#54 lore raw

PATCH 25/25 sunxi: A23/A33/V3S: Enable DM_MMC

In reply to Jagan Teki

Enable DM_MMC for Allwinner A23/A33/V3S SoC.

---
 arch/arm/mach-sunxi/Kconfig | 3 +++
 1 file changed, 3 insertions(+)
arch/arm/mach-sunxi/Kconfig +3 -0
index 0d277f9e2b..be1ff10212 100644
@@ -196,6 +196,7 @@ config MACH_SUN8I_A23
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
 	select DRAM_SUN8I_A23
+	select DM_MMC if MMC
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
@@ -209,6 +210,7 @@ config MACH_SUN8I_A33
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
 	select DRAM_SUN8I_A33
+	select DM_MMC if MMC
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
@@ -252,6 +254,7 @@ config MACH_SUN8I_V3S
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
+	select DM_MMC if MMC
 	select SUNXI_GEN_SUN6I
 	select SUNXI_DRAM_DW
 	select SUNXI_DRAM_DW_16BIT
Signature · 1 line
2.17.1
#55 lore raw

cover sunxi: Enable DM_MMC for U-Boot proper

In reply to Jagan Teki
Quoted 11 lines · Jagan Teki

Enabling DM_MMC is not straight forward for Allwinner SoC's to make proper compatibility in mmc driver vs DT nodes.

Existing dm code for ahb gate clock will be suitable to handle sun4i,5i,6i and 7i U-Boot specific mmc dt nodes, which are different from Linux in terms of clocks phandle notation.

U-Boot DT clocks phandle follow direct ahb and clock address on node definition with specific bit position, but Linux clocks phandle follow macros to define AHB and MMC clocks so-that the ccu driver will set the bits accordingly.

And that has been deprecated upstream.

Quoted 3 lines

Clocks phandle notations in U-Boot for higher Allwinner SoC start from sun8i, sun50i are following Linux notation so-that both Linux and U-Boot can have common node definition.

So basically you're saying the additional code for clock/reset handling through the device tree only works for half of the SoCs, based on a deprecated device tree binding. Which means we're going to throw it out some time in the future. Is it worth the churn of driver and device tree changes?

IMHO the new clock handling code is no better than the old. The only thing that has changed is how the clock register address is derived. Not even the index numbers, which BTW are actual bit offsets, for the AHB gates from the device tree are used. Neither is the device tree used for the AHB resets.

If we remove that portion from the series, and also sync up all device tree files to Linux 4.17 (or a later -rc or -next), instead of manually adding device nodes based on the old device tree binding, it probably would still work.

Regards
ChenYu

Quoted 107 lines

This series will address the ahb gate, clock setup to handle all type of Allwinner SoCs. and sync mmc node definitions from Linux for sun4i and sun5i.

Note:
- sun6i, A23, A33, V3S were untested these need to have a closer look on dt nodes along with default ENV_FAT device.

All these changes available at u-boot-sunxi/next

Let me know if any questions or missings,
Jagan.

Jagan Teki (25):
ARM: dts: sun4i: Sync A10 MMC nodes from Linux
ARM: dts: sun4i: Sync A10 board dts mmc0 node from Linux
ARM: dts: sun4i: Add mmc0 node for iNet 3F
ARM: dts: sun4i: Add mmc0 node for iNet 3W
dm: mmc: sunxi: Refactor ahb gate and clock setup
dm: mmc: sunxi: Add ahb reset0 register write
ARM: dts: sun7i: Sync A20 MMC nodes from Linux
ARM: dts: sun7i: Add mmc0 node for Primo73 tablet
ARM: dts: sun7i: Add mmc0 node for Ainol AW1
ARM: dts: sun7i: Add mmc0 node for Mele M5
ARM: dts: sun7i: Add mmc0 node for Toptech BD1078
sunxi: A20: Enable DM_MMC
mmc: sunxi: Add mmc, emmc H5/A64 compatible
sunxi: H3_H5: Enable DM_MMC
sunxi: A64: Enable DM_MMC
ARM: dts: sun8i: Update A83T dts(i) files from Linux
mmc: sunxi: Add A83T emmc compatible
sunxi: A83T: Enable DM_MMC
ARM: dts: sun8i: Update R40 dts(i) files from Linux
sunxi: V40: Enable DM_MMC
fastboot: sunxi: Update fastboot mmc default device
env: sunxi: Update default env fat device
sunxi: Use mmc_bootdev=2 for MMC2 boot
[DO NOT MERGE] sunxi: A13/A31: Enable DM_MMC [DO NOT MERGE] sunxi: A23/A33/V3S: Enable DM_MMC

 arch/arm/dts/axp81x.dtsi                      | 169 ++++
 arch/arm/dts/sun4i-a10-a1000.dts              |   5 +-
 arch/arm/dts/sun4i-a10-ba10-tvbox.dts         |   5 +-
 arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts    |   5 +-
 arch/arm/dts/sun4i-a10-cubieboard.dts         |   5 +-
 arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts   |   5 +-
 arch/arm/dts/sun4i-a10-gemei-g9.dts           |   5 +-
 arch/arm/dts/sun4i-a10-hackberry.dts          |   5 +-
 arch/arm/dts/sun4i-a10-hyundai-a7hd.dts       |   5 +-
 arch/arm/dts/sun4i-a10-inet-3f.dts            |   9 +
 arch/arm/dts/sun4i-a10-inet-3w.dts            |   9 +
 arch/arm/dts/sun4i-a10-inet1.dts              |   5 +-
 arch/arm/dts/sun4i-a10-inet97fv2.dts          |   5 +-
 arch/arm/dts/sun4i-a10-inet9f-rev03.dts       |   5 +-
 .../dts/sun4i-a10-itead-iteaduino-plus.dts    |   5 +-
 arch/arm/dts/sun4i-a10-jesurun-q5.dts         |   5 +-
 arch/arm/dts/sun4i-a10-marsboard.dts          |   5 +-
 arch/arm/dts/sun4i-a10-mini-xplus.dts         |   5 +-
 arch/arm/dts/sun4i-a10-mk802.dts              |   5 +-
 arch/arm/dts/sun4i-a10-mk802ii.dts            |   5 +-
 arch/arm/dts/sun4i-a10-olinuxino-lime.dts     |   5 +-
 arch/arm/dts/sun4i-a10-pcduino.dts            |   5 +-
 arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts   |   5 +-
 arch/arm/dts/sun4i-a10.dtsi                   | 112 +--
 arch/arm/dts/sun7i-a20-ainol-aw1.dts          |  13 +
 arch/arm/dts/sun7i-a20-m5.dts                 |  12 +
 arch/arm/dts/sun7i-a20-primo73.dts            |  20 +-
 .../dts/sun7i-a20-yones-toptech-bd1078.dts    |  13 +
 arch/arm/dts/sun7i-a20.dtsi                   | 102 +-
 .../dts/sun8i-a83t-allwinner-h8homlet-v2.dts  | 195 +++-
 arch/arm/dts/sun8i-a83t-bananapi-m3.dts       | 298 +++++-
 arch/arm/dts/sun8i-a83t-cubietruck-plus.dts   | 322 ++++++-
 arch/arm/dts/sun8i-a83t-tbs-a711.dts          | 355 ++++++-
 arch/arm/dts/sun8i-a83t.dtsi                  | 885 ++++++++++++++++--
 arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts  | 197 +++-
 arch/arm/dts/sun8i-r40.dtsi                   | 616 +++++++++++-
 arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts  |  50 +
 arch/arm/mach-sunxi/Kconfig                   |  10 +
 board/sunxi/board.c                           |   2 +-
 configs/A20-OLinuXino-Lime2-eMMC_defconfig    |   2 +
 configs/A20-OLinuXino_MICRO-eMMC_defconfig    |   1 +
 configs/A20-OLinuXino_MICRO_defconfig         |   1 +
 configs/A20-Olimex-SOM-EVB_defconfig          |   1 +
 configs/A20-Olimex-SOM204-EVB-eMMC_defconfig  |   1 +
 configs/Mele_M3_defconfig                     |   1 +
 configs/Orangepi_mini_defconfig               |   1 +
 configs/Sinlinx_SinA33_defconfig              |   2 +
 configs/Yones_Toptech_BD1078_defconfig        |   1 +
 configs/amarula_a64_relic_defconfig           |   2 +
 drivers/fastboot/Kconfig                      |   3 +-
 drivers/mmc/sunxi_mmc.c                       |  81 +-
 env/Kconfig                                   |   3 +-
 include/configs/sunxi-common.h                |   4 +-
 include/dt-bindings/clock/sun4i-a10-ccu.h     | 202 ++++
 include/dt-bindings/clock/sun7i-a20-ccu.h     |  53 ++
 include/dt-bindings/clock/sun8i-a83t-ccu.h    | 140 +++
 include/dt-bindings/reset/sun8i-a83t-ccu.h    |  98 ++
 57 files changed, 3715 insertions(+), 371 deletions(-)
 create mode 100644 arch/arm/dts/axp81x.dtsi
 create mode 100644 include/dt-bindings/clock/sun4i-a10-ccu.h
 create mode 100644 include/dt-bindings/clock/sun7i-a20-ccu.h
 create mode 100644 include/dt-bindings/clock/sun8i-a83t-ccu.h
 create mode 100644 include/dt-bindings/reset/sun8i-a83t-ccu.h

--
2.17.1

#56 lore raw

cover sunxi: Enable DM_MMC for U-Boot proper

Quoted 25 lines · Chen-Yu Tsai
Quoted 11 lines · Jagan Teki

Enabling DM_MMC is not straight forward for Allwinner SoC's to make proper compatibility in mmc driver vs DT nodes.

Existing dm code for ahb gate clock will be suitable to handle sun4i,5i,6i and 7i U-Boot specific mmc dt nodes, which are different from Linux in terms of clocks phandle notation.

U-Boot DT clocks phandle follow direct ahb and clock address on node definition with specific bit position, but Linux clocks phandle follow macros to define AHB and MMC clocks so-that the ccu driver will set the bits accordingly.

And that has been deprecated upstream.

Quoted 3 lines

Clocks phandle notations in U-Boot for higher Allwinner SoC start from sun8i, sun50i are following Linux notation so-that both Linux and U-Boot can have common node definition.

So basically you're saying the additional code for clock/reset handling through the device tree only works for half of the SoCs, based on a deprecated device tree binding. Which means we're going to throw it out some time in the future. Is it worth the churn of driver and device tree changes?

Quoted 5 lines

IMHO the new clock handling code is no better than the old. The only thing that has changed is how the clock register address is derived. Not even the index numbers, which BTW are actual bit offsets, for the AHB gates from the device tree are used. Neither is the device tree used for the AHB resets.

I'd say that it's even worse. We want an actual, common, clock driver. Not a quick hack that doesn't solve any of the issues we're facing.

Maxime

Signature · 10 lines
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20180716/f1e08381/attachment.sig>
#57 lore raw

cover sunxi: Enable DM_MMC for U-Boot proper

Hi,

Quoted 32 lines · Maxime Ripard
Quoted 25 lines · Chen-Yu Tsai
Quoted 11 lines · Jagan Teki

Enabling DM_MMC is not straight forward for Allwinner SoC's to make proper compatibility in mmc driver vs DT nodes.

Existing dm code for ahb gate clock will be suitable to handle sun4i,5i,6i and 7i U-Boot specific mmc dt nodes, which are different from Linux in terms of clocks phandle notation.

U-Boot DT clocks phandle follow direct ahb and clock address on node definition with specific bit position, but Linux clocks phandle follow macros to define AHB and MMC clocks so-that the ccu driver will set the bits accordingly.

And that has been deprecated upstream.

Quoted 3 lines

Clocks phandle notations in U-Boot for higher Allwinner SoC start from sun8i, sun50i are following Linux notation so-that both Linux and U-Boot can have common node definition.

So basically you're saying the additional code for clock/reset handling through the device tree only works for half of the SoCs, based on a deprecated device tree binding. Which means we're going to throw it out some time in the future. Is it worth the churn of driver and device tree changes?

Quoted 5 lines

IMHO the new clock handling code is no better than the old. The only thing that has changed is how the clock register address is derived. Not even the index numbers, which BTW are actual bit offsets, for the AHB gates from the device tree are used. Neither is the device tree used for the AHB resets.

Quoted 3 lines

I'd say that it's even worse. We want an actual, common, clock driver. Not a quick hack that doesn't solve any of the issues we're facing.

So is the purpose of this whole series to just comply with the deprecation of non-DM_MMC configurations?
As mentioned before I am wondering how useful this is, and if we could ever get rid of those hardcoded hacks for the SPL anyway (so the driver would technically be DM_MMC compliant, but still had non-DM_MMC code in). So I would suggest we push the clock DM driver forward first [1], implementing the new CCU binding, then possibly convert over the pre-H3 boards.
And meanwhile we try to appease the maintainers to not remove any boards which don't support DM_MMC, because the purpose of U-Boot should be to get boards booting and not to have some fancy driver model just for the sake of it.

Cheers,
Andre.

[1] https://github.com/apritzel/u-boot/commits/sunxi-dm-WIP

author
#58 lore raw

cover sunxi: Enable DM_MMC for U-Boot proper

Quoted 39 lines · Andre Przywara

Hi,

Quoted 32 lines · Maxime Ripard
Quoted 25 lines · Chen-Yu Tsai
Quoted 11 lines · Jagan Teki

Enabling DM_MMC is not straight forward for Allwinner SoC's to make proper compatibility in mmc driver vs DT nodes.

Existing dm code for ahb gate clock will be suitable to handle sun4i,5i,6i and 7i U-Boot specific mmc dt nodes, which are different from Linux in terms of clocks phandle notation.

U-Boot DT clocks phandle follow direct ahb and clock address on node definition with specific bit position, but Linux clocks phandle follow macros to define AHB and MMC clocks so-that the ccu driver will set the bits accordingly.

And that has been deprecated upstream.

Quoted 3 lines

Clocks phandle notations in U-Boot for higher Allwinner SoC start from sun8i, sun50i are following Linux notation so-that both Linux and U-Boot can have common node definition.

So basically you're saying the additional code for clock/reset handling through the device tree only works for half of the SoCs, based on a deprecated device tree binding. Which means we're going to throw it out some time in the future. Is it worth the churn of driver and device tree changes?

Quoted 5 lines

IMHO the new clock handling code is no better than the old. The only thing that has changed is how the clock register address is derived. Not even the index numbers, which BTW are actual bit offsets, for the AHB gates from the device tree are used. Neither is the device tree used for the AHB resets.

Quoted 3 lines

I'd say that it's even worse. We want an actual, common, clock driver. Not a quick hack that doesn't solve any of the issues we're facing.

Quoted 5 lines

So is the purpose of this whole series to just comply with the deprecation of non-DM_MMC configurations?
As mentioned before I am wondering how useful this is, and if we could ever get rid of those hardcoded hacks for the SPL anyway (so the driver would technically be DM_MMC compliant, but still had non-DM_MMC code in).

The migration idea about DM_MMC would be for U-Boot proper[2] (not for SPL as of now). Even if we put the migration aside, we have a problem with SPL size for DM_MMC for arm64 SoCs. indeed we need to wait for this to fix for having full DM_MMC code.

[2] https://patchwork.ozlabs.org/patch/933761/