clk: Add Allwinner CLK, RESET support

new file mode 100644
index 0000000000..f628c893de
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions.
+ * Author: Jagan Teki <[email protected]>
+ */
+
+#ifndef _ASM_ARCH_CCU_H
+#define _ASM_ARCH_CCU_H
+
+/**
+ * ccu_clk_map - common clock unit clock map
+ *
+ * @off:		ccu clock offset
+ * @bit:		ccu clock bit value
+ * @ccu_clk_set_rate:	ccu clock set rate func
+ */
+struct ccu_clk_map {
+	u16 off;
+	u32 bit;
+	int (*ccu_clk_set_rate)(void *base, u32 bit, ulong rate);
+};
+
+/**
+ * struct ccu_desc - common clock unit descriptor
+ *
+ * @clks:		mapping clocks descriptor
+ * @num_clks:		number of mapped clocks
+ */
+struct ccu_desc {
+	struct ccu_clk_map *clks;
+	unsigned long num_clks;
+};
+
+/**
+ * struct sunxi_clk_priv - sunxi clock private structure
+ *
+ * @base:	base address
+ * @desc:	ccu descriptor
+ */
+struct sunxi_clk_priv {
+	void *base;
+	const struct ccu_desc *desc;
+};
+
+extern struct clk_ops sunxi_clk_ops;
+
+#endif /* _ASM_ARCH_CCU_H */

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index 3899537635..99881b8b99 100644
@@ -14,6 +14,11 @@ static inline struct reset_ops *reset_dev_ops(struct udevice *dev)
 	return (struct reset_ops *)dev->driver->ops;
 }
 
+static int reset_request_default(struct reset_ctl *reset_ctl)
+{
+	return 0;
+}
+
 static int reset_of_xlate_default(struct reset_ctl *reset_ctl,
 				  struct ofnode_phandle_args *args)
 {

@@ -69,7 +74,10 @@ int reset_get_by_index(struct udevice *dev, int index,
 		return ret;
 	}
 
-	ret = ops->request(reset_ctl);
+	if (ops->request)
+		ret = ops->request(reset_ctl);
+	else
+		ret = reset_request_default(reset_ctl);
 	if (ret) {
 		debug("ops->request() failed: %d\n", ret);
 		return ret;

index f628c893de..bacd052ef3 100644
@@ -20,15 +20,31 @@ struct ccu_clk_map {
 	int (*ccu_clk_set_rate)(void *base, u32 bit, ulong rate);
 };
 
+/**
+ * ccu_reset_map - common clock unit reset map
+ *
+ * @off:	ccu reset offset
+ * @bit:	ccu reset bit value
+ */
+struct ccu_reset_map {
+	u16 off;
+	u32 bit;
+};
+
 /**
  * struct ccu_desc - common clock unit descriptor
  *
  * @clks:		mapping clocks descriptor
  * @num_clks:		number of mapped clocks
+ * @resets:		mapping resets descriptor
+ * @num_resets:		number of mapped resets
  */
 struct ccu_desc {
 	struct ccu_clk_map *clks;
 	unsigned long num_clks;
+
+	struct ccu_reset_map *resets;
+	unsigned long num_resets;
 };
 
 /**

@@ -44,4 +60,13 @@ struct sunxi_clk_priv {
 
 extern struct clk_ops sunxi_clk_ops;
 
+/**
+ * sunxi_reset_bind() - reset binding
+ *
+ * @dev:	reset device
+ * @count:	reset count
+ * @return 0 success, or error value
+ */
+int sunxi_reset_bind(struct udevice *dev, ulong count);
+
 #endif /* _ASM_ARCH_CCU_H */

index 9393a01ccf..890bf8ca21 100644
@@ -10,6 +10,7 @@
 #include <errno.h>
 #include <asm/arch/ccu.h>
 #include <dt-bindings/clock/sun50i-a64-ccu.h>
+#include <dt-bindings/reset/sun50i-a64-ccu.h>
 
 static struct ccu_clk_map a64_clks[] = {
 	[CLK_BUS_OTG]		= { 0x060, BIT(23), NULL },

@@ -26,9 +27,24 @@ static struct ccu_clk_map a64_clks[] = {
 	[CLK_USB_OHCI1]		= { 0x0cc, BIT(17), NULL },
 };
 
+static struct ccu_reset_map a64_resets[] = {
+	[RST_USB_PHY0]		=  { 0x0cc, BIT(0) },
+	[RST_USB_PHY1]		=  { 0x0cc, BIT(1) },
+	[RST_USB_HSIC]		=  { 0x0cc, BIT(2) },
+
+	[RST_BUS_OTG]		=  { 0x2c0, BIT(23) },
+	[RST_BUS_EHCI0]		=  { 0x2c0, BIT(24) },
+	[RST_BUS_EHCI1]		=  { 0x2c0, BIT(25) },
+	[RST_BUS_OHCI0]		=  { 0x2c0, BIT(28) },
+	[RST_BUS_OHCI1]		=  { 0x2c0, BIT(29) },
+};
+
 static const struct ccu_desc sun50i_a64_ccu_desc = {
 	.clks = a64_clks,
 	.num_clks = ARRAY_SIZE(a64_clks),
+
+	.resets = a64_resets,
+	.num_resets =  ARRAY_SIZE(a64_resets),
 };
 
 static int a64_clk_probe(struct udevice *dev)

@@ -46,6 +62,11 @@ static int a64_clk_probe(struct udevice *dev)
 	return 0;
 }
 
+static int a64_clk_bind(struct udevice *dev)
+{
+	return sunxi_reset_bind(dev, 50);
+}
+
 static const struct udevice_id a64_clk_ids[] = {
 	{ .compatible = "allwinner,sun50i-a64-ccu",
 	  .data = (ulong)&sun50i_a64_ccu_desc },

@@ -59,4 +80,5 @@ U_BOOT_DRIVER(clk_sun50i_a64) = {
 	.priv_auto_alloc_size	= sizeof(struct sunxi_clk_priv),
 	.ops		= &sunxi_clk_ops,
 	.probe		= a64_clk_probe,
+	.bind		= a64_clk_bind,
 };

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index 8cd9d3a4bc..424e065a66 100644
@@ -65,6 +65,8 @@ static int a23_clk_bind(struct udevice *dev)
 static const struct udevice_id a23_clk_ids[] = {
 	{ .compatible = "allwinner,sun8i-a23-ccu",
 	  .data = (ulong)&sun8i_a23_ccu_desc },
+	{ .compatible = "allwinner,sun8i-a33-ccu",
+	  .data = (ulong)&sun8i_a23_ccu_desc },
 	{ }
 };
 

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index 9f71b84fd1..440be83f4e 100644
@@ -16,9 +16,11 @@
  * This file is part of the Inventra Controller Driver for Linux.
  */
 #include <common.h>
+#include <clk.h>
 #include <dm.h>
 #include <generic-phy.h>
 #include <phy-sun4i-usb.h>
+#include <reset.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>

@@ -78,16 +80,15 @@
 
 struct sunxi_musb_config {
 	struct musb_hdrc_config *config;
-	u8 rst_bit;
-	u8 clkgate_bit;
 };
 
 struct sunxi_glue {
 	struct musb_host_data mdata;
-	struct sunxi_ccm_reg *ccm;
 	struct sunxi_musb_config *cfg;
 	struct device dev;
 	struct phy phy;
+	struct clk clocks;
+	struct reset_ctl resets;
 };
 #define to_sunxi_glue(d)	container_of(d, struct sunxi_glue, dev)
 

@@ -291,6 +292,18 @@ static int sunxi_musb_init(struct musb *musb)
 
 	pr_debug("%s():\n", __func__);
 
+	ret = clk_enable(&glue->clocks);
+	if (ret) {
+		dev_err(dev, "failed to enable clock\n");
+		return ret;
+	}
+
+	ret = reset_deassert(&glue->resets);
+	if (ret) {
+		dev_err(dev, "failed to deassert reset\n");
+		return ret;
+	}
+
 	ret = generic_phy_init(&glue->phy);
 	if (ret) {
 		pr_err("failed to init USB PHY\n");

@@ -299,17 +312,6 @@ static int sunxi_musb_init(struct musb *musb)
 
 	musb->isr = sunxi_musb_interrupt;
 
-	setbits_le32(&glue->ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_USB0));
-	if (glue->cfg->clkgate_bit)
-		setbits_le32(&glue->ccm->ahb_gate0,
-			     BIT(glue->cfg->clkgate_bit));
-#ifdef CONFIG_SUNXI_GEN_SUN6I
-	setbits_le32(&glue->ccm->ahb_reset0_cfg, BIT(AHB_GATE_OFFSET_USB0));
-	if (glue->cfg->rst_bit)
-		setbits_le32(&glue->ccm->ahb_reset0_cfg,
-			     BIT(glue->cfg->rst_bit));
-#endif
-
 	USBC_ConfigFIFO_Base();
 	USBC_EnableDpDmPullUp(musb->mregs);
 	USBC_EnableIdPullUp(musb->mregs);

@@ -339,16 +341,17 @@ static int sunxi_musb_exit(struct musb *musb)
 		}
 	}
 
-#ifdef CONFIG_SUNXI_GEN_SUN6I
-	clrbits_le32(&glue->ccm->ahb_reset0_cfg, BIT(AHB_GATE_OFFSET_USB0));
-	if (glue->cfg->rst_bit)
-		clrbits_le32(&glue->ccm->ahb_reset0_cfg,
-			     BIT(glue->cfg->rst_bit));
-#endif
-	clrbits_le32(&glue->ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_USB0));
-	if (glue->cfg->clkgate_bit)
-		clrbits_le32(&glue->ccm->ahb_gate0,
-			     BIT(glue->cfg->clkgate_bit));
+	ret = reset_assert(&glue->resets);
+	if (ret) {
+		dev_err(dev, "failed to deassert reset\n");
+		return ret;
+	}
+
+	ret = clk_disable(&glue->clocks);
+	if (ret) {
+		dev_err(dev, "failed to enable clock\n");
+		return ret;
+	}
 
 	return 0;
 }

@@ -433,6 +436,7 @@ static int musb_usb_probe(struct udevice *dev)
 	struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
 	struct musb_hdrc_platform_data pdata;
 	void *base = dev_read_addr_ptr(dev);
+	int clock_nb, reset_nb;
 	int ret;
 
 	if (!base)

@@ -442,9 +446,31 @@ static int musb_usb_probe(struct udevice *dev)
 	if (!glue->cfg)
 		return -EINVAL;
 
-	glue->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-	if (IS_ERR(glue->ccm))
-		return PTR_ERR(glue->ccm);
+	clock_nb = ofnode_count_phandle_with_args(dev_ofnode(dev), "clocks",
+						  "#clock-cells");
+	if (clock_nb < 0) {
+		dev_err(dev, "failed to get clock phandle(%d)\n", clock_nb);
+		return clock_nb;
+	}
+
+	ret = clk_get_by_index(dev, 0, &glue->clocks);
+	if (ret) {
+		dev_err(dev, "failed to get clock 0\n");
+		clk_free(&glue->clocks);
+	}
+
+	reset_nb = ofnode_count_phandle_with_args(dev_ofnode(dev), "resets",
+						  "#reset-cells");
+	if (reset_nb < 0) {
+		dev_err(dev, "failed to get reset phandle(%d)\n", clock_nb);
+		return reset_nb;
+	}
+
+	ret = reset_get_by_index(dev, 0, &glue->resets);
+	if (ret) {
+		dev_err(dev, "failed to get reset 0\n");
+		reset_free(&glue->resets);
+	}
 
 	ret = generic_phy_get_by_name(dev, "usb", &glue->phy);
 	if (ret) {

@@ -499,8 +525,6 @@ static const struct sunxi_musb_config sun4i_a10_cfg = {
 
 static const struct sunxi_musb_config sun8i_h3_cfg = {
 	.config = &musb_config_h3,
-	.rst_bit = 23,
-	.clkgate_bit = 23,
 };
 
 static const struct udevice_id sunxi_musb_ids[] = {

index a7d7e3f044..f206fa3f5d 100644
@@ -11,10 +11,12 @@
  */
 
 #include <common.h>
+#include <clk.h>
 #include <dm.h>
 #include <dm/device.h>
 #include <generic-phy.h>
 #include <phy-sun4i-usb.h>
+#include <reset.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>

@@ -80,6 +82,7 @@ struct sun4i_usb_phy_cfg {
 	enum sun4i_usb_phy_type type;
 	u32 disc_thresh;
 	u8 phyctl_offset;
+	bool dedicated_clocks;
 	bool enable_pmu_unk1;
 	bool phy0_dual_route;
 };

@@ -88,30 +91,21 @@ struct sun4i_usb_phy_info {
 	const char *gpio_vbus;
 	const char *gpio_vbus_det;
 	const char *gpio_id_det;
-	int rst_mask;
 } phy_info[] = {
 	{
 		.gpio_vbus = CONFIG_USB0_VBUS_PIN,
 		.gpio_vbus_det = CONFIG_USB0_VBUS_DET,
 		.gpio_id_det = CONFIG_USB0_ID_DET,
-		.rst_mask = (CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK),
 	},
 	{
 		.gpio_vbus = CONFIG_USB1_VBUS_PIN,
 		.gpio_vbus_det = NULL,
 		.gpio_id_det = NULL,
-		.rst_mask = (CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK),
 	},
 	{
 		.gpio_vbus = CONFIG_USB2_VBUS_PIN,
 		.gpio_vbus_det = NULL,
 		.gpio_id_det = NULL,
-#ifdef CONFIG_MACH_SUN8I_A83T
-		.rst_mask = (CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK |
-			     CCM_USB_CTRL_12M_CLK),
-#else
-		.rst_mask = (CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK),
-#endif
 	},
 	{
 		.gpio_vbus = CONFIG_USB3_VBUS_PIN,

@@ -126,13 +120,13 @@ struct sun4i_usb_phy_plat {
 	int gpio_vbus;
 	int gpio_vbus_det;
 	int gpio_id_det;
-	int rst_mask;
+	struct clk clocks;
+	struct reset_ctl resets;
 	int id;
 };
 
 struct sun4i_usb_phy_data {
 	void __iomem *base;
-	struct sunxi_ccm_reg *ccm;
 	const struct sun4i_usb_phy_cfg *cfg;
 	struct sun4i_usb_phy_plat *usb_phy;
 };

@@ -266,8 +260,19 @@ static int sun4i_usb_phy_init(struct phy *phy)
 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 	u32 val;
+	int ret;
 
-	setbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask);
+	ret = clk_enable(&usb_phy->clocks);
+	if (ret) {
+		dev_err(dev, "failed to enable usb_%ldphy clock\n", phy->id);
+		return ret;
+	}
+
+	ret = reset_deassert(&usb_phy->resets);
+	if (ret) {
+		dev_err(dev, "failed to deassert usb_%ldreset reset\n", phy->id);
+		return ret;
+	}
 
 	if (data->cfg->type == sun8i_a83t_phy) {
 		if (phy->id == 0) {

@@ -308,6 +313,7 @@ static int sun4i_usb_phy_exit(struct phy *phy)
 {
 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
+	int ret;
 
 	if (phy->id == 0) {
 		if (data->cfg->type == sun8i_a83t_phy) {

@@ -320,7 +326,17 @@ static int sun4i_usb_phy_exit(struct phy *phy)
 
 	sun4i_usb_phy_passby(phy, false);
 
-	clrbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask);
+	ret = clk_disable(&usb_phy->clocks);
+	if (ret) {
+		dev_err(dev, "failed to disable usb_%ldphy clock\n", phy->id);
+		return ret;
+	}
+
+	ret = reset_assert(&usb_phy->resets);
+	if (ret) {
+		dev_err(dev, "failed to assert usb_%ldreset reset\n", phy->id);
+		return ret;
+	}
 
 	return 0;
 }

@@ -407,10 +423,6 @@ static int sun4i_usb_phy_probe(struct udevice *dev)
 	if (IS_ERR(data->base))
 		return PTR_ERR(data->base);
 
-	data->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-	if (IS_ERR(data->ccm))
-		return PTR_ERR(data->ccm);
-
 	data->usb_phy = plat;
 	for (i = 0; i < data->cfg->num_phys; i++) {
 		struct sun4i_usb_phy_plat *phy = &plat[i];

@@ -448,6 +460,24 @@ static int sun4i_usb_phy_probe(struct udevice *dev)
 			sunxi_gpio_set_pull(phy->gpio_id_det, SUNXI_GPIO_PULL_UP);
 		}
 
+		if (data->cfg->dedicated_clocks)
+			snprintf(name, sizeof(name), "usb%d_phy", i);
+		else
+			strlcpy(name, "usb_phy", sizeof(name));
+
+		ret = clk_get_by_name(dev, name, &phy->clocks);
+		if (ret) {
+			dev_err(dev, "failed to get usb%d_phy clock phandle\n", i);
+			return ret;
+		}
+
+		snprintf(name, sizeof(name), "usb%d_reset", i);
+		ret = reset_get_by_name(dev, name, &phy->resets);
+		if (ret) {
+			dev_err(dev, "failed to get usb%d_reset reset phandle\n", i);
+			return ret;
+		}
+
 		if (i || data->cfg->phy0_dual_route) {
 			snprintf(name, sizeof(name), "pmu%d", i);
 			phy->pmu = (void __iomem *)devfdt_get_addr_name(dev, name);

@@ -456,9 +486,6 @@ static int sun4i_usb_phy_probe(struct udevice *dev)
 		}
 
 		phy->id = i;
-		phy->rst_mask = info->rst_mask;
-		if ((data->cfg->type == sun8i_h3_phy) && (phy->id == 3))
-			phy->rst_mask = (BIT(3) | BIT(11));
 	};
 
 	debug("Allwinner Sun4I USB PHY driver loaded\n");

@@ -470,6 +497,7 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
 	.type = sun4i_a10_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A10,
+	.dedicated_clocks = false,
 	.enable_pmu_unk1 = false,
 };
 

@@ -478,6 +506,7 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
 	.type = sun4i_a10_phy,
 	.disc_thresh = 2,
 	.phyctl_offset = REG_PHYCTL_A10,
+	.dedicated_clocks = false,
 	.enable_pmu_unk1 = false,
 };
 

@@ -486,6 +515,7 @@ static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
 	.type = sun6i_a31_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A10,
+	.dedicated_clocks = true,
 	.enable_pmu_unk1 = false,
 };
 

@@ -494,6 +524,7 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
 	.type = sun4i_a10_phy,
 	.disc_thresh = 2,
 	.phyctl_offset = REG_PHYCTL_A10,
+	.dedicated_clocks = false,
 	.enable_pmu_unk1 = false,
 };
 

@@ -502,6 +533,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
 	.type = sun4i_a10_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A10,
+	.dedicated_clocks = true,
 	.enable_pmu_unk1 = false,
 };
 

@@ -510,6 +542,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
 	.type = sun8i_a33_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
 	.enable_pmu_unk1 = false,
 };
 

@@ -517,6 +550,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
 	.num_phys = 3,
 	.type = sun8i_a83t_phy,
 	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
 };
 
 static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {

@@ -524,6 +558,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
 	.type = sun8i_h3_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
 	.enable_pmu_unk1 = true,
 	.phy0_dual_route = true,
 };

@@ -533,6 +568,7 @@ static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
 	.type = sun8i_v3s_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
 	.enable_pmu_unk1 = true,
 	.phy0_dual_route = true,
 };

@@ -542,6 +578,7 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 	.type = sun50i_a64_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
 	.enable_pmu_unk1 = true,
 	.phy0_dual_route = true,
 };

index af079a71ee..6033760583 100644
@@ -11,10 +11,6 @@
  * A10 specific configuration
  */
 
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_SUNXI
-#endif
-
 /*
  * Include common sunxi configuration where most the settings are
  */

index 2d73c75b8c..e050a5299f 100644
@@ -10,11 +10,6 @@
  * A64 specific configuration
  */
 
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_SUNXI
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#endif
-
 #ifndef CONFIG_MACH_SUN50I_H6
 #define GICD_BASE		0x1c81000
 #define GICC_BASE		0x1c82000

index c3692caa73..ee42af80d4 100644
@@ -11,10 +11,6 @@
  * High Level Configuration Options
  */
 
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_SUNXI
-#endif
-
 /*
  * Include common sunxi configuration where most the settings are
  */

index 1523684fad..1e490daac1 100644
@@ -14,10 +14,6 @@
  * A31 specific configuration
  */
 
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_SUNXI
-#endif
-
 #define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
 #define CONFIG_ARMV7_SECURE_MAX_SIZE    (64 * 1024) /* 64 KB */
 

index bb8f217b25..d2fd586672 100644
@@ -12,10 +12,6 @@
  * A20 specific configuration
  */
 
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_SUNXI
-#endif
-
 #define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
 #define CONFIG_ARMV7_SECURE_MAX_SIZE	(64 * 1024) /* 64 KB */
 

index 7dc8693b76..9b4675e4c3 100644
@@ -12,10 +12,6 @@
  * A23 specific configuration
  */
 
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_SUNXI
-#endif
-
 /*
  * Include common sunxi configuration where most the settings are
  */

index 93690481a1..f1578d3754 100644
@@ -302,7 +302,6 @@ extern int soft_i2c_gpio_scl;
 
 #ifdef CONFIG_USB_EHCI_HCD
 #define CONFIG_USB_OHCI_NEW
-#define CONFIG_USB_OHCI_SUNXI
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
 #endif
 

204 lines not on this page · raw message

233 lines not on this page · raw message

index 7492e1367a..fb11231dd1 100644
@@ -18,6 +18,10 @@ static struct ccu_clk_map a10_clks[] = {
 	[CLK_AHB_OHCI0]		= { 0x060, BIT(2), NULL },
 	[CLK_AHB_EHCI1]		= { 0x060, BIT(3), NULL },
 	[CLK_AHB_OHCI1]		= { 0x060, BIT(4), NULL },
+	[CLK_AHB_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_AHB_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_AHB_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_AHB_MMC3]		= { 0x060, BIT(11), NULL },
 
 	[CLK_USB_OHCI0]		= { 0x0cc, BIT(6), NULL },
 	[CLK_USB_OHCI1]		= { 0x0cc, BIT(7), NULL },

index 45ef10d7a5..ba5e2e323d 100644
@@ -16,6 +16,9 @@ static struct ccu_clk_map a10s_clks[] = {
 	[CLK_AHB_OTG]		= { 0x060, BIT(0), NULL },
 	[CLK_AHB_EHCI]		= { 0x060, BIT(1), NULL },
 	[CLK_AHB_OHCI]		= { 0x060, BIT(2), NULL },
+	[CLK_AHB_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_AHB_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_AHB_MMC2]		= { 0x060, BIT(10), NULL },
 
 	[CLK_USB_OHCI]		= { 0x0cc, BIT(6), NULL },
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },

index 424e065a66..43e6dd63bf 100644
@@ -13,6 +13,9 @@
 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
 
 static struct ccu_clk_map a23_clks[] = {
+	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(24), NULL },
 	[CLK_BUS_EHCI]		= { 0x060, BIT(26), NULL },
 	[CLK_BUS_OHCI]		= { 0x060, BIT(29), NULL },

index c6d82be120..f314feff69 100644
@@ -13,6 +13,10 @@
 #include <dt-bindings/reset/sun6i-a31-ccu.h>
 
 static struct ccu_clk_map a31_clks[] = {
+	[CLK_AHB1_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_AHB1_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_AHB1_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_AHB1_MMC3]		= { 0x060, BIT(12), NULL },
 	[CLK_AHB1_OTG]		= { 0x060, BIT(24), NULL },
 	[CLK_AHB1_EHCI0]	= { 0x060, BIT(26), NULL },
 	[CLK_AHB1_EHCI1]	= { 0x060, BIT(27), NULL },

index 890bf8ca21..0574b88f9b 100644
@@ -13,6 +13,9 @@
 #include <dt-bindings/reset/sun50i-a64-ccu.h>
 
 static struct ccu_clk_map a64_clks[] = {
+	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(23), NULL },
 	[CLK_BUS_EHCI0]		= { 0x060, BIT(24), NULL },
 	[CLK_BUS_EHCI1]		= { 0x060, BIT(25), NULL },

index 58d28eb6ad..cc18975a06 100644
@@ -13,6 +13,9 @@
 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
 
 static struct ccu_clk_map a83t_clks[] = {
+	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(24), NULL },
 	[CLK_BUS_EHCI0]		= { 0x060, BIT(26), NULL },
 	[CLK_BUS_EHCI1]		= { 0x060, BIT(27), NULL },

index 96bf2f4fa9..505616a889 100644
@@ -13,6 +13,9 @@
 #include <dt-bindings/reset/sun8i-h3-ccu.h>
 
 static struct ccu_clk_map h3_clks[] = {
+	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(23), NULL },
 	[CLK_BUS_EHCI0]		= { 0x060, BIT(24), NULL },
 	[CLK_BUS_EHCI1]		= { 0x060, BIT(25), NULL },

index 746d6734b2..006aa138b6 100644
@@ -13,6 +13,10 @@
 #include <dt-bindings/reset/sun8i-r40-ccu.h>
 
 static struct ccu_clk_map r40_clks[] = {
+	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_BUS_MMC3]		= { 0x060, BIT(11), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(25), NULL },
 	[CLK_BUS_EHCI0]		= { 0x060, BIT(26), NULL },
 	[CLK_BUS_EHCI1]		= { 0x060, BIT(27), NULL },

index 3bd793eb40..125b847bac 100644
@@ -13,6 +13,9 @@
 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
 
 static struct ccu_clk_map v3s_clks[] = {
+	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(24), NULL },
 
 	[CLK_USB_PHY0]          = { 0x0cc, BIT(8), NULL },

index bacd052ef3..4e30ab330c 100644
@@ -60,6 +60,16 @@ struct sunxi_clk_priv {
 
 extern struct clk_ops sunxi_clk_ops;
 
+/**
+ * mmc_clk_set_rate - mmc clock set rate
+ *
+ * @base:	clock register base address
+ * @bit:	clock bit value
+ * @rate:	clock input rate in Hz
+ * @return 0, or -ve error code.
+ */
+int mmc_clk_set_rate(void *base, u32 bit, ulong rate);
+
 /**
  * sunxi_reset_bind() - reset binding
  *

index fb11231dd1..55176bc174 100644
@@ -23,6 +23,11 @@ static struct ccu_clk_map a10_clks[] = {
 	[CLK_AHB_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_AHB_MMC3]		= { 0x060, BIT(11), NULL },
 
+	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC3]		= { 0x094, BIT(31), &mmc_clk_set_rate },
+
 	[CLK_USB_OHCI0]		= { 0x0cc, BIT(6), NULL },
 	[CLK_USB_OHCI1]		= { 0x0cc, BIT(7), NULL },
 	[CLK_USB_PHY]		= { 0x0cc, BIT(8), NULL },

index ba5e2e323d..89c4897000 100644
@@ -20,6 +20,12 @@ static struct ccu_clk_map a10s_clks[] = {
 	[CLK_AHB_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_AHB_MMC2]		= { 0x060, BIT(10), NULL },
 
+#ifdef CONFIG_MMC
+	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
+#endif
+
 	[CLK_USB_OHCI]		= { 0x0cc, BIT(6), NULL },
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
 	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },

index 43e6dd63bf..911d6987c8 100644
@@ -20,6 +20,12 @@ static struct ccu_clk_map a23_clks[] = {
 	[CLK_BUS_EHCI]		= { 0x060, BIT(26), NULL },
 	[CLK_BUS_OHCI]		= { 0x060, BIT(29), NULL },
 
+#ifdef CONFIG_MMC
+	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
+#endif
+
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
 	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },
 	[CLK_USB_HSIC]		= { 0x0cc, BIT(10), NULL },

index f314feff69..3c807bde77 100644
@@ -24,6 +24,11 @@ static struct ccu_clk_map a31_clks[] = {
 	[CLK_AHB1_OHCI1]	= { 0x060, BIT(30), NULL },
 	[CLK_AHB1_OHCI2]	= { 0x060, BIT(31), NULL },
 
+	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC3]		= { 0x094, BIT(31), &mmc_clk_set_rate },
+
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
 	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },
 	[CLK_USB_PHY2]		= { 0x0cc, BIT(10), NULL },

index 0574b88f9b..a3392d7e8f 100644
@@ -22,6 +22,10 @@ static struct ccu_clk_map a64_clks[] = {
 	[CLK_BUS_OHCI0]		= { 0x060, BIT(28), NULL },
 	[CLK_BUS_OHCI1]		= { 0x060, BIT(29), NULL },
 
+	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
+
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
 	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },
 	[CLK_USB_HSIC]		= { 0x0cc, BIT(10), NULL },

index cc18975a06..a2e0ac7a26 100644
@@ -21,6 +21,10 @@ static struct ccu_clk_map a83t_clks[] = {
 	[CLK_BUS_EHCI1]		= { 0x060, BIT(27), NULL },
 	[CLK_BUS_OHCI0]		= { 0x060, BIT(29), NULL },
 
+	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
+
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
 	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },
 	[CLK_USB_HSIC]		= { 0x0cc, BIT(10), NULL },

index 505616a889..316c20889d 100644
@@ -26,6 +26,10 @@ static struct ccu_clk_map h3_clks[] = {
 	[CLK_BUS_OHCI2]		= { 0x060, BIT(30), NULL },
 	[CLK_BUS_OHCI3]		= { 0x060, BIT(31), NULL },
 
+	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
+
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
 	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },
 	[CLK_USB_PHY2]		= { 0x0cc, BIT(10), NULL },

index 006aa138b6..9273f3b7ea 100644
@@ -25,6 +25,10 @@ static struct ccu_clk_map r40_clks[] = {
 	[CLK_BUS_OHCI1]		= { 0x060, BIT(30), NULL },
 	[CLK_BUS_OHCI2]		= { 0x060, BIT(31), NULL },
 
+	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC3]		= { 0x094, BIT(31), &mmc_clk_set_rate },
 
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
 	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },

index 791b1ac7f2..ca147ec9cc 100644
@@ -12,6 +12,24 @@
 #include <asm/arch/ccu.h>
 #include <linux/log2.h>
 
+static ulong sunxi_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct sunxi_clk_priv *priv = dev_get_priv(clk->dev);
+	struct ccu_clk_map *map = &priv->desc->clks[clk->id];
+	u32 *base;
+
+	if (!map->ccu_clk_set_rate) {
+		debug("%s (CLK#%ld) unhandled\n", __func__, clk->id);
+		return 0;
+	}
+
+	debug("%s(#%ld) off#0x%x, BIT(%d)\n", __func__,
+	      clk->id, map->off, ilog2(map->bit));
+
+	base = priv->base + map->off;
+	return map->ccu_clk_set_rate(base, map->bit, rate);
+}
+
 static int sunxi_clk_enable(struct clk *clk)
 {
 	struct sunxi_clk_priv *priv = dev_get_priv(clk->dev);

@@ -55,4 +73,5 @@ static int sunxi_clk_disable(struct clk *clk)
 struct clk_ops sunxi_clk_ops = {
 	.enable = sunxi_clk_enable,
 	.disable = sunxi_clk_disable,
+	.set_rate = sunxi_clk_set_rate,
 };

index 125b847bac..4af6b9abfb 100644
@@ -18,6 +18,10 @@ static struct ccu_clk_map v3s_clks[] = {
 	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(24), NULL },
 
+	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
+
 	[CLK_USB_PHY0]          = { 0x0cc, BIT(8), NULL },
 };
 

139 lines not on this page · raw message

index 911d6987c8..06a2e6bc79 100644
@@ -38,6 +38,9 @@ static struct ccu_reset_map a23_resets[] = {
 	[RST_USB_PHY1]		=  { 0x0cc, BIT(1) },
 	[RST_USB_HSIC]		=  { 0x0cc, BIT(2) },
 
+	[RST_BUS_MMC0]		=  { 0x2c0, BIT(8) },
+	[RST_BUS_MMC1]		=  { 0x2c0, BIT(9) },
+	[RST_BUS_MMC2]		=  { 0x2c0, BIT(10) },
 	[RST_BUS_OTG]		=  { 0x2c0, BIT(24) },
 	[RST_BUS_EHCI]		=  { 0x2c0, BIT(26) },
 	[RST_BUS_OHCI]		=  { 0x2c0, BIT(29) },

index 3c807bde77..15076d0e72 100644
@@ -42,6 +42,10 @@ static struct ccu_reset_map a31_resets[] = {
 	[RST_USB_PHY1]		= { 0x0cc, BIT(1) },
 	[RST_USB_PHY2]		= { 0x0cc, BIT(2) },
 
+	[RST_AHB1_MMC0]		= { 0x2c0, BIT(8) },
+	[RST_AHB1_MMC1]		= { 0x2c0, BIT(9) },
+	[RST_AHB1_MMC2]		= { 0x2c0, BIT(10) },
+	[RST_AHB1_MMC3]		= { 0x2c0, BIT(11) },
 	[RST_AHB1_OTG]		= { 0x2c0, BIT(24) },
 	[RST_AHB1_EHCI0]	= { 0x2c0, BIT(26) },
 	[RST_AHB1_EHCI1]	= { 0x2c0, BIT(27) },

index a3392d7e8f..5b652d5d7d 100644
@@ -39,6 +39,9 @@ static struct ccu_reset_map a64_resets[] = {
 	[RST_USB_PHY1]		=  { 0x0cc, BIT(1) },
 	[RST_USB_HSIC]		=  { 0x0cc, BIT(2) },
 
+	[RST_BUS_MMC0]		=  { 0x2c0, BIT(8) },
+	[RST_BUS_MMC1]		=  { 0x2c0, BIT(9) },
+	[RST_BUS_MMC2]		=  { 0x2c0, BIT(10) },
 	[RST_BUS_OTG]		=  { 0x2c0, BIT(23) },
 	[RST_BUS_EHCI0]		=  { 0x2c0, BIT(24) },
 	[RST_BUS_EHCI1]		=  { 0x2c0, BIT(25) },

index a2e0ac7a26..47b7672e7f 100644
@@ -37,6 +37,9 @@ static struct ccu_reset_map a83t_resets[] = {
 	[RST_USB_PHY1]		= { 0x0cc, BIT(1) },
 	[RST_USB_HSIC]		= { 0x0cc, BIT(2) },
 
+	[RST_BUS_MMC0]		= { 0x2c0, BIT(8) },
+	[RST_BUS_MMC1]		= { 0x2c0, BIT(9) },
+	[RST_BUS_MMC2]		= { 0x2c0, BIT(10) },
 	[RST_BUS_OTG]		= { 0x2c0, BIT(24) },
 	[RST_BUS_EHCI0]		= { 0x2c0, BIT(26) },
 	[RST_BUS_EHCI1]		= { 0x2c0, BIT(27) },

index 316c20889d..a47a9d04d5 100644
@@ -46,6 +46,9 @@ static struct ccu_reset_map h3_resets[] = {
 	[RST_USB_PHY2]		=  { 0x0cc, BIT(2) },
 	[RST_USB_PHY3]		=  { 0x0cc, BIT(3) },
 
+	[RST_BUS_MMC0]		=  { 0x2c0, BIT(8) },
+	[RST_BUS_MMC1]		=  { 0x2c0, BIT(9) },
+	[RST_BUS_MMC2]		=  { 0x2c0, BIT(10) },
 	[RST_BUS_OTG]		=  { 0x2c0, BIT(23) },
 	[RST_BUS_EHCI0]		=  { 0x2c0, BIT(24) },
 	[RST_BUS_EHCI1]		=  { 0x2c0, BIT(25) },

index 9273f3b7ea..24c26ad3be 100644
@@ -43,6 +43,10 @@ static struct ccu_reset_map r40_resets[] = {
 	[RST_USB_PHY1]		= { 0x0cc, BIT(1) },
 	[RST_USB_PHY2]		= { 0x0cc, BIT(2) },
 
+	[RST_BUS_MMC0]		= { 0x2c0, BIT(8) },
+	[RST_BUS_MMC1]		= { 0x2c0, BIT(9) },
+	[RST_BUS_MMC2]		= { 0x2c0, BIT(10) },
+	[RST_BUS_MMC3]		= { 0x2c0, BIT(11) },
 	[RST_BUS_OTG]		= { 0x2c0, BIT(25) },
 	[RST_BUS_EHCI0]		= { 0x2c0, BIT(26) },
 	[RST_BUS_EHCI1]		= { 0x2c0, BIT(27) },

index 4af6b9abfb..c49990245c 100644
@@ -28,6 +28,9 @@ static struct ccu_clk_map v3s_clks[] = {
 static struct ccu_reset_map v3s_resets[] = {
 	[RST_USB_PHY0]		=  { 0x0cc, BIT(0) },
 
+	[RST_BUS_MMC0]		=  { 0x2c0, BIT(8) },
+	[RST_BUS_MMC1]		=  { 0x2c0, BIT(9) },
+	[RST_BUS_MMC2]		=  { 0x2c0, BIT(10) },
 	[RST_BUS_OTG]		=  { 0x2c0, BIT(24) },
 };
 

index 99881b8b99..3bc280be5e 100644
@@ -138,6 +138,23 @@ int reset_get_by_name(struct udevice *dev, const char *name,
 	return reset_get_by_index(dev, index, reset_ctl);
 }
 
+int reset_get_by_name_optional(struct udevice *dev, const char *name,
+			       struct reset_ctl *reset_ctl, bool optional)
+{
+	int index;
+
+	debug("%s(dev=%p, name=%s, reset_ctl=%p)\n", __func__, dev, name,
+	      reset_ctl);
+	reset_ctl->dev = NULL;
+
+	index = dev_read_stringlist_search(dev, "reset-names", name);
+	if (index < 0) {
+		printf("reset_get_by_name_optional: optional = %d, index = %d\n", optional, index);
+		return optional ? 0 : index;
+	}
+
+	return reset_get_by_index(dev, index, reset_ctl);
+}
 int reset_request(struct reset_ctl *reset_ctl)
 {
 	struct reset_ops *ops = reset_dev_ops(reset_ctl->dev);

index a7bbc1c331..a5af31f549 100644
@@ -132,6 +132,23 @@ int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk);
 int reset_get_by_name(struct udevice *dev, const char *name,
 		      struct reset_ctl *reset_ctl);
 
+/**
+ * reset_get_by_name_optional - Get/request a reset signal by name optionally.
+ *
+ * This look up and requests a reset signal similar to reset_get_by_name()
+ * but with optional flag.
+ *
+ * @dev:	The client device.
+ * @name:	The name of the reset signal to request, within the client's
+ *		list of reset signals.
+ * @reset_ctl:	A pointer to a reset control struct to initialize.
+ * @optional:	Optional flag, true if reset is optional, false if reset is
+ *		necessary which is same as reset_get_by_name()
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_get_by_name_optional(struct udevice *dev, const char *name,
+			       struct reset_ctl *reset_ctl, bool optional);
+
 /**
  * reset_request - Request a reset signal.
  *

@@ -254,6 +271,14 @@ static inline int reset_get_by_name(struct udevice *dev, const char *name,
 	return -ENOTSUPP;
 }
 
+static inline int reset_get_by_name_optional(struct udevice *dev,
+					     const char *name,
+					     struct reset_ctl *reset_ctl,
+					     bool optional)
+{
+	return -ENOTSUPP;
+}
+
 static inline int reset_free(struct reset_ctl *reset_ctl)
 {
 	return 0;

index a5af31f549..70130bb886 100644
@@ -315,4 +315,15 @@ static inline int reset_release_bulk(struct reset_ctl_bulk *bulk)
 }
 #endif
 
+/**
+ * reset_valid() - check if reset is valid
+ *
+ * @reset_ctl:		the reset to check
+ * @return TRUE if valid, or FALSE
+ */
+static inline bool reset_valid(struct reset_ctl *reset_ctl)
+{
+	return !!reset_ctl->dev;
+}
+
 #endif

index bf82014a64..3011ec9498 100644
@@ -8,10 +8,12 @@
  */
 
 #include <common.h>
+#include <clk.h>
 #include <dm.h>
 #include <errno.h>
 #include <malloc.h>
 #include <mmc.h>
+#include <reset.h>
 #include <asm/io.h>
 #include <asm/arch/ccu.h>
 #include <asm/arch/clock.h>

@@ -26,8 +28,12 @@ struct sunxi_mmc_plat {
 };
 
 struct sunxi_mmc_priv {
+#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(CLK)
+	struct clk mmc_clk;
+#else
 	unsigned mmc_no;
 	uint32_t *mclkreg;
+#endif
 	unsigned fatal_err;
 	struct gpio_desc cd_gpio;	/* Change Detect GPIO */
 	int cd_inverted;		/* Inverted Card Detect */

@@ -188,6 +194,15 @@ int mmc_clk_set_rate(void *base, u32 bit, ulong rate)
 static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
 {
 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(CLK)
+	int ret;
+
+	ret = clk_set_rate(&priv->mmc_clk, hz);
+	if (ret) {
+		dev_err(dev, "failed to set rate for mmc_clk\n");
+		return ret;
+	}
+
+	return ret;
 #else
 	if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))
 		new_mode = true;

@@ -379,7 +394,7 @@ static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv,
 		writel(data->blocks * data->blocksize, &priv->reg->bytecnt);
 	}
 
-	debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv->mmc_no,
+	debug("mmc cmd %d(0x%08x), arg 0x%08x\n",
 	      cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
 	writel(cmd->cmdarg, &priv->reg->arg);
 

@@ -591,8 +606,8 @@ static int sunxi_mmc_probe(struct udevice *dev)
 	struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
 	struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 	struct mmc_config *cfg = &plat->cfg;
-	struct ofnode_phandle_args args;
-	u32 *gate_reg;
+	struct clk ahb_clk;
+	struct reset_ctl reset;
 	int bus_width, ret;
 
 	cfg->name = dev->name;

@@ -615,20 +630,37 @@ static int sunxi_mmc_probe(struct udevice *dev)
 
 	priv->reg = (void *)dev_read_addr(dev);
 
-	/* We don't have a sunxi clock driver so find the clock address here */
-	ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
-					  1, &args);
-	if (ret)
+	ret = clk_get_by_name(dev, "ahb", &ahb_clk);
+	if (ret) {
+		dev_err(dev, "falied to get ahb clock\n");
 		return ret;
-	priv->mclkreg = (u32 *)ofnode_get_addr(args.node);
+	}
 
-	ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
-					  0, &args);
-	if (ret)
+	ret = clk_get_by_name(dev, "mmc", &priv->mmc_clk);
+	if (ret) {
+		dev_err(dev, "falied to get mmc clock\n");
 		return ret;
-	gate_reg = (u32 *)ofnode_get_addr(args.node);
-	setbits_le32(gate_reg, 1 << args.args[0]);
-	priv->mmc_no = args.args[0] - 8;
+	}
+
+	ret = reset_get_by_name_optional(dev, "ahb", &reset, true);
+	if (ret) {
+		dev_err(dev, "falied to get ahb reset\n");
+		return ret;
+	}
+
+	ret = clk_enable(&ahb_clk);
+	if (ret) {
+		dev_err(dev, "failed to enable ahb clock\n");
+		return ret;
+	}
+
+	if (reset_valid(&reset)) {
+		ret = reset_deassert(&reset);
+		if (ret) {
+			dev_err(dev, "failed to deassert ahb reset\n");
+			return ret;
+		}
+	}
 
 	ret = mmc_set_mod_clk(priv, 24000000);
 	if (ret)

index 857d5ff010..89012daad1 100644
@@ -775,7 +775,7 @@ int misc_init_r(void)
 	} else if (boot == BOOT_DEVICE_MMC1) {
 		env_set("mmc_bootdev", "0");
 	} else if (boot == BOOT_DEVICE_MMC2) {
-		env_set("mmc_bootdev", "1");
+		env_set("mmc_bootdev", "2");
 	}
 
 	setup_environment(gd->fdt_blob);

index f1578d3754..9016c048ab 100644
@@ -377,8 +377,10 @@ extern int soft_i2c_gpio_scl;
 #define BOOTENV_DEV_MMC_AUTO(devtypeu, devtypel, instance)		\
 	BOOTENV_DEV_MMC(MMC, mmc, 0)					\
 	BOOTENV_DEV_MMC(MMC, mmc, 1)					\
+	BOOTENV_DEV_MMC(MMC, mmc, 2)					\
 	"bootcmd_mmc_auto="						\
-		"if test ${mmc_bootdev} -eq 1; then "			\
+		"if test ${mmc_bootdev} -eq 2; then "			\
+			"run bootcmd_mmc2; "				\
 			"run bootcmd_mmc1; "				\
 			"run bootcmd_mmc0; "				\
 		"elif test ${mmc_bootdev} -eq 0; then "			\

index 3011ec9498..5191a3e3dd 100644
@@ -697,6 +697,8 @@ static const struct udevice_id sunxi_mmc_ids[] = {
 	{ .compatible = "allwinner,sun4i-a10-mmc" },
 	{ .compatible = "allwinner,sun5i-a13-mmc" },
 	{ .compatible = "allwinner,sun7i-a20-mmc" },
+	{ .compatible = "allwinner,sun50i-a64-mmc" },
+	{ .compatible = "allwinner,sun50i-a64-emmc" },
 	{ }
 };
 

index 5191a3e3dd..229a7b2811 100644
@@ -697,6 +697,7 @@ static const struct udevice_id sunxi_mmc_ids[] = {
 	{ .compatible = "allwinner,sun4i-a10-mmc" },
 	{ .compatible = "allwinner,sun5i-a13-mmc" },
 	{ .compatible = "allwinner,sun7i-a20-mmc" },
+	{ .compatible = "allwinner,sun8i-a83t-emmc" },
 	{ .compatible = "allwinner,sun50i-a64-mmc" },
 	{ .compatible = "allwinner,sun50i-a64-emmc" },
 	{ }

index 55176bc174..ee499c402a 100644
@@ -22,12 +22,21 @@ static struct ccu_clk_map a10_clks[] = {
 	[CLK_AHB_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_AHB_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_AHB_MMC3]		= { 0x060, BIT(11), NULL },
+	[CLK_AHB_SPI0]		= { 0x060, BIT(20), NULL },
+	[CLK_AHB_SPI1]		= { 0x060, BIT(21), NULL },
+	[CLK_AHB_SPI2]		= { 0x060, BIT(22), NULL },
+	[CLK_AHB_SPI3]		= { 0x060, BIT(23), NULL },
 
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC3]		= { 0x094, BIT(31), &mmc_clk_set_rate },
 
+	[CLK_SPI0]		= { 0x0a0, BIT(31), NULL },
+	[CLK_SPI1]		= { 0x0a4, BIT(31), NULL },
+	[CLK_SPI2]		= { 0x0a8, BIT(31), NULL },
+	[CLK_SPI3]		= { 0x0d4, BIT(31), NULL },
+
 	[CLK_USB_OHCI0]		= { 0x0cc, BIT(6), NULL },
 	[CLK_USB_OHCI1]		= { 0x0cc, BIT(7), NULL },
 	[CLK_USB_PHY]		= { 0x0cc, BIT(8), NULL },

index 89c4897000..0c71e5b698 100644
@@ -19,6 +19,9 @@ static struct ccu_clk_map a10s_clks[] = {
 	[CLK_AHB_MMC0]		= { 0x060, BIT(8), NULL },
 	[CLK_AHB_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_AHB_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_AHB_SPI0]		= { 0x060, BIT(20), NULL },
+	[CLK_AHB_SPI1]		= { 0x060, BIT(21), NULL },
+	[CLK_AHB_SPI2]		= { 0x060, BIT(22), NULL },
 
 #ifdef CONFIG_MMC
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },

@@ -26,6 +29,10 @@ static struct ccu_clk_map a10s_clks[] = {
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
 #endif
 
+	[CLK_SPI0]		= { 0x0a0, BIT(31), NULL },
+	[CLK_SPI1]		= { 0x0a4, BIT(31), NULL },
+	[CLK_SPI2]		= { 0x0a8, BIT(31), NULL },
+
 	[CLK_USB_OHCI]		= { 0x0cc, BIT(6), NULL },
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
 	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },

index 15076d0e72..1fa77e1272 100644
@@ -17,6 +17,10 @@ static struct ccu_clk_map a31_clks[] = {
 	[CLK_AHB1_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_AHB1_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_AHB1_MMC3]		= { 0x060, BIT(12), NULL },
+	[CLK_AHB1_SPI0]		= { 0x060, BIT(20), NULL },
+	[CLK_AHB1_SPI1]		= { 0x060, BIT(21), NULL },
+	[CLK_AHB1_SPI2]		= { 0x060, BIT(22), NULL },
+	[CLK_AHB1_SPI3]		= { 0x060, BIT(23), NULL },
 	[CLK_AHB1_OTG]		= { 0x060, BIT(24), NULL },
 	[CLK_AHB1_EHCI0]	= { 0x060, BIT(26), NULL },
 	[CLK_AHB1_EHCI1]	= { 0x060, BIT(27), NULL },

@@ -29,6 +33,11 @@ static struct ccu_clk_map a31_clks[] = {
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC3]		= { 0x094, BIT(31), &mmc_clk_set_rate },
 
+	[CLK_SPI0]		= { 0x0a0, BIT(31), NULL },
+	[CLK_SPI1]		= { 0x0a4, BIT(31), NULL },
+	[CLK_SPI2]		= { 0x0a8, BIT(31), NULL },
+	[CLK_SPI3]		= { 0x0ac, BIT(31), NULL },
+
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
 	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },
 	[CLK_USB_PHY2]		= { 0x0cc, BIT(10), NULL },

index 5b652d5d7d..07e15fb1ac 100644
@@ -16,6 +16,8 @@ static struct ccu_clk_map a64_clks[] = {
 	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
 	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_BUS_SPI0]		= { 0x060, BIT(20), NULL },
+	[CLK_BUS_SPI1]		= { 0x060, BIT(21), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(23), NULL },
 	[CLK_BUS_EHCI0]		= { 0x060, BIT(24), NULL },
 	[CLK_BUS_EHCI1]		= { 0x060, BIT(25), NULL },

@@ -26,6 +28,9 @@ static struct ccu_clk_map a64_clks[] = {
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
 
+	[CLK_SPI0]		= { 0x0a0, BIT(31), NULL },
+	[CLK_SPI1]		= { 0x0a4, BIT(31), NULL },
+
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
 	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },
 	[CLK_USB_HSIC]		= { 0x0cc, BIT(10), NULL },

index a47a9d04d5..47647b6688 100644
@@ -16,6 +16,8 @@ static struct ccu_clk_map h3_clks[] = {
 	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
 	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_BUS_SPI0]		= { 0x060, BIT(20), NULL },
+	[CLK_BUS_SPI1]		= { 0x060, BIT(21), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(23), NULL },
 	[CLK_BUS_EHCI0]		= { 0x060, BIT(24), NULL },
 	[CLK_BUS_EHCI1]		= { 0x060, BIT(25), NULL },

@@ -30,6 +32,9 @@ static struct ccu_clk_map h3_clks[] = {
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
 
+	[CLK_SPI0]		= { 0x0a0, BIT(31), NULL },
+	[CLK_SPI1]		= { 0x0a4, BIT(31), NULL },
+
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
 	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },
 	[CLK_USB_PHY2]		= { 0x0cc, BIT(10), NULL },

index c49990245c..2595049eba 100644
@@ -16,12 +16,15 @@ static struct ccu_clk_map v3s_clks[] = {
 	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
 	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_BUS_SPI0]		= { 0x060, BIT(20), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(24), NULL },
 
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
 
+	[CLK_SPI0]		= { 0x0a0, BIT(31), NULL },
+
 	[CLK_USB_PHY0]          = { 0x0cc, BIT(8), NULL },
 };
 

index 1fa77e1272..a5c6628c63 100644
@@ -55,6 +55,10 @@ static struct ccu_reset_map a31_resets[] = {
 	[RST_AHB1_MMC1]		= { 0x2c0, BIT(9) },
 	[RST_AHB1_MMC2]		= { 0x2c0, BIT(10) },
 	[RST_AHB1_MMC3]		= { 0x2c0, BIT(11) },
+	[RST_AHB1_SPI0]		= { 0x2c0, BIT(20) },
+	[RST_AHB1_SPI1]		= { 0x2c0, BIT(21) },
+	[RST_AHB1_SPI2]		= { 0x2c0, BIT(22) },
+	[RST_AHB1_SPI3]		= { 0x2c0, BIT(23) },
 	[RST_AHB1_OTG]		= { 0x2c0, BIT(24) },
 	[RST_AHB1_EHCI0]	= { 0x2c0, BIT(26) },
 	[RST_AHB1_EHCI1]	= { 0x2c0, BIT(27) },

index 07e15fb1ac..e991c8d2d1 100644
@@ -47,6 +47,8 @@ static struct ccu_reset_map a64_resets[] = {
 	[RST_BUS_MMC0]		=  { 0x2c0, BIT(8) },
 	[RST_BUS_MMC1]		=  { 0x2c0, BIT(9) },
 	[RST_BUS_MMC2]		=  { 0x2c0, BIT(10) },
+	[RST_BUS_SPI0]		=  { 0x2c0, BIT(20) },
+	[RST_BUS_SPI1]		=  { 0x2c0, BIT(21) },
 	[RST_BUS_OTG]		=  { 0x2c0, BIT(23) },
 	[RST_BUS_EHCI0]		=  { 0x2c0, BIT(24) },
 	[RST_BUS_EHCI1]		=  { 0x2c0, BIT(25) },

index 47647b6688..1cc32a0b91 100644
@@ -54,6 +54,8 @@ static struct ccu_reset_map h3_resets[] = {
 	[RST_BUS_MMC0]		=  { 0x2c0, BIT(8) },
 	[RST_BUS_MMC1]		=  { 0x2c0, BIT(9) },
 	[RST_BUS_MMC2]		=  { 0x2c0, BIT(10) },
+	[RST_BUS_SPI0]		=  { 0x2c0, BIT(20) },
+	[RST_BUS_SPI1]		=  { 0x2c0, BIT(21) },
 	[RST_BUS_OTG]		=  { 0x2c0, BIT(23) },
 	[RST_BUS_EHCI0]		=  { 0x2c0, BIT(24) },
 	[RST_BUS_EHCI1]		=  { 0x2c0, BIT(25) },

index 2595049eba..525b6dcb39 100644
@@ -34,6 +34,7 @@ static struct ccu_reset_map v3s_resets[] = {
 	[RST_BUS_MMC0]		=  { 0x2c0, BIT(8) },
 	[RST_BUS_MMC1]		=  { 0x2c0, BIT(9) },
 	[RST_BUS_MMC2]		=  { 0x2c0, BIT(10) },
+	[RST_BUS_SPI0]		=  { 0x2c0, BIT(20) },
 	[RST_BUS_OTG]		=  { 0x2c0, BIT(24) },
 };
 

index b86b5a00ad..3be80bb39f 100644
@@ -19,6 +19,7 @@
  */
 
 #include <common.h>
+#include <clk.h>
 #include <dm.h>
 #include <spi.h>
 #include <errno.h>

@@ -238,13 +239,36 @@ static int sun4i_spi_parse_pins(struct udevice *dev)
 	return 0;
 }
 
-static inline void sun4i_spi_enable_clock(void)
+static inline int sun4i_spi_enable_clock(struct udevice *dev)
 {
-	struct sunxi_ccm_reg *const ccm =
-		(struct sunxi_ccm_reg *const)SUNXI_CCM_BASE;
+	struct clk ahb_clk, mod_clk;
+	int ret;
+
+	ret = clk_get_by_name(dev, "ahb", &ahb_clk);
+	if (ret) {
+		dev_err(dev, "falied to get ahb clock\n");
+		return ret;
+	}
+
+	ret = clk_get_by_name(dev, "mod", &mod_clk);
+	if (ret) {
+		dev_err(dev, "falied to get mod clock\n");
+		return ret;
+	}
+
+	ret = clk_enable(&ahb_clk);
+	if (ret) {
+		dev_err(dev, "failed to enable ahb clock\n");
+		return ret;
+	}
+
+	ret = clk_enable(&mod_clk);
+	if (ret) {
+		dev_err(dev, "failed to enable mod clock\n");
+		return ret;
+	}
 
-	setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_SPI0));
-	writel((1 << 31), &ccm->spi0_clk_cfg);
+	return 0;
 }
 
 static int sun4i_spi_ofdata_to_platdata(struct udevice *bus)

@@ -267,8 +291,12 @@ static int sun4i_spi_probe(struct udevice *bus)
 {
 	struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
 	struct sun4i_spi_priv *priv = dev_get_priv(bus);
+	int ret;
+
+	ret = sun4i_spi_enable_clock(bus);
+	if (ret)
+		return ret;
 
-	sun4i_spi_enable_clock();
 	sun4i_spi_parse_pins(bus);
 
 	priv->regs = (struct sun4i_spi_regs *)(uintptr_t)plat->base_addr;

475 lines not on this page · raw message

index ee499c402a..d145d37217 100644
@@ -27,6 +27,15 @@ static struct ccu_clk_map a10_clks[] = {
 	[CLK_AHB_SPI2]		= { 0x060, BIT(22), NULL },
 	[CLK_AHB_SPI3]		= { 0x060, BIT(23), NULL },
 
+	[CLK_APB1_UART0]	= { 0x06c, BIT(16), NULL },
+	[CLK_APB1_UART1]	= { 0x06c, BIT(17), NULL },
+	[CLK_APB1_UART2]	= { 0x06c, BIT(18), NULL },
+	[CLK_APB1_UART3]	= { 0x06c, BIT(19), NULL },
+	[CLK_APB1_UART4]	= { 0x06c, BIT(20), NULL },
+	[CLK_APB1_UART5]	= { 0x06c, BIT(21), NULL },
+	[CLK_APB1_UART6]	= { 0x06c, BIT(22), NULL },
+	[CLK_APB1_UART7]	= { 0x06c, BIT(23), NULL },
+
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },

index 0c71e5b698..d2e9af2555 100644
@@ -23,6 +23,11 @@ static struct ccu_clk_map a10s_clks[] = {
 	[CLK_AHB_SPI1]		= { 0x060, BIT(21), NULL },
 	[CLK_AHB_SPI2]		= { 0x060, BIT(22), NULL },
 
+	[CLK_APB1_UART0]	= { 0x06c, BIT(16), NULL },
+	[CLK_APB1_UART1]	= { 0x06c, BIT(17), NULL },
+	[CLK_APB1_UART2]	= { 0x06c, BIT(18), NULL },
+	[CLK_APB1_UART3]	= { 0x06c, BIT(19), NULL },
+
 #ifdef CONFIG_MMC
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },

index 06a2e6bc79..9dbc83c531 100644
@@ -20,6 +20,12 @@ static struct ccu_clk_map a23_clks[] = {
 	[CLK_BUS_EHCI]		= { 0x060, BIT(26), NULL },
 	[CLK_BUS_OHCI]		= { 0x060, BIT(29), NULL },
 
+	[CLK_BUS_UART0]		= { 0x06c, BIT(16), NULL },
+	[CLK_BUS_UART1]		= { 0x06c, BIT(17), NULL },
+	[CLK_BUS_UART2]		= { 0x06c, BIT(18), NULL },
+	[CLK_BUS_UART3]		= { 0x06c, BIT(19), NULL },
+	[CLK_BUS_UART4]		= { 0x06c, BIT(20), NULL },
+
 #ifdef CONFIG_MMC
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },

index a5c6628c63..40803a1d64 100644
@@ -28,6 +28,13 @@ static struct ccu_clk_map a31_clks[] = {
 	[CLK_AHB1_OHCI1]	= { 0x060, BIT(30), NULL },
 	[CLK_AHB1_OHCI2]	= { 0x060, BIT(31), NULL },
 
+	[CLK_APB2_UART0]	= { 0x06c, BIT(16), NULL },
+	[CLK_APB2_UART1]	= { 0x06c, BIT(17), NULL },
+	[CLK_APB2_UART2]	= { 0x06c, BIT(18), NULL },
+	[CLK_APB2_UART3]	= { 0x06c, BIT(19), NULL },
+	[CLK_APB2_UART4]	= { 0x06c, BIT(20), NULL },
+	[CLK_APB2_UART5]	= { 0x06c, BIT(21), NULL },
+
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },

index e991c8d2d1..ae96ce7803 100644
@@ -24,6 +24,12 @@ static struct ccu_clk_map a64_clks[] = {
 	[CLK_BUS_OHCI0]		= { 0x060, BIT(28), NULL },
 	[CLK_BUS_OHCI1]		= { 0x060, BIT(29), NULL },
 
+	[CLK_BUS_UART0]		= { 0x06c, BIT(16), NULL },
+	[CLK_BUS_UART1]		= { 0x06c, BIT(17), NULL },
+	[CLK_BUS_UART2]		= { 0x06c, BIT(18), NULL },
+	[CLK_BUS_UART3]		= { 0x06c, BIT(19), NULL },
+	[CLK_BUS_UART4]		= { 0x06c, BIT(20), NULL },
+
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },

index 47b7672e7f..5c1235fa7b 100644
@@ -21,6 +21,12 @@ static struct ccu_clk_map a83t_clks[] = {
 	[CLK_BUS_EHCI1]		= { 0x060, BIT(27), NULL },
 	[CLK_BUS_OHCI0]		= { 0x060, BIT(29), NULL },
 
+	[CLK_BUS_UART0]		= { 0x06c, BIT(16), NULL },
+	[CLK_BUS_UART1]		= { 0x06c, BIT(17), NULL },
+	[CLK_BUS_UART2]		= { 0x06c, BIT(18), NULL },
+	[CLK_BUS_UART3]		= { 0x06c, BIT(19), NULL },
+	[CLK_BUS_UART4]		= { 0x06c, BIT(20), NULL },
+
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },

index 1cc32a0b91..3be6f4cdac 100644
@@ -28,6 +28,11 @@ static struct ccu_clk_map h3_clks[] = {
 	[CLK_BUS_OHCI2]		= { 0x060, BIT(30), NULL },
 	[CLK_BUS_OHCI3]		= { 0x060, BIT(31), NULL },
 
+	[CLK_BUS_UART0]		= { 0x06c, BIT(16), NULL },
+	[CLK_BUS_UART1]		= { 0x06c, BIT(17), NULL },
+	[CLK_BUS_UART2]		= { 0x06c, BIT(18), NULL },
+	[CLK_BUS_UART3]		= { 0x06c, BIT(19), NULL },
+
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },

index 24c26ad3be..1e5b1d10f7 100644
@@ -25,6 +25,15 @@ static struct ccu_clk_map r40_clks[] = {
 	[CLK_BUS_OHCI1]		= { 0x060, BIT(30), NULL },
 	[CLK_BUS_OHCI2]		= { 0x060, BIT(31), NULL },
 
+	[CLK_BUS_UART0]		= { 0x06c, BIT(16), NULL },
+	[CLK_BUS_UART1]		= { 0x06c, BIT(17), NULL },
+	[CLK_BUS_UART2]		= { 0x06c, BIT(18), NULL },
+	[CLK_BUS_UART3]		= { 0x06c, BIT(19), NULL },
+	[CLK_BUS_UART4]		= { 0x06c, BIT(20), NULL },
+	[CLK_BUS_UART5]		= { 0x06c, BIT(21), NULL },
+	[CLK_BUS_UART6]		= { 0x06c, BIT(22), NULL },
+	[CLK_BUS_UART7]		= { 0x06c, BIT(23), NULL },
+
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },

index 525b6dcb39..e12ab2bc65 100644
@@ -19,6 +19,10 @@ static struct ccu_clk_map v3s_clks[] = {
 	[CLK_BUS_SPI0]		= { 0x060, BIT(20), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(24), NULL },
 
+	[CLK_BUS_UART0]		= { 0x06c, BIT(16), NULL },
+	[CLK_BUS_UART1]		= { 0x06c, BIT(17), NULL },
+	[CLK_BUS_UART2]		= { 0x06c, BIT(18), NULL },
+
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },

index 9dbc83c531..8ce5383bb1 100644
@@ -50,6 +50,12 @@ static struct ccu_reset_map a23_resets[] = {
 	[RST_BUS_OTG]		=  { 0x2c0, BIT(24) },
 	[RST_BUS_EHCI]		=  { 0x2c0, BIT(26) },
 	[RST_BUS_OHCI]		=  { 0x2c0, BIT(29) },
+
+	[RST_BUS_UART0]		=  { 0x2d8, BIT(16) },
+	[RST_BUS_UART1]		=  { 0x2d8, BIT(17) },
+	[RST_BUS_UART2]		=  { 0x2d8, BIT(18) },
+	[RST_BUS_UART3]		=  { 0x2d8, BIT(19) },
+	[RST_BUS_UART4]		=  { 0x2d8, BIT(20) },
 };
 
 static const struct ccu_desc sun8i_a23_ccu_desc = {

index 40803a1d64..288979a18f 100644
@@ -72,6 +72,13 @@ static struct ccu_reset_map a31_resets[] = {
 	[RST_AHB1_OHCI0]	= { 0x2c0, BIT(29) },
 	[RST_AHB1_OHCI1]	= { 0x2c0, BIT(30) },
 	[RST_AHB1_OHCI2]	= { 0x2c0, BIT(31) },
+
+	[RST_APB2_UART0]	= { 0x2d8, BIT(16) },
+	[RST_APB2_UART1]	= { 0x2d8, BIT(17) },
+	[RST_APB2_UART2]	= { 0x2d8, BIT(18) },
+	[RST_APB2_UART3]	= { 0x2d8, BIT(19) },
+	[RST_APB2_UART4]	= { 0x2d8, BIT(20) },
+	[RST_APB2_UART5]	= { 0x2d8, BIT(21) },
 };
 
 static const struct ccu_desc sun6i_a31_ccu_desc = {

index ae96ce7803..26cbd69a4c 100644
@@ -60,6 +60,12 @@ static struct ccu_reset_map a64_resets[] = {
 	[RST_BUS_EHCI1]		=  { 0x2c0, BIT(25) },
 	[RST_BUS_OHCI0]		=  { 0x2c0, BIT(28) },
 	[RST_BUS_OHCI1]		=  { 0x2c0, BIT(29) },
+
+	[RST_BUS_UART0]		=  { 0x2d8, BIT(16) },
+	[RST_BUS_UART1]		=  { 0x2d8, BIT(17) },
+	[RST_BUS_UART2]		=  { 0x2d8, BIT(18) },
+	[RST_BUS_UART3]		=  { 0x2d8, BIT(19) },
+	[RST_BUS_UART4]		=  { 0x2d8, BIT(20) },
 };
 
 static const struct ccu_desc sun50i_a64_ccu_desc = {

index 5c1235fa7b..cf9455da97 100644
@@ -50,6 +50,12 @@ static struct ccu_reset_map a83t_resets[] = {
 	[RST_BUS_EHCI0]		= { 0x2c0, BIT(26) },
 	[RST_BUS_EHCI1]		= { 0x2c0, BIT(27) },
 	[RST_BUS_OHCI0]		= { 0x2c0, BIT(29) },
+
+	[RST_BUS_UART0]		= { 0x2d8, BIT(16) },
+	[RST_BUS_UART1]		= { 0x2d8, BIT(17) },
+	[RST_BUS_UART2]		= { 0x2d8, BIT(18) },
+	[RST_BUS_UART3]		= { 0x2d8, BIT(19) },
+	[RST_BUS_UART4]		= { 0x2d8, BIT(20) },
 };
 
 static const struct ccu_desc sun8i_a83t_ccu_desc = {

index 3be6f4cdac..c9bdb209fc 100644
@@ -70,6 +70,11 @@ static struct ccu_reset_map h3_resets[] = {
 	[RST_BUS_OHCI1]		=  { 0x2c0, BIT(29) },
 	[RST_BUS_OHCI2]		=  { 0x2c0, BIT(30) },
 	[RST_BUS_OHCI3]		=  { 0x2c0, BIT(31) },
+
+	[RST_BUS_UART0]		=  { 0x2d8, BIT(16) },
+	[RST_BUS_UART1]		=  { 0x2d8, BIT(17) },
+	[RST_BUS_UART2]		=  { 0x2d8, BIT(18) },
+	[RST_BUS_UART3]		=  { 0x2d8, BIT(19) },
 };
 
 static const struct ccu_desc sun8i_h3_ccu_desc = {

index 1e5b1d10f7..ee699d26ee 100644
@@ -63,6 +63,15 @@ static struct ccu_reset_map r40_resets[] = {
 	[RST_BUS_OHCI0]		= { 0x2c0, BIT(29) },
 	[RST_BUS_OHCI1]		= { 0x2c0, BIT(30) },
 	[RST_BUS_OHCI2]		= { 0x2c0, BIT(31) },
+
+	[RST_BUS_UART0]		= { 0x2d8, BIT(16) },
+	[RST_BUS_UART1]		= { 0x2d8, BIT(17) },
+	[RST_BUS_UART2]		= { 0x2d8, BIT(18) },
+	[RST_BUS_UART3]		= { 0x2d8, BIT(19) },
+	[RST_BUS_UART4]		= { 0x2d8, BIT(20) },
+	[RST_BUS_UART5]		= { 0x2d8, BIT(21) },
+	[RST_BUS_UART6]		= { 0x2d8, BIT(22) },
+	[RST_BUS_UART7]		= { 0x2d8, BIT(23) },
 };
 
 static const struct ccu_desc sun8i_r40_ccu_desc = {

index e12ab2bc65..722af3a91b 100644
@@ -40,6 +40,10 @@ static struct ccu_reset_map v3s_resets[] = {
 	[RST_BUS_MMC2]		=  { 0x2c0, BIT(10) },
 	[RST_BUS_SPI0]		=  { 0x2c0, BIT(20) },
 	[RST_BUS_OTG]		=  { 0x2c0, BIT(24) },
+
+	[RST_BUS_UART0]		=  { 0x2d8, BIT(16) },
+	[RST_BUS_UART1]		=  { 0x2d8, BIT(17) },
+	[RST_BUS_UART2]		=  { 0x2d8, BIT(18) },
 };
 
 static const struct ccu_desc sun8i_v3s_ccu_desc = {