clk: Add Allwinner CLK, RESET support

PATCH Superseded Jagan Teki 4 participants 87 messages Aug 19, 2018 – Aug 31, 2018

Subsystems (13)

Network drivers Arm (32-bit) USB Arm sub-architectures +9 more subsystems

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Jagan Teki

author

2018-08-19 13:56 UTC #0 lore raw

v3 cover clk: Add Allwinner CLK, RESET support

This series is refined version of Allwinner CLK, RESET support for previous RFC[3] which implements CLK and RESET for
- USB
- MMC
- SPI
- UART
- Ethernet

This series depends on 'musb shutdown' series [1] and Linux dts(i) sync series [2].

Since this series supporting MMC, the previous version[4] DM_MMC migration changes are squashed and droped reset and clock ccm hacks.

Tested on A64, H3, H5, H6, R40, A83T, A20.

Changes for v3:
- Added H6 CLK, RESET changes
- Added fastboot mmc device patch
- Added fat env mmc device patch
- Update bootorder to check eMMC as per DT
- Collect Tested-by
Changes for v2:
- Fixed few warnings and spaces in reset descriptor table.
- Add Ethernet CLK and RESET changes

All these changes available at u-boot-sunxi/clk

Note:
- V3S, A23, A33 still need to test.

Any inputs,
Jagan.

Jagan Teki (58):
clk: Add Allwinner A64 CLK driver
reset: Add default request ops
reset: Add Allwinner RESET driver
clk: sunxi: Add Allwinner H3/H5 CLK driver
clk: sunxi: Add Allwinner A10/A20 CLK driver
clk: sunxi: Add Allwinner A10s/A13 CLK driver
clk: sunxi: Add Allwinner A31 CLK driver
clk: sunxi: Add Allwinner A23 CLK driver
clk: sunxi: a23: Add CLK support for A33
clk: sunxi: Add Allwinner A83T CLK driver
clk: sunxi: Add Allwinner R40 CLK driver
clk: sunxi: Add Allwinner V3S CLK driver
sunxi: Enable CLK
musb-new: sunxi: Use CLK and RESET support
phy: sun4i-usb: Use CLK and RESET support
sunxi: usb: Switch to Generic host controllers
usb: host: Drop [e-o]hci-sunxi drivers
clk: sunxi: Implement AHB bus MMC clocks
clk: sunxi: Implement direct MMC clocks
clk: sunxi: Implement AHB bus MMC resets
reset: Add get reset by name optionally
reset: Add reset valid
clk: sunxi: Add Allwinner H6 CLK, RESET driver
arm64: allwinner: dts: h6: fix Pine H64 MMC bus width
sunxi: h6: Enable CLK, RESET
dm: mmc: sunxi: Add CLK and RESET support
fastboot: sunxi: Update fastboot mmc default device
env: fat: Add func to get fat device, partition
sunxi: Get fat device wrt boot device, 'auto' partition
env: sunxi: Don't update fat dev, part wrt MMC_SUNXI_SLOT_EXTRA
sunxi: Add mmc 2, 3 bootenv devices
sunxi: A20: Enable DM_MMC
mmc: sunxi: Add mmc, emmc H5/A64 compatible
sunxi: H3_H5: Enable DM_MMC
sunxi: A64: Enable DM_MMC
mmc: sunxi: Add A83T emmc compatible
sunxi: A83T: Enable DM_MMC
sunxi: V40: Enable DM_MMC
sunxi: H6: Enable DM_MMC
sunxi: A13/A31: Enable DM_MMC
sunxi: A23/A33/V3S: Enable DM_MMC
clk: sunxi: Implement SPI clocks
clk: sunxi: Implement SPI resets
spi: sun4i: Add CLK support
spi: Add Allwinner A31 SPI driver
clk: sunxi: Implement UART clocks
clk: sunxi: Implement UART resets
clk: sunxi: Implement Ethernet clocks
clk: sunxi: Implement Ethernet resets
net: sunxi_emac: Add CLK support
net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle
net: sun8i_emac: Add CLK and RESET support
clk: Get the CLK by index without device
clk: Use clk_get_by_index_tail()
reset: Get the RESET by index without device
clk: sunxi: h3: Implement EPHY CLK and RESET
net: sun8i_emac: Add EPHY CLK and RESET support
board: sunxi: gmac: Remove Ethernet clock and reset

 arch/arm/dts/sun50i-h6-pine-h64.dts           |   2 +
 arch/arm/include/asm/arch-sunxi/ccu.h         |  82 +++
 arch/arm/mach-sunxi/Kconfig                   |  24 +
 arch/arm/mach-sunxi/board.c                   |  50 ++
 board/sunxi/gmac.c                            |   8 -
 configs/A10-OLinuXino-Lime_defconfig          |   1 +
 configs/A10s-OLinuXino-M_defconfig            |   1 +
 configs/A13-OLinuXinoM_defconfig              |   1 +
 configs/A13-OLinuXino_defconfig               |   1 +
 configs/A20-OLinuXino-Lime2-eMMC_defconfig    |   2 +
 configs/A20-OLinuXino-Lime2_defconfig         |   1 +
 configs/A20-OLinuXino-Lime_defconfig          |   1 +
 configs/A20-Olimex-SOM204-EVB-eMMC_defconfig  |   1 +
 configs/A20-Olimex-SOM204-EVB_defconfig       |   2 +
 configs/Auxtek-T003_defconfig                 |   1 +
 configs/Auxtek-T004_defconfig                 |   1 +
 configs/Bananapi_defconfig                    |   1 +
 configs/Bananapi_m2m_defconfig                |   1 +
 configs/Bananapro_defconfig                   |   1 +
 configs/CHIP_defconfig                        |   1 +
 configs/CHIP_pro_defconfig                    |   1 +
 configs/CSQ_CS908_defconfig                   |   1 +
 configs/Colombus_defconfig                    |   1 +
 configs/Cubieboard2_defconfig                 |   1 +
 configs/Cubieboard_defconfig                  |   1 +
 configs/Cubietruck_plus_defconfig             |   1 +
 configs/Hummingbird_A31_defconfig             |   1 +
 configs/Itead_Ibox_A20_defconfig              |   1 +
 configs/Linksprite_pcDuino3_Nano_defconfig    |   1 +
 configs/Linksprite_pcDuino3_defconfig         |   1 +
 configs/Linksprite_pcDuino_defconfig          |   1 +
 configs/MK808C_defconfig                      |   1 +
 configs/Marsboard_A10_defconfig               |   1 +
 configs/Mele_A1000G_quad_defconfig            |   1 +
 configs/Mele_A1000_defconfig                  |   1 +
 configs/Mele_I7_defconfig                     |   1 +
 configs/Mele_M3_defconfig                     |   1 +
 configs/Mele_M5_defconfig                     |   1 +
 configs/Mele_M9_defconfig                     |   1 +
 configs/Mini-X_defconfig                      |   1 +
 configs/Orangepi_defconfig                    |   1 +
 configs/Orangepi_mini_defconfig               |   1 +
 configs/Sinlinx_SinA31s_defconfig             |   1 +
 configs/Sinlinx_SinA33_defconfig              |   2 +
 configs/Sinovoip_BPI_M2_Plus_defconfig        |   1 +
 configs/Sinovoip_BPI_M2_defconfig             |   1 +
 configs/Sinovoip_BPI_M3_defconfig             |   1 +
 configs/Wexler_TAB7200_defconfig              |   1 +
 configs/Wobo_i5_defconfig                     |   1 +
 configs/a64-olinuxino_defconfig               |   1 +
 configs/amarula_a64_relic_defconfig           |   1 +
 configs/ba10_tv_box_defconfig                 |   1 +
 configs/bananapi_m1_plus_defconfig            |   1 +
 configs/bananapi_m64_defconfig                |   1 +
 configs/ga10h_v1_1_defconfig                  |   1 +
 configs/h8_homlet_v2_defconfig                |   1 +
 configs/i12-tvbox_defconfig                   |   1 +
 configs/icnova-a20-swac_defconfig             |   1 +
 configs/inet1_defconfig                       |   1 +
 configs/inet_q972_defconfig                   |   1 +
 configs/jesurun_q5_defconfig                  |   1 +
 configs/libretech_all_h3_cc_h2_plus_defconfig |   1 +
 configs/libretech_all_h3_cc_h3_defconfig      |   1 +
 configs/libretech_all_h3_cc_h5_defconfig      |   1 +
 configs/mixtile_loftq_defconfig               |   1 +
 configs/mk802_a10s_defconfig                  |   1 +
 configs/mk802_defconfig                       |   1 +
 configs/mk802ii_defconfig                     |   1 +
 configs/nanopi_a64_defconfig                  |   1 +
 configs/nanopi_m1_defconfig                   |   1 +
 configs/nanopi_m1_plus_defconfig              |   1 +
 configs/nanopi_neo2_defconfig                 |   1 +
 configs/nanopi_neo_air_defconfig              |   1 +
 configs/nanopi_neo_defconfig                  |   1 +
 configs/nanopi_neo_plus2_defconfig            |   1 +
 configs/orangepi_2_defconfig                  |   1 +
 configs/orangepi_lite_defconfig               |   1 +
 configs/orangepi_one_defconfig                |   1 +
 configs/orangepi_pc2_defconfig                |   1 +
 configs/orangepi_pc_defconfig                 |   1 +
 configs/orangepi_pc_plus_defconfig            |   1 +
 configs/orangepi_plus2e_defconfig             |   1 +
 configs/orangepi_plus_defconfig               |   1 +
 configs/orangepi_prime_defconfig              |   1 +
 configs/orangepi_r1_defconfig                 |   1 +
 configs/orangepi_win_defconfig                |   1 +
 configs/orangepi_zero_defconfig               |   1 +
 configs/orangepi_zero_plus2_defconfig         |   1 +
 configs/orangepi_zero_plus_defconfig          |   1 +
 configs/parrot_r16_defconfig                  |   2 +
 configs/pine64_plus_defconfig                 |   1 +
 configs/r7-tv-dongle_defconfig                |   1 +
 configs/sopine_baseboard_defconfig            |   1 +
 configs/sun8i_a23_evb_defconfig               |   1 +
 configs/sunxi_Gemei_G9_defconfig              |   1 +
 configs/tbs_a711_defconfig                    |   1 +
 drivers/clk/Kconfig                           |   1 +
 drivers/clk/Makefile                          |   1 +
 drivers/clk/clk-uclass.c                      |  84 +++-
 drivers/clk/sunxi/Kconfig                     |  82 +++
 drivers/clk/sunxi/Makefile                    |  18 +
 drivers/clk/sunxi/clk_a10.c                   | 107 ++++
 drivers/clk/sunxi/clk_a10s.c                  |  96 ++++
 drivers/clk/sunxi/clk_a23.c                   | 105 ++++
 drivers/clk/sunxi/clk_a31.c                   | 128 +++++
 drivers/clk/sunxi/clk_a64.c                   | 115 +++++
 drivers/clk/sunxi/clk_a83t.c                  | 105 ++++
 drivers/clk/sunxi/clk_h3.c                    | 130 +++++
 drivers/clk/sunxi/clk_h6.c                    |  73 +++
 drivers/clk/sunxi/clk_r40.c                   | 123 +++++
 drivers/clk/sunxi/clk_sunxi.c                 |  77 +++
 drivers/clk/sunxi/clk_v3s.c                   |  91 ++++
 drivers/fastboot/Kconfig                      |   3 +-
 drivers/mmc/sunxi_mmc.c                       | 121 +++--
 drivers/net/sun8i_emac.c                      | 179 ++++---
 drivers/net/sunxi_emac.c                      |  28 +-
 drivers/phy/allwinner/phy-sun4i-usb.c         |  77 ++-
 drivers/reset/Kconfig                         |   8 +
 drivers/reset/Makefile                        |   1 +
 drivers/reset/reset-sunxi.c                   | 124 +++++
 drivers/reset/reset-uclass.c                  |  81 ++-
 drivers/spi/Kconfig                           |   6 +
 drivers/spi/Makefile                          |   1 +
 drivers/spi/sun4i_spi.c                       |  40 +-
 drivers/spi/sun6i_spi.c                       | 475 ++++++++++++++++++
 drivers/usb/host/Kconfig                      |   2 +
 drivers/usb/host/Makefile                     |   2 -
 drivers/usb/host/ehci-sunxi.c                 | 204 --------
 drivers/usb/host/ohci-sunxi.c                 | 233 ---------
 drivers/usb/musb-new/sunxi.c                  |  82 +--
 env/Kconfig                                   |   3 +-
 env/fat.c                                     |   9 +-
 include/clk.h                                 |  15 +
 include/configs/sun4i.h                       |   4 -
 include/configs/sun50i.h                      |   5 -
 include/configs/sun5i.h                       |   4 -
 include/configs/sun6i.h                       |   4 -
 include/configs/sun7i.h                       |   4 -
 include/configs/sun8i.h                       |   4 -
 include/configs/sunxi-common.h                |   9 +-
 include/fat.h                                 |   1 +
 include/reset.h                               |  52 ++
 scripts/config_whitelist.txt                  |   2 -
 143 files changed, 2695 insertions(+), 685 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-sunxi/ccu.h
 create mode 100644 drivers/clk/sunxi/Kconfig
 create mode 100644 drivers/clk/sunxi/Makefile
 create mode 100644 drivers/clk/sunxi/clk_a10.c
 create mode 100644 drivers/clk/sunxi/clk_a10s.c
 create mode 100644 drivers/clk/sunxi/clk_a23.c
 create mode 100644 drivers/clk/sunxi/clk_a31.c
 create mode 100644 drivers/clk/sunxi/clk_a64.c
 create mode 100644 drivers/clk/sunxi/clk_a83t.c
 create mode 100644 drivers/clk/sunxi/clk_h3.c
 create mode 100644 drivers/clk/sunxi/clk_h6.c
 create mode 100644 drivers/clk/sunxi/clk_r40.c
 create mode 100644 drivers/clk/sunxi/clk_sunxi.c
 create mode 100644 drivers/clk/sunxi/clk_v3s.c
 create mode 100644 drivers/reset/reset-sunxi.c
 create mode 100644 drivers/spi/sun6i_spi.c
 delete mode 100644 drivers/usb/host/ehci-sunxi.c
 delete mode 100644 drivers/usb/host/ohci-sunxi.c

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #1 lore raw

PATCH v3 1/58 clk: Add Allwinner A64 CLK driver

Add initial clock driver for Allwinner A64.

Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers.

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/include/asm/arch-sunxi/ccu.h | 47 ++++++++++++++++++++
 drivers/clk/Kconfig                   |  1 +
 drivers/clk/Makefile                  |  1 +
 drivers/clk/sunxi/Kconfig             | 18 ++++++++
 drivers/clk/sunxi/Makefile            |  9 ++++
 drivers/clk/sunxi/clk_a64.c           | 62 +++++++++++++++++++++++++++
 drivers/clk/sunxi/clk_sunxi.c         | 58 +++++++++++++++++++++++++
 7 files changed, 196 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-sunxi/ccu.h
 create mode 100644 drivers/clk/sunxi/Kconfig
 create mode 100644 drivers/clk/sunxi/Makefile
 create mode 100644 drivers/clk/sunxi/clk_a64.c
 create mode 100644 drivers/clk/sunxi/clk_sunxi.c

arch/arm/include/asm/arch-sunxi/ccu.h new file +47 -0

new file mode 100644
index 0000000000..f628c893de
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions.
+ * Author: Jagan Teki <[email protected]>
+ */
+
+#ifndef _ASM_ARCH_CCU_H
+#define _ASM_ARCH_CCU_H
+
+/**
+ * ccu_clk_map - common clock unit clock map
+ *
+ * @off:		ccu clock offset
+ * @bit:		ccu clock bit value
+ * @ccu_clk_set_rate:	ccu clock set rate func
+ */
+struct ccu_clk_map {
+	u16 off;
+	u32 bit;
+	int (*ccu_clk_set_rate)(void *base, u32 bit, ulong rate);
+};
+
+/**
+ * struct ccu_desc - common clock unit descriptor
+ *
+ * @clks:		mapping clocks descriptor
+ * @num_clks:		number of mapped clocks
+ */
+struct ccu_desc {
+	struct ccu_clk_map *clks;
+	unsigned long num_clks;
+};
+
+/**
+ * struct sunxi_clk_priv - sunxi clock private structure
+ *
+ * @base:	base address
+ * @desc:	ccu descriptor
+ */
+struct sunxi_clk_priv {
+	void *base;
+	const struct ccu_desc *desc;
+};
+
+extern struct clk_ops sunxi_clk_ops;
+
+#endif /* _ASM_ARCH_CCU_H */

drivers/clk/Kconfig +1 -0

index a99abed9e9..b4992e9ff1 100644
@@ -88,6 +88,7 @@ source "drivers/clk/exynos/Kconfig"
 source "drivers/clk/mvebu/Kconfig"
 source "drivers/clk/owl/Kconfig"
 source "drivers/clk/renesas/Kconfig"
+source "drivers/clk/sunxi/Kconfig"
 source "drivers/clk/tegra/Kconfig"
 source "drivers/clk/uniphier/Kconfig"

drivers/clk/Makefile +1 -0

index 146283c723..7cefcd99a0 100644
@@ -11,6 +11,7 @@ obj-y += tegra/
 obj-$(CONFIG_ARCH_ASPEED) += aspeed/
 obj-$(CONFIG_ARCH_MESON) += clk_meson.o
 obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
+obj-$(CONFIG_ARCH_SUNXI) += sunxi/
 obj-$(CONFIG_CLK_AT91) += at91/
 obj-$(CONFIG_CLK_MVEBU) += mvebu/
 obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o

drivers/clk/sunxi/Kconfig new file +18 -0

new file mode 100644
index 0000000000..bf5ecb3801
@@ -0,0 +1,18 @@
+config CLK_SUNXI
+	bool "Clock support for Allwinner SoCs"
+	depends on CLK && ARCH_SUNXI
+	default y
+	help
+	  This enables support for common clock driver API on Allwinner
+	  SoCs.
+
+if CLK_SUNXI
+
+config CLK_SUN50I_A64
+	bool "Clock driver for Allwinner A64"
+	default MACH_SUN50I
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner A64 SoC.
+
+endif # CLK_SUNXI

drivers/clk/sunxi/Makefile new file +9 -0

new file mode 100644
index 0000000000..fb20d28333
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2018 Amarula Solutions.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
+
+obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o

drivers/clk/sunxi/clk_a64.c new file +62 -0

62 lines not on this page · raw message

drivers/clk/sunxi/clk_sunxi.c new file +58 -0

58 lines not on this page · raw message

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #2 lore raw

PATCH v3 2/58 reset: Add default request ops

In reply to Jagan Teki

Missing request ops from respective uclass driver generating "synchronous abort" in Allwinner platform, may be in arm. So add default request ops and give a chance to uclass driver to think whether they really need request or not.

Cc Simon Glass <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/reset/reset-uclass.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

drivers/reset/reset-uclass.c +9 -1

index 3899537635..99881b8b99 100644
@@ -14,6 +14,11 @@ static inline struct reset_ops *reset_dev_ops(struct udevice *dev)
 	return (struct reset_ops *)dev->driver->ops;
 }
 
+static int reset_request_default(struct reset_ctl *reset_ctl)
+{
+	return 0;
+}
+
 static int reset_of_xlate_default(struct reset_ctl *reset_ctl,
 				  struct ofnode_phandle_args *args)
 {

@@ -69,7 +74,10 @@ int reset_get_by_index(struct udevice *dev, int index,
 		return ret;
 	}
 
-	ret = ops->request(reset_ctl);
+	if (ops->request)
+		ret = ops->request(reset_ctl);
+	else
+		ret = reset_request_default(reset_ctl);
 	if (ret) {
 		debug("ops->request() failed: %d\n", ret);
 		return ret;

Signature · 1 line

2.18.0.321.gffc6fa0e3

Maxime Ripard

2018-08-20 11:22 UTC #3 lore raw

PATCH v3 2/58 reset: Add default request ops

Quoted 5 lines · Jagan Teki

Missing request ops from respective uclass driver generating "synchronous abort" in Allwinner platform, may be in arm. So add default request ops and give a chance to uclass driver to think whether they really need request or not.

I'm not sure why anyone would not want a request operation for a reset line.

Maxime

Signature · 10 lines

Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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Jagan Teki

author

2018-08-19 13:56 UTC #4 lore raw

PATCH v3 3/58 reset: Add Allwinner RESET driver

In reply to Jagan Teki

Add common reset driver for all Allwinner SoC's.

Since CLK and RESET share common DT compatible, it is CLK driver job is to bind the reset driver. So add CLK bind call on respective SoC driver by passing ccu map descriptor so-that reset deassert, deassert operations held based on reset register map defined by CLK driver.

Select DM_RESET via CLK_SUNXI, this make hidden section of RESET since CLK and RESET share common DT compatible and code.

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/include/asm/arch-sunxi/ccu.h |  25 ++++++
 drivers/clk/sunxi/Kconfig             |   1 +
 drivers/clk/sunxi/clk_a64.c           |  22 +++++
 drivers/reset/Kconfig                 |   8 ++
 drivers/reset/Makefile                |   1 +
 drivers/reset/reset-sunxi.c           | 124 ++++++++++++++++++++++++++
 6 files changed, 181 insertions(+)
 create mode 100644 drivers/reset/reset-sunxi.c

arch/arm/include/asm/arch-sunxi/ccu.h +25 -0

index f628c893de..bacd052ef3 100644
@@ -20,15 +20,31 @@ struct ccu_clk_map {
 	int (*ccu_clk_set_rate)(void *base, u32 bit, ulong rate);
 };
 
+/**
+ * ccu_reset_map - common clock unit reset map
+ *
+ * @off:	ccu reset offset
+ * @bit:	ccu reset bit value
+ */
+struct ccu_reset_map {
+	u16 off;
+	u32 bit;
+};
+
 /**
  * struct ccu_desc - common clock unit descriptor
  *
  * @clks:		mapping clocks descriptor
  * @num_clks:		number of mapped clocks
+ * @resets:		mapping resets descriptor
+ * @num_resets:		number of mapped resets
  */
 struct ccu_desc {
 	struct ccu_clk_map *clks;
 	unsigned long num_clks;
+
+	struct ccu_reset_map *resets;
+	unsigned long num_resets;
 };
 
 /**

@@ -44,4 +60,13 @@ struct sunxi_clk_priv {
 
 extern struct clk_ops sunxi_clk_ops;
 
+/**
+ * sunxi_reset_bind() - reset binding
+ *
+ * @dev:	reset device
+ * @count:	reset count
+ * @return 0 success, or error value
+ */
+int sunxi_reset_bind(struct udevice *dev, ulong count);
+
 #endif /* _ASM_ARCH_CCU_H */

drivers/clk/sunxi/Kconfig +1 -0

index bf5ecb3801..041d711e58 100644
@@ -1,6 +1,7 @@
 config CLK_SUNXI
 	bool "Clock support for Allwinner SoCs"
 	depends on CLK && ARCH_SUNXI
+	select DM_RESET
 	default y
 	help
 	  This enables support for common clock driver API on Allwinner

drivers/clk/sunxi/clk_a64.c +22 -0

index 9393a01ccf..e5257b62c7 100644
@@ -10,6 +10,7 @@
 #include <errno.h>
 #include <asm/arch/ccu.h>
 #include <dt-bindings/clock/sun50i-a64-ccu.h>
+#include <dt-bindings/reset/sun50i-a64-ccu.h>
 
 static struct ccu_clk_map a64_clks[] = {
 	[CLK_BUS_OTG]		= { 0x060, BIT(23), NULL },

@@ -26,9 +27,24 @@ static struct ccu_clk_map a64_clks[] = {
 	[CLK_USB_OHCI1]		= { 0x0cc, BIT(17), NULL },
 };
 
+static struct ccu_reset_map a64_resets[] = {
+	[RST_USB_PHY0]		= { 0x0cc, BIT(0) },
+	[RST_USB_PHY1]		= { 0x0cc, BIT(1) },
+	[RST_USB_HSIC]		= { 0x0cc, BIT(2) },
+
+	[RST_BUS_OTG]		= { 0x2c0, BIT(23) },
+	[RST_BUS_EHCI0]		= { 0x2c0, BIT(24) },
+	[RST_BUS_EHCI1]		= { 0x2c0, BIT(25) },
+	[RST_BUS_OHCI0]		= { 0x2c0, BIT(28) },
+	[RST_BUS_OHCI1]		= { 0x2c0, BIT(29) },
+};
+
 static const struct ccu_desc sun50i_a64_ccu_desc = {
 	.clks = a64_clks,
 	.num_clks = ARRAY_SIZE(a64_clks),
+
+	.resets = a64_resets,
+	.num_resets =  ARRAY_SIZE(a64_resets),
 };
 
 static int a64_clk_probe(struct udevice *dev)

@@ -46,6 +62,11 @@ static int a64_clk_probe(struct udevice *dev)
 	return 0;
 }
 
+static int a64_clk_bind(struct udevice *dev)
+{
+	return sunxi_reset_bind(dev, 50);
+}
+
 static const struct udevice_id a64_clk_ids[] = {
 	{ .compatible = "allwinner,sun50i-a64-ccu",
 	  .data = (ulong)&sun50i_a64_ccu_desc },

@@ -59,4 +80,5 @@ U_BOOT_DRIVER(clk_sun50i_a64) = {
 	.priv_auto_alloc_size	= sizeof(struct sunxi_clk_priv),
 	.ops		= &sunxi_clk_ops,
 	.probe		= a64_clk_probe,
+	.bind		= a64_clk_bind,
 };

drivers/reset/Kconfig +8 -0

index 33c39b7fb6..bdc06564a0 100644
@@ -98,4 +98,12 @@ config RESET_SOCFPGA
 	help
 	  Support for reset controller on SoCFPGA platform.
 
+config RESET_SUNXI
+	bool "RESET support for Allwinner SoCs"
+	depends on DM_RESET && ARCH_SUNXI
+	default y
+	help
+	  This enables support for common reset driver for
+	  Allwinner SoCs.
+
 endmenu

drivers/reset/Makefile +1 -0

index ad08be4c8c..698d15a0e0 100644
@@ -15,3 +15,4 @@ obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
 obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
 obj-$(CONFIG_RESET_MESON) += reset-meson.o
 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
+obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o

drivers/reset/reset-sunxi.c new file +124 -0

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Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #5 lore raw

PATCH v3 4/58 clk: sunxi: Add Allwinner H3/H5 CLK driver

In reply to Jagan Teki

Add initial clock driver for Allwinner H3/H5.

- Implement USB bus and USB clocks via ccu_clk_map descriptor for H3/H5, so it can accessed in common clk enable and disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset_map descriptor for H3/H5, so it can accessed in common reset deassert and assert functions from reset-sunxi.c

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/Kconfig  |  7 +++
 drivers/clk/sunxi/Makefile |  1 +
 drivers/clk/sunxi/clk_h3.c | 97 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 105 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk_h3.c

drivers/clk/sunxi/Kconfig +7 -0

index 041d711e58..c3713bbac2 100644
@@ -9,6 +9,13 @@ config CLK_SUNXI
 
 if CLK_SUNXI
 
+config CLK_SUN8I_H3
+	bool "Clock driver for Allwinner H3/H5"
+	default MACH_SUNXI_H3_H5
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner H3/H5 SoC.
+
 config CLK_SUN50I_A64
 	bool "Clock driver for Allwinner A64"
 	default MACH_SUN50I

drivers/clk/sunxi/Makefile +1 -0

index fb20d28333..dec49f27a1 100644
@@ -6,4 +6,5 @@
 
 obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
 
+obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o

drivers/clk/sunxi/clk_h3.c new file +97 -0

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2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #6 lore raw

PATCH v3 5/58 clk: sunxi: Add Allwinner A10/A20 CLK driver

In reply to Jagan Teki

Add initial clock driver for Allwinner A10/A20.

- Implement USB ahb and USB clocks via ccu_clk_map descriptor for A10/A20, so it can accessed in common clk enable and disable functions from clk_sunxi.c
- Implement USB resets via ccu_reset_map descriptor for A10/A20, so it can accessed in common reset deassert and assert functions from reset-sunxi.c

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/Kconfig   |  7 ++++
 drivers/clk/sunxi/Makefile  |  1 +
 drivers/clk/sunxi/clk_a10.c | 77 +++++++++++++++++++++++++++++++++++++
 3 files changed, 85 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk_a10.c

drivers/clk/sunxi/Kconfig +7 -0

index c3713bbac2..fbbf94ef55 100644
@@ -9,6 +9,13 @@ config CLK_SUNXI
 
 if CLK_SUNXI
 
+config CLK_SUN4I_A10
+	bool "Clock driver for Allwinner A10/A20"
+	default MACH_SUN4I || MACH_SUN7I
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner A10/A20 SoC.
+
 config CLK_SUN8I_H3
 	bool "Clock driver for Allwinner H3/H5"
 	default MACH_SUNXI_H3_H5

drivers/clk/sunxi/Makefile +1 -0

index dec49f27a1..bba830922f 100644
@@ -6,5 +6,6 @@
 
 obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
 
+obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
 obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o

drivers/clk/sunxi/clk_a10.c new file +77 -0

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Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #7 lore raw

PATCH v3 6/58 clk: sunxi: Add Allwinner A10s/A13 CLK driver

In reply to Jagan Teki

Add initial clock driver for Allwinner A10s/A13.

- Implement USB ahb and USB clocks via ccu_clk_map descriptor for A10s/A13, so it can accessed in common clk enable and disable functions from clk_sunxi.c
- Implement USB resets via ccu_reset_map descriptor for A10s/A13, so it can accessed in common reset deassert and assert functions from reset-sunxi.c

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/Kconfig    |  7 ++++
 drivers/clk/sunxi/Makefile   |  1 +
 drivers/clk/sunxi/clk_a10s.c | 74 ++++++++++++++++++++++++++++++++++++
 3 files changed, 82 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk_a10s.c

drivers/clk/sunxi/Kconfig +7 -0

index fbbf94ef55..b228c2fa3a 100644
@@ -16,6 +16,13 @@ config CLK_SUN4I_A10
 	  This enables common clock driver support for platforms based
 	  on Allwinner A10/A20 SoC.
 
+config CLK_SUN5I_A10S
+	bool "Clock driver for Allwinner A10s/A13"
+	default MACH_SUN5I
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner A10s/A13 SoC.
+
 config CLK_SUN8I_H3
 	bool "Clock driver for Allwinner H3/H5"
 	default MACH_SUNXI_H3_H5

drivers/clk/sunxi/Makefile +1 -0

index bba830922f..466d4b79d6 100644
@@ -7,5 +7,6 @@
 obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
 
 obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
+obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
 obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o

drivers/clk/sunxi/clk_a10s.c new file +74 -0

74 lines not on this page · raw message

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #8 lore raw

PATCH v3 7/58 clk: sunxi: Add Allwinner A31 CLK driver

In reply to Jagan Teki

Add initial clock driver for Allwinner A31.

- Implement USB ahb1 and USB clocks via ccu_clk_map descriptor for A31, so it can accessed in common clk enable and disable functions from clk_sunxi.c
- Implement USB ahb1 and USB resets via ccu_reset_map descriptor for A31, so it can accessed in common reset deassert and assert functions from reset-sunxi.c

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/Kconfig   |  7 +++
 drivers/clk/sunxi/Makefile  |  1 +
 drivers/clk/sunxi/clk_a31.c | 86 +++++++++++++++++++++++++++++++++++++
 3 files changed, 94 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk_a31.c

drivers/clk/sunxi/Kconfig +7 -0

index b228c2fa3a..535b0dc02c 100644
@@ -23,6 +23,13 @@ config CLK_SUN5I_A10S
 	  This enables common clock driver support for platforms based
 	  on Allwinner A10s/A13 SoC.
 
+config CLK_SUN6I_A31
+	bool "Clock driver for Allwinner A31/A31s"
+	default MACH_SUN6I
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner A31/A31s SoC.
+
 config CLK_SUN8I_H3
 	bool "Clock driver for Allwinner H3/H5"
 	default MACH_SUNXI_H3_H5

drivers/clk/sunxi/Makefile +1 -0

index 466d4b79d6..3cf0071b0c 100644
@@ -8,5 +8,6 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
 
 obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
 obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
+obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
 obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o

drivers/clk/sunxi/clk_a31.c new file +86 -0

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Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #9 lore raw

PATCH v3 8/58 clk: sunxi: Add Allwinner A23 CLK driver

In reply to Jagan Teki

Add initial clock driver for Allwinner A23.

- Implement USB bus and USB clocks via ccu_clk_map descriptor for A23, so it can accessed in common clk enable and disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset_map descriptor for A23, so it can accessed in common reset deassert and assert functions from reset-sunxi.c

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/Kconfig   |  7 ++++
 drivers/clk/sunxi/Makefile  |  1 +
 drivers/clk/sunxi/clk_a23.c | 79 +++++++++++++++++++++++++++++++++++++
 3 files changed, 87 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk_a23.c

drivers/clk/sunxi/Kconfig +7 -0

index 535b0dc02c..54600e8e1f 100644
@@ -30,6 +30,13 @@ config CLK_SUN6I_A31
 	  This enables common clock driver support for platforms based
 	  on Allwinner A31/A31s SoC.
 
+config CLK_SUN8I_A23
+	bool "Clock driver for Allwinner A23"
+	default MACH_SUN8I_A23
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner A23 SoC.
+
 config CLK_SUN8I_H3
 	bool "Clock driver for Allwinner H3/H5"
 	default MACH_SUNXI_H3_H5

drivers/clk/sunxi/Makefile +1 -0

index 3cf0071b0c..6924897036 100644
@@ -9,5 +9,6 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
 obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
 obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
 obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
+obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
 obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o

drivers/clk/sunxi/clk_a23.c new file +79 -0

79 lines not on this page · raw message

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #10 lore raw

PATCH v3 9/58 clk: sunxi: a23: Add CLK support for A33

In reply to Jagan Teki

A33 has separate clock driver in Linux because of few clock differences wrt to A23 like audio etc,. these may not useful for U-Boot so added a33 ccu compatible on existing a23 clock driver.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/Kconfig   | 6 +++---
 drivers/clk/sunxi/clk_a23.c | 2 ++
 2 files changed, 5 insertions(+), 3 deletions(-)

drivers/clk/sunxi/Kconfig +3 -3

index 54600e8e1f..38ff99d345 100644
@@ -31,11 +31,11 @@ config CLK_SUN6I_A31
 	  on Allwinner A31/A31s SoC.
 
 config CLK_SUN8I_A23
-	bool "Clock driver for Allwinner A23"
-	default MACH_SUN8I_A23
+	bool "Clock driver for Allwinner A23/A33"
+	default MACH_SUN8I_A23 || MACH_SUN8I_A33
 	help
 	  This enables common clock driver support for platforms based
-	  on Allwinner A23 SoC.
+	  on Allwinner A23/A33 SoC.
 
 config CLK_SUN8I_H3
 	bool "Clock driver for Allwinner H3/H5"

drivers/clk/sunxi/clk_a23.c +2 -0

index 799c8ac0aa..ec9834e1a8 100644
@@ -65,6 +65,8 @@ static int a23_clk_bind(struct udevice *dev)
 static const struct udevice_id a23_clk_ids[] = {
 	{ .compatible = "allwinner,sun8i-a23-ccu",
 	  .data = (ulong)&sun8i_a23_ccu_desc },
+	{ .compatible = "allwinner,sun8i-a33-ccu",
+	  .data = (ulong)&sun8i_a23_ccu_desc },
 	{ }
 };

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #11 lore raw

PATCH v3 10/58 clk: sunxi: Add Allwinner A83T CLK driver

In reply to Jagan Teki

Add initial clock driver for Allwinner A83T.

- Implement USB bus and USB clocks via ccu_clk_map descriptor for A83T, so it can accessed in common clk enable and disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset_map descriptor for A83T, so it can accessed in common reset deassert and assert functions from reset-sunxi.c

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/Kconfig    |  7 ++++
 drivers/clk/sunxi/Makefile   |  1 +
 drivers/clk/sunxi/clk_a83t.c | 81 ++++++++++++++++++++++++++++++++++++
 3 files changed, 89 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk_a83t.c

drivers/clk/sunxi/Kconfig +7 -0

index 38ff99d345..90af70d171 100644
@@ -37,6 +37,13 @@ config CLK_SUN8I_A23
 	  This enables common clock driver support for platforms based
 	  on Allwinner A23/A33 SoC.
 
+config CLK_SUN8I_A83T
+	bool "Clock driver for Allwinner A83T"
+	default MACH_SUN8I_A83T
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner A83T SoC.
+
 config CLK_SUN8I_H3
 	bool "Clock driver for Allwinner H3/H5"
 	default MACH_SUNXI_H3_H5

drivers/clk/sunxi/Makefile +1 -0

index 6924897036..4a254c8671 100644
@@ -10,5 +10,6 @@ obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
 obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
 obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
 obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
+obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
 obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o

drivers/clk/sunxi/clk_a83t.c new file +81 -0

81 lines not on this page · raw message

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #12 lore raw

PATCH v3 11/58 clk: sunxi: Add Allwinner R40 CLK driver

In reply to Jagan Teki

Add initial clock driver for Allwinner R40.

- Implement USB bus and USB clocks via ccu_clk_map descriptor for R40, so it can accessed in common clk enable and disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset_map descriptor for R40, so it can accessed in common reset deassert and assert functions from reset-sunxi.c

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/Kconfig   |  7 +++
 drivers/clk/sunxi/Makefile  |  1 +
 drivers/clk/sunxi/clk_r40.c | 89 +++++++++++++++++++++++++++++++++++++
 3 files changed, 97 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk_r40.c

drivers/clk/sunxi/Kconfig +7 -0

index 90af70d171..c45a4ba378 100644
@@ -44,6 +44,13 @@ config CLK_SUN8I_A83T
 	  This enables common clock driver support for platforms based
 	  on Allwinner A83T SoC.
 
+config CLK_SUN8I_R40
+	bool "Clock driver for Allwinner R40"
+	default MACH_SUN8I_R40
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner R40 SoC.
+
 config CLK_SUN8I_H3
 	bool "Clock driver for Allwinner H3/H5"
 	default MACH_SUNXI_H3_H5

drivers/clk/sunxi/Makefile +1 -0

index 4a254c8671..61f8b87396 100644
@@ -11,5 +11,6 @@ obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
 obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
 obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
 obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
+obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
 obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o

drivers/clk/sunxi/clk_r40.c new file +89 -0

89 lines not on this page · raw message

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #13 lore raw

PATCH v3 12/58 clk: sunxi: Add Allwinner V3S CLK driver

In reply to Jagan Teki

Add initial clock driver for Allwinner V3S.

- Implement USB bus and USB clocks via ccu_clk_map descriptor for V3S, so it can accessed in common clk enable and disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset_map descriptor for V3S, so it can accessed in common reset deassert and assert functions from reset-sunxi.c

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/Kconfig   |  7 ++++
 drivers/clk/sunxi/Makefile  |  1 +
 drivers/clk/sunxi/clk_v3s.c | 69 +++++++++++++++++++++++++++++++++++++
 3 files changed, 77 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk_v3s.c

drivers/clk/sunxi/Kconfig +7 -0

index c45a4ba378..a6f84e9e56 100644
@@ -51,6 +51,13 @@ config CLK_SUN8I_R40
 	  This enables common clock driver support for platforms based
 	  on Allwinner R40 SoC.
 
+config CLK_SUN8I_V3S
+	bool "Clock driver for Allwinner V3S"
+	default MACH_SUN8I_V3S
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner V3S SoC.
+
 config CLK_SUN8I_H3
 	bool "Clock driver for Allwinner H3/H5"
 	default MACH_SUNXI_H3_H5

drivers/clk/sunxi/Makefile +1 -0

index 61f8b87396..fbd43527a6 100644
@@ -12,5 +12,6 @@ obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
 obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
 obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
 obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
+obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o
 obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o

drivers/clk/sunxi/clk_v3s.c new file +69 -0

69 lines not on this page · raw message

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #14 lore raw

PATCH v3 13/58 sunxi: Enable CLK

In reply to Jagan Teki

CLK and DM_RESET drivers are now available for most of the Allwinner platforms, so enable in mach-sunxi/Kconfig

Enabling CLK will select DM_RESET by default.

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/mach-sunxi/Kconfig | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/arm/mach-sunxi/Kconfig +12 -0

index 558363b52d..dce81b7d53 100644
@@ -132,6 +132,7 @@ endif
 
 config MACH_SUNXI_H3_H5
 	bool
+	select CLK
 	select DM_I2C
 	select PHY_SUN4I_USB
 	select SUNXI_DE2

@@ -147,6 +148,7 @@ choice
 config MACH_SUN4I
 	bool "sun4i (Allwinner A10)"
 	select CPU_V7A
+	select CLK
 	select ARM_CORTEX_CPU_IS_UP
 	select DM_MMC if MMC
 	select DM_SCSI if SCSI

@@ -158,6 +160,7 @@ config MACH_SUN4I
 config MACH_SUN5I
 	bool "sun5i (Allwinner A13)"
 	select CPU_V7A
+	select CLK
 	select ARM_CORTEX_CPU_IS_UP
 	select DRAM_SUN4I
 	select PHY_SUN4I_USB

@@ -171,6 +174,7 @@ config MACH_SUN6I
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
+	select CLK
 	select DRAM_SUN6I
 	select PHY_SUN4I_USB
 	select SUN6I_P2WI

@@ -185,6 +189,7 @@ config MACH_SUN7I
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
+	select CLK
 	select DRAM_SUN4I
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN4I

@@ -197,6 +202,7 @@ config MACH_SUN8I_A23
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
+	select CLK
 	select DRAM_SUN8I_A23
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN6I

@@ -210,6 +216,7 @@ config MACH_SUN8I_A33
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
+	select CLK
 	select DRAM_SUN8I_A33
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN6I

@@ -220,6 +227,7 @@ config MACH_SUN8I_A33
 config MACH_SUN8I_A83T
 	bool "sun8i (Allwinner A83T)"
 	select CPU_V7A
+	select CLK
 	select DRAM_SUN8I_A83T
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN6I

@@ -231,6 +239,7 @@ config MACH_SUN8I_H3
 	select CPU_V7A
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
+	select CLK
 	select ARCH_SUPPORT_PSCI
 	select MACH_SUNXI_H3_H5
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT

@@ -241,6 +250,7 @@ config MACH_SUN8I_R40
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
+	select CLK
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
 	select SUNXI_DRAM_DW

@@ -252,6 +262,7 @@ config MACH_SUN8I_V3S
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
+	select CLK
 	select SUNXI_GEN_SUN6I
 	select SUNXI_DRAM_DW
 	select SUNXI_DRAM_DW_16BIT

@@ -270,6 +281,7 @@ config MACH_SUN9I
 config MACH_SUN50I
 	bool "sun50i (Allwinner A64)"
 	select ARM64
+	select CLK
 	select DM_I2C
 	select PHY_SUN4I_USB
 	select SUNXI_DE2

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #15 lore raw

PATCH v3 14/58 musb-new: sunxi: Use CLK and RESET support

In reply to Jagan Teki

Now clock and reset drivers are available for respective SoC's so use clk and reset ops on musb driver.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/usb/musb-new/sunxi.c | 82 +++++++++++++++++++++++-------------
 1 file changed, 53 insertions(+), 29 deletions(-)

drivers/usb/musb-new/sunxi.c +53 ~~-29~~

index 9f71b84fd1..440be83f4e 100644
@@ -16,9 +16,11 @@
  * This file is part of the Inventra Controller Driver for Linux.
  */
 #include <common.h>
+#include <clk.h>
 #include <dm.h>
 #include <generic-phy.h>
 #include <phy-sun4i-usb.h>
+#include <reset.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>

@@ -78,16 +80,15 @@
 
 struct sunxi_musb_config {
 	struct musb_hdrc_config *config;
-	u8 rst_bit;
-	u8 clkgate_bit;
 };
 
 struct sunxi_glue {
 	struct musb_host_data mdata;
-	struct sunxi_ccm_reg *ccm;
 	struct sunxi_musb_config *cfg;
 	struct device dev;
 	struct phy phy;
+	struct clk clocks;
+	struct reset_ctl resets;
 };
 #define to_sunxi_glue(d)	container_of(d, struct sunxi_glue, dev)

@@ -291,6 +292,18 @@ static int sunxi_musb_init(struct musb *musb)
 
 	pr_debug("%s():\n", __func__);
 
+	ret = clk_enable(&glue->clocks);
+	if (ret) {
+		dev_err(dev, "failed to enable clock\n");
+		return ret;
+	}
+
+	ret = reset_deassert(&glue->resets);
+	if (ret) {
+		dev_err(dev, "failed to deassert reset\n");
+		return ret;
+	}
+
 	ret = generic_phy_init(&glue->phy);
 	if (ret) {
 		pr_err("failed to init USB PHY\n");

@@ -299,17 +312,6 @@ static int sunxi_musb_init(struct musb *musb)
 
 	musb->isr = sunxi_musb_interrupt;
 
-	setbits_le32(&glue->ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_USB0));
-	if (glue->cfg->clkgate_bit)
-		setbits_le32(&glue->ccm->ahb_gate0,
-			     BIT(glue->cfg->clkgate_bit));
-#ifdef CONFIG_SUNXI_GEN_SUN6I
-	setbits_le32(&glue->ccm->ahb_reset0_cfg, BIT(AHB_GATE_OFFSET_USB0));
-	if (glue->cfg->rst_bit)
-		setbits_le32(&glue->ccm->ahb_reset0_cfg,
-			     BIT(glue->cfg->rst_bit));
-#endif
-
 	USBC_ConfigFIFO_Base();
 	USBC_EnableDpDmPullUp(musb->mregs);
 	USBC_EnableIdPullUp(musb->mregs);

@@ -339,16 +341,17 @@ static int sunxi_musb_exit(struct musb *musb)
 		}
 	}
 
-#ifdef CONFIG_SUNXI_GEN_SUN6I
-	clrbits_le32(&glue->ccm->ahb_reset0_cfg, BIT(AHB_GATE_OFFSET_USB0));
-	if (glue->cfg->rst_bit)
-		clrbits_le32(&glue->ccm->ahb_reset0_cfg,
-			     BIT(glue->cfg->rst_bit));
-#endif
-	clrbits_le32(&glue->ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_USB0));
-	if (glue->cfg->clkgate_bit)
-		clrbits_le32(&glue->ccm->ahb_gate0,
-			     BIT(glue->cfg->clkgate_bit));
+	ret = reset_assert(&glue->resets);
+	if (ret) {
+		dev_err(dev, "failed to deassert reset\n");
+		return ret;
+	}
+
+	ret = clk_disable(&glue->clocks);
+	if (ret) {
+		dev_err(dev, "failed to enable clock\n");
+		return ret;
+	}
 
 	return 0;
 }

@@ -433,6 +436,7 @@ static int musb_usb_probe(struct udevice *dev)
 	struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
 	struct musb_hdrc_platform_data pdata;
 	void *base = dev_read_addr_ptr(dev);
+	int clock_nb, reset_nb;
 	int ret;
 
 	if (!base)

@@ -442,9 +446,31 @@ static int musb_usb_probe(struct udevice *dev)
 	if (!glue->cfg)
 		return -EINVAL;
 
-	glue->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-	if (IS_ERR(glue->ccm))
-		return PTR_ERR(glue->ccm);
+	clock_nb = ofnode_count_phandle_with_args(dev_ofnode(dev), "clocks",
+						  "#clock-cells");
+	if (clock_nb < 0) {
+		dev_err(dev, "failed to get clock phandle(%d)\n", clock_nb);
+		return clock_nb;
+	}
+
+	ret = clk_get_by_index(dev, 0, &glue->clocks);
+	if (ret) {
+		dev_err(dev, "failed to get clock 0\n");
+		clk_free(&glue->clocks);
+	}
+
+	reset_nb = ofnode_count_phandle_with_args(dev_ofnode(dev), "resets",
+						  "#reset-cells");
+	if (reset_nb < 0) {
+		dev_err(dev, "failed to get reset phandle(%d)\n", clock_nb);
+		return reset_nb;
+	}
+
+	ret = reset_get_by_index(dev, 0, &glue->resets);
+	if (ret) {
+		dev_err(dev, "failed to get reset 0\n");
+		reset_free(&glue->resets);
+	}
 
 	ret = generic_phy_get_by_name(dev, "usb", &glue->phy);
 	if (ret) {

@@ -499,8 +525,6 @@ static const struct sunxi_musb_config sun4i_a10_cfg = {
 
 static const struct sunxi_musb_config sun8i_h3_cfg = {
 	.config = &musb_config_h3,
-	.rst_bit = 23,
-	.clkgate_bit = 23,
 };
 
 static const struct udevice_id sunxi_musb_ids[] = {

Signature · 1 line

2.18.0.321.gffc6fa0e3

Maxime Ripard

2018-08-20 11:26 UTC #16 lore raw

PATCH v3 14/58 musb-new: sunxi: Use CLK and RESET support

Quoted 119 lines · Jagan Teki

Now clock and reset drivers are available for respective SoC's so use clk and reset ops on musb driver.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/usb/musb-new/sunxi.c | 82 +++++++++++++++++++++++-------------
 1 file changed, 53 insertions(+), 29 deletions(-)

drivers/usb/musb-new/sunxi.c +28 ~~-24~~

index 9f71b84fd1..440be83f4e 100644
@@ -16,9 +16,11 @@
  * This file is part of the Inventra Controller Driver for Linux.
  */
 #include <common.h>
+#include <clk.h>
 #include <dm.h>
 #include <generic-phy.h>
 #include <phy-sun4i-usb.h>
+#include <reset.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>

@@ -78,16 +80,15 @@
 
 struct sunxi_musb_config {
 	struct musb_hdrc_config *config;
-	u8 rst_bit;
-	u8 clkgate_bit;
 };
 
 struct sunxi_glue {
 	struct musb_host_data mdata;
-	struct sunxi_ccm_reg *ccm;
 	struct sunxi_musb_config *cfg;
 	struct device dev;
 	struct phy phy;
+	struct clk clocks;
+	struct reset_ctl resets;
 };
 #define to_sunxi_glue(d)	container_of(d, struct sunxi_glue, dev)

@@ -291,6 +292,18 @@ static int sunxi_musb_init(struct musb *musb)
 
 	pr_debug("%s():\n", __func__);
 
+	ret = clk_enable(&glue->clocks);
+	if (ret) {
+		dev_err(dev, "failed to enable clock\n");
+		return ret;
+	}
+
+	ret = reset_deassert(&glue->resets);
+	if (ret) {
+		dev_err(dev, "failed to deassert reset\n");
+		return ret;
+	}
+
 	ret = generic_phy_init(&glue->phy);
 	if (ret) {
 		pr_err("failed to init USB PHY\n");

@@ -299,17 +312,6 @@ static int sunxi_musb_init(struct musb *musb)
 
 	musb->isr = sunxi_musb_interrupt;
 
-	setbits_le32(&glue->ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_USB0));
-	if (glue->cfg->clkgate_bit)
-		setbits_le32(&glue->ccm->ahb_gate0,
-			     BIT(glue->cfg->clkgate_bit));
-#ifdef CONFIG_SUNXI_GEN_SUN6I
-	setbits_le32(&glue->ccm->ahb_reset0_cfg, BIT(AHB_GATE_OFFSET_USB0));
-	if (glue->cfg->rst_bit)
-		setbits_le32(&glue->ccm->ahb_reset0_cfg,
-			     BIT(glue->cfg->rst_bit));
-#endif
-
 	USBC_ConfigFIFO_Base();
 	USBC_EnableDpDmPullUp(musb->mregs);
 	USBC_EnableIdPullUp(musb->mregs);

@@ -339,16 +341,17 @@ static int sunxi_musb_exit(struct musb *musb)
 		}
 	}
 
-#ifdef CONFIG_SUNXI_GEN_SUN6I
-	clrbits_le32(&glue->ccm->ahb_reset0_cfg, BIT(AHB_GATE_OFFSET_USB0));
-	if (glue->cfg->rst_bit)
-		clrbits_le32(&glue->ccm->ahb_reset0_cfg,
-			     BIT(glue->cfg->rst_bit));
-#endif
-	clrbits_le32(&glue->ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_USB0));
-	if (glue->cfg->clkgate_bit)
-		clrbits_le32(&glue->ccm->ahb_gate0,
-			     BIT(glue->cfg->clkgate_bit));
+	ret = reset_assert(&glue->resets);
+	if (ret) {
+		dev_err(dev, "failed to deassert reset\n");
+		return ret;
+	}
+
+	ret = clk_disable(&glue->clocks);
+	if (ret) {
+		dev_err(dev, "failed to enable clock\n");
+		return ret;
+	}
 
 	return 0;
 }

@@ -433,6 +436,7 @@ static int musb_usb_probe(struct udevice *dev)
 	struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
 	struct musb_hdrc_platform_data pdata;
 	void *base = dev_read_addr_ptr(dev);
+	int clock_nb, reset_nb;
 	int ret;
 
 	if (!base)

@@ -442,9 +446,31 @@ static int musb_usb_probe(struct udevice *dev)
 	if (!glue->cfg)
 		return -EINVAL;

drivers/usb/musb-new/sunxi.c static int musb_usb_probe(struct udevice *dev) · line 454

Quoted 10 lines

drivers/usb/musb-new/sunxi.c +6 -3

 
-	glue->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-	if (IS_ERR(glue->ccm))
-		return PTR_ERR(glue->ccm);
+	clock_nb = ofnode_count_phandle_with_args(dev_ofnode(dev), "clocks",
+						  "#clock-cells");
+	if (clock_nb < 0) {
+		dev_err(dev, "failed to get clock phandle(%d)\n", clock_nb);
+		return clock_nb;
+	}

What are you using that variable for?

drivers/usb/musb-new/sunxi.c static int musb_usb_probe(struct udevice *dev) · line 467

Quoted 12 lines

drivers/usb/musb-new/sunxi.c +12 -0

+	ret = clk_get_by_index(dev, 0, &glue->clocks);
+	if (ret) {
+		dev_err(dev, "failed to get clock 0\n");
+		clk_free(&glue->clocks);
+	}
+
+	reset_nb = ofnode_count_phandle_with_args(dev_ofnode(dev), "resets",
+						  "#reset-cells");
+	if (reset_nb < 0) {
+		dev_err(dev, "failed to get reset phandle(%d)\n", clock_nb);
+		return reset_nb;
+	}

Ditto.

Maxime

Signature · 10 lines

Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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Jagan Teki

author

2018-08-19 13:56 UTC #17 lore raw

PATCH v3 15/58 phy: sun4i-usb: Use CLK and RESET support

In reply to Jagan Teki

Now clock and reset drivers are available for respective SoC's so use clk and reset ops on phy driver.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/phy/allwinner/phy-sun4i-usb.c | 77 ++++++++++++++++++++-------
 1 file changed, 57 insertions(+), 20 deletions(-)

drivers/phy/allwinner/phy-sun4i-usb.c +57 ~~-20~~

index a7d7e3f044..f206fa3f5d 100644
@@ -11,10 +11,12 @@
  */
 
 #include <common.h>
+#include <clk.h>
 #include <dm.h>
 #include <dm/device.h>
 #include <generic-phy.h>
 #include <phy-sun4i-usb.h>
+#include <reset.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>

@@ -80,6 +82,7 @@ struct sun4i_usb_phy_cfg {
 	enum sun4i_usb_phy_type type;
 	u32 disc_thresh;
 	u8 phyctl_offset;
+	bool dedicated_clocks;
 	bool enable_pmu_unk1;
 	bool phy0_dual_route;
 };

@@ -88,30 +91,21 @@ struct sun4i_usb_phy_info {
 	const char *gpio_vbus;
 	const char *gpio_vbus_det;
 	const char *gpio_id_det;
-	int rst_mask;
 } phy_info[] = {
 	{
 		.gpio_vbus = CONFIG_USB0_VBUS_PIN,
 		.gpio_vbus_det = CONFIG_USB0_VBUS_DET,
 		.gpio_id_det = CONFIG_USB0_ID_DET,
-		.rst_mask = (CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK),
 	},
 	{
 		.gpio_vbus = CONFIG_USB1_VBUS_PIN,
 		.gpio_vbus_det = NULL,
 		.gpio_id_det = NULL,
-		.rst_mask = (CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK),
 	},
 	{
 		.gpio_vbus = CONFIG_USB2_VBUS_PIN,
 		.gpio_vbus_det = NULL,
 		.gpio_id_det = NULL,
-#ifdef CONFIG_MACH_SUN8I_A83T
-		.rst_mask = (CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK |
-			     CCM_USB_CTRL_12M_CLK),
-#else
-		.rst_mask = (CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK),
-#endif
 	},
 	{
 		.gpio_vbus = CONFIG_USB3_VBUS_PIN,

@@ -126,13 +120,13 @@ struct sun4i_usb_phy_plat {
 	int gpio_vbus;
 	int gpio_vbus_det;
 	int gpio_id_det;
-	int rst_mask;
+	struct clk clocks;
+	struct reset_ctl resets;
 	int id;
 };
 
 struct sun4i_usb_phy_data {
 	void __iomem *base;
-	struct sunxi_ccm_reg *ccm;
 	const struct sun4i_usb_phy_cfg *cfg;
 	struct sun4i_usb_phy_plat *usb_phy;
 };

@@ -266,8 +260,19 @@ static int sun4i_usb_phy_init(struct phy *phy)
 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 	u32 val;
+	int ret;
 
-	setbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask);
+	ret = clk_enable(&usb_phy->clocks);
+	if (ret) {
+		dev_err(dev, "failed to enable usb_%ldphy clock\n", phy->id);
+		return ret;
+	}
+
+	ret = reset_deassert(&usb_phy->resets);
+	if (ret) {
+		dev_err(dev, "failed to deassert usb_%ldreset reset\n", phy->id);
+		return ret;
+	}
 
 	if (data->cfg->type == sun8i_a83t_phy) {
 		if (phy->id == 0) {

@@ -308,6 +313,7 @@ static int sun4i_usb_phy_exit(struct phy *phy)
 {
 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
+	int ret;
 
 	if (phy->id == 0) {
 		if (data->cfg->type == sun8i_a83t_phy) {

@@ -320,7 +326,17 @@ static int sun4i_usb_phy_exit(struct phy *phy)
 
 	sun4i_usb_phy_passby(phy, false);
 
-	clrbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask);
+	ret = clk_disable(&usb_phy->clocks);
+	if (ret) {
+		dev_err(dev, "failed to disable usb_%ldphy clock\n", phy->id);
+		return ret;
+	}
+
+	ret = reset_assert(&usb_phy->resets);
+	if (ret) {
+		dev_err(dev, "failed to assert usb_%ldreset reset\n", phy->id);
+		return ret;
+	}
 
 	return 0;
 }

@@ -407,10 +423,6 @@ static int sun4i_usb_phy_probe(struct udevice *dev)
 	if (IS_ERR(data->base))
 		return PTR_ERR(data->base);
 
-	data->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-	if (IS_ERR(data->ccm))
-		return PTR_ERR(data->ccm);
-
 	data->usb_phy = plat;
 	for (i = 0; i < data->cfg->num_phys; i++) {
 		struct sun4i_usb_phy_plat *phy = &plat[i];

@@ -448,6 +460,24 @@ static int sun4i_usb_phy_probe(struct udevice *dev)
 			sunxi_gpio_set_pull(phy->gpio_id_det, SUNXI_GPIO_PULL_UP);
 		}
 
+		if (data->cfg->dedicated_clocks)
+			snprintf(name, sizeof(name), "usb%d_phy", i);
+		else
+			strlcpy(name, "usb_phy", sizeof(name));
+
+		ret = clk_get_by_name(dev, name, &phy->clocks);
+		if (ret) {
+			dev_err(dev, "failed to get usb%d_phy clock phandle\n", i);
+			return ret;
+		}
+
+		snprintf(name, sizeof(name), "usb%d_reset", i);
+		ret = reset_get_by_name(dev, name, &phy->resets);
+		if (ret) {
+			dev_err(dev, "failed to get usb%d_reset reset phandle\n", i);
+			return ret;
+		}
+
 		if (i || data->cfg->phy0_dual_route) {
 			snprintf(name, sizeof(name), "pmu%d", i);
 			phy->pmu = (void __iomem *)devfdt_get_addr_name(dev, name);

@@ -456,9 +486,6 @@ static int sun4i_usb_phy_probe(struct udevice *dev)
 		}
 
 		phy->id = i;
-		phy->rst_mask = info->rst_mask;
-		if ((data->cfg->type == sun8i_h3_phy) && (phy->id == 3))
-			phy->rst_mask = (BIT(3) | BIT(11));
 	};
 
 	debug("Allwinner Sun4I USB PHY driver loaded\n");

@@ -470,6 +497,7 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
 	.type = sun4i_a10_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A10,
+	.dedicated_clocks = false,
 	.enable_pmu_unk1 = false,
 };

@@ -478,6 +506,7 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
 	.type = sun4i_a10_phy,
 	.disc_thresh = 2,
 	.phyctl_offset = REG_PHYCTL_A10,
+	.dedicated_clocks = false,
 	.enable_pmu_unk1 = false,
 };

@@ -486,6 +515,7 @@ static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
 	.type = sun6i_a31_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A10,
+	.dedicated_clocks = true,
 	.enable_pmu_unk1 = false,
 };

@@ -494,6 +524,7 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
 	.type = sun4i_a10_phy,
 	.disc_thresh = 2,
 	.phyctl_offset = REG_PHYCTL_A10,
+	.dedicated_clocks = false,
 	.enable_pmu_unk1 = false,
 };

@@ -502,6 +533,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
 	.type = sun4i_a10_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A10,
+	.dedicated_clocks = true,
 	.enable_pmu_unk1 = false,
 };

@@ -510,6 +542,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
 	.type = sun8i_a33_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
 	.enable_pmu_unk1 = false,
 };

@@ -517,6 +550,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
 	.num_phys = 3,
 	.type = sun8i_a83t_phy,
 	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
 };
 
 static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {

@@ -524,6 +558,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
 	.type = sun8i_h3_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
 	.enable_pmu_unk1 = true,
 	.phy0_dual_route = true,
 };

@@ -533,6 +568,7 @@ static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
 	.type = sun8i_v3s_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
 	.enable_pmu_unk1 = true,
 	.phy0_dual_route = true,
 };

@@ -542,6 +578,7 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 	.type = sun50i_a64_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
 	.enable_pmu_unk1 = true,
 	.phy0_dual_route = true,
 };

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #18 lore raw

PATCH v3 16/58 sunxi: usb: Switch to Generic host controllers

In reply to Jagan Teki

Once of key blocker for using USB Generic host controller drivers in Allwinner are CLK and RESET drivers, now these available for USB usage. So switch to use EHCI and OHCI Generic controllers.

Enabling USB is wisely a board choise, so Enable USB_OHCI_HCD where it already have USB_EHCI_HCD

Signed-off-by Jagan Teki <[email protected]>

---
 configs/A10-OLinuXino-Lime_defconfig          | 1 +
 configs/A10s-OLinuXino-M_defconfig            | 1 +
 configs/A13-OLinuXinoM_defconfig              | 1 +
 configs/A13-OLinuXino_defconfig               | 1 +
 configs/A20-OLinuXino-Lime2-eMMC_defconfig    | 1 +
 configs/A20-OLinuXino-Lime2_defconfig         | 1 +
 configs/A20-OLinuXino-Lime_defconfig          | 1 +
 configs/A20-Olimex-SOM204-EVB_defconfig       | 2 ++
 configs/Auxtek-T003_defconfig                 | 1 +
 configs/Auxtek-T004_defconfig                 | 1 +
 configs/Bananapi_defconfig                    | 1 +
 configs/Bananapi_m2m_defconfig                | 1 +
 configs/Bananapro_defconfig                   | 1 +
 configs/CHIP_defconfig                        | 1 +
 configs/CHIP_pro_defconfig                    | 1 +
 configs/CSQ_CS908_defconfig                   | 1 +
 configs/Colombus_defconfig                    | 1 +
 configs/Cubieboard2_defconfig                 | 1 +
 configs/Cubieboard_defconfig                  | 1 +
 configs/Cubietruck_plus_defconfig             | 1 +
 configs/Hummingbird_A31_defconfig             | 1 +
 configs/Itead_Ibox_A20_defconfig              | 1 +
 configs/Linksprite_pcDuino3_Nano_defconfig    | 1 +
 configs/Linksprite_pcDuino3_defconfig         | 1 +
 configs/Linksprite_pcDuino_defconfig          | 1 +
 configs/MK808C_defconfig                      | 1 +
 configs/Marsboard_A10_defconfig               | 1 +
 configs/Mele_A1000G_quad_defconfig            | 1 +
 configs/Mele_A1000_defconfig                  | 1 +
 configs/Mele_I7_defconfig                     | 1 +
 configs/Mele_M3_defconfig                     | 1 +
 configs/Mele_M5_defconfig                     | 1 +
 configs/Mele_M9_defconfig                     | 1 +
 configs/Mini-X_defconfig                      | 1 +
 configs/Orangepi_defconfig                    | 1 +
 configs/Orangepi_mini_defconfig               | 1 +
 configs/Sinlinx_SinA31s_defconfig             | 1 +
 configs/Sinlinx_SinA33_defconfig              | 1 +
 configs/Sinovoip_BPI_M2_Plus_defconfig        | 1 +
 configs/Sinovoip_BPI_M2_defconfig             | 1 +
 configs/Sinovoip_BPI_M3_defconfig             | 1 +
 configs/Wexler_TAB7200_defconfig              | 1 +
 configs/Wobo_i5_defconfig                     | 1 +
 configs/a64-olinuxino_defconfig               | 1 +
 configs/ba10_tv_box_defconfig                 | 1 +
 configs/bananapi_m1_plus_defconfig            | 1 +
 configs/bananapi_m64_defconfig                | 1 +
 configs/ga10h_v1_1_defconfig                  | 1 +
 configs/h8_homlet_v2_defconfig                | 1 +
 configs/i12-tvbox_defconfig                   | 1 +
 configs/icnova-a20-swac_defconfig             | 1 +
 configs/inet1_defconfig                       | 1 +
 configs/inet_q972_defconfig                   | 1 +
 configs/jesurun_q5_defconfig                  | 1 +
 configs/libretech_all_h3_cc_h2_plus_defconfig | 1 +
 configs/libretech_all_h3_cc_h3_defconfig      | 1 +
 configs/libretech_all_h3_cc_h5_defconfig      | 1 +
 configs/mixtile_loftq_defconfig               | 1 +
 configs/mk802_a10s_defconfig                  | 1 +
 configs/mk802_defconfig                       | 1 +
 configs/mk802ii_defconfig                     | 1 +
 configs/nanopi_a64_defconfig                  | 1 +
 configs/nanopi_m1_defconfig                   | 1 +
 configs/nanopi_m1_plus_defconfig              | 1 +
 configs/nanopi_neo2_defconfig                 | 1 +
 configs/nanopi_neo_air_defconfig              | 1 +
 configs/nanopi_neo_defconfig                  | 1 +
 configs/nanopi_neo_plus2_defconfig            | 1 +
 configs/orangepi_2_defconfig                  | 1 +
 configs/orangepi_lite_defconfig               | 1 +
 configs/orangepi_one_defconfig                | 1 +
 configs/orangepi_pc2_defconfig                | 1 +
 configs/orangepi_pc_defconfig                 | 1 +
 configs/orangepi_pc_plus_defconfig            | 1 +
 configs/orangepi_plus2e_defconfig             | 1 +
 configs/orangepi_plus_defconfig               | 1 +
 configs/orangepi_prime_defconfig              | 1 +
 configs/orangepi_r1_defconfig                 | 1 +
 configs/orangepi_win_defconfig                | 1 +
 configs/orangepi_zero_defconfig               | 1 +
 configs/orangepi_zero_plus2_defconfig         | 1 +
 configs/orangepi_zero_plus_defconfig          | 1 +
 configs/parrot_r16_defconfig                  | 1 +
 configs/pine64_plus_defconfig                 | 1 +
 configs/r7-tv-dongle_defconfig                | 1 +
 configs/sopine_baseboard_defconfig            | 1 +
 configs/sun8i_a23_evb_defconfig               | 1 +
 configs/sunxi_Gemei_G9_defconfig              | 1 +
 configs/tbs_a711_defconfig                    | 1 +
 drivers/usb/host/Kconfig                      | 2 ++
 include/configs/sun4i.h                       | 4 ----
 include/configs/sun50i.h                      | 5 -----
 include/configs/sun5i.h                       | 4 ----
 include/configs/sun6i.h                       | 4 ----
 include/configs/sun7i.h                       | 4 ----
 include/configs/sun8i.h                       | 4 ----
 include/configs/sunxi-common.h                | 1 -
 97 files changed, 92 insertions(+), 26 deletions(-)

configs/A10-OLinuXino-Lime_defconfig +1 -0

index feb1173c0b..e8fecbe15f 100644
@@ -20,5 +20,6 @@ CONFIG_SUN4I_EMAC=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/A10s-OLinuXino-M_defconfig +1 -0

index 9498a6d752..bee913cb0b 100644
@@ -16,5 +16,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SUN4I_EMAC=y
 CONFIG_AXP152_POWER=y
 CONFIG_CONS_INDEX=2
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/A13-OLinuXinoM_defconfig +1 -0

index ed507cdf0b..dd5c25ca9f 100644
@@ -18,5 +18,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino-micro"
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUNXI_NO_PMIC=y
 CONFIG_CONS_INDEX=2
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/A13-OLinuXino_defconfig +1 -0

index b8ec1e54db..04682dcac4 100644
@@ -25,6 +25,7 @@ CONFIG_DFU_RAM=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_CONS_INDEX=2
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/A20-OLinuXino-Lime2-eMMC_defconfig +1 -0

index 5657fc2594..2851a461e8 100644
@@ -27,6 +27,7 @@ CONFIG_SUN7I_GMAC=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/A20-OLinuXino-Lime2_defconfig +1 -0

index 134d1d3fef..99987a8683 100644
@@ -26,6 +26,7 @@ CONFIG_SUN7I_GMAC=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/A20-OLinuXino-Lime_defconfig +1 -0

index b7c13a6932..1b59174120 100644
@@ -19,5 +19,6 @@ CONFIG_SUN7I_GMAC=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/A20-Olimex-SOM204-EVB_defconfig +2 -0

index cfb7ffa556..0537378ba1 100644
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y

@@ -27,6 +28,7 @@ CONFIG_SUN7I_GMAC=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Auxtek-T003_defconfig +1 -0

index ce4806cf5e..a2bf5037ed 100644
@@ -14,5 +14,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_AXP152_POWER=y
 CONFIG_CONS_INDEX=2
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Auxtek-T004_defconfig +1 -0

index 5faf45c3d7..4c1117e4bb 100644
@@ -12,5 +12,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_AXP152_POWER=y
 CONFIG_CONS_INDEX=2
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Bananapi_defconfig +1 -0

index 7a9b5fe0e5..53752b2e12 100644
@@ -19,5 +19,6 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Bananapi_m2m_defconfig +1 -0

index 2316437c94..a21796fa67 100644
@@ -14,6 +14,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-bananapi-m2m"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_FUNCTION_MASS_STORAGE=y

configs/Bananapro_defconfig +1 -0

index 5a8ded0493..ad4ce1f662 100644
@@ -22,5 +22,6 @@ CONFIG_RGMII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_AXP_ALDO4_VOLT=2500
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/CHIP_defconfig +1 -0

index c122944881..2dfa5237bc 100644
@@ -16,6 +16,7 @@ CONFIG_DFU_RAM=y
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_AXP_ALDO4_VOLT=3300
 CONFIG_CONS_INDEX=2
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/CHIP_pro_defconfig +1 -0

index 5d63fadef5..1333877957 100644
@@ -20,6 +20,7 @@ CONFIG_SYS_NAND_OOBSIZE=0x100
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_AXP_ALDO4_VOLT=3300
 CONFIG_CONS_INDEX=2
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/CSQ_CS908_defconfig +1 -0

index b103e7e00d..7612cc8989 100644
@@ -14,6 +14,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Colombus_defconfig +1 -0

index c85e47cb11..6310420c29 100644
@@ -24,5 +24,6 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_AXP_ALDO1_VOLT=3300
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Cubieboard2_defconfig +1 -0

index 418da63ba8..6e883155b9 100644
@@ -16,5 +16,6 @@ CONFIG_SCSI_AHCI=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Cubieboard_defconfig +1 -0

index 27223d201e..dbeda7370d 100644
@@ -15,5 +15,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SCSI_AHCI=y
 CONFIG_SUN4I_EMAC=y
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Cubietruck_plus_defconfig +1 -0

index d76bc6748b..6a0e4c5836 100644
@@ -22,6 +22,7 @@ CONFIG_CONSOLE_MUX=y
 CONFIG_AXP_DLDO3_VOLT=2500
 CONFIG_AXP_DLDO4_VOLT=3300
 CONFIG_AXP_FLDO1_VOLT=1200
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Hummingbird_A31_defconfig +1 -0

index 24126fde28..81eb59ebd1 100644
@@ -16,5 +16,6 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_AXP_ALDO1_VOLT=3300
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Itead_Ibox_A20_defconfig +1 -0

index dfef071476..93c89890a7 100644
@@ -16,5 +16,6 @@ CONFIG_SCSI_AHCI=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Linksprite_pcDuino3_Nano_defconfig +1 -0

index 2df6761455..8487263fd8 100644
@@ -19,5 +19,6 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Linksprite_pcDuino3_defconfig +1 -0

index d7e9c26cbf..7a1fc26434 100644
@@ -18,5 +18,6 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_SCSI=y
 CONFIG_DM_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Linksprite_pcDuino_defconfig +1 -0

index 500f885599..b18b02307f 100644
@@ -11,5 +11,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN4I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/MK808C_defconfig +1 -0

index 62768b8656..c3d914efe3 100644
@@ -9,5 +9,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Marsboard_A10_defconfig +1 -0

index 55c27b8435..37bdeb0c37 100644
@@ -12,5 +12,6 @@ CONFIG_SCSI_AHCI=y
 CONFIG_SUN4I_EMAC=y
 CONFIG_SUNXI_NO_PMIC=y
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Mele_A1000G_quad_defconfig +1 -0

index e084454293..b3a05f2c0d 100644
@@ -17,6 +17,7 @@ CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_AXP_DLDO4_VOLT=3300
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Mele_A1000_defconfig +1 -0

index 367f2aaf7a..021753c221 100644
@@ -15,5 +15,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SCSI_AHCI=y
 CONFIG_SUN4I_EMAC=y
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Mele_I7_defconfig +1 -0

index 4fa61d311f..c9398676e2 100644
@@ -16,5 +16,6 @@ CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_AXP_DLDO4_VOLT=3300
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Mele_M3_defconfig +1 -0

index 9f48bd91e0..22497aaeb4 100644
@@ -15,5 +15,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Mele_M5_defconfig +1 -0

index 6b198be6f6..37e90e1eaf 100644
@@ -17,5 +17,6 @@ CONFIG_SCSI_AHCI=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Mele_M9_defconfig +1 -0

index af89c50ee1..94190499bf 100644
@@ -16,5 +16,6 @@ CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_AXP_DLDO4_VOLT=3300
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Mini-X_defconfig +1 -0

index e32935e132..dfaa649e95 100644
@@ -10,6 +10,7 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Orangepi_defconfig +1 -0

index 88e55495d5..c347e32927 100644
@@ -21,5 +21,6 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Orangepi_mini_defconfig +1 -0

index 46f27be254..7eeae25010 100644
@@ -23,5 +23,6 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Sinlinx_SinA31s_defconfig +1 -0

index 9744aef096..0aa02d687c 100644
@@ -17,5 +17,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sina31s"
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Sinlinx_SinA33_defconfig +1 -0

index 394534b8b5..7f5aaab5fb 100644
@@ -19,6 +19,7 @@ CONFIG_CMD_DFU=y
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_DFU_RAM=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Sinovoip_BPI_M2_Plus_defconfig +1 -0

index a325e9f806..b01aa560d2 100644
@@ -13,6 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-bananapi-m2-plus"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Sinovoip_BPI_M2_defconfig +1 -0

index 65d81a5284..fa42670355 100644
@@ -16,5 +16,6 @@ CONFIG_SUN7I_GMAC=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_ALDO2_VOLT=1800
 CONFIG_AXP_DLDO1_VOLT=3000
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Sinovoip_BPI_M3_defconfig +1 -0

index 479dd05dfb..91a3621d77 100644
@@ -23,6 +23,7 @@ CONFIG_CONSOLE_MUX=y
 CONFIG_AXP_DCDC5_VOLT=1200
 CONFIG_AXP_DLDO3_VOLT=2500
 CONFIG_AXP_SW_ON=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Wexler_TAB7200_defconfig +1 -0

index 9a431ee4cd..d031b05f1a 100644
@@ -17,6 +17,7 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Wobo_i5_defconfig +1 -0

index 88ccfd406e..8ae00abcff 100644
@@ -14,5 +14,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_AXP_ALDO4_VOLT=3300
 CONFIG_CONS_INDEX=2
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/a64-olinuxino_defconfig +1 -0

index b32df990a0..54f6a98472 100644
@@ -10,5 +10,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-olinuxino"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/ba10_tv_box_defconfig +1 -0

index 88199c8e78..b6776e3cb9 100644
@@ -14,6 +14,7 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN4I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/bananapi_m1_plus_defconfig +1 -0

index 539ed73495..dde7b17229 100644
@@ -19,4 +19,5 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y

configs/bananapi_m64_defconfig +1 -0

index 40c1c18aca..df0bbb4db5 100644
@@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-bananapi-m64"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/ga10h_v1_1_defconfig +1 -0

index 02cc9677aa..4196ad6863 100644
@@ -22,6 +22,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ga10h-v1.1"
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_CONS_INDEX=5
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/h8_homlet_v2_defconfig +1 -0

index 80bdb20e8a..380949b1c2 100644
@@ -15,6 +15,7 @@ CONFIG_CONSOLE_MUX=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_AXP_DLDO4_VOLT=3300
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/i12-tvbox_defconfig +1 -0

index a3c4b0e76c..983627afbb 100644
@@ -13,5 +13,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/icnova-a20-swac_defconfig +1 -0

index 8fca6e81ed..6d6792553e 100644
@@ -20,5 +20,6 @@ CONFIG_CMD_UNZIP=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/inet1_defconfig +1 -0

index 100d075960..46f8f3c095 100644
@@ -18,6 +18,7 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/inet_q972_defconfig +1 -0

index b928622813..9a22499b23 100644
@@ -19,6 +19,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-inet-q972"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/jesurun_q5_defconfig +1 -0

index 00bb745be2..c0c46a1d4e 100644
@@ -13,6 +13,7 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN4I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/libretech_all_h3_cc_h2_plus_defconfig +1 -0

index 071be93697..ccf0b73ffd 100644
@@ -12,5 +12,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-libretech-all-h3-cc"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/libretech_all_h3_cc_h3_defconfig +1 -0

index c20ad9f3a2..159b00ea91 100644
@@ -12,5 +12,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-libretech-all-h3-cc"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/libretech_all_h3_cc_h5_defconfig +1 -0

index 5db8dfcd4f..003e2dc0f3 100644
@@ -12,5 +12,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-libretech-all-h3-cc"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/mixtile_loftq_defconfig +1 -0

index 79d984ba7b..59321b108d 100644
@@ -16,5 +16,6 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_RGMII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_AXP_ALDO1_VOLT=3300
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/mk802_a10s_defconfig +1 -0

index 5129b49506..233925ee6e 100644
@@ -13,5 +13,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_AXP152_POWER=y
 CONFIG_CONS_INDEX=2
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/mk802_defconfig +1 -0

index 81d121fb84..454339a7cf 100644
@@ -9,5 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUNXI_NO_PMIC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/mk802ii_defconfig +1 -0

index 84ae234fdc..2ce58ca64d 100644
@@ -8,5 +8,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/nanopi_a64_defconfig +1 -0

index 0a04911c81..091f395db3 100644
@@ -9,5 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-nanopi-a64"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/nanopi_m1_defconfig +1 -0

index e0ae3c7c60..8440bd28c9 100644
@@ -10,5 +10,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1"
 # CONFIG_CMD_FLASH is not set
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/nanopi_m1_plus_defconfig +1 -0

index ee22364760..3918b7e21e 100644
@@ -12,5 +12,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1-plus"
 # CONFIG_CMD_FLASH is not set
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/nanopi_neo2_defconfig +1 -0

index 35058186f5..100f144ed0 100644
@@ -10,5 +10,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo2"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/nanopi_neo_air_defconfig +1 -0

index f953b71f03..c2659627bc 100644
@@ -12,5 +12,6 @@ CONFIG_CONSOLE_MUX=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/nanopi_neo_defconfig +1 -0

index 66919e5a2b..44cd1036dd 100644
@@ -13,5 +13,6 @@ CONFIG_CONSOLE_MUX=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/nanopi_neo_plus2_defconfig +1 -0

index 70798a8e9f..bcaf2e5068 100644
@@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo-plus2"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y

configs/orangepi_2_defconfig +1 -0

index 577a32255b..e88615c8c6 100644
@@ -15,5 +15,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
 CONFIG_SY8106A_POWER=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_lite_defconfig +1 -0

index f3fd864a6d..21b05daf45 100644
@@ -10,5 +10,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-lite"
 # CONFIG_CMD_FLASH is not set
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_one_defconfig +1 -0

index 23f4973e5b..4c7f6027ac 100644
@@ -11,5 +11,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_pc2_defconfig +1 -0

index ca1e586e89..3dabfeb300 100644
@@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-pc2"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_pc_defconfig +1 -0

index 134db79e72..083e0eba9b 100644
@@ -13,5 +13,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
 CONFIG_SY8106A_POWER=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_pc_plus_defconfig +1 -0

index 01c1cd7736..4068afb20e 100644
@@ -14,5 +14,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
 CONFIG_SY8106A_POWER=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_plus2e_defconfig +1 -0

index a6e61a5065..f049d3f8b9 100644
@@ -15,5 +15,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
 CONFIG_SY8106A_POWER=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_plus_defconfig +1 -0

index 8e32b0af32..4c1d609760 100644
@@ -17,5 +17,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
 CONFIG_SY8106A_POWER=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_prime_defconfig +1 -0

index 6161863258..b20835b0d7 100644
@@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-prime"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_r1_defconfig +1 -0

index 8e6ee7b2db..289f8d7650 100644
@@ -12,5 +12,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-r1"
 CONFIG_CONSOLE_MUX=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_win_defconfig +1 -0

index d7211b5823..e14faacfaf 100644
@@ -10,5 +10,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-orangepi-win"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_zero_defconfig +1 -0

index 6afd4a3bfa..6f2a64002f 100644
@@ -12,5 +12,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-zero"
 CONFIG_CONSOLE_MUX=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_zero_plus2_defconfig +1 -0

index fdb6bb4ed9..95c3d29b85 100644
@@ -12,5 +12,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-zero-plus2"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_zero_plus_defconfig +1 -0

index fc656ce733..cd61b17cd4 100644
@@ -12,5 +12,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-zero-plus"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/parrot_r16_defconfig +1 -0

index 553a8d6572..936f08185f 100644
@@ -17,6 +17,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-parrot"
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_CONS_INDEX=5
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/pine64_plus_defconfig +1 -0

index 21ce06f370..c632d24456 100644
@@ -12,5 +12,6 @@ CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus"
 CONFIG_PHY_REALTEK=y
 CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/r7-tv-dongle_defconfig +1 -0

index 9a66ee90f9..eaf7f4816a 100644
@@ -12,5 +12,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_AXP152_POWER=y
 CONFIG_CONS_INDEX=2
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/sopine_baseboard_defconfig +1 -0

index c79c111b5d..0da899c155 100644
@@ -16,5 +16,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-sopine-baseboard"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/sun8i_a23_evb_defconfig +1 -0

index 4cb2798ce7..c32f024cd2 100644
@@ -13,5 +13,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-evb"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_CONS_INDEX=5
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/sunxi_Gemei_G9_defconfig +1 -0

index d88dd4ebad..c42074c0d8 100644
@@ -15,5 +15,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/tbs_a711_defconfig +1 -0

index 5d58f5ceb4..d7d99c4dba 100644
@@ -18,6 +18,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-tbs-a711"
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_AXP_DCDC5_VOLT=1200
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_FUNCTION_MASS_STORAGE=y

drivers/usb/host/Kconfig +2 -0

index b4dd005651..60a152704a 100644
@@ -191,6 +191,7 @@ config USB_EHCI_GENERIC
 	bool "Support for generic EHCI USB controller"
 	depends on OF_CONTROL
 	depends on DM_USB
+	default ARCH_SUNXI
 	default n
 	---help---
 	  Enables support for generic EHCI controller.

@@ -221,6 +222,7 @@ config USB_OHCI_GENERIC
 	bool "Support for generic OHCI USB controller"
 	depends on OF_CONTROL
 	depends on DM_USB
+	default ARCH_SUNXI
 	select USB_HOST
 	---help---
 	  Enables support for generic OHCI controller.

include/configs/sun4i.h +0 -4

index af079a71ee..6033760583 100644
@@ -11,10 +11,6 @@
  * A10 specific configuration
  */
 
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_SUNXI
-#endif
-
 /*
  * Include common sunxi configuration where most the settings are
  */

include/configs/sun50i.h +0 -5

index 2d73c75b8c..e050a5299f 100644
@@ -10,11 +10,6 @@
  * A64 specific configuration
  */
 
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_SUNXI
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#endif
-
 #ifndef CONFIG_MACH_SUN50I_H6
 #define GICD_BASE		0x1c81000
 #define GICC_BASE		0x1c82000

include/configs/sun5i.h +0 -4

index c3692caa73..ee42af80d4 100644
@@ -11,10 +11,6 @@
  * High Level Configuration Options
  */
 
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_SUNXI
-#endif
-
 /*
  * Include common sunxi configuration where most the settings are
  */

include/configs/sun6i.h +0 -4

index 1523684fad..1e490daac1 100644
@@ -14,10 +14,6 @@
  * A31 specific configuration
  */
 
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_SUNXI
-#endif
-
 #define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
 #define CONFIG_ARMV7_SECURE_MAX_SIZE    (64 * 1024) /* 64 KB */

include/configs/sun7i.h +0 -4

index bb8f217b25..d2fd586672 100644
@@ -12,10 +12,6 @@
  * A20 specific configuration
  */
 
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_SUNXI
-#endif
-
 #define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
 #define CONFIG_ARMV7_SECURE_MAX_SIZE	(64 * 1024) /* 64 KB */

include/configs/sun8i.h +0 -4

index 7dc8693b76..9b4675e4c3 100644
@@ -12,10 +12,6 @@
  * A23 specific configuration
  */
 
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_SUNXI
-#endif
-
 /*
  * Include common sunxi configuration where most the settings are
  */

include/configs/sunxi-common.h +0 -1

index 93690481a1..f1578d3754 100644
@@ -302,7 +302,6 @@ extern int soft_i2c_gpio_scl;
 
 #ifdef CONFIG_USB_EHCI_HCD
 #define CONFIG_USB_OHCI_NEW
-#define CONFIG_USB_OHCI_SUNXI
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
 #endif

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #19 lore raw

PATCH v3 17/58 usb: host: Drop [e-o]hci-sunxi drivers

In reply to Jagan Teki

Now Allwinner platform is all set to use Generic USB controller drivers, so remove the legacy sunxi drivers.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/usb/host/Makefile     |   2 -
 drivers/usb/host/ehci-sunxi.c | 204 -----------------------------
 drivers/usb/host/ohci-sunxi.c | 233 ----------------------------------
 scripts/config_whitelist.txt  |   2 -
 4 files changed, 441 deletions(-)
 delete mode 100644 drivers/usb/host/ehci-sunxi.c
 delete mode 100644 drivers/usb/host/ohci-sunxi.c

drivers/usb/host/Makefile +0 -2

index cb8c315a15..b62fdbb1d2 100644
@@ -15,7 +15,6 @@ obj-$(CONFIG_USB_OHCI_DA8XX) += ohci-da8xx.o
 obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
 obj-$(CONFIG_USB_SL811HS) += sl811-hcd.o
 obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o
-obj-$(CONFIG_USB_OHCI_SUNXI) += ohci-sunxi.o
 obj-$(CONFIG_USB_OHCI_LPC32XX) += ohci-lpc32xx.o
 obj-$(CONFIG_USB_OHCI_GENERIC) += ohci-generic.o

@@ -37,7 +36,6 @@ obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
 obj-$(CONFIG_USB_EHCI_MSM) += ehci-msm.o
 obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
 obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
-obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o
 obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
 obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
 obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o

drivers/usb/host/ehci-sunxi.c deleted +0 ~~-204~~

204 lines not on this page · raw message

drivers/usb/host/ohci-sunxi.c deleted +0 ~~-233~~

233 lines not on this page · raw message

scripts/config_whitelist.txt +0 -2

index 0d60da3f28..4cca3d1c73 100644
@@ -4611,7 +4611,6 @@ CONFIG_USB_EHCI_MX5
 CONFIG_USB_EHCI_MXC
 CONFIG_USB_EHCI_MXS
 CONFIG_USB_EHCI_SPEAR
-CONFIG_USB_EHCI_SUNXI
 CONFIG_USB_EHCI_TEGRA
 CONFIG_USB_EHCI_TXFIFO_THRESH
 CONFIG_USB_EHCI_VCT

@@ -4653,7 +4652,6 @@ CONFIG_USB_OHCI
 CONFIG_USB_OHCI_EP93XX
 CONFIG_USB_OHCI_LPC32XX
 CONFIG_USB_OHCI_NEW
-CONFIG_USB_OHCI_SUNXI
 CONFIG_USB_OTG
 CONFIG_USB_OTG_BLACKLIST_HUB
 CONFIG_USB_PHY_CFG_BASE

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #20 lore raw

PATCH v3 18/58 clk: sunxi: Implement AHB bus MMC clocks

In reply to Jagan Teki

Implement AHB bus MMC clocks for all Allwinner SoC clock drivers via clock map descriptor table.

Cc Jaehoon Chung <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/clk_a10.c  | 4 ++++
 drivers/clk/sunxi/clk_a10s.c | 3 +++
 drivers/clk/sunxi/clk_a23.c  | 3 +++
 drivers/clk/sunxi/clk_a31.c  | 4 ++++
 drivers/clk/sunxi/clk_a64.c  | 3 +++
 drivers/clk/sunxi/clk_a83t.c | 3 +++
 drivers/clk/sunxi/clk_h3.c   | 3 +++
 drivers/clk/sunxi/clk_r40.c  | 4 ++++
 drivers/clk/sunxi/clk_v3s.c  | 3 +++
 9 files changed, 30 insertions(+)

drivers/clk/sunxi/clk_a10.c +4 -0

index 7492e1367a..fb11231dd1 100644
@@ -18,6 +18,10 @@ static struct ccu_clk_map a10_clks[] = {
 	[CLK_AHB_OHCI0]		= { 0x060, BIT(2), NULL },
 	[CLK_AHB_EHCI1]		= { 0x060, BIT(3), NULL },
 	[CLK_AHB_OHCI1]		= { 0x060, BIT(4), NULL },
+	[CLK_AHB_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_AHB_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_AHB_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_AHB_MMC3]		= { 0x060, BIT(11), NULL },
 
 	[CLK_USB_OHCI0]		= { 0x0cc, BIT(6), NULL },
 	[CLK_USB_OHCI1]		= { 0x0cc, BIT(7), NULL },

drivers/clk/sunxi/clk_a10s.c +3 -0

index 976595201f..bc4ae7352b 100644
@@ -16,6 +16,9 @@ static struct ccu_clk_map a10s_clks[] = {
 	[CLK_AHB_OTG]		= { 0x060, BIT(0), NULL },
 	[CLK_AHB_EHCI]		= { 0x060, BIT(1), NULL },
 	[CLK_AHB_OHCI]		= { 0x060, BIT(2), NULL },
+	[CLK_AHB_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_AHB_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_AHB_MMC2]		= { 0x060, BIT(10), NULL },
 
 	[CLK_USB_OHCI]		= { 0x0cc, BIT(6), NULL },
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },

drivers/clk/sunxi/clk_a23.c +3 -0

index ec9834e1a8..62770a58fe 100644
@@ -13,6 +13,9 @@
 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
 
 static struct ccu_clk_map a23_clks[] = {
+	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(24), NULL },
 	[CLK_BUS_EHCI]		= { 0x060, BIT(26), NULL },
 	[CLK_BUS_OHCI]		= { 0x060, BIT(29), NULL },

drivers/clk/sunxi/clk_a31.c +4 -0

index c6d82be120..f314feff69 100644
@@ -13,6 +13,10 @@
 #include <dt-bindings/reset/sun6i-a31-ccu.h>
 
 static struct ccu_clk_map a31_clks[] = {
+	[CLK_AHB1_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_AHB1_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_AHB1_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_AHB1_MMC3]		= { 0x060, BIT(12), NULL },
 	[CLK_AHB1_OTG]		= { 0x060, BIT(24), NULL },
 	[CLK_AHB1_EHCI0]	= { 0x060, BIT(26), NULL },
 	[CLK_AHB1_EHCI1]	= { 0x060, BIT(27), NULL },

drivers/clk/sunxi/clk_a64.c +3 -0

index e5257b62c7..71f3510c74 100644
@@ -13,6 +13,9 @@
 #include <dt-bindings/reset/sun50i-a64-ccu.h>
 
 static struct ccu_clk_map a64_clks[] = {
+	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(23), NULL },
 	[CLK_BUS_EHCI0]		= { 0x060, BIT(24), NULL },
 	[CLK_BUS_EHCI1]		= { 0x060, BIT(25), NULL },

drivers/clk/sunxi/clk_a83t.c +3 -0

index 58d28eb6ad..cc18975a06 100644
@@ -13,6 +13,9 @@
 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
 
 static struct ccu_clk_map a83t_clks[] = {
+	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(24), NULL },
 	[CLK_BUS_EHCI0]		= { 0x060, BIT(26), NULL },
 	[CLK_BUS_EHCI1]		= { 0x060, BIT(27), NULL },

drivers/clk/sunxi/clk_h3.c +3 -0

index 0b7f4947dd..85dd06ee2d 100644
@@ -13,6 +13,9 @@
 #include <dt-bindings/reset/sun8i-h3-ccu.h>
 
 static struct ccu_clk_map h3_clks[] = {
+	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(23), NULL },
 	[CLK_BUS_EHCI0]		= { 0x060, BIT(24), NULL },
 	[CLK_BUS_EHCI1]		= { 0x060, BIT(25), NULL },

drivers/clk/sunxi/clk_r40.c +4 -0

index 746d6734b2..006aa138b6 100644
@@ -13,6 +13,10 @@
 #include <dt-bindings/reset/sun8i-r40-ccu.h>
 
 static struct ccu_clk_map r40_clks[] = {
+	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_BUS_MMC3]		= { 0x060, BIT(11), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(25), NULL },
 	[CLK_BUS_EHCI0]		= { 0x060, BIT(26), NULL },
 	[CLK_BUS_EHCI1]		= { 0x060, BIT(27), NULL },

drivers/clk/sunxi/clk_v3s.c +3 -0

index 2494518798..ab2cc45640 100644
@@ -13,6 +13,9 @@
 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
 
 static struct ccu_clk_map v3s_clks[] = {
+	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(24), NULL },
 
 	[CLK_USB_PHY0]          = { 0x0cc, BIT(8), NULL },

Signature · 1 line

2.18.0.321.gffc6fa0e3

Maxime Ripard

2018-08-20 11:28 UTC #21 lore raw

PATCH v3 18/58 clk: sunxi: Implement AHB bus MMC clocks

Quoted 5 lines · Jagan Teki

Implement AHB bus MMC clocks for all Allwinner SoC clock drivers via clock map descriptor table.
Cc Jaehoon Chung <[email protected]>
Signed-off-by Jagan Teki <[email protected]>

That should be merged in the clock driver patches.

Maxime

Signature · 10 lines

Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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Jagan Teki

author

2018-08-19 13:56 UTC #22 lore raw

PATCH v3 19/58 clk: sunxi: Implement direct MMC clocks

In reply to Jagan Teki

Implement direct MMC clocks for all Allwinner SoC clock drivers via clock map descriptor table.

This includes adding ccu_clk_set_rate function pointer, which indeed support CLK set_rate API, so update clock handling in sunxi_mmc driver to support both no-dm and dm code.

Cc Jaehoon Chung <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/include/asm/arch-sunxi/ccu.h | 10 +++++
 drivers/clk/sunxi/clk_a10.c           |  5 +++
 drivers/clk/sunxi/clk_a10s.c          |  6 +++
 drivers/clk/sunxi/clk_a23.c           |  6 +++
 drivers/clk/sunxi/clk_a31.c           |  5 +++
 drivers/clk/sunxi/clk_a64.c           |  4 ++
 drivers/clk/sunxi/clk_a83t.c          |  4 ++
 drivers/clk/sunxi/clk_h3.c            |  4 ++
 drivers/clk/sunxi/clk_r40.c           |  4 ++
 drivers/clk/sunxi/clk_sunxi.c         | 19 +++++++++
 drivers/clk/sunxi/clk_v3s.c           |  4 ++
 drivers/mmc/sunxi_mmc.c               | 58 +++++++++++++++++----------
 12 files changed, 107 insertions(+), 22 deletions(-)

arch/arm/include/asm/arch-sunxi/ccu.h +10 -0

index bacd052ef3..4e30ab330c 100644
@@ -60,6 +60,16 @@ struct sunxi_clk_priv {
 
 extern struct clk_ops sunxi_clk_ops;
 
+/**
+ * mmc_clk_set_rate - mmc clock set rate
+ *
+ * @base:	clock register base address
+ * @bit:	clock bit value
+ * @rate:	clock input rate in Hz
+ * @return 0, or -ve error code.
+ */
+int mmc_clk_set_rate(void *base, u32 bit, ulong rate);
+
 /**
  * sunxi_reset_bind() - reset binding
  *

drivers/clk/sunxi/clk_a10.c +5 -0

index fb11231dd1..55176bc174 100644
@@ -23,6 +23,11 @@ static struct ccu_clk_map a10_clks[] = {
 	[CLK_AHB_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_AHB_MMC3]		= { 0x060, BIT(11), NULL },
 
+	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC3]		= { 0x094, BIT(31), &mmc_clk_set_rate },
+
 	[CLK_USB_OHCI0]		= { 0x0cc, BIT(6), NULL },
 	[CLK_USB_OHCI1]		= { 0x0cc, BIT(7), NULL },
 	[CLK_USB_PHY]		= { 0x0cc, BIT(8), NULL },

drivers/clk/sunxi/clk_a10s.c +6 -0

index bc4ae7352b..fbac0ad751 100644
@@ -20,6 +20,12 @@ static struct ccu_clk_map a10s_clks[] = {
 	[CLK_AHB_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_AHB_MMC2]		= { 0x060, BIT(10), NULL },
 
+#ifdef CONFIG_MMC
+	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
+#endif
+
 	[CLK_USB_OHCI]		= { 0x0cc, BIT(6), NULL },
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
 	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },

drivers/clk/sunxi/clk_a23.c +6 -0

index 62770a58fe..0b5406c5b3 100644
@@ -20,6 +20,12 @@ static struct ccu_clk_map a23_clks[] = {
 	[CLK_BUS_EHCI]		= { 0x060, BIT(26), NULL },
 	[CLK_BUS_OHCI]		= { 0x060, BIT(29), NULL },
 
+#ifdef CONFIG_MMC
+	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
+#endif
+
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
 	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },
 	[CLK_USB_HSIC]		= { 0x0cc, BIT(10), NULL },

drivers/clk/sunxi/clk_a31.c +5 -0

index f314feff69..3c807bde77 100644
@@ -24,6 +24,11 @@ static struct ccu_clk_map a31_clks[] = {
 	[CLK_AHB1_OHCI1]	= { 0x060, BIT(30), NULL },
 	[CLK_AHB1_OHCI2]	= { 0x060, BIT(31), NULL },
 
+	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC3]		= { 0x094, BIT(31), &mmc_clk_set_rate },
+
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
 	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },
 	[CLK_USB_PHY2]		= { 0x0cc, BIT(10), NULL },

drivers/clk/sunxi/clk_a64.c +4 -0

index 71f3510c74..62cd6d6464 100644
@@ -22,6 +22,10 @@ static struct ccu_clk_map a64_clks[] = {
 	[CLK_BUS_OHCI0]		= { 0x060, BIT(28), NULL },
 	[CLK_BUS_OHCI1]		= { 0x060, BIT(29), NULL },
 
+	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
+
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
 	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },
 	[CLK_USB_HSIC]		= { 0x0cc, BIT(10), NULL },

drivers/clk/sunxi/clk_a83t.c +4 -0

index cc18975a06..a2e0ac7a26 100644
@@ -21,6 +21,10 @@ static struct ccu_clk_map a83t_clks[] = {
 	[CLK_BUS_EHCI1]		= { 0x060, BIT(27), NULL },
 	[CLK_BUS_OHCI0]		= { 0x060, BIT(29), NULL },
 
+	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
+
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
 	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },
 	[CLK_USB_HSIC]		= { 0x0cc, BIT(10), NULL },

drivers/clk/sunxi/clk_h3.c +4 -0

index 85dd06ee2d..f467187c01 100644
@@ -26,6 +26,10 @@ static struct ccu_clk_map h3_clks[] = {
 	[CLK_BUS_OHCI2]		= { 0x060, BIT(30), NULL },
 	[CLK_BUS_OHCI3]		= { 0x060, BIT(31), NULL },
 
+	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
+
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
 	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },
 	[CLK_USB_PHY2]		= { 0x0cc, BIT(10), NULL },

drivers/clk/sunxi/clk_r40.c +4 -0

index 006aa138b6..9273f3b7ea 100644
@@ -25,6 +25,10 @@ static struct ccu_clk_map r40_clks[] = {
 	[CLK_BUS_OHCI1]		= { 0x060, BIT(30), NULL },
 	[CLK_BUS_OHCI2]		= { 0x060, BIT(31), NULL },
 
+	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC3]		= { 0x094, BIT(31), &mmc_clk_set_rate },
 
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
 	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },

drivers/clk/sunxi/clk_sunxi.c +19 -0

index 791b1ac7f2..ca147ec9cc 100644
@@ -12,6 +12,24 @@
 #include <asm/arch/ccu.h>
 #include <linux/log2.h>
 
+static ulong sunxi_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct sunxi_clk_priv *priv = dev_get_priv(clk->dev);
+	struct ccu_clk_map *map = &priv->desc->clks[clk->id];
+	u32 *base;
+
+	if (!map->ccu_clk_set_rate) {
+		debug("%s (CLK#%ld) unhandled\n", __func__, clk->id);
+		return 0;
+	}
+
+	debug("%s(#%ld) off#0x%x, BIT(%d)\n", __func__,
+	      clk->id, map->off, ilog2(map->bit));
+
+	base = priv->base + map->off;
+	return map->ccu_clk_set_rate(base, map->bit, rate);
+}
+
 static int sunxi_clk_enable(struct clk *clk)
 {
 	struct sunxi_clk_priv *priv = dev_get_priv(clk->dev);

@@ -55,4 +73,5 @@ static int sunxi_clk_disable(struct clk *clk)
 struct clk_ops sunxi_clk_ops = {
 	.enable = sunxi_clk_enable,
 	.disable = sunxi_clk_disable,
+	.set_rate = sunxi_clk_set_rate,
 };

drivers/clk/sunxi/clk_v3s.c +4 -0

index ab2cc45640..e0d757debe 100644
@@ -18,6 +18,10 @@ static struct ccu_clk_map v3s_clks[] = {
 	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(24), NULL },
 
+	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
+
 	[CLK_USB_PHY0]          = { 0x0cc, BIT(8), NULL },
 };

drivers/mmc/sunxi_mmc.c +36 ~~-22~~

139 lines not on this page · raw message

Signature · 1 line

2.18.0.321.gffc6fa0e3

Maxime Ripard

2018-08-20 11:33 UTC #23 lore raw

PATCH v3 19/58 clk: sunxi: Implement direct MMC clocks

Quoted 66 lines · Jagan Teki

Implement direct MMC clocks for all Allwinner SoC clock drivers via clock map descriptor table.

This includes adding ccu_clk_set_rate function pointer, which indeed support CLK set_rate API, so update clock handling in sunxi_mmc driver to support both no-dm and dm code.

Cc Jaehoon Chung <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/include/asm/arch-sunxi/ccu.h | 10 +++++
 drivers/clk/sunxi/clk_a10.c           |  5 +++
 drivers/clk/sunxi/clk_a10s.c          |  6 +++
 drivers/clk/sunxi/clk_a23.c           |  6 +++
 drivers/clk/sunxi/clk_a31.c           |  5 +++
 drivers/clk/sunxi/clk_a64.c           |  4 ++
 drivers/clk/sunxi/clk_a83t.c          |  4 ++
 drivers/clk/sunxi/clk_h3.c            |  4 ++
 drivers/clk/sunxi/clk_r40.c           |  4 ++
 drivers/clk/sunxi/clk_sunxi.c         | 19 +++++++++
 drivers/clk/sunxi/clk_v3s.c           |  4 ++
 drivers/mmc/sunxi_mmc.c               | 58 +++++++++++++++++----------
 12 files changed, 107 insertions(+), 22 deletions(-)

arch/arm/include/asm/arch-sunxi/ccu.h +10 -0

index bacd052ef3..4e30ab330c 100644
@@ -60,6 +60,16 @@ struct sunxi_clk_priv {
 
 extern struct clk_ops sunxi_clk_ops;
 
+/**
+ * mmc_clk_set_rate - mmc clock set rate
+ *
+ * @base:	clock register base address
+ * @bit:	clock bit value
+ * @rate:	clock input rate in Hz
+ * @return 0, or -ve error code.
+ */
+int mmc_clk_set_rate(void *base, u32 bit, ulong rate);
+
 /**
  * sunxi_reset_bind() - reset binding
  *

drivers/clk/sunxi/clk_a10.c +5 -0

index fb11231dd1..55176bc174 100644
@@ -23,6 +23,11 @@ static struct ccu_clk_map a10_clks[] = {
 	[CLK_AHB_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_AHB_MMC3]		= { 0x060, BIT(11), NULL },
 
+	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC3]		= { 0x094, BIT(31), &mmc_clk_set_rate },
+
 	[CLK_USB_OHCI0]		= { 0x0cc, BIT(6), NULL },
 	[CLK_USB_OHCI1]		= { 0x0cc, BIT(7), NULL },
 	[CLK_USB_PHY]		= { 0x0cc, BIT(8), NULL },

drivers/clk/sunxi/clk_a10s.c +0 -0

index bc4ae7352b..fbac0ad751 100644

drivers/clk/sunxi/clk_a10s.c static struct ccu_clk_map a10s_clks[] = { · line 28

Quoted 9 lines

drivers/clk/sunxi/clk_a10s.c +6 -0

@@ -20,6 +20,12 @@ static struct ccu_clk_map a10s_clks[] = {
 	[CLK_AHB_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_AHB_MMC2]		= { 0x060, BIT(10), NULL },
 
+#ifdef CONFIG_MMC
+	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
+	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
+#endif
+

I'm not too sure about the ifdef here. Or at least, we should be consistent, and if we do it for the MMC, we should do it for all the SoCs (including the A10), and for all the controllers (including USB, for example).

Quoted 35 lines

drivers/mmc/sunxi_mmc.c +4 -5

index 39f15eb423..bf82014a64 100644
@@ -13,6 +13,7 @@
 #include <malloc.h>
 #include <mmc.h>
 #include <asm/io.h>
+#include <asm/arch/ccu.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/gpio.h>

@@ -34,6 +35,8 @@ struct sunxi_mmc_priv {
 	struct mmc_config cfg;
 };
 
+bool new_mode;
+
 #if !CONFIG_IS_ENABLED(DM_MMC)
 /* support 4 mmc hosts */
 struct sunxi_mmc_priv mmc_host[4];

@@ -95,23 +98,19 @@ static int mmc_resource_init(int sdc_no)
 }
 #endif
 
-static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
+int mmc_clk_set_rate(void *base, u32 bit, ulong rate)
 {
 	unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
-	bool new_mode = false;
 	u32 val = 0;
 
-	if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))
-		new_mode = true;
-

[..]

drivers/mmc/sunxi_mmc.c static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) · line 194

Quoted 7 lines

drivers/mmc/sunxi_mmc.c +7 -0

+static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
+{
+#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(CLK)
+#else
+	if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))
+		new_mode = true;
+

I'm not sure why you need the global variable.

The A83t emmc case you have below is caught in this condition, and therefore, the scope doesn't need to be global.

Maxime

Signature · 10 lines

Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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Jagan Teki

author

2018-08-27 10:04 UTC #24 lore raw

PATCH v3 19/58 clk: sunxi: Implement direct MMC clocks

Quoted 70 lines · Maxime Ripard

Quoted 69 lines · Jagan Teki

Implement direct MMC clocks for all Allwinner SoC clock drivers via clock map descriptor table.

This includes adding ccu_clk_set_rate function pointer, which indeed support CLK set_rate API, so update clock handling in sunxi_mmc driver to support both no-dm and dm code.

Cc Jaehoon Chung <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/include/asm/arch-sunxi/ccu.h | 10 +++++
 drivers/clk/sunxi/clk_a10.c           |  5 +++
 drivers/clk/sunxi/clk_a10s.c          |  6 +++
 drivers/clk/sunxi/clk_a23.c           |  6 +++
 drivers/clk/sunxi/clk_a31.c           |  5 +++
 drivers/clk/sunxi/clk_a64.c           |  4 ++
 drivers/clk/sunxi/clk_a83t.c          |  4 ++
 drivers/clk/sunxi/clk_h3.c            |  4 ++
 drivers/clk/sunxi/clk_r40.c           |  4 ++
 drivers/clk/sunxi/clk_sunxi.c         | 19 +++++++++
 drivers/clk/sunxi/clk_v3s.c           |  4 ++
 drivers/mmc/sunxi_mmc.c               | 58 +++++++++++++++++----------
 12 files changed, 107 insertions(+), 22 deletions(-)

arch/arm/include/asm/arch-sunxi/ccu.h +10 -0

index bacd052ef3..4e30ab330c 100644
@@ -60,6 +60,16 @@ struct sunxi_clk_priv {
 
 extern struct clk_ops sunxi_clk_ops;
 
+/**
+ * mmc_clk_set_rate - mmc clock set rate
+ *
+ * @base:    clock register base address
+ * @bit:     clock bit value
+ * @rate:    clock input rate in Hz
+ * @return 0, or -ve error code.
+ */
+int mmc_clk_set_rate(void *base, u32 bit, ulong rate);
+
 /**
  * sunxi_reset_bind() - reset binding
  *

drivers/clk/sunxi/clk_a10.c +5 -0

index fb11231dd1..55176bc174 100644
@@ -23,6 +23,11 @@ static struct ccu_clk_map a10_clks[] = {
      [CLK_AHB_MMC2]          = { 0x060, BIT(10), NULL },
      [CLK_AHB_MMC3]          = { 0x060, BIT(11), NULL },
 
+     [CLK_MMC0]              = { 0x088, BIT(31), &mmc_clk_set_rate },
+     [CLK_MMC1]              = { 0x08c, BIT(31), &mmc_clk_set_rate },
+     [CLK_MMC2]              = { 0x090, BIT(31), &mmc_clk_set_rate },
+     [CLK_MMC3]              = { 0x094, BIT(31), &mmc_clk_set_rate },
+
      [CLK_USB_OHCI0]         = { 0x0cc, BIT(6), NULL },
      [CLK_USB_OHCI1]         = { 0x0cc, BIT(7), NULL },
      [CLK_USB_PHY]           = { 0x0cc, BIT(8), NULL },

drivers/clk/sunxi/clk_a10s.c +0 -0

index bc4ae7352b..fbac0ad751 100644
@@ -20,6 +20,12 @@ static struct ccu_clk_map a10s_clks[] = {
      [CLK_AHB_MMC1]          = { 0x060, BIT(9), NULL },
      [CLK_AHB_MMC2]          = { 0x060, BIT(10), NULL },

Quoted 11 lines

drivers/clk/sunxi/clk_a10s.c static struct ccu_clk_map a10s_clks[] = { · line 28
Quoted 6 lines
drivers/clk/sunxi/clk_a10s.c +6 -0
+#ifdef CONFIG_MMC
+     [CLK_MMC0]              = { 0x088, BIT(31), &mmc_clk_set_rate },
+     [CLK_MMC1]              = { 0x08c, BIT(31), &mmc_clk_set_rate },
+     [CLK_MMC2]              = { 0x090, BIT(31), &mmc_clk_set_rate },
+#endif
+
I'm not too sure about the ifdef here. Or at least, we should be consistent, and if we do it for the MMC, we should do it for all the SoCs (including the A10), and for all the controllers (including USB, for example).

because few of sun5i boards not using MMC, example CHIP and CHIP_pro otherwise we need to use intermediate wrapper to call mmc_clk_set_rate.

Quoted 49 lines

Quoted 36 lines

drivers/mmc/sunxi_mmc.c +4 -5

index 39f15eb423..bf82014a64 100644
@@ -13,6 +13,7 @@
 #include <malloc.h>
 #include <mmc.h>
 #include <asm/io.h>
+#include <asm/arch/ccu.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/gpio.h>

@@ -34,6 +35,8 @@ struct sunxi_mmc_priv {
      struct mmc_config cfg;
 };
 
+bool new_mode;
+
 #if !CONFIG_IS_ENABLED(DM_MMC)
 /* support 4 mmc hosts */
 struct sunxi_mmc_priv mmc_host[4];

@@ -95,23 +98,19 @@ static int mmc_resource_init(int sdc_no)
 }
 #endif
 
-static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
+int mmc_clk_set_rate(void *base, u32 bit, ulong rate)
 {
      unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
-     bool new_mode = false;
      u32 val = 0;
 
-     if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))
-             new_mode = true;
-

[..]

drivers/mmc/sunxi_mmc.c static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) · line 194

Quoted 7 lines

drivers/mmc/sunxi_mmc.c +7 -0

+static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
+{
+#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(CLK)
+#else
+     if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))
+             new_mode = true;
+

I'm not sure why you need the global variable.

Quoted 2 lines

The A83t emmc case you have below is caught in this condition, and therefore, the scope doesn't need to be global.

Since mmc_set_rate calling with base and reg bits, which doesn't have any possibility know private data of driver we need a global to check to update the same in dm and non-dm.

Maxime Ripard

2018-08-28 09:51 UTC #25 lore raw

PATCH v3 19/58 clk: sunxi: Implement direct MMC clocks

Quoted 36 lines · Jagan Teki

Quoted 24 lines

drivers/clk/sunxi/clk_a10.c +5 -0

index fb11231dd1..55176bc174 100644
@@ -23,6 +23,11 @@ static struct ccu_clk_map a10_clks[] = {
      [CLK_AHB_MMC2]          = { 0x060, BIT(10), NULL },
      [CLK_AHB_MMC3]          = { 0x060, BIT(11), NULL },
 
+     [CLK_MMC0]              = { 0x088, BIT(31), &mmc_clk_set_rate },
+     [CLK_MMC1]              = { 0x08c, BIT(31), &mmc_clk_set_rate },
+     [CLK_MMC2]              = { 0x090, BIT(31), &mmc_clk_set_rate },
+     [CLK_MMC3]              = { 0x094, BIT(31), &mmc_clk_set_rate },
+
      [CLK_USB_OHCI0]         = { 0x0cc, BIT(6), NULL },
      [CLK_USB_OHCI1]         = { 0x0cc, BIT(7), NULL },
      [CLK_USB_PHY]           = { 0x0cc, BIT(8), NULL },

drivers/clk/sunxi/clk_a10s.c +0 -0

index bc4ae7352b..fbac0ad751 100644
@@ -20,6 +20,12 @@ static struct ccu_clk_map a10s_clks[] = {
      [CLK_AHB_MMC1]          = { 0x060, BIT(9), NULL },
      [CLK_AHB_MMC2]          = { 0x060, BIT(10), NULL },

Quoted 11 lines

drivers/clk/sunxi/clk_a10s.c static struct ccu_clk_map a10s_clks[] = { · line 28
Quoted 6 lines
drivers/clk/sunxi/clk_a10s.c +6 -0
+#ifdef CONFIG_MMC
+     [CLK_MMC0]              = { 0x088, BIT(31), &mmc_clk_set_rate },
+     [CLK_MMC1]              = { 0x08c, BIT(31), &mmc_clk_set_rate },
+     [CLK_MMC2]              = { 0x090, BIT(31), &mmc_clk_set_rate },
+#endif
+
I'm not too sure about the ifdef here. Or at least, we should be consistent, and if we do it for the MMC, we should do it for all the SoCs (including the A10), and for all the controllers (including USB, for example).

Quoted 3 lines

because few of sun5i boards not using MMC, example CHIP and CHIP_pro otherwise we need to use intermediate wrapper to call mmc_clk_set_rate.

Well, yes, but you can make the same argument for other SoCs, and other features. So really, I think this is a good idea, but if we remain consistent between SoCs and features.

Quoted 49 lines

Quoted 36 lines

drivers/mmc/sunxi_mmc.c +4 -5

index 39f15eb423..bf82014a64 100644
@@ -13,6 +13,7 @@
 #include <malloc.h>
 #include <mmc.h>
 #include <asm/io.h>
+#include <asm/arch/ccu.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/gpio.h>

@@ -34,6 +35,8 @@ struct sunxi_mmc_priv {
      struct mmc_config cfg;
 };
 
+bool new_mode;
+
 #if !CONFIG_IS_ENABLED(DM_MMC)
 /* support 4 mmc hosts */
 struct sunxi_mmc_priv mmc_host[4];

@@ -95,23 +98,19 @@ static int mmc_resource_init(int sdc_no)
 }
 #endif
 
-static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
+int mmc_clk_set_rate(void *base, u32 bit, ulong rate)
 {
      unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
-     bool new_mode = false;
      u32 val = 0;
 
-     if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))
-             new_mode = true;
-

[..]

drivers/mmc/sunxi_mmc.c static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) · line 194

Quoted 7 lines

drivers/mmc/sunxi_mmc.c +7 -0

+static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
+{
+#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(CLK)
+#else
+     if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))
+             new_mode = true;
+

I'm not sure why you need the global variable.

Quoted 6 lines

Quoted 2 lines
The A83t emmc case you have below is caught in this condition, and therefore, the scope doesn't need to be global.
Since mmc_set_rate calling with base and reg bits, which doesn't have any possibility know private data of driver we need a global to check to update the same in dm and non-dm.

Wouldn't that lead to issues if we have two controllers being active, one with the new mode enabled, the other without, and you call mmc_set_rate on the one without?

Maxime

Signature · 10 lines

Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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Jagan Teki

author

2018-08-28 16:46 UTC #26 lore raw

PATCH v3 19/58 clk: sunxi: Implement direct MMC clocks

Quoted 37 lines · Maxime Ripard

Quoted 36 lines · Jagan Teki

Quoted 35 lines

Quoted 21 lines

drivers/clk/sunxi/clk_a10.c +5 -0

index fb11231dd1..55176bc174 100644
@@ -23,6 +23,11 @@ static struct ccu_clk_map a10_clks[] = {
      [CLK_AHB_MMC2]          = { 0x060, BIT(10), NULL },
      [CLK_AHB_MMC3]          = { 0x060, BIT(11), NULL },
 
+     [CLK_MMC0]              = { 0x088, BIT(31), &mmc_clk_set_rate },
+     [CLK_MMC1]              = { 0x08c, BIT(31), &mmc_clk_set_rate },
+     [CLK_MMC2]              = { 0x090, BIT(31), &mmc_clk_set_rate },
+     [CLK_MMC3]              = { 0x094, BIT(31), &mmc_clk_set_rate },
+
      [CLK_USB_OHCI0]         = { 0x0cc, BIT(6), NULL },
      [CLK_USB_OHCI1]         = { 0x0cc, BIT(7), NULL },
      [CLK_USB_PHY]           = { 0x0cc, BIT(8), NULL },

drivers/clk/sunxi/clk_a10s.c +0 -0

index bc4ae7352b..fbac0ad751 100644

drivers/clk/sunxi/clk_a10s.c static struct ccu_clk_map a10s_clks[] = { · line 28

Quoted 9 lines

drivers/clk/sunxi/clk_a10s.c +6 -0

@@ -20,6 +20,12 @@ static struct ccu_clk_map a10s_clks[] = {
      [CLK_AHB_MMC1]          = { 0x060, BIT(9), NULL },
      [CLK_AHB_MMC2]          = { 0x060, BIT(10), NULL },
 
+#ifdef CONFIG_MMC
+     [CLK_MMC0]              = { 0x088, BIT(31), &mmc_clk_set_rate },
+     [CLK_MMC1]              = { 0x08c, BIT(31), &mmc_clk_set_rate },
+     [CLK_MMC2]              = { 0x090, BIT(31), &mmc_clk_set_rate },
+#endif
+

Quoted 7 lines

Quoted 3 lines
because few of sun5i boards not using MMC, example CHIP and CHIP_pro otherwise we need to use intermediate wrapper to call mmc_clk_set_rate.
Well, yes, but you can make the same argument for other SoCs, and other features. So really, I think this is a good idea, but if we remain consistent between SoCs and features.

True, I see adding wrapper make consistent on these descriptor table, so the wrapper will call the actual set_rate, of course we need to add ifdef in wrapper for non-MMC targets or __weak function.

Jagan Teki

author

2018-08-19 13:56 UTC #27 lore raw

PATCH v3 20/58 clk: sunxi: Implement AHB bus MMC resets

In reply to Jagan Teki

Implement AHB bus MMC resets for all Allwinner SoC clock drivers via reset map descriptor table.

Cc Jaehoon Chung <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/clk_a23.c  | 3 +++
 drivers/clk/sunxi/clk_a31.c  | 4 ++++
 drivers/clk/sunxi/clk_a64.c  | 3 +++
 drivers/clk/sunxi/clk_a83t.c | 3 +++
 drivers/clk/sunxi/clk_h3.c   | 3 +++
 drivers/clk/sunxi/clk_r40.c  | 4 ++++
 drivers/clk/sunxi/clk_v3s.c  | 3 +++
 7 files changed, 23 insertions(+)

drivers/clk/sunxi/clk_a23.c +3 -0

index 0b5406c5b3..183c6275f3 100644
@@ -38,6 +38,9 @@ static struct ccu_reset_map a23_resets[] = {
 	[RST_USB_PHY1]		= { 0x0cc, BIT(1) },
 	[RST_USB_HSIC]		= { 0x0cc, BIT(2) },
 
+	[RST_BUS_MMC0]		= { 0x2c0, BIT(8) },
+	[RST_BUS_MMC1]		= { 0x2c0, BIT(9) },
+	[RST_BUS_MMC2]		= { 0x2c0, BIT(10) },
 	[RST_BUS_OTG]		= { 0x2c0, BIT(24) },
 	[RST_BUS_EHCI]		= { 0x2c0, BIT(26) },
 	[RST_BUS_OHCI]		= { 0x2c0, BIT(29) },

drivers/clk/sunxi/clk_a31.c +4 -0

index 3c807bde77..15076d0e72 100644
@@ -42,6 +42,10 @@ static struct ccu_reset_map a31_resets[] = {
 	[RST_USB_PHY1]		= { 0x0cc, BIT(1) },
 	[RST_USB_PHY2]		= { 0x0cc, BIT(2) },
 
+	[RST_AHB1_MMC0]		= { 0x2c0, BIT(8) },
+	[RST_AHB1_MMC1]		= { 0x2c0, BIT(9) },
+	[RST_AHB1_MMC2]		= { 0x2c0, BIT(10) },
+	[RST_AHB1_MMC3]		= { 0x2c0, BIT(11) },
 	[RST_AHB1_OTG]		= { 0x2c0, BIT(24) },
 	[RST_AHB1_EHCI0]	= { 0x2c0, BIT(26) },
 	[RST_AHB1_EHCI1]	= { 0x2c0, BIT(27) },

drivers/clk/sunxi/clk_a64.c +3 -0

index 62cd6d6464..9ef9b606d2 100644
@@ -39,6 +39,9 @@ static struct ccu_reset_map a64_resets[] = {
 	[RST_USB_PHY1]		= { 0x0cc, BIT(1) },
 	[RST_USB_HSIC]		= { 0x0cc, BIT(2) },
 
+	[RST_BUS_MMC0]		= { 0x2c0, BIT(8) },
+	[RST_BUS_MMC1]		= { 0x2c0, BIT(9) },
+	[RST_BUS_MMC2]		= { 0x2c0, BIT(10) },
 	[RST_BUS_OTG]		= { 0x2c0, BIT(23) },
 	[RST_BUS_EHCI0]		= { 0x2c0, BIT(24) },
 	[RST_BUS_EHCI1]		= { 0x2c0, BIT(25) },

drivers/clk/sunxi/clk_a83t.c +3 -0

index a2e0ac7a26..47b7672e7f 100644
@@ -37,6 +37,9 @@ static struct ccu_reset_map a83t_resets[] = {
 	[RST_USB_PHY1]		= { 0x0cc, BIT(1) },
 	[RST_USB_HSIC]		= { 0x0cc, BIT(2) },
 
+	[RST_BUS_MMC0]		= { 0x2c0, BIT(8) },
+	[RST_BUS_MMC1]		= { 0x2c0, BIT(9) },
+	[RST_BUS_MMC2]		= { 0x2c0, BIT(10) },
 	[RST_BUS_OTG]		= { 0x2c0, BIT(24) },
 	[RST_BUS_EHCI0]		= { 0x2c0, BIT(26) },
 	[RST_BUS_EHCI1]		= { 0x2c0, BIT(27) },

drivers/clk/sunxi/clk_h3.c +3 -0

index f467187c01..ad15aaae67 100644
@@ -46,6 +46,9 @@ static struct ccu_reset_map h3_resets[] = {
 	[RST_USB_PHY2]		= { 0x0cc, BIT(2) },
 	[RST_USB_PHY3]		= { 0x0cc, BIT(3) },
 
+	[RST_BUS_MMC0]		= { 0x2c0, BIT(8) },
+	[RST_BUS_MMC1]		= { 0x2c0, BIT(9) },
+	[RST_BUS_MMC2]		= { 0x2c0, BIT(10) },
 	[RST_BUS_OTG]		= { 0x2c0, BIT(23) },
 	[RST_BUS_EHCI0]		= { 0x2c0, BIT(24) },
 	[RST_BUS_EHCI1]		= { 0x2c0, BIT(25) },

drivers/clk/sunxi/clk_r40.c +4 -0

index 9273f3b7ea..24c26ad3be 100644
@@ -43,6 +43,10 @@ static struct ccu_reset_map r40_resets[] = {
 	[RST_USB_PHY1]		= { 0x0cc, BIT(1) },
 	[RST_USB_PHY2]		= { 0x0cc, BIT(2) },
 
+	[RST_BUS_MMC0]		= { 0x2c0, BIT(8) },
+	[RST_BUS_MMC1]		= { 0x2c0, BIT(9) },
+	[RST_BUS_MMC2]		= { 0x2c0, BIT(10) },
+	[RST_BUS_MMC3]		= { 0x2c0, BIT(11) },
 	[RST_BUS_OTG]		= { 0x2c0, BIT(25) },
 	[RST_BUS_EHCI0]		= { 0x2c0, BIT(26) },
 	[RST_BUS_EHCI1]		= { 0x2c0, BIT(27) },

drivers/clk/sunxi/clk_v3s.c +3 -0

index e0d757debe..6eeec201a2 100644
@@ -28,6 +28,9 @@ static struct ccu_clk_map v3s_clks[] = {
 static struct ccu_reset_map v3s_resets[] = {
 	[RST_USB_PHY0]		= { 0x0cc, BIT(0) },
 
+	[RST_BUS_MMC0]		= { 0x2c0, BIT(8) },
+	[RST_BUS_MMC1]		= { 0x2c0, BIT(9) },
+	[RST_BUS_MMC2]		= { 0x2c0, BIT(10) },
 	[RST_BUS_OTG]		= { 0x2c0, BIT(24) },
 };

Signature · 1 line

2.18.0.321.gffc6fa0e3

Maxime Ripard

2018-08-20 11:28 UTC #28 lore raw

PATCH v3 20/58 clk: sunxi: Implement AHB bus MMC resets

Quoted 5 lines · Jagan Teki

Implement AHB bus MMC resets for all Allwinner SoC clock drivers via reset map descriptor table.
Cc Jaehoon Chung <[email protected]>
Signed-off-by Jagan Teki <[email protected]>

That should be merged in the reset driver patches.

Maxime

Signature · 10 lines

Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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Jagan Teki

author

2018-08-19 13:56 UTC #29 lore raw

PATCH v3 21/58 reset: Add get reset by name optionally

In reply to Jagan Teki

Reset is an optional for some controllers with some families of CPU's with same SoC where the common IP driver can handle to drive the entire SoC families. optional reset get by name is useful for those drivers to make common way of reset handling.

Example, In Allwinner SoC with MMC controllers has no reset for Sun4i, 5i, 7i but reset have reset.

Cc Simon Glass <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/reset/reset-uclass.c | 18 ++++++++++++++++++
 include/reset.h              | 25 +++++++++++++++++++++++++
 2 files changed, 43 insertions(+)

drivers/reset/reset-uclass.c +18 -0

index 99881b8b99..6320efcb49 100644
@@ -138,6 +138,24 @@ int reset_get_by_name(struct udevice *dev, const char *name,
 	return reset_get_by_index(dev, index, reset_ctl);
 }
 
+int reset_get_by_name_optional(struct udevice *dev, const char *name,
+			       struct reset_ctl *reset_ctl, bool optional)
+{
+	int index;
+
+	debug("%s(dev=%p, name=%s, reset_ctl=%p)\n", __func__, dev, name,
+	      reset_ctl);
+	reset_ctl->dev = NULL;
+
+	index = dev_read_stringlist_search(dev, "reset-names", name);
+	if (index < 0) {
+		debug("fdt_stringlist_search() failed: %d\n", index);
+		return optional ? 0 : index;
+	}
+
+	return reset_get_by_index(dev, index, reset_ctl);
+}
+
 int reset_request(struct reset_ctl *reset_ctl)
 {
 	struct reset_ops *ops = reset_dev_ops(reset_ctl->dev);

include/reset.h +25 -0

index a7bbc1c331..a5af31f549 100644
@@ -132,6 +132,23 @@ int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk);
 int reset_get_by_name(struct udevice *dev, const char *name,
 		      struct reset_ctl *reset_ctl);
 
+/**
+ * reset_get_by_name_optional - Get/request a reset signal by name optionally.
+ *
+ * This look up and requests a reset signal similar to reset_get_by_name()
+ * but with optional flag.
+ *
+ * @dev:	The client device.
+ * @name:	The name of the reset signal to request, within the client's
+ *		list of reset signals.
+ * @reset_ctl:	A pointer to a reset control struct to initialize.
+ * @optional:	Optional flag, true if reset is optional, false if reset is
+ *		necessary which is same as reset_get_by_name()
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_get_by_name_optional(struct udevice *dev, const char *name,
+			       struct reset_ctl *reset_ctl, bool optional);
+
 /**
  * reset_request - Request a reset signal.
  *

@@ -254,6 +271,14 @@ static inline int reset_get_by_name(struct udevice *dev, const char *name,
 	return -ENOTSUPP;
 }
 
+static inline int reset_get_by_name_optional(struct udevice *dev,
+					     const char *name,
+					     struct reset_ctl *reset_ctl,
+					     bool optional)
+{
+	return -ENOTSUPP;
+}
+
 static inline int reset_free(struct reset_ctl *reset_ctl)
 {
 	return 0;

Signature · 1 line

2.18.0.321.gffc6fa0e3

Maxime Ripard

2018-08-20 11:34 UTC #30 lore raw

PATCH v3 21/58 reset: Add get reset by name optionally

Quoted 7 lines · Jagan Teki

Reset is an optional for some controllers with some families of CPU's with same SoC where the common IP driver can handle to drive the entire SoC families. optional reset get by name is useful for those drivers to make common way of reset handling.
Example, In Allwinner SoC with MMC controllers has no reset for Sun4i, 5i, 7i but reset have reset.

So, in other words, it's not needed for the A10, A20 and A13, but needed for all the others. It's not optional then, it's useless in one case, and mandatory in the other.

Maxime

Signature · 10 lines

Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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Jagan Teki

author

2018-08-19 13:56 UTC #31 lore raw

PATCH v3 22/58 reset: Add reset valid

In reply to Jagan Teki

Add reset_valid to check whether given reset is valid or not.

Cc Simon Glass <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 include/reset.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

include/reset.h +11 -0

index a5af31f549..70130bb886 100644
@@ -315,4 +315,15 @@ static inline int reset_release_bulk(struct reset_ctl_bulk *bulk)
 }
 #endif
 
+/**
+ * reset_valid() - check if reset is valid
+ *
+ * @reset_ctl:		the reset to check
+ * @return TRUE if valid, or FALSE
+ */
+static inline bool reset_valid(struct reset_ctl *reset_ctl)
+{
+	return !!reset_ctl->dev;
+}
+
 #endif

Signature · 1 line

2.18.0.321.gffc6fa0e3

Simon Glass

2018-08-23 10:44 UTC #32 lore raw

PATCH v3 22/58 reset: Add reset valid

Quoted 10 lines · Jagan Teki

Add reset_valid to check whether given reset is valid or not.
Cc Simon Glass <[email protected]>
Signed-off-by Jagan Teki <[email protected]>
---
 include/reset.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

Reviewed-by Simon Glass <[email protected]>

Jagan Teki

author

2018-08-19 13:56 UTC #33 lore raw

PATCH v3 23/58 clk: sunxi: Add Allwinner H6 CLK, RESET driver

In reply to Jagan Teki

Add initial clock, reset driver for Allwinner H6.

- Implement MMC clocking like AHB bus, MMC clocks
via clock map descriptor table.
- Implement AHB bus MMC resets via reset map
descriptor table.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/Kconfig  |  7 ++++
 drivers/clk/sunxi/Makefile |  1 +
 drivers/clk/sunxi/clk_h6.c | 73 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 81 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk_h6.c

drivers/clk/sunxi/Kconfig +7 -0

index a6f84e9e56..736a61fbc0 100644
@@ -72,4 +72,11 @@ config CLK_SUN50I_A64
 	  This enables common clock driver support for platforms based
 	  on Allwinner A64 SoC.
 
+config CLK_SUN50I_H6
+	bool "Clock driver for Allwinner H6"
+	default MACH_SUN50I_H6
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner H6 SoC.
+
 endif # CLK_SUNXI

drivers/clk/sunxi/Makefile +1 -0

index fbd43527a6..7f8af8f36b 100644
@@ -15,3 +15,4 @@ obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
 obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o
 obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
+obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o

drivers/clk/sunxi/clk_h6.c new file +73 -0

73 lines not on this page · raw message

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #34 lore raw

PATCH v3 24/58 arm64: allwinner: dts: h6: fix Pine H64 MMC bus width

In reply to Jagan Teki

Currently the enabled MMC controllers on Pine H64 do not have bus-width set, which make them fall back to 1-bit mode and become quite slow.

Fix this by add the corresponding bus-width properties.

Same commit is there in mailing-list, but yet to merge, commit fb8971bea0910a3172cd8ce75ccc01b50104ebf7

Author: Icenowy Zheng <[email protected]>
Date:   Thu Jul 26 12:41:27 2018 +0800

arm64: allwinner: dts: h6: fix Pine H64 MMC bus width

Cc Icenowy Zheng <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/dts/sun50i-h6-pine-h64.dts | 2 ++
 1 file changed, 2 insertions(+)

arch/arm/dts/sun50i-h6-pine-h64.dts +2 -0

index ceffc40810..48daec7f78 100644
@@ -46,6 +46,7 @@
 	pinctrl-0 = <&mmc0_pins>;
 	vmmc-supply = <&reg_cldo1>;
 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+	bus-width = <4>;
 	status = "okay";
 };

@@ -56,6 +57,7 @@
 	vqmmc-supply = <&reg_bldo2>;
 	non-removable;
 	cap-mmc-hw-reset;
+	bus-width = <8>;
 	status = "okay";
 };

Signature · 1 line

2.18.0.321.gffc6fa0e3

Maxime Ripard

2018-08-20 11:35 UTC #35 lore raw

PATCH v3 24/58 arm64: allwinner: dts: h6: fix Pine H64 MMC bus width

Quoted 7 lines · Jagan Teki

Currently the enabled MMC controllers on Pine H64 do not have bus-width set, which make them fall back to 1-bit mode and become quite slow.
Fix this by add the corresponding bus-width properties.
Same commit is there in mailing-list, but yet to merge, commit fb8971bea0910a3172cd8ce75ccc01b50104ebf7

Quoted 7 lines

Author: Icenowy Zheng <[email protected]>
Date:   Thu Jul 26 12:41:27 2018 +0800
arm64: allwinner: dts: h6: fix Pine H64 MMC bus width
Cc Icenowy Zheng <[email protected]>
Signed-off-by Jagan Teki <[email protected]>

That also has nothing to do with this serie. Please send independant patches independantly.

Maxime

Signature · 10 lines

Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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Jagan Teki

author

2018-08-20 11:39 UTC #36 lore raw

PATCH v3 24/58 arm64: allwinner: dts: h6: fix Pine H64 MMC bus width

Quoted 11 lines · Maxime Ripard

Quoted 10 lines · Jagan Teki
Currently the enabled MMC controllers on Pine H64 do not have bus-width set, which make them fall back to 1-bit mode and become quite slow.
Fix this by add the corresponding bus-width properties.
Same commit is there in mailing-list, but yet to merge, commit fb8971bea0910a3172cd8ce75ccc01b50104ebf7
Author: Icenowy Zheng <[email protected]>
Date:   Thu Jul 26 12:41:27 2018 +0800

Quoted 7 lines

Quoted 4 lines
arm64: allwinner: dts: h6: fix Pine H64 MMC bus width
Cc Icenowy Zheng <[email protected]>
Signed-off-by Jagan Teki <[email protected]>
That also has nothing to do with this serie. Please send independant patches independantly.

This change required for U-Boot proper to detect mmc0, mmc2 with new CLK, RESET and DM_MMC

Maxime Ripard

2018-08-20 14:16 UTC #37 lore raw

PATCH v3 24/58 arm64: allwinner: dts: h6: fix Pine H64 MMC bus width

Quoted 15 lines · Jagan Teki

Quoted 13 lines · Maxime Ripard
Quoted 12 lines · Jagan Teki
Currently the enabled MMC controllers on Pine H64 do not have bus-width set, which make them fall back to 1-bit mode and become quite slow.
Fix this by add the corresponding bus-width properties.
Same commit is there in mailing-list, but yet to merge, commit fb8971bea0910a3172cd8ce75ccc01b50104ebf7
Author: Icenowy Zheng <[email protected]>
Date:   Thu Jul 26 12:41:27 2018 +0800
arm64: allwinner: dts: h6: fix Pine H64 MMC bus width

Quoted 8 lines

Quoted 5 lines
Quoted 2 lines
Cc Icenowy Zheng <[email protected]>
Signed-off-by Jagan Teki <[email protected]>
That also has nothing to do with this serie. Please send independant patches independantly.
This change required for U-Boot proper to detect mmc0, mmc2 with new CLK, RESET and DM_MMC

No, it will work just fine without that patch, no matter if we're having DM_MMC, RESET or CLK. What we won't have is optimal data rates, but this doesn't really have anything to do with it.

Maxime

Signature · 10 lines

Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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Jagan Teki

author

2018-08-19 13:56 UTC #38 lore raw

PATCH v3 25/58 sunxi: h6: Enable CLK, RESET

In reply to Jagan Teki

Enable clock and reset drivers for Allwinner H6 SoC.

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/mach-sunxi/Kconfig | 1 +
 1 file changed, 1 insertion(+)

arch/arm/mach-sunxi/Kconfig +1 -0

index dce81b7d53..da7f6b1e95 100644
@@ -303,6 +303,7 @@ config MACH_SUN50I_H5
 config MACH_SUN50I_H6
 	bool "sun50i (Allwinner H6)"
 	select ARM64
+	select CLK
 	select SUPPORT_SPL
 	select FIT
 	select SPL_LOAD_FIT

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #39 lore raw

PATCH v3 26/58 dm: mmc: sunxi: Add CLK and RESET support

In reply to Jagan Teki

Now CLK and RESET driver for Allwinner SoC are available, so add the relevant operations on mmc sunxi driver.

Cc Jaehoon Chung <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/mmc/sunxi_mmc.c | 60 +++++++++++++++++++++++++++++++----------
 1 file changed, 46 insertions(+), 14 deletions(-)

drivers/mmc/sunxi_mmc.c +46 ~~-14~~

index bf82014a64..3011ec9498 100644
@@ -8,10 +8,12 @@
  */
 
 #include <common.h>
+#include <clk.h>
 #include <dm.h>
 #include <errno.h>
 #include <malloc.h>
 #include <mmc.h>
+#include <reset.h>
 #include <asm/io.h>
 #include <asm/arch/ccu.h>
 #include <asm/arch/clock.h>

@@ -26,8 +28,12 @@ struct sunxi_mmc_plat {
 };
 
 struct sunxi_mmc_priv {
+#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(CLK)
+	struct clk mmc_clk;
+#else
 	unsigned mmc_no;
 	uint32_t *mclkreg;
+#endif
 	unsigned fatal_err;
 	struct gpio_desc cd_gpio;	/* Change Detect GPIO */
 	int cd_inverted;		/* Inverted Card Detect */

@@ -188,6 +194,15 @@ int mmc_clk_set_rate(void *base, u32 bit, ulong rate)
 static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
 {
 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(CLK)
+	int ret;
+
+	ret = clk_set_rate(&priv->mmc_clk, hz);
+	if (ret) {
+		dev_err(dev, "failed to set rate for mmc_clk\n");
+		return ret;
+	}
+
+	return ret;
 #else
 	if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))
 		new_mode = true;

@@ -379,7 +394,7 @@ static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv,
 		writel(data->blocks * data->blocksize, &priv->reg->bytecnt);
 	}
 
-	debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv->mmc_no,
+	debug("mmc cmd %d(0x%08x), arg 0x%08x\n",
 	      cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
 	writel(cmd->cmdarg, &priv->reg->arg);

@@ -591,8 +606,8 @@ static int sunxi_mmc_probe(struct udevice *dev)
 	struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
 	struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 	struct mmc_config *cfg = &plat->cfg;
-	struct ofnode_phandle_args args;
-	u32 *gate_reg;
+	struct clk ahb_clk;
+	struct reset_ctl reset;
 	int bus_width, ret;
 
 	cfg->name = dev->name;

@@ -615,20 +630,37 @@ static int sunxi_mmc_probe(struct udevice *dev)
 
 	priv->reg = (void *)dev_read_addr(dev);
 
-	/* We don't have a sunxi clock driver so find the clock address here */
-	ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
-					  1, &args);
-	if (ret)
+	ret = clk_get_by_name(dev, "ahb", &ahb_clk);
+	if (ret) {
+		dev_err(dev, "falied to get ahb clock\n");
 		return ret;
-	priv->mclkreg = (u32 *)ofnode_get_addr(args.node);
+	}
 
-	ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
-					  0, &args);
-	if (ret)
+	ret = clk_get_by_name(dev, "mmc", &priv->mmc_clk);
+	if (ret) {
+		dev_err(dev, "falied to get mmc clock\n");
 		return ret;
-	gate_reg = (u32 *)ofnode_get_addr(args.node);
-	setbits_le32(gate_reg, 1 << args.args[0]);
-	priv->mmc_no = args.args[0] - 8;
+	}
+
+	ret = reset_get_by_name_optional(dev, "ahb", &reset, true);
+	if (ret) {
+		dev_err(dev, "falied to get ahb reset\n");
+		return ret;
+	}
+
+	ret = clk_enable(&ahb_clk);
+	if (ret) {
+		dev_err(dev, "failed to enable ahb clock\n");
+		return ret;
+	}
+
+	if (reset_valid(&reset)) {
+		ret = reset_deassert(&reset);
+		if (ret) {
+			dev_err(dev, "failed to deassert ahb reset\n");
+			return ret;
+		}
+	}
 
 	ret = mmc_set_mod_clk(priv, 24000000);
 	if (ret)

Signature · 1 line

2.18.0.321.gffc6fa0e3

Maxime Ripard

2018-08-20 11:36 UTC #40 lore raw

PATCH v3 26/58 dm: mmc: sunxi: Add CLK and RESET support

drivers/mmc/sunxi_mmc.c static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv, · line 398

Quoted 3 lines · Jagan Teki

drivers/mmc/sunxi_mmc.c +1 -1

-	debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv->mmc_no,
+	debug("mmc cmd %d(0x%08x), arg 0x%08x\n",
 	      cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);

Why is priv->mmc_no removed?

Maxime

Signature · 10 lines

Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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Jagan Teki

author

2018-08-19 13:56 UTC #41 lore raw

PATCH v3 27/58 fastboot: sunxi: Update fastboot mmc default device

In reply to Jagan Teki

Usually eMMC is default mmc device for fastboot.

By enabling DM_MMC, the mmc devices are probed as per DT status not with respect to MMC_SUNXI_SLOT_EXTRA in U-Boot proper.

Allwinner SoC has maximum of 4 mmc controllers start from mmc0...mmc3 on which mmc2 can be used an eMMC controller eventhough mmc3 some boards used as eMMC.

So, update the default fastboot device as 2 to make the standard usage irrespective of DT node status.

Other corner cases like different device usage, or specific mmc node status is not enabled in order in DTS must explicitly add config on the specific defconfig file.

Cc Olliver Schinagl <[email protected]>

Cc Chen-Yu Tsai <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 configs/A20-OLinuXino-Lime2-eMMC_defconfig   | 1 +
 configs/A20-Olimex-SOM204-EVB-eMMC_defconfig | 1 +
 configs/Sinlinx_SinA33_defconfig             | 1 +
 configs/amarula_a64_relic_defconfig          | 1 +
 configs/parrot_r16_defconfig                 | 1 +
 drivers/fastboot/Kconfig                     | 3 +--
 6 files changed, 6 insertions(+), 2 deletions(-)

configs/A20-OLinuXino-Lime2-eMMC_defconfig +1 -0

index 2851a461e8..8cedf9cf24 100644
@@ -30,4 +30,5 @@ CONFIG_SCSI=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/A20-Olimex-SOM204-EVB-eMMC_defconfig +1 -0

index 3bb8c4c7e6..c96d7ada7c 100644
@@ -30,4 +30,5 @@ CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Sinlinx_SinA33_defconfig +1 -0

index 7f5aaab5fb..80741b58f9 100644
@@ -22,5 +22,6 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
 CONFIG_USB_FUNCTION_MASS_STORAGE=y

configs/amarula_a64_relic_defconfig +1 -0

index b72cbfabc6..caeb3f6008 100644
@@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/parrot_r16_defconfig +1 -0

index 936f08185f..242886f78e 100644
@@ -20,5 +20,6 @@ CONFIG_CONS_INDEX=5
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
 CONFIG_USB_FUNCTION_MASS_STORAGE=y

drivers/fastboot/Kconfig +1 -2

index bc25ea1d9c..0e4b50e1cf 100644
@@ -87,8 +87,7 @@ endchoice
 config FASTBOOT_FLASH_MMC_DEV
 	int "Define FASTBOOT MMC FLASH default device"
 	depends on FASTBOOT_FLASH_MMC
-	default 0 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
-	default 1 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
+	default 2 if ARCH_SUNXI
 	help
 	  The fastboot "flash" command requires additional information
 	  regarding the non-volatile storage device. Define this to

Signature · 1 line

2.18.0.321.gffc6fa0e3

Maxime Ripard

2018-08-20 11:44 UTC #42 lore raw

PATCH v3 27/58 fastboot: sunxi: Update fastboot mmc default device

Quoted 13 lines · Jagan Teki

Usually eMMC is default mmc device for fastboot.
By enabling DM_MMC, the mmc devices are probed as per DT status not with respect to MMC_SUNXI_SLOT_EXTRA in U-Boot proper.
Allwinner SoC has maximum of 4 mmc controllers start from mmc0...mmc3 on which mmc2 can be used an eMMC controller eventhough mmc3 some boards used as eMMC.
So, update the default fastboot device as 2 to make the standard usage irrespective of DT node status.

Quoted 7 lines

Other corner cases like different device usage, or specific mmc node status is not enabled in order in DTS must explicitly add config on the specific defconfig file.
Cc Olliver Schinagl <[email protected]>
Cc Chen-Yu Tsai <[email protected]>
Signed-off-by Jagan Teki <[email protected]>

This breaks all existing users, since if DM_MMC isn't set (and it isn't at the moment), the MMC IDs won't change, and you're changing it from either 0 or 1 to 2.

Can't we have a DT property instead? It looks much better than having to deal with a non stable ID in Kconfig.

Maxime

Signature · 10 lines

Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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Jagan Teki

author

2018-08-21 16:57 UTC #43 lore raw

PATCH v3 27/58 fastboot: sunxi: Update fastboot mmc default device

Quoted 18 lines · Maxime Ripard

Quoted 17 lines · Jagan Teki
Usually eMMC is default mmc device for fastboot.
By enabling DM_MMC, the mmc devices are probed as per DT status not with respect to MMC_SUNXI_SLOT_EXTRA in U-Boot proper.
Allwinner SoC has maximum of 4 mmc controllers start from mmc0...mmc3 on which mmc2 can be used an eMMC controller eventhough mmc3 some boards used as eMMC.
So, update the default fastboot device as 2 to make the standard usage irrespective of DT node status.
Other corner cases like different device usage, or specific mmc node status is not enabled in order in DTS must explicitly add config on the specific defconfig file.

Quoted 7 lines

Quoted 3 lines
Cc Olliver Schinagl <[email protected]>
Cc Chen-Yu Tsai <[email protected]>
Signed-off-by Jagan Teki <[email protected]>
This breaks all existing users, since if DM_MMC isn't set (and it isn't at the moment), the MMC IDs won't change, and you're changing it from either 0 or 1 to 2.

True, bisectable issue. will take care on next version.

Quoted 3 lines

Can't we have a DT property instead? It looks much better than having to deal with a non stable ID in Kconfig.

What do you mean by DT property handle? mmc2 is eMMC in all sunXi isn't? ie reason I make it default.

Maxime Ripard

2018-08-22 16:43 UTC #44 lore raw

PATCH v3 27/58 fastboot: sunxi: Update fastboot mmc default device

Quoted 28 lines · Jagan Teki

Quoted 18 lines · Maxime Ripard
Quoted 17 lines · Jagan Teki
Usually eMMC is default mmc device for fastboot.
By enabling DM_MMC, the mmc devices are probed as per DT status not with respect to MMC_SUNXI_SLOT_EXTRA in U-Boot proper.
Allwinner SoC has maximum of 4 mmc controllers start from mmc0...mmc3 on which mmc2 can be used an eMMC controller eventhough mmc3 some boards used as eMMC.
So, update the default fastboot device as 2 to make the standard usage irrespective of DT node status.
Other corner cases like different device usage, or specific mmc node status is not enabled in order in DTS must explicitly add config on the specific defconfig file.
Quoted 7 lines
Quoted 3 lines
Cc Olliver Schinagl <[email protected]>
Cc Chen-Yu Tsai <[email protected]>
Signed-off-by Jagan Teki <[email protected]>
This breaks all existing users, since if DM_MMC isn't set (and it isn't at the moment), the MMC IDs won't change, and you're changing it from either 0 or 1 to 2.

Quoted 8 lines

True, bisectable issue. will take care on next version.
Quoted 3 lines
Can't we have a DT property instead? It looks much better than having to deal with a non stable ID in Kconfig.
What do you mean by DT property handle? mmc2 is eMMC in all sunXi isn't? ie reason I make it default.

I meant to select the fastboot and environment devices. That way, each board can select the one it wants in a truly deterministic way.

Maxime

Signature · 10 lines

Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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Jagan Teki

author

2018-08-27 09:20 UTC #45 lore raw

PATCH v3 27/58 fastboot: sunxi: Update fastboot mmc default device

Quoted 32 lines · Maxime Ripard

Quoted 31 lines · Jagan Teki
Quoted 18 lines · Maxime Ripard
Quoted 17 lines · Jagan Teki
Usually eMMC is default mmc device for fastboot.
By enabling DM_MMC, the mmc devices are probed as per DT status not with respect to MMC_SUNXI_SLOT_EXTRA in U-Boot proper.
Allwinner SoC has maximum of 4 mmc controllers start from mmc0...mmc3 on which mmc2 can be used an eMMC controller eventhough mmc3 some boards used as eMMC.
So, update the default fastboot device as 2 to make the standard usage irrespective of DT node status.
Other corner cases like different device usage, or specific mmc node status is not enabled in order in DTS must explicitly add config on the specific defconfig file.
Quoted 7 lines
Quoted 3 lines
Cc Olliver Schinagl <[email protected]>
Cc Chen-Yu Tsai <[email protected]>
Signed-off-by Jagan Teki <[email protected]>
This breaks all existing users, since if DM_MMC isn't set (and it isn't at the moment), the MMC IDs won't change, and you're changing it from either 0 or 1 to 2.
True, bisectable issue. will take care on next version.
Quoted 1 line

Quoted 8 lines

Quoted 5 lines
Quoted 2 lines
Can't we have a DT property instead? It looks much better than having to deal with a non stable ID in Kconfig.
What do you mean by DT property handle? mmc2 is eMMC in all sunXi isn't? ie reason I make it default.
I meant to select the fastboot and environment devices. That way, each board can select the one it wants in a truly deterministic way.

ie what get_env_fat_dev_part is doing. Identify the dev no.of initialized mmc or emmc. are you referring something like this?

Maxime Ripard

2018-08-31 10:14 UTC #46 lore raw

PATCH v3 27/58 fastboot: sunxi: Update fastboot mmc default device

Quoted 37 lines · Jagan Teki

Quoted 35 lines · Maxime Ripard
Quoted 34 lines · Jagan Teki
Quoted 18 lines · Maxime Ripard
Quoted 17 lines · Jagan Teki
Usually eMMC is default mmc device for fastboot.
By enabling DM_MMC, the mmc devices are probed as per DT status not with respect to MMC_SUNXI_SLOT_EXTRA in U-Boot proper.
Allwinner SoC has maximum of 4 mmc controllers start from mmc0...mmc3 on which mmc2 can be used an eMMC controller eventhough mmc3 some boards used as eMMC.
So, update the default fastboot device as 2 to make the standard usage irrespective of DT node status.
Other corner cases like different device usage, or specific mmc node status is not enabled in order in DTS must explicitly add config on the specific defconfig file.
Quoted 7 lines
Quoted 3 lines
Cc Olliver Schinagl <[email protected]>
Cc Chen-Yu Tsai <[email protected]>
Signed-off-by Jagan Teki <[email protected]>
This breaks all existing users, since if DM_MMC isn't set (and it isn't at the moment), the MMC IDs won't change, and you're changing it from either 0 or 1 to 2.
True, bisectable issue. will take care on next version.
Quoted 3 lines
Can't we have a DT property instead? It looks much better than having to deal with a non stable ID in Kconfig.

Quoted 8 lines

Quoted 5 lines
Quoted 2 lines
What do you mean by DT property handle? mmc2 is eMMC in all sunXi isn't? ie reason I make it default.
I meant to select the fastboot and environment devices. That way, each board can select the one it wants in a truly deterministic way.
ie what get_env_fat_dev_part is doing. Identify the dev no.of initialized mmc or emmc. are you referring something like this?

Yep, but through a DT property instead of some code.

Maxime

Signature · 10 lines

Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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Olliver Schinagl

2018-08-22 18:56 UTC #47 lore raw

PATCH v3 27/58 fastboot: sunxi: Update fastboot mmc default device

In reply to Jagan Teki

Quoted 26 lines · Jagan Teki

Quoted 18 lines · Maxime Ripard
Quoted 17 lines · Jagan Teki
Usually eMMC is default mmc device for fastboot.
By enabling DM_MMC, the mmc devices are probed as per DT status not with respect to MMC_SUNXI_SLOT_EXTRA in U-Boot proper.
Allwinner SoC has maximum of 4 mmc controllers start from mmc0...mmc3 on which mmc2 can be used an eMMC controller eventhough mmc3 some boards used as eMMC.
So, update the default fastboot device as 2 to make the standard usage irrespective of DT node status.
Other corner cases like different device usage, or specific mmc node status is not enabled in order in DTS must explicitly add config on the specific defconfig file.
Quoted 6 lines
Quoted 3 lines
Cc Olliver Schinagl <[email protected]>
Cc Chen-Yu Tsai <[email protected]>
Signed-off-by Jagan Teki <[email protected]>
This breaks all existing users, since if DM_MMC isn't set (and it isn't at the moment), the MMC IDs won't change, and you're changing it from either 0 or 1 to 2.

Quoted 6 lines

True, bisectable issue. will take care on next version.
Quoted 2 lines
Can't we have a DT property instead? It looks much better than having to deal with a non stable ID in Kconfig.
What do you mean by DT property handle? mmc2 is eMMC in all sunXi isn't? ie reason I make it default.

That's absurdly naive :)

eMMC is whatever the board designer decides to hook it up to (and one can even argue that there could be vendor trees that also have strange designs)

While from a 'hacker' standpoint mmc0 SD, mmc2 eMMC makes tons of sense, as those are the allwinner default bootable mmc interfaces, a proper product may opt to put eMMC on mmc0 for 'security reasons'. E.g. secure boot and what not. (Lets not get into discussions about how to secure our platform or how secure it really is)

Further more, a designed board may use an SPI to boot, and end up with eMMC on mmc3 due to the fact all other pins are in use.

Making this assumption that mmc2 is always eMMC (if mmc is used) is very naive in my opinion and may bite us in the ass eventually.

Having a default, and letting it be overridable, is not a big issue of course :)

Olliver

Jagan Teki

author

2018-08-19 13:56 UTC #48 lore raw

PATCH v3 28/58 env: fat: Add func to get fat device, partition

In reply to Jagan Teki

Get a fat device and partition for multiple families of same SoC type can be difficult to handle with static CONFIG_ENV_FAT_DEVICE_AND_PART via Kconfig.

So, add a generic weak function to get the device, partition and give relevant users to define their own logic to setup fat device and partition.

Signed-off-by Jagan Teki <[email protected]>

---
 env/fat.c     | 9 +++++++--
 include/fat.h | 1 +
 2 files changed, 8 insertions(+), 2 deletions(-)

env/fat.c +7 -2

index 7f74c64dfe..2147cc0326 100644
@@ -30,6 +30,11 @@
 # endif
 #endif
 
+__weak char *get_env_fat_dev_part(void)
+{
+	return CONFIG_ENV_FAT_DEVICE_AND_PART;
+}
+
 #ifdef CMD_SAVEENV
 static int env_fat_save(void)
 {

@@ -45,7 +50,7 @@ static int env_fat_save(void)
 		return err;
 
 	part = blk_get_device_part_str(CONFIG_ENV_FAT_INTERFACE,
-					CONFIG_ENV_FAT_DEVICE_AND_PART,
+					get_env_fat_dev_part(),
 					&dev_desc, &info, 1);
 	if (part < 0)
 		return 1;

@@ -92,7 +97,7 @@ static int env_fat_load(void)
 #endif
 
 	part = blk_get_device_part_str(CONFIG_ENV_FAT_INTERFACE,
-					CONFIG_ENV_FAT_DEVICE_AND_PART,
+					get_env_fat_dev_part(),
 					&dev_desc, &info, 1);
 	if (part < 0)
 		goto err_env_relocate;

include/fat.h +1 -0

index 09e1423685..0552fa54b5 100644
@@ -185,6 +185,7 @@ static inline u32 sect_to_clust(fsdata *fsdata, int sect)
 	return (sect - fsdata->data_begin) / fsdata->clust_size;
 }
 
+char *get_env_fat_dev_part(void);
 int file_fat_detectfs(void);
 int fat_exists(const char *filename);
 int fat_size(const char *filename, loff_t *size);

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #49 lore raw

PATCH v3 29/58 sunxi: Get fat device wrt boot device, 'auto' partition

In reply to Jagan Teki

Setting fat device, partition using CONFIG_ENV_FAT_DEVICE_AND_PART via Kconfig option is difficult to maintain since Allwinner support more than one mmc controllers with SD and eMMC.

So, add dynamic function to get the device based on the boot device source with 'auto' partition.

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/mach-sunxi/board.c | 50 +++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

arch/arm/mach-sunxi/board.c +50 -0

index d22a84ea6b..cf174bd0a3 100644
@@ -10,6 +10,7 @@
  */
 
 #include <common.h>
+#include <fat.h>
 #include <mmc.h>
 #include <i2c.h>
 #include <serial.h>

@@ -253,6 +254,55 @@ uint32_t sunxi_get_boot_device(void)
 	return -1;		/* Never reached */
 }
 
+#if CONFIG_IS_ENABLED(ENV_IS_IN_FAT)
+static int find_first_sd_device(void)
+{
+	struct mmc *mmc;
+	int i;
+
+	for (i = 0; (mmc = find_mmc_device(i)); i++) {
+		if (!mmc_init(mmc) && IS_SD(mmc))
+			return i;
+	}
+
+	return -ENODEV;
+}
+
+static int find_first_mmc_device(void)
+{
+	struct mmc *mmc;
+	int i;
+
+	for (i = 0; (mmc = find_mmc_device(i)); i++) {
+		if (!mmc_init(mmc) && IS_MMC(mmc))
+			return i;
+	}
+
+	return -ENODEV;
+}
+
+char *get_env_fat_dev_part(void)
+{
+	int devno, boot_source;
+	static char dev_part[10];
+
+	boot_source = readb(SPL_ADDR + 0x28);
+	switch (boot_source) {
+	case SUNXI_BOOTED_FROM_MMC0:
+		devno = find_first_sd_device();
+		break;
+	case SUNXI_BOOTED_FROM_MMC2:
+		devno = find_first_mmc_device();
+		break;
+	default:
+		return CONFIG_ENV_FAT_DEVICE_AND_PART;
+        }
+
+	snprintf(dev_part, sizeof(dev_part), "%d:auto", devno);
+	return dev_part;
+}
+#endif
+
 #ifdef CONFIG_SPL_BUILD
 u32 spl_boot_device(void)
 {

Signature · 1 line

2.18.0.321.gffc6fa0e3

Maxime Ripard

2018-08-20 11:45 UTC #50 lore raw

PATCH v3 29/58 sunxi: Get fat device wrt boot device, 'auto' partition

Quoted 58 lines · Jagan Teki

Setting fat device, partition using CONFIG_ENV_FAT_DEVICE_AND_PART via Kconfig option is difficult to maintain since Allwinner support more than one mmc controllers with SD and eMMC.

So, add dynamic function to get the device based on the boot device source with 'auto' partition.

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/mach-sunxi/board.c | 50 +++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

arch/arm/mach-sunxi/board.c +31 -0

index d22a84ea6b..cf174bd0a3 100644
@@ -10,6 +10,7 @@
  */
 
 #include <common.h>
+#include <fat.h>
 #include <mmc.h>
 #include <i2c.h>
 #include <serial.h>

@@ -253,6 +254,55 @@ uint32_t sunxi_get_boot_device(void)
 	return -1;		/* Never reached */
 }
 
+#if CONFIG_IS_ENABLED(ENV_IS_IN_FAT)
+static int find_first_sd_device(void)
+{
+	struct mmc *mmc;
+	int i;
+
+	for (i = 0; (mmc = find_mmc_device(i)); i++) {
+		if (!mmc_init(mmc) && IS_SD(mmc))
+			return i;
+	}
+
+	return -ENODEV;
+}
+
+static int find_first_mmc_device(void)
+{
+	struct mmc *mmc;
+	int i;
+
+	for (i = 0; (mmc = find_mmc_device(i)); i++) {
+		if (!mmc_init(mmc) && IS_MMC(mmc))
+			return i;
+	}
+
+	return -ENODEV;
+}
+
+char *get_env_fat_dev_part(void)
+{
+	int devno, boot_source;

arch/arm/mach-sunxi/board.c uint32_t sunxi_get_boot_device(void) · line 296

Quoted 10 lines

arch/arm/mach-sunxi/board.c +10 -0

+	static char dev_part[10];
+
+	boot_source = readb(SPL_ADDR + 0x28);
+	switch (boot_source) {
+	case SUNXI_BOOTED_FROM_MMC0:
+		devno = find_first_sd_device();
+		break;
+	case SUNXI_BOOTED_FROM_MMC2:
+		devno = find_first_mmc_device();
+		break;

You're changing the behaviour from having the environment fixed in a particular device to detecting that device at runtime.

Again, can't we use a DT property for this instead?

Maxime

Signature · 10 lines

Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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Jagan Teki

author

2018-08-19 13:56 UTC #51 lore raw

PATCH v3 30/58 env: sunxi: Don't update fat dev, part wrt MMC_SUNXI_SLOT_EXTRA

In reply to Jagan Teki

By enabling DM_MMC, the mmc devices are probed as per DT status not with respect to MMC_SUNXI_SLOT_EXTRA in U-Boot proper.

Allwinner now support runtime relevant fat device via get_env_fat_dev_part, so add 0:auto as a default dev, part for sunxi platform and drop unneeded MMC_SUNXI_SLOT_EXTRA conditions.

Signed-off-by Jagan Teki <[email protected]>

---
 env/Kconfig | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

env/Kconfig +1 -2

index be99efb937..2bbb02e3bb 100644
@@ -373,8 +373,7 @@ config ENV_FAT_DEVICE_AND_PART
 	depends on ENV_IS_IN_FAT
 	default "0:1" if TI_COMMON_CMD_OPTIONS
 	default "0:auto" if ARCH_ZYNQMP
-	default "0:auto" if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
-	default "1:auto" if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
+	default "0:auto" if ARCH_SUNXI
 	default "0" if ARCH_AT91
 	help
 	  Define this to a string to specify the partition of the device. It can

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #52 lore raw

PATCH v3 31/58 sunxi: Add mmc 2, 3 bootenv devices

In reply to Jagan Teki

By enabling DM_MMC, the mmc devices are probed as per DT status not with respect to MMC_SUNXI_SLOT_EXTRA in U-Boot proper and eMMC can probed maximum device of 3, if all nodes mmc0, mmc1, mmc2 and mmc3 status's are 'okay'

This patch create bootcmd env for mmc2, mmc3 and start boot priority with mmc3...mmc0

Signed-off-by Jagan Teki <[email protected]>

---
 include/configs/sunxi-common.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

include/configs/sunxi-common.h +4 -4

index f1578d3754..176ee06036 100644
@@ -373,12 +373,15 @@ extern int soft_i2c_gpio_scl;
 	"ramdisk ram " RAMDISK_ADDR_R " 0x4000000\0"
 
 #ifdef CONFIG_MMC
-#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
 #define BOOTENV_DEV_MMC_AUTO(devtypeu, devtypel, instance)		\
 	BOOTENV_DEV_MMC(MMC, mmc, 0)					\
 	BOOTENV_DEV_MMC(MMC, mmc, 1)					\
+	BOOTENV_DEV_MMC(MMC, mmc, 2)					\
+	BOOTENV_DEV_MMC(MMC, mmc, 3)					\
 	"bootcmd_mmc_auto="						\
 		"if test ${mmc_bootdev} -eq 1; then "			\
+			"run bootcmd_mmc3; "				\
+			"run bootcmd_mmc2; "				\
 			"run bootcmd_mmc1; "				\
 			"run bootcmd_mmc0; "				\
 		"elif test ${mmc_bootdev} -eq 0; then "			\

@@ -391,9 +394,6 @@ extern int soft_i2c_gpio_scl;
 
 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC_AUTO, mmc_auto, na)
 #else
-#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
-#endif
-#else
 #define BOOT_TARGET_DEVICES_MMC(func)
 #endif

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #53 lore raw

PATCH v3 32/58 sunxi: A20: Enable DM_MMC

In reply to Jagan Teki

Enable DM_MMC for Allwinner A20 SoC.

Tested on A20-OLinuXino-LIME2.

Cc Stefan Mavrodiev <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/mach-sunxi/Kconfig | 1 +
 1 file changed, 1 insertion(+)

arch/arm/mach-sunxi/Kconfig +1 -0

index da7f6b1e95..cac6ed9503 100644
@@ -191,6 +191,7 @@ config MACH_SUN7I
 	select ARCH_SUPPORT_PSCI
 	select CLK
 	select DRAM_SUN4I
+	select DM_MMC if MMC
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #54 lore raw

PATCH v3 33/58 mmc: sunxi: Add mmc, emmc H5/A64 compatible

In reply to Jagan Teki

Added H5, A64 compatible for mmc and emmc.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/mmc/sunxi_mmc.c | 2 ++
 1 file changed, 2 insertions(+)

drivers/mmc/sunxi_mmc.c +2 -0

index 3011ec9498..5191a3e3dd 100644
@@ -697,6 +697,8 @@ static const struct udevice_id sunxi_mmc_ids[] = {
 	{ .compatible = "allwinner,sun4i-a10-mmc" },
 	{ .compatible = "allwinner,sun5i-a13-mmc" },
 	{ .compatible = "allwinner,sun7i-a20-mmc" },
+	{ .compatible = "allwinner,sun50i-a64-mmc" },
+	{ .compatible = "allwinner,sun50i-a64-emmc" },
 	{ }
 };

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #55 lore raw

PATCH v3 34/58 sunxi: H3_H5: Enable DM_MMC

In reply to Jagan Teki

Enable DM_MMC for Allwinner H3/H5 SoCs.

Tested on
H3: BPI-M2+
H5: Orangepi pc2, prime, zero+2

Tested-by Jagan Teki <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/mach-sunxi/Kconfig | 1 +
 1 file changed, 1 insertion(+)

arch/arm/mach-sunxi/Kconfig +1 -0

index cac6ed9503..2388718209 100644
@@ -134,6 +134,7 @@ config MACH_SUNXI_H3_H5
 	bool
 	select CLK
 	select DM_I2C
+	select DM_MMC if MMC
 	select PHY_SUN4I_USB
 	select SUNXI_DE2
 	select SUNXI_DRAM_DW

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #56 lore raw

PATCH v3 35/58 sunxi: A64: Enable DM_MMC

In reply to Jagan Teki

Enable DM_MMC for Allwinner A64 SoCs.

Tested on BPI-M64, Amarula A64-Relic

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/mach-sunxi/Kconfig | 1 +
 1 file changed, 1 insertion(+)

arch/arm/mach-sunxi/Kconfig +1 -0

index 2388718209..14cbc51040 100644
@@ -285,6 +285,7 @@ config MACH_SUN50I
 	select ARM64
 	select CLK
 	select DM_I2C
+	select DM_MMC if MMC
 	select PHY_SUN4I_USB
 	select SUNXI_DE2
 	select SUNXI_GEN_SUN6I

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #57 lore raw

PATCH v3 36/58 mmc: sunxi: Add A83T emmc compatible

In reply to Jagan Teki

Add emmc compatible for A83T SoC.

Cc VishnuPatekar <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/mmc/sunxi_mmc.c | 1 +
 1 file changed, 1 insertion(+)

drivers/mmc/sunxi_mmc.c +1 -0

index 5191a3e3dd..229a7b2811 100644
@@ -697,6 +697,7 @@ static const struct udevice_id sunxi_mmc_ids[] = {
 	{ .compatible = "allwinner,sun4i-a10-mmc" },
 	{ .compatible = "allwinner,sun5i-a13-mmc" },
 	{ .compatible = "allwinner,sun7i-a20-mmc" },
+	{ .compatible = "allwinner,sun8i-a83t-emmc" },
 	{ .compatible = "allwinner,sun50i-a64-mmc" },
 	{ .compatible = "allwinner,sun50i-a64-emmc" },
 	{ }

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #58 lore raw

PATCH v3 37/58 sunxi: A83T: Enable DM_MMC

In reply to Jagan Teki

Enable DM_MMC for Allwinner A83T SoC.

Tested on BPI-M3.

Cc VishnuPatekar <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/mach-sunxi/Kconfig | 1 +
 1 file changed, 1 insertion(+)

arch/arm/mach-sunxi/Kconfig +1 -0

index 14cbc51040..b6287fc00e 100644
@@ -230,6 +230,7 @@ config MACH_SUN8I_A83T
 	bool "sun8i (Allwinner A83T)"
 	select CPU_V7A
 	select CLK
+	select DM_MMC if MMC
 	select DRAM_SUN8I_A83T
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN6I

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #59 lore raw

PATCH v3 38/58 sunxi: V40: Enable DM_MMC

In reply to Jagan Teki

Enable DM_MMC for Allwinner V40 SoC.

Tested on BPI-M2 Ultra, BPI-M2 Berry.

Cc Lothar Felten <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/mach-sunxi/Kconfig | 1 +
 1 file changed, 1 insertion(+)

arch/arm/mach-sunxi/Kconfig +1 -0

index b6287fc00e..2828a33572 100644
@@ -254,6 +254,7 @@ config MACH_SUN8I_R40
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
 	select CLK
+	select DM_MMC if MMC
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
 	select SUNXI_DRAM_DW

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #60 lore raw

PATCH v3 39/58 sunxi: H6: Enable DM_MMC

In reply to Jagan Teki

Enable DM_MMC for Allwinner H6 SoC.

Tested-by Jagan Teki <[email protected]> # Opi-1+

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/mach-sunxi/Kconfig | 1 +
 1 file changed, 1 insertion(+)

arch/arm/mach-sunxi/Kconfig +1 -0

index 2828a33572..dd973cc821 100644
@@ -309,6 +309,7 @@ config MACH_SUN50I_H6
 	bool "sun50i (Allwinner H6)"
 	select ARM64
 	select CLK
+	select DM_MMC if MMC
 	select SUPPORT_SPL
 	select FIT
 	select SPL_LOAD_FIT

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #61 lore raw

PATCH v3 40/58 sunxi: A13/A31: Enable DM_MMC

In reply to Jagan Teki

Enable DM_MMC for Allwinner A13/A31 SoC.

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/mach-sunxi/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

arch/arm/mach-sunxi/Kconfig +2 -0

index dd973cc821..593999391a 100644
@@ -164,6 +164,7 @@ config MACH_SUN5I
 	select CLK
 	select ARM_CORTEX_CPU_IS_UP
 	select DRAM_SUN4I
+	select DM_MMC if MMC
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL

@@ -177,6 +178,7 @@ config MACH_SUN6I
 	select ARCH_SUPPORT_PSCI
 	select CLK
 	select DRAM_SUN6I
+	select DM_MMC if MMC
 	select PHY_SUN4I_USB
 	select SUN6I_P2WI
 	select SUN6I_PRCM

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #62 lore raw

PATCH v3 41/58 sunxi: A23/A33/V3S: Enable DM_MMC

In reply to Jagan Teki

Enable DM_MMC for Allwinner A23/A33/V3S SoC.

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/mach-sunxi/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

arch/arm/mach-sunxi/Kconfig +3 -0

index 593999391a..14d80d19c8 100644
@@ -207,6 +207,7 @@ config MACH_SUN8I_A23
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
 	select CLK
+	select DM_MMC if MMC
 	select DRAM_SUN8I_A23
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN6I

@@ -221,6 +222,7 @@ config MACH_SUN8I_A33
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
 	select CLK
+	select DM_MMC if MMC
 	select DRAM_SUN8I_A33
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN6I

@@ -269,6 +271,7 @@ config MACH_SUN8I_V3S
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
 	select CLK
+	select DM_MMC if MMC
 	select SUNXI_GEN_SUN6I
 	select SUNXI_DRAM_DW
 	select SUNXI_DRAM_DW_16BIT

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:56 UTC #63 lore raw

PATCH v3 42/58 clk: sunxi: Implement SPI clocks

In reply to Jagan Teki

Implement SPI AHB and MOD clocks for all Allwinner SoC clock drivers via clock map descriptor table.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/clk_a10.c  | 9 +++++++++
 drivers/clk/sunxi/clk_a10s.c | 7 +++++++
 drivers/clk/sunxi/clk_a31.c  | 9 +++++++++
 drivers/clk/sunxi/clk_a64.c  | 5 +++++
 drivers/clk/sunxi/clk_h3.c   | 5 +++++
 drivers/clk/sunxi/clk_v3s.c  | 3 +++
 6 files changed, 38 insertions(+)

drivers/clk/sunxi/clk_a10.c +9 -0

index 55176bc174..ee499c402a 100644
@@ -22,12 +22,21 @@ static struct ccu_clk_map a10_clks[] = {
 	[CLK_AHB_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_AHB_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_AHB_MMC3]		= { 0x060, BIT(11), NULL },
+	[CLK_AHB_SPI0]		= { 0x060, BIT(20), NULL },
+	[CLK_AHB_SPI1]		= { 0x060, BIT(21), NULL },
+	[CLK_AHB_SPI2]		= { 0x060, BIT(22), NULL },
+	[CLK_AHB_SPI3]		= { 0x060, BIT(23), NULL },
 
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC3]		= { 0x094, BIT(31), &mmc_clk_set_rate },
 
+	[CLK_SPI0]		= { 0x0a0, BIT(31), NULL },
+	[CLK_SPI1]		= { 0x0a4, BIT(31), NULL },
+	[CLK_SPI2]		= { 0x0a8, BIT(31), NULL },
+	[CLK_SPI3]		= { 0x0d4, BIT(31), NULL },
+
 	[CLK_USB_OHCI0]		= { 0x0cc, BIT(6), NULL },
 	[CLK_USB_OHCI1]		= { 0x0cc, BIT(7), NULL },
 	[CLK_USB_PHY]		= { 0x0cc, BIT(8), NULL },

drivers/clk/sunxi/clk_a10s.c +7 -0

index fbac0ad751..bca248f59f 100644
@@ -19,6 +19,9 @@ static struct ccu_clk_map a10s_clks[] = {
 	[CLK_AHB_MMC0]		= { 0x060, BIT(8), NULL },
 	[CLK_AHB_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_AHB_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_AHB_SPI0]		= { 0x060, BIT(20), NULL },
+	[CLK_AHB_SPI1]		= { 0x060, BIT(21), NULL },
+	[CLK_AHB_SPI2]		= { 0x060, BIT(22), NULL },
 
 #ifdef CONFIG_MMC
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },

@@ -26,6 +29,10 @@ static struct ccu_clk_map a10s_clks[] = {
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
 #endif
 
+	[CLK_SPI0]		= { 0x0a0, BIT(31), NULL },
+	[CLK_SPI1]		= { 0x0a4, BIT(31), NULL },
+	[CLK_SPI2]		= { 0x0a8, BIT(31), NULL },
+
 	[CLK_USB_OHCI]		= { 0x0cc, BIT(6), NULL },
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
 	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },

drivers/clk/sunxi/clk_a31.c +9 -0

index 15076d0e72..1fa77e1272 100644
@@ -17,6 +17,10 @@ static struct ccu_clk_map a31_clks[] = {
 	[CLK_AHB1_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_AHB1_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_AHB1_MMC3]		= { 0x060, BIT(12), NULL },
+	[CLK_AHB1_SPI0]		= { 0x060, BIT(20), NULL },
+	[CLK_AHB1_SPI1]		= { 0x060, BIT(21), NULL },
+	[CLK_AHB1_SPI2]		= { 0x060, BIT(22), NULL },
+	[CLK_AHB1_SPI3]		= { 0x060, BIT(23), NULL },
 	[CLK_AHB1_OTG]		= { 0x060, BIT(24), NULL },
 	[CLK_AHB1_EHCI0]	= { 0x060, BIT(26), NULL },
 	[CLK_AHB1_EHCI1]	= { 0x060, BIT(27), NULL },

@@ -29,6 +33,11 @@ static struct ccu_clk_map a31_clks[] = {
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC3]		= { 0x094, BIT(31), &mmc_clk_set_rate },
 
+	[CLK_SPI0]		= { 0x0a0, BIT(31), NULL },
+	[CLK_SPI1]		= { 0x0a4, BIT(31), NULL },
+	[CLK_SPI2]		= { 0x0a8, BIT(31), NULL },
+	[CLK_SPI3]		= { 0x0ac, BIT(31), NULL },
+
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
 	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },
 	[CLK_USB_PHY2]		= { 0x0cc, BIT(10), NULL },

drivers/clk/sunxi/clk_a64.c +5 -0

index 9ef9b606d2..aa2e69d0a3 100644
@@ -16,6 +16,8 @@ static struct ccu_clk_map a64_clks[] = {
 	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
 	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_BUS_SPI0]		= { 0x060, BIT(20), NULL },
+	[CLK_BUS_SPI1]		= { 0x060, BIT(21), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(23), NULL },
 	[CLK_BUS_EHCI0]		= { 0x060, BIT(24), NULL },
 	[CLK_BUS_EHCI1]		= { 0x060, BIT(25), NULL },

@@ -26,6 +28,9 @@ static struct ccu_clk_map a64_clks[] = {
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
 
+	[CLK_SPI0]		= { 0x0a0, BIT(31), NULL },
+	[CLK_SPI1]		= { 0x0a4, BIT(31), NULL },
+
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
 	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },
 	[CLK_USB_HSIC]		= { 0x0cc, BIT(10), NULL },

drivers/clk/sunxi/clk_h3.c +5 -0

index ad15aaae67..386289b654 100644
@@ -16,6 +16,8 @@ static struct ccu_clk_map h3_clks[] = {
 	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
 	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_BUS_SPI0]		= { 0x060, BIT(20), NULL },
+	[CLK_BUS_SPI1]		= { 0x060, BIT(21), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(23), NULL },
 	[CLK_BUS_EHCI0]		= { 0x060, BIT(24), NULL },
 	[CLK_BUS_EHCI1]		= { 0x060, BIT(25), NULL },

@@ -30,6 +32,9 @@ static struct ccu_clk_map h3_clks[] = {
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
 
+	[CLK_SPI0]		= { 0x0a0, BIT(31), NULL },
+	[CLK_SPI1]		= { 0x0a4, BIT(31), NULL },
+
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
 	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },
 	[CLK_USB_PHY2]		= { 0x0cc, BIT(10), NULL },

drivers/clk/sunxi/clk_v3s.c +3 -0

index 6eeec201a2..1cca57e065 100644
@@ -16,12 +16,15 @@ static struct ccu_clk_map v3s_clks[] = {
 	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
 	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_BUS_SPI0]		= { 0x060, BIT(20), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(24), NULL },
 
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },
 
+	[CLK_SPI0]		= { 0x0a0, BIT(31), NULL },
+
 	[CLK_USB_PHY0]          = { 0x0cc, BIT(8), NULL },
 };

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:57 UTC #64 lore raw

PATCH v3 43/58 clk: sunxi: Implement SPI resets

In reply to Jagan Teki

Implement SPI resets for all relevant Allwinner SoC clock drivers via reset map descriptor table.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/clk_a31.c | 4 ++++
 drivers/clk/sunxi/clk_a64.c | 2 ++
 drivers/clk/sunxi/clk_h3.c  | 2 ++
 drivers/clk/sunxi/clk_v3s.c | 1 +
 4 files changed, 9 insertions(+)

drivers/clk/sunxi/clk_a31.c +4 -0

index 1fa77e1272..a5c6628c63 100644
@@ -55,6 +55,10 @@ static struct ccu_reset_map a31_resets[] = {
 	[RST_AHB1_MMC1]		= { 0x2c0, BIT(9) },
 	[RST_AHB1_MMC2]		= { 0x2c0, BIT(10) },
 	[RST_AHB1_MMC3]		= { 0x2c0, BIT(11) },
+	[RST_AHB1_SPI0]		= { 0x2c0, BIT(20) },
+	[RST_AHB1_SPI1]		= { 0x2c0, BIT(21) },
+	[RST_AHB1_SPI2]		= { 0x2c0, BIT(22) },
+	[RST_AHB1_SPI3]		= { 0x2c0, BIT(23) },
 	[RST_AHB1_OTG]		= { 0x2c0, BIT(24) },
 	[RST_AHB1_EHCI0]	= { 0x2c0, BIT(26) },
 	[RST_AHB1_EHCI1]	= { 0x2c0, BIT(27) },

drivers/clk/sunxi/clk_a64.c +2 -0

index aa2e69d0a3..218d4f09ea 100644
@@ -47,6 +47,8 @@ static struct ccu_reset_map a64_resets[] = {
 	[RST_BUS_MMC0]		= { 0x2c0, BIT(8) },
 	[RST_BUS_MMC1]		= { 0x2c0, BIT(9) },
 	[RST_BUS_MMC2]		= { 0x2c0, BIT(10) },
+	[RST_BUS_SPI0]		= { 0x2c0, BIT(20) },
+	[RST_BUS_SPI1]		= { 0x2c0, BIT(21) },
 	[RST_BUS_OTG]		= { 0x2c0, BIT(23) },
 	[RST_BUS_EHCI0]		= { 0x2c0, BIT(24) },
 	[RST_BUS_EHCI1]		= { 0x2c0, BIT(25) },

drivers/clk/sunxi/clk_h3.c +2 -0

index 386289b654..f610cee745 100644
@@ -54,6 +54,8 @@ static struct ccu_reset_map h3_resets[] = {
 	[RST_BUS_MMC0]		= { 0x2c0, BIT(8) },
 	[RST_BUS_MMC1]		= { 0x2c0, BIT(9) },
 	[RST_BUS_MMC2]		= { 0x2c0, BIT(10) },
+	[RST_BUS_SPI0]		= { 0x2c0, BIT(20) },
+	[RST_BUS_SPI1]		= { 0x2c0, BIT(21) },
 	[RST_BUS_OTG]		= { 0x2c0, BIT(23) },
 	[RST_BUS_EHCI0]		= { 0x2c0, BIT(24) },
 	[RST_BUS_EHCI1]		= { 0x2c0, BIT(25) },

drivers/clk/sunxi/clk_v3s.c +1 -0

index 1cca57e065..ae4f6ee066 100644
@@ -34,6 +34,7 @@ static struct ccu_reset_map v3s_resets[] = {
 	[RST_BUS_MMC0]		= { 0x2c0, BIT(8) },
 	[RST_BUS_MMC1]		= { 0x2c0, BIT(9) },
 	[RST_BUS_MMC2]		= { 0x2c0, BIT(10) },
+	[RST_BUS_SPI0]		= { 0x2c0, BIT(20) },
 	[RST_BUS_OTG]		= { 0x2c0, BIT(24) },
 };

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:57 UTC #65 lore raw

PATCH v3 44/58 spi: sun4i: Add CLK support

In reply to Jagan Teki

Add CLK support to enable AHB and MOD SPI clocks
on sun4i_spi driver.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/spi/sun4i_spi.c | 40 ++++++++++++++++++++++++++++++++++------
 1 file changed, 34 insertions(+), 6 deletions(-)

drivers/spi/sun4i_spi.c +34 -6

index b86b5a00ad..3be80bb39f 100644
@@ -19,6 +19,7 @@
  */
 
 #include <common.h>
+#include <clk.h>
 #include <dm.h>
 #include <spi.h>
 #include <errno.h>

@@ -238,13 +239,36 @@ static int sun4i_spi_parse_pins(struct udevice *dev)
 	return 0;
 }
 
-static inline void sun4i_spi_enable_clock(void)
+static inline int sun4i_spi_enable_clock(struct udevice *dev)
 {
-	struct sunxi_ccm_reg *const ccm =
-		(struct sunxi_ccm_reg *const)SUNXI_CCM_BASE;
+	struct clk ahb_clk, mod_clk;
+	int ret;
+
+	ret = clk_get_by_name(dev, "ahb", &ahb_clk);
+	if (ret) {
+		dev_err(dev, "falied to get ahb clock\n");
+		return ret;
+	}
+
+	ret = clk_get_by_name(dev, "mod", &mod_clk);
+	if (ret) {
+		dev_err(dev, "falied to get mod clock\n");
+		return ret;
+	}
+
+	ret = clk_enable(&ahb_clk);
+	if (ret) {
+		dev_err(dev, "failed to enable ahb clock\n");
+		return ret;
+	}
+
+	ret = clk_enable(&mod_clk);
+	if (ret) {
+		dev_err(dev, "failed to enable mod clock\n");
+		return ret;
+	}
 
-	setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_SPI0));
-	writel((1 << 31), &ccm->spi0_clk_cfg);
+	return 0;
 }
 
 static int sun4i_spi_ofdata_to_platdata(struct udevice *bus)

@@ -267,8 +291,12 @@ static int sun4i_spi_probe(struct udevice *bus)
 {
 	struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
 	struct sun4i_spi_priv *priv = dev_get_priv(bus);
+	int ret;
+
+	ret = sun4i_spi_enable_clock(bus);
+	if (ret)
+		return ret;
 
-	sun4i_spi_enable_clock();
 	sun4i_spi_parse_pins(bus);
 
 	priv->regs = (struct sun4i_spi_regs *)(uintptr_t)plat->base_addr;

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:57 UTC #66 lore raw

PATCH v3 45/58 spi: Add Allwinner A31 SPI driver

In reply to Jagan Teki

Add Allwinner sun6i SPI driver for A31, H3/H5 an A64.

Tested-by Fahad Sadah <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/spi/Kconfig     |   6 +
 drivers/spi/Makefile    |   1 +
 drivers/spi/sun6i_spi.c | 475 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 482 insertions(+)
 create mode 100644 drivers/spi/sun6i_spi.c

drivers/spi/Kconfig +6 -0

index dcd719ff0a..671658dddc 100644
@@ -179,6 +179,12 @@ config SUN4I_SPI
 	help
 	  SPI driver for Allwinner sun4i, sun5i and sun7i SoCs
 
+config SUN6I_SPI
+	bool "Allwinner A31 SPI controller"
+	depends on ARCH_SUNXI
+	help
+	  This enables using the SPI controller on the Allwinner A31 SoCs.
+
 config TEGRA114_SPI
 	bool "nVidia Tegra114 SPI driver"
 	help

drivers/spi/Makefile +1 -0

index 728e30c538..6e60091bc1 100644
@@ -45,6 +45,7 @@ obj-$(CONFIG_SH_SPI) += sh_spi.o
 obj-$(CONFIG_SH_QSPI) += sh_qspi.o
 obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o
 obj-$(CONFIG_SUN4I_SPI) += sun4i_spi.o
+obj-$(CONFIG_SUN6I_SPI) += sun6i_spi.o
 obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
 obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
 obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o

drivers/spi/sun6i_spi.c new file +475 -0

475 lines not on this page · raw message

Signature · 1 line

2.18.0.321.gffc6fa0e3

Maxime Ripard

2018-08-20 11:18 UTC #67 lore raw

PATCH v3 45/58 spi: Add Allwinner A31 SPI driver

Quoted 4 lines · Jagan Teki

Add Allwinner sun6i SPI driver for A31, H3/H5 an A64.
Tested-by Fahad Sadah <[email protected]>
Signed-off-by Jagan Teki <[email protected]>

This has nothing to do in this serie.

Maxime

Signature · 10 lines

Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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Jagan Teki

author

2018-08-20 11:42 UTC #68 lore raw

PATCH v3 45/58 spi: Add Allwinner A31 SPI driver

Quoted 7 lines · Maxime Ripard

Quoted 4 lines · Jagan Teki
Add Allwinner sun6i SPI driver for A31, H3/H5 an A64.
Tested-by Fahad Sadah <[email protected]>
Signed-off-by Jagan Teki <[email protected]>
This has nothing to do in this serie.

Driver require CLK, RESET changes, so added on top of it.

Maxime Ripard

2018-08-20 14:19 UTC #69 lore raw

PATCH v3 45/58 spi: Add Allwinner A31 SPI driver

1;5202;0c

Quoted 11 lines · Jagan Teki

Quoted 7 lines · Maxime Ripard
Quoted 4 lines · Jagan Teki
Add Allwinner sun6i SPI driver for A31, H3/H5 an A64.
Tested-by Fahad Sadah <[email protected]>
Signed-off-by Jagan Teki <[email protected]>
This has nothing to do in this serie.
Driver require CLK, RESET changes, so added on top of it.

I understand why it has a dependency on this serie, but it doesn't belong in it. It's far too big to review already to not have an unrelated patch in the middle of the serie.

Maxime

Signature · 10 lines

Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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Jagan Teki

author

2018-08-20 15:25 UTC #70 lore raw

PATCH v3 45/58 spi: Add Allwinner A31 SPI driver

Quoted 10 lines · Maxime Ripard

1;5202;0c
Quoted 8 lines · Jagan Teki
Quoted 6 lines · Maxime Ripard
Quoted 4 lines · Jagan Teki
Add Allwinner sun6i SPI driver for A31, H3/H5 an A64.
Tested-by Fahad Sadah <[email protected]>
Signed-off-by Jagan Teki <[email protected]>

Quoted 7 lines

Quoted 3 lines
Quoted 1 line
This has nothing to do in this serie.
Driver require CLK, RESET changes, so added on top of it.
I understand why it has a dependency on this serie, but it doesn't belong in it. It's far too big to review already to not have an unrelated patch in the middle of the serie.

OK, then I break the series with CLK and DM_MMC separately which I did initially, that look easy for review.

Jagan Teki

author

2018-08-19 13:57 UTC #71 lore raw

PATCH v3 46/58 clk: sunxi: Implement UART clocks

In reply to Jagan Teki

Implement UART clocks for all Allwinner SoC
clock drivers via clock map descriptor table.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/clk_a10.c  | 9 +++++++++
 drivers/clk/sunxi/clk_a10s.c | 5 +++++
 drivers/clk/sunxi/clk_a23.c  | 6 ++++++
 drivers/clk/sunxi/clk_a31.c  | 7 +++++++
 drivers/clk/sunxi/clk_a64.c  | 6 ++++++
 drivers/clk/sunxi/clk_a83t.c | 6 ++++++
 drivers/clk/sunxi/clk_h3.c   | 5 +++++
 drivers/clk/sunxi/clk_r40.c  | 9 +++++++++
 drivers/clk/sunxi/clk_v3s.c  | 4 ++++
 9 files changed, 57 insertions(+)

drivers/clk/sunxi/clk_a10.c +9 -0

index ee499c402a..d145d37217 100644
@@ -27,6 +27,15 @@ static struct ccu_clk_map a10_clks[] = {
 	[CLK_AHB_SPI2]		= { 0x060, BIT(22), NULL },
 	[CLK_AHB_SPI3]		= { 0x060, BIT(23), NULL },
 
+	[CLK_APB1_UART0]	= { 0x06c, BIT(16), NULL },
+	[CLK_APB1_UART1]	= { 0x06c, BIT(17), NULL },
+	[CLK_APB1_UART2]	= { 0x06c, BIT(18), NULL },
+	[CLK_APB1_UART3]	= { 0x06c, BIT(19), NULL },
+	[CLK_APB1_UART4]	= { 0x06c, BIT(20), NULL },
+	[CLK_APB1_UART5]	= { 0x06c, BIT(21), NULL },
+	[CLK_APB1_UART6]	= { 0x06c, BIT(22), NULL },
+	[CLK_APB1_UART7]	= { 0x06c, BIT(23), NULL },
+
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },

drivers/clk/sunxi/clk_a10s.c +5 -0

index bca248f59f..5912043f19 100644
@@ -23,6 +23,11 @@ static struct ccu_clk_map a10s_clks[] = {
 	[CLK_AHB_SPI1]		= { 0x060, BIT(21), NULL },
 	[CLK_AHB_SPI2]		= { 0x060, BIT(22), NULL },
 
+	[CLK_APB1_UART0]	= { 0x06c, BIT(16), NULL },
+	[CLK_APB1_UART1]	= { 0x06c, BIT(17), NULL },
+	[CLK_APB1_UART2]	= { 0x06c, BIT(18), NULL },
+	[CLK_APB1_UART3]	= { 0x06c, BIT(19), NULL },
+
 #ifdef CONFIG_MMC
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },

drivers/clk/sunxi/clk_a23.c +6 -0

index 183c6275f3..331c79af81 100644
@@ -20,6 +20,12 @@ static struct ccu_clk_map a23_clks[] = {
 	[CLK_BUS_EHCI]		= { 0x060, BIT(26), NULL },
 	[CLK_BUS_OHCI]		= { 0x060, BIT(29), NULL },
 
+	[CLK_BUS_UART0]		= { 0x06c, BIT(16), NULL },
+	[CLK_BUS_UART1]		= { 0x06c, BIT(17), NULL },
+	[CLK_BUS_UART2]		= { 0x06c, BIT(18), NULL },
+	[CLK_BUS_UART3]		= { 0x06c, BIT(19), NULL },
+	[CLK_BUS_UART4]		= { 0x06c, BIT(20), NULL },
+
 #ifdef CONFIG_MMC
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },

drivers/clk/sunxi/clk_a31.c +7 -0

index a5c6628c63..40803a1d64 100644
@@ -28,6 +28,13 @@ static struct ccu_clk_map a31_clks[] = {
 	[CLK_AHB1_OHCI1]	= { 0x060, BIT(30), NULL },
 	[CLK_AHB1_OHCI2]	= { 0x060, BIT(31), NULL },
 
+	[CLK_APB2_UART0]	= { 0x06c, BIT(16), NULL },
+	[CLK_APB2_UART1]	= { 0x06c, BIT(17), NULL },
+	[CLK_APB2_UART2]	= { 0x06c, BIT(18), NULL },
+	[CLK_APB2_UART3]	= { 0x06c, BIT(19), NULL },
+	[CLK_APB2_UART4]	= { 0x06c, BIT(20), NULL },
+	[CLK_APB2_UART5]	= { 0x06c, BIT(21), NULL },
+
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },

drivers/clk/sunxi/clk_a64.c +6 -0

index 218d4f09ea..13b506f983 100644
@@ -24,6 +24,12 @@ static struct ccu_clk_map a64_clks[] = {
 	[CLK_BUS_OHCI0]		= { 0x060, BIT(28), NULL },
 	[CLK_BUS_OHCI1]		= { 0x060, BIT(29), NULL },
 
+	[CLK_BUS_UART0]		= { 0x06c, BIT(16), NULL },
+	[CLK_BUS_UART1]		= { 0x06c, BIT(17), NULL },
+	[CLK_BUS_UART2]		= { 0x06c, BIT(18), NULL },
+	[CLK_BUS_UART3]		= { 0x06c, BIT(19), NULL },
+	[CLK_BUS_UART4]		= { 0x06c, BIT(20), NULL },
+
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },

drivers/clk/sunxi/clk_a83t.c +6 -0

index 47b7672e7f..5c1235fa7b 100644
@@ -21,6 +21,12 @@ static struct ccu_clk_map a83t_clks[] = {
 	[CLK_BUS_EHCI1]		= { 0x060, BIT(27), NULL },
 	[CLK_BUS_OHCI0]		= { 0x060, BIT(29), NULL },
 
+	[CLK_BUS_UART0]		= { 0x06c, BIT(16), NULL },
+	[CLK_BUS_UART1]		= { 0x06c, BIT(17), NULL },
+	[CLK_BUS_UART2]		= { 0x06c, BIT(18), NULL },
+	[CLK_BUS_UART3]		= { 0x06c, BIT(19), NULL },
+	[CLK_BUS_UART4]		= { 0x06c, BIT(20), NULL },
+
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },

drivers/clk/sunxi/clk_h3.c +5 -0

index f610cee745..b132ae0a0d 100644
@@ -28,6 +28,11 @@ static struct ccu_clk_map h3_clks[] = {
 	[CLK_BUS_OHCI2]		= { 0x060, BIT(30), NULL },
 	[CLK_BUS_OHCI3]		= { 0x060, BIT(31), NULL },
 
+	[CLK_BUS_UART0]		= { 0x06c, BIT(16), NULL },
+	[CLK_BUS_UART1]		= { 0x06c, BIT(17), NULL },
+	[CLK_BUS_UART2]		= { 0x06c, BIT(18), NULL },
+	[CLK_BUS_UART3]		= { 0x06c, BIT(19), NULL },
+
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },

drivers/clk/sunxi/clk_r40.c +9 -0

index 24c26ad3be..1e5b1d10f7 100644
@@ -25,6 +25,15 @@ static struct ccu_clk_map r40_clks[] = {
 	[CLK_BUS_OHCI1]		= { 0x060, BIT(30), NULL },
 	[CLK_BUS_OHCI2]		= { 0x060, BIT(31), NULL },
 
+	[CLK_BUS_UART0]		= { 0x06c, BIT(16), NULL },
+	[CLK_BUS_UART1]		= { 0x06c, BIT(17), NULL },
+	[CLK_BUS_UART2]		= { 0x06c, BIT(18), NULL },
+	[CLK_BUS_UART3]		= { 0x06c, BIT(19), NULL },
+	[CLK_BUS_UART4]		= { 0x06c, BIT(20), NULL },
+	[CLK_BUS_UART5]		= { 0x06c, BIT(21), NULL },
+	[CLK_BUS_UART6]		= { 0x06c, BIT(22), NULL },
+	[CLK_BUS_UART7]		= { 0x06c, BIT(23), NULL },
+
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },

drivers/clk/sunxi/clk_v3s.c +4 -0

index ae4f6ee066..c6e57147ee 100644
@@ -19,6 +19,10 @@ static struct ccu_clk_map v3s_clks[] = {
 	[CLK_BUS_SPI0]		= { 0x060, BIT(20), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(24), NULL },
 
+	[CLK_BUS_UART0]		= { 0x06c, BIT(16), NULL },
+	[CLK_BUS_UART1]		= { 0x06c, BIT(17), NULL },
+	[CLK_BUS_UART2]		= { 0x06c, BIT(18), NULL },
+
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:57 UTC #72 lore raw

PATCH v3 47/58 clk: sunxi: Implement UART resets

In reply to Jagan Teki

Implement UART resets for all relevant Allwinner SoC clock drivers via reset map descriptor table.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/clk_a23.c  | 6 ++++++
 drivers/clk/sunxi/clk_a31.c  | 7 +++++++
 drivers/clk/sunxi/clk_a64.c  | 6 ++++++
 drivers/clk/sunxi/clk_a83t.c | 6 ++++++
 drivers/clk/sunxi/clk_h3.c   | 5 +++++
 drivers/clk/sunxi/clk_r40.c  | 9 +++++++++
 drivers/clk/sunxi/clk_v3s.c  | 4 ++++
 7 files changed, 43 insertions(+)

drivers/clk/sunxi/clk_a23.c +6 -0

index 331c79af81..268148002b 100644
@@ -50,6 +50,12 @@ static struct ccu_reset_map a23_resets[] = {
 	[RST_BUS_OTG]		= { 0x2c0, BIT(24) },
 	[RST_BUS_EHCI]		= { 0x2c0, BIT(26) },
 	[RST_BUS_OHCI]		= { 0x2c0, BIT(29) },
+
+	[RST_BUS_UART0]		= { 0x2d8, BIT(16) },
+	[RST_BUS_UART1]		= { 0x2d8, BIT(17) },
+	[RST_BUS_UART2]		= { 0x2d8, BIT(18) },
+	[RST_BUS_UART3]		= { 0x2d8, BIT(19) },
+	[RST_BUS_UART4]		= { 0x2d8, BIT(20) },
 };
 
 static const struct ccu_desc sun8i_a23_ccu_desc = {

drivers/clk/sunxi/clk_a31.c +7 -0

index 40803a1d64..288979a18f 100644
@@ -72,6 +72,13 @@ static struct ccu_reset_map a31_resets[] = {
 	[RST_AHB1_OHCI0]	= { 0x2c0, BIT(29) },
 	[RST_AHB1_OHCI1]	= { 0x2c0, BIT(30) },
 	[RST_AHB1_OHCI2]	= { 0x2c0, BIT(31) },
+
+	[RST_APB2_UART0]	= { 0x2d8, BIT(16) },
+	[RST_APB2_UART1]	= { 0x2d8, BIT(17) },
+	[RST_APB2_UART2]	= { 0x2d8, BIT(18) },
+	[RST_APB2_UART3]	= { 0x2d8, BIT(19) },
+	[RST_APB2_UART4]	= { 0x2d8, BIT(20) },
+	[RST_APB2_UART5]	= { 0x2d8, BIT(21) },
 };
 
 static const struct ccu_desc sun6i_a31_ccu_desc = {

drivers/clk/sunxi/clk_a64.c +6 -0

index 13b506f983..344cfb59aa 100644
@@ -60,6 +60,12 @@ static struct ccu_reset_map a64_resets[] = {
 	[RST_BUS_EHCI1]		= { 0x2c0, BIT(25) },
 	[RST_BUS_OHCI0]		= { 0x2c0, BIT(28) },
 	[RST_BUS_OHCI1]		= { 0x2c0, BIT(29) },
+
+	[RST_BUS_UART0]		= { 0x2d8, BIT(16) },
+	[RST_BUS_UART1]		= { 0x2d8, BIT(17) },
+	[RST_BUS_UART2]		= { 0x2d8, BIT(18) },
+	[RST_BUS_UART3]		= { 0x2d8, BIT(19) },
+	[RST_BUS_UART4]		= { 0x2d8, BIT(20) },
 };
 
 static const struct ccu_desc sun50i_a64_ccu_desc = {

drivers/clk/sunxi/clk_a83t.c +6 -0

index 5c1235fa7b..cf9455da97 100644
@@ -50,6 +50,12 @@ static struct ccu_reset_map a83t_resets[] = {
 	[RST_BUS_EHCI0]		= { 0x2c0, BIT(26) },
 	[RST_BUS_EHCI1]		= { 0x2c0, BIT(27) },
 	[RST_BUS_OHCI0]		= { 0x2c0, BIT(29) },
+
+	[RST_BUS_UART0]		= { 0x2d8, BIT(16) },
+	[RST_BUS_UART1]		= { 0x2d8, BIT(17) },
+	[RST_BUS_UART2]		= { 0x2d8, BIT(18) },
+	[RST_BUS_UART3]		= { 0x2d8, BIT(19) },
+	[RST_BUS_UART4]		= { 0x2d8, BIT(20) },
 };
 
 static const struct ccu_desc sun8i_a83t_ccu_desc = {

drivers/clk/sunxi/clk_h3.c +5 -0

index b132ae0a0d..15d933a6c5 100644
@@ -70,6 +70,11 @@ static struct ccu_reset_map h3_resets[] = {
 	[RST_BUS_OHCI1]		= { 0x2c0, BIT(29) },
 	[RST_BUS_OHCI2]		= { 0x2c0, BIT(30) },
 	[RST_BUS_OHCI3]		= { 0x2c0, BIT(31) },
+
+	[RST_BUS_UART0]		= { 0x2d8, BIT(16) },
+	[RST_BUS_UART1]		= { 0x2d8, BIT(17) },
+	[RST_BUS_UART2]		= { 0x2d8, BIT(18) },
+	[RST_BUS_UART3]		= { 0x2d8, BIT(19) },
 };
 
 static const struct ccu_desc sun8i_h3_ccu_desc = {

drivers/clk/sunxi/clk_r40.c +9 -0

index 1e5b1d10f7..ee699d26ee 100644
@@ -63,6 +63,15 @@ static struct ccu_reset_map r40_resets[] = {
 	[RST_BUS_OHCI0]		= { 0x2c0, BIT(29) },
 	[RST_BUS_OHCI1]		= { 0x2c0, BIT(30) },
 	[RST_BUS_OHCI2]		= { 0x2c0, BIT(31) },
+
+	[RST_BUS_UART0]		= { 0x2d8, BIT(16) },
+	[RST_BUS_UART1]		= { 0x2d8, BIT(17) },
+	[RST_BUS_UART2]		= { 0x2d8, BIT(18) },
+	[RST_BUS_UART3]		= { 0x2d8, BIT(19) },
+	[RST_BUS_UART4]		= { 0x2d8, BIT(20) },
+	[RST_BUS_UART5]		= { 0x2d8, BIT(21) },
+	[RST_BUS_UART6]		= { 0x2d8, BIT(22) },
+	[RST_BUS_UART7]		= { 0x2d8, BIT(23) },
 };
 
 static const struct ccu_desc sun8i_r40_ccu_desc = {

drivers/clk/sunxi/clk_v3s.c +4 -0

index c6e57147ee..87ca0350d8 100644
@@ -40,6 +40,10 @@ static struct ccu_reset_map v3s_resets[] = {
 	[RST_BUS_MMC2]		= { 0x2c0, BIT(10) },
 	[RST_BUS_SPI0]		= { 0x2c0, BIT(20) },
 	[RST_BUS_OTG]		= { 0x2c0, BIT(24) },
+
+	[RST_BUS_UART0]		= { 0x2d8, BIT(16) },
+	[RST_BUS_UART1]		= { 0x2d8, BIT(17) },
+	[RST_BUS_UART2]		= { 0x2d8, BIT(18) },
 };
 
 static const struct ccu_desc sun8i_v3s_ccu_desc = {

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:57 UTC #73 lore raw

PATCH v3 48/58 clk: sunxi: Implement Ethernet clocks

In reply to Jagan Teki

Implement Ethernet clocks for all Allwinner SoCs
clock drivers via clock map descriptor table.

Cc Joe Hershberger <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/clk_a10.c  | 3 +++
 drivers/clk/sunxi/clk_a10s.c | 1 +
 drivers/clk/sunxi/clk_a31.c  | 1 +
 drivers/clk/sunxi/clk_a64.c  | 1 +
 drivers/clk/sunxi/clk_a83t.c | 1 +
 drivers/clk/sunxi/clk_h3.c   | 1 +
 drivers/clk/sunxi/clk_r40.c  | 2 ++
 7 files changed, 10 insertions(+)

drivers/clk/sunxi/clk_a10.c +3 -0

index d145d37217..fc939a313d 100644
@@ -22,11 +22,14 @@ static struct ccu_clk_map a10_clks[] = {
 	[CLK_AHB_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_AHB_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_AHB_MMC3]		= { 0x060, BIT(11), NULL },
+	[CLK_AHB_EMAC]		= { 0x060, BIT(17), NULL },
 	[CLK_AHB_SPI0]		= { 0x060, BIT(20), NULL },
 	[CLK_AHB_SPI1]		= { 0x060, BIT(21), NULL },
 	[CLK_AHB_SPI2]		= { 0x060, BIT(22), NULL },
 	[CLK_AHB_SPI3]		= { 0x060, BIT(23), NULL },
 
+	[CLK_AHB_GMAC]		= { 0x064, BIT(17), NULL },
+
 	[CLK_APB1_UART0]	= { 0x06c, BIT(16), NULL },
 	[CLK_APB1_UART1]	= { 0x06c, BIT(17), NULL },
 	[CLK_APB1_UART2]	= { 0x06c, BIT(18), NULL },

drivers/clk/sunxi/clk_a10s.c +1 -0

index 5912043f19..6ce53dc27d 100644
@@ -19,6 +19,7 @@ static struct ccu_clk_map a10s_clks[] = {
 	[CLK_AHB_MMC0]		= { 0x060, BIT(8), NULL },
 	[CLK_AHB_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_AHB_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_AHB_EMAC]		= { 0x060, BIT(17), NULL },
 	[CLK_AHB_SPI0]		= { 0x060, BIT(20), NULL },
 	[CLK_AHB_SPI1]		= { 0x060, BIT(21), NULL },
 	[CLK_AHB_SPI2]		= { 0x060, BIT(22), NULL },

drivers/clk/sunxi/clk_a31.c +1 -0

index 288979a18f..d7a6b2421f 100644
@@ -17,6 +17,7 @@ static struct ccu_clk_map a31_clks[] = {
 	[CLK_AHB1_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_AHB1_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_AHB1_MMC3]		= { 0x060, BIT(12), NULL },
+	[CLK_AHB1_EMAC]		= { 0x060, BIT(17), NULL },
 	[CLK_AHB1_SPI0]		= { 0x060, BIT(20), NULL },
 	[CLK_AHB1_SPI1]		= { 0x060, BIT(21), NULL },
 	[CLK_AHB1_SPI2]		= { 0x060, BIT(22), NULL },

drivers/clk/sunxi/clk_a64.c +1 -0

index 344cfb59aa..546ddcffa2 100644
@@ -16,6 +16,7 @@ static struct ccu_clk_map a64_clks[] = {
 	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
 	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_BUS_EMAC]		= { 0x060, BIT(17), NULL },
 	[CLK_BUS_SPI0]		= { 0x060, BIT(20), NULL },
 	[CLK_BUS_SPI1]		= { 0x060, BIT(21), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(23), NULL },

drivers/clk/sunxi/clk_a83t.c +1 -0

index cf9455da97..593ce1ac1b 100644
@@ -16,6 +16,7 @@ static struct ccu_clk_map a83t_clks[] = {
 	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
 	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_BUS_EMAC]		= { 0x060, BIT(17), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(24), NULL },
 	[CLK_BUS_EHCI0]		= { 0x060, BIT(26), NULL },
 	[CLK_BUS_EHCI1]		= { 0x060, BIT(27), NULL },

drivers/clk/sunxi/clk_h3.c +1 -0

index 15d933a6c5..ff9f294097 100644
@@ -16,6 +16,7 @@ static struct ccu_clk_map h3_clks[] = {
 	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
 	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_BUS_EMAC]		= { 0x060, BIT(17), NULL },
 	[CLK_BUS_SPI0]		= { 0x060, BIT(20), NULL },
 	[CLK_BUS_SPI1]		= { 0x060, BIT(21), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(23), NULL },

drivers/clk/sunxi/clk_r40.c +2 -0

index ee699d26ee..e5bddc77ee 100644
@@ -25,6 +25,8 @@ static struct ccu_clk_map r40_clks[] = {
 	[CLK_BUS_OHCI1]		= { 0x060, BIT(30), NULL },
 	[CLK_BUS_OHCI2]		= { 0x060, BIT(31), NULL },
 
+	[CLK_BUS_GMAC]		= { 0x064, BIT(17), NULL },
+
 	[CLK_BUS_UART0]		= { 0x06c, BIT(16), NULL },
 	[CLK_BUS_UART1]		= { 0x06c, BIT(17), NULL },
 	[CLK_BUS_UART2]		= { 0x06c, BIT(18), NULL },

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:57 UTC #74 lore raw

PATCH v3 49/58 clk: sunxi: Implement Ethernet resets

In reply to Jagan Teki

Implement Ethernet resets for all relevant Allwinner SoC clock drivers via reset map descriptor table.

Cc Joe Hershberger <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/clk_a31.c  | 1 +
 drivers/clk/sunxi/clk_a64.c  | 1 +
 drivers/clk/sunxi/clk_a83t.c | 1 +
 drivers/clk/sunxi/clk_h3.c   | 1 +
 drivers/clk/sunxi/clk_r40.c  | 2 ++
 5 files changed, 6 insertions(+)

drivers/clk/sunxi/clk_a31.c +1 -0

index d7a6b2421f..9023640913 100644
@@ -63,6 +63,7 @@ static struct ccu_reset_map a31_resets[] = {
 	[RST_AHB1_MMC1]		= { 0x2c0, BIT(9) },
 	[RST_AHB1_MMC2]		= { 0x2c0, BIT(10) },
 	[RST_AHB1_MMC3]		= { 0x2c0, BIT(11) },
+	[RST_AHB1_EMAC]		= { 0x2c0, BIT(17) },
 	[RST_AHB1_SPI0]		= { 0x2c0, BIT(20) },
 	[RST_AHB1_SPI1]		= { 0x2c0, BIT(21) },
 	[RST_AHB1_SPI2]		= { 0x2c0, BIT(22) },

drivers/clk/sunxi/clk_a64.c +1 -0

index 546ddcffa2..b2df499a24 100644
@@ -54,6 +54,7 @@ static struct ccu_reset_map a64_resets[] = {
 	[RST_BUS_MMC0]		= { 0x2c0, BIT(8) },
 	[RST_BUS_MMC1]		= { 0x2c0, BIT(9) },
 	[RST_BUS_MMC2]		= { 0x2c0, BIT(10) },
+	[RST_BUS_EMAC]		= { 0x2c0, BIT(17) },
 	[RST_BUS_SPI0]		= { 0x2c0, BIT(20) },
 	[RST_BUS_SPI1]		= { 0x2c0, BIT(21) },
 	[RST_BUS_OTG]		= { 0x2c0, BIT(23) },

drivers/clk/sunxi/clk_a83t.c +1 -0

index 593ce1ac1b..e1780d6729 100644
@@ -47,6 +47,7 @@ static struct ccu_reset_map a83t_resets[] = {
 	[RST_BUS_MMC0]		= { 0x2c0, BIT(8) },
 	[RST_BUS_MMC1]		= { 0x2c0, BIT(9) },
 	[RST_BUS_MMC2]		= { 0x2c0, BIT(10) },
+	[RST_BUS_EMAC]		= { 0x2c0, BIT(17) },
 	[RST_BUS_OTG]		= { 0x2c0, BIT(24) },
 	[RST_BUS_EHCI0]		= { 0x2c0, BIT(26) },
 	[RST_BUS_EHCI1]		= { 0x2c0, BIT(27) },

drivers/clk/sunxi/clk_h3.c +1 -0

index ff9f294097..88086580f4 100644
@@ -60,6 +60,7 @@ static struct ccu_reset_map h3_resets[] = {
 	[RST_BUS_MMC0]		= { 0x2c0, BIT(8) },
 	[RST_BUS_MMC1]		= { 0x2c0, BIT(9) },
 	[RST_BUS_MMC2]		= { 0x2c0, BIT(10) },
+	[RST_BUS_EMAC]		= { 0x2c0, BIT(17) },
 	[RST_BUS_SPI0]		= { 0x2c0, BIT(20) },
 	[RST_BUS_SPI1]		= { 0x2c0, BIT(21) },
 	[RST_BUS_OTG]		= { 0x2c0, BIT(23) },

drivers/clk/sunxi/clk_r40.c +2 -0

index e5bddc77ee..cf00cf1011 100644
@@ -66,6 +66,8 @@ static struct ccu_reset_map r40_resets[] = {
 	[RST_BUS_OHCI1]		= { 0x2c0, BIT(30) },
 	[RST_BUS_OHCI2]		= { 0x2c0, BIT(31) },
 
+	[RST_BUS_GMAC]		= { 0x2c0, BIT(17) },
+
 	[RST_BUS_UART0]		= { 0x2d8, BIT(16) },
 	[RST_BUS_UART1]		= { 0x2d8, BIT(17) },
 	[RST_BUS_UART2]		= { 0x2d8, BIT(18) },

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:57 UTC #75 lore raw

PATCH v3 50/58 net: sunxi_emac: Add CLK support

In reply to Jagan Teki

Add CLk support for sunxi_emac to enable AHB_EMAC clock via CLK framework.

Cc Joe Hershberger <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/net/sunxi_emac.c | 28 ++++++++++++++++++++++------
 1 file changed, 22 insertions(+), 6 deletions(-)

drivers/net/sunxi_emac.c +22 -6

index 8dbd3c50c1..4d152b0ca0 100644
@@ -6,6 +6,7 @@
  */
 
 #include <common.h>
+#include <clk.h>
 #include <dm.h>
 #include <linux/err.h>
 #include <malloc.h>

@@ -157,6 +158,7 @@ struct sunxi_sramc_regs {
 
 struct emac_eth_dev {
 	struct emac_regs *regs;
+	struct clk clk;
 	struct mii_dev *bus;
 	struct phy_device *phydev;
 	int link_printed;

@@ -500,14 +502,12 @@ static int _sunxi_emac_eth_send(struct emac_eth_dev *priv, void *packet,
 	return 0;
 }
 
-static void sunxi_emac_board_setup(struct emac_eth_dev *priv)
+static int sunxi_emac_board_setup(struct emac_eth_dev *priv)
 {
-	struct sunxi_ccm_reg *const ccm =
-		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 	struct sunxi_sramc_regs *sram =
 		(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
 	struct emac_regs *regs = priv->regs;
-	int pin;
+	int pin, ret;
 
 	/* Map SRAM to EMAC */
 	setbits_le32(&sram->ctrl1, 0x5 << 2);

@@ -517,10 +517,16 @@ static void sunxi_emac_board_setup(struct emac_eth_dev *priv)
 		sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);
 
 	/* Set up clock gating */
-	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC);
+	ret = clk_enable(&priv->clk);
+	if (ret) {
+		dev_err(dev, "failed to enable emac clock\n");
+		return ret;
+	}
 
 	/* Set MII clock */
 	clrsetbits_le32(&regs->mac_mcfg, 0xf << 2, 0xd << 2);
+
+	return 0;
 }
 
 static int sunxi_emac_eth_start(struct udevice *dev)

@@ -557,9 +563,19 @@ static int sunxi_emac_eth_probe(struct udevice *dev)
 {
 	struct eth_pdata *pdata = dev_get_platdata(dev);
 	struct emac_eth_dev *priv = dev_get_priv(dev);
+	int ret;
 
 	priv->regs = (struct emac_regs *)pdata->iobase;
-	sunxi_emac_board_setup(priv);
+
+	ret = clk_get_by_index(dev, 0, &priv->clk);
+	if (ret) {
+		dev_err(dev, "falied to get emac clock\n");
+		return ret;
+	}
+
+	ret = sunxi_emac_board_setup(priv);
+	if (ret)
+		return ret;
 
 	return sunxi_emac_init_phy(priv, dev);
 }

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:57 UTC #76 lore raw

PATCH v3 51/58 net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle

In reply to Jagan Teki

Unlike other Allwinner SoC's R40 GMAC clock control register is locate in CCU, but rest located via syscon itself. Since the phandle property for current code look for 'syscon' and it will grab the respective ccu or syscon base address based on DT property defined in respective SoC dtsi.

So, use the existing 'syscon' code even for R40 for retrieving GMAC clock via CCU and update the register directly in sun8i_emac_set_syscon instead of writing it separately using ccm base.

Cc Joe Hershberger <[email protected]>

Cc Lothar Felten <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/net/sun8i_emac.c | 55 ++++++++++++++++++++--------------------
 1 file changed, 27 insertions(+), 28 deletions(-)

drivers/net/sun8i_emac.c +27 ~~-28~~

index 3ba3a1ff8b..5ee4c2f993 100644
@@ -278,10 +278,18 @@ static int sun8i_emac_set_syscon(struct emac_eth_dev *priv)
 	int ret;
 	u32 reg;
 
-	reg = readl(priv->sysctl_reg + 0x30);
+	if (priv->variant == R40_GMAC) {
+		/* Select RGMII for R40 */
+		reg = readl(priv->sysctl_reg + 0x164);
+		reg |= CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
+		       CCM_GMAC_CTRL_GPIT_RGMII |
+		       CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY);
 
-	if (priv->variant == R40_GMAC)
+		writel(reg, priv->sysctl_reg + 0x164);
 		return 0;
+	}
+
+	reg = readl(priv->sysctl_reg + 0x30);
 
 	if (priv->variant == H3_EMAC) {
 		ret = sun8i_emac_set_syscon_ephy(priv, &reg);

@@ -647,13 +655,6 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
 
 		/* De-assert EMAC */
 		setbits_le32(&ccm->ahb_gate1, BIT(AHB_GATE_OFFSET_GMAC));
-
-		/* Select RGMII for R40 */
-		setbits_le32(&ccm->gmac_clk_cfg,
-			     CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
-			     CCM_GMAC_CTRL_GPIT_RGMII);
-		setbits_le32(&ccm->gmac_clk_cfg,
-			     CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
 	} else {
 		/* Set clock gating for emac */
 		setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));

@@ -834,25 +835,23 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
 		return -EINVAL;
 	}
 
-	if (priv->variant != R40_GMAC) {
-		offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
-		if (offset < 0) {
-			debug("%s: cannot find syscon node\n", __func__);
-			return -EINVAL;
-		}
-		reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
-		if (!reg) {
-			debug("%s: cannot find reg property in syscon node\n",
-			      __func__);
-			return -EINVAL;
-		}
-		priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
-							 offset, reg);
-		if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
-			debug("%s: Cannot find syscon base address\n",
-			      __func__);
-			return -EINVAL;
-		}
+	offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
+	if (offset < 0) {
+		debug("%s: cannot find syscon node\n", __func__);
+		return -EINVAL;
+	}
+
+	reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
+	if (!reg) {
+		debug("%s: cannot find reg property in syscon node\n",
+		      __func__);
+		return -EINVAL;
+	}
+	priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
+						 offset, reg);
+	if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
+		debug("%s: Cannot find syscon base address\n", __func__);
+		return -EINVAL;
 	}
 
 	pdata->phy_interface = -1;

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:57 UTC #77 lore raw

PATCH v3 52/58 net: sun8i_emac: Add CLK and RESET support

In reply to Jagan Teki

Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework.

Cc Joe Hershberger <[email protected]>

Cc Lothar Felten <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/net/sun8i_emac.c | 56 ++++++++++++++++++++++++++++------------
 1 file changed, 40 insertions(+), 16 deletions(-)

drivers/net/sun8i_emac.c +40 ~~-16~~

index 5ee4c2f993..ad2d390f4e 100644
@@ -10,6 +10,7 @@
  *
 */
 
+#include <clk.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>

@@ -20,6 +21,7 @@
 #include <malloc.h>
 #include <miiphy.h>
 #include <net.h>
+#include <reset.h>
 #include <dt-bindings/pinctrl/sun4i-a10.h>
 #ifdef CONFIG_DM_GPIO
 #include <asm-generic/gpio.h>

@@ -131,6 +133,8 @@ struct emac_eth_dev {
 	phys_addr_t sysctl_reg;
 	struct phy_device *phydev;
 	struct mii_dev *bus;
+	struct clk tx_clk;
+	struct reset_ctl tx_rst;
 #ifdef CONFIG_DM_GPIO
 	struct gpio_desc reset_gpio;
 #endif

@@ -632,9 +636,24 @@ static int sun8i_eth_write_hwaddr(struct udevice *dev)
 	return _sun8i_write_hwaddr(priv, pdata->enetaddr);
 }
 
-static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
+static int sun8i_emac_board_setup(struct emac_eth_dev *priv)
 {
 	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	int ret;
+
+	ret = clk_enable(&priv->tx_clk);
+	if (ret) {
+		dev_err(dev, "failed to enable TX clock\n");
+		return ret;
+	}
+
+	if (reset_valid(&priv->tx_rst)) {
+		ret = reset_deassert(&priv->tx_rst);
+		if (ret) {
+			dev_err(dev, "failed to deassert TX reset\n");
+			return ret;
+		}
+	}
 
 	if (priv->variant == H3_EMAC) {
 		/* Only H3/H5 have clock controls for internal EPHY */

@@ -649,19 +668,7 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
 		}
 	}
 
-	if (priv->variant == R40_GMAC) {
-		/* Set clock gating for emac */
-		setbits_le32(&ccm->ahb_reset1_cfg, BIT(AHB_RESET_OFFSET_GMAC));
-
-		/* De-assert EMAC */
-		setbits_le32(&ccm->ahb_gate1, BIT(AHB_GATE_OFFSET_GMAC));
-	} else {
-		/* Set clock gating for emac */
-		setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
-
-		/* De-assert EMAC */
-		setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
-	}
+	return 0;
 }
 
 #if defined(CONFIG_DM_GPIO)

@@ -787,10 +794,14 @@ static int sun8i_emac_eth_probe(struct udevice *dev)
 {
 	struct eth_pdata *pdata = dev_get_platdata(dev);
 	struct emac_eth_dev *priv = dev_get_priv(dev);
+	int ret;
 
 	priv->mac_reg = (void *)pdata->iobase;
 
-	sun8i_emac_board_setup(priv);
+	ret = sun8i_emac_board_setup(priv);
+	if (ret)
+		return ret;
+
 	sun8i_emac_set_syscon(priv);
 
 	sun8i_mdio_init(dev->name, dev);

@@ -819,8 +830,8 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
 	int offset = 0;
 #ifdef CONFIG_DM_GPIO
 	int reset_flags = GPIOD_IS_OUT;
-	int ret = 0;
 #endif
+	int ret;
 
 	pdata->iobase = devfdt_get_addr(dev);
 	if (pdata->iobase == FDT_ADDR_T_NONE) {

@@ -835,6 +846,19 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
 		return -EINVAL;
 	}
 
+	ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk);
+	if (ret) {
+		dev_err(dev, "failed to get TX clock\n");
+		return ret;
+	}
+
+	ret = reset_get_by_name_optional(dev, "stmmaceth",
+					 &priv->tx_rst, true);
+	if (ret) {
+		dev_err(dev, "failed to get TX reset\n");
+		return ret;
+	}
+
 	offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
 	if (offset < 0) {
 		debug("%s: cannot find syscon node\n", __func__);

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:57 UTC #78 lore raw

PATCH v3 53/58 clk: Get the CLK by index without device

In reply to Jagan Teki

Getting a CLK by index with device is not straight forward for some use-cases like handling clock operations for child node in parent driver. So we need to process the child node in parent probe via ofnode and process CLK operation for child without udevice but with ofnode.

So add clk_get_by_index_nodev() and move the common code in clk_get_by_index_tail() to use for clk_get_by_index()

Cc Simon Glass <[email protected]>

Cc Joe Hershberger <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/clk-uclass.c | 61 +++++++++++++++++++++++++++++++++++++++-
 include/clk.h            | 15 ++++++++++
 2 files changed, 75 insertions(+), 1 deletion(-)

drivers/clk/clk-uclass.c +60 -1

index 2b15978e14..8bb41a4de5 100644
@@ -98,9 +98,68 @@ static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
 	return clk_request(dev_clk, clk);
 }
 
+static int clk_get_by_index_tail(int ret, ofnode node,
+				 struct ofnode_phandle_args *args,
+				 const char *list_name, int index,
+				 struct clk *clk)
+{
+	struct udevice *dev_clk;
+	const struct clk_ops *ops;
+
+	assert(clk);
+	clk->dev = NULL;
+	if (ret)
+		goto err;
+
+	ret = uclass_get_device_by_ofnode(UCLASS_CLK, args->node, &dev_clk);
+	if (ret) {
+		debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
+		      __func__, ret);
+		return ret;
+	}
+
+	clk->dev = dev_clk;
+
+	ops = clk_dev_ops(dev_clk);
+
+	if (ops->of_xlate)
+		ret = ops->of_xlate(clk, args);
+	else
+		ret = clk_of_xlate_default(clk, args);
+	if (ret) {
+		debug("of_xlate() failed: %d\n", ret);
+		return ret;
+	}
+
+	return clk_request(dev_clk, clk);
+err:
+	debug("%s: Node '%s', property '%s', failed to request CLK index %d: %d\n",
+	       __func__, ofnode_get_name(node), list_name, index, ret);
+	return ret;
+}
+
 int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
 {
-	return clk_get_by_indexed_prop(dev, "clocks", index, clk);
+	struct ofnode_phandle_args args;
+	int ret;
+
+	ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
+					 index, &args);
+
+	return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
+				     index > 0, clk);
+}
+
+int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk)
+{
+	struct ofnode_phandle_args args;
+	int ret;
+
+	ret = ofnode_parse_phandle_with_args(node, "clocks", "#clock-cells", 0,
+					     index > 0, &args);
+
+	return clk_get_by_index_tail(ret, node, &args, "clocks",
+				     index > 0, clk);
 }
 
 int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)

include/clk.h +15 -0

index f6d1cc53a1..1d8478f061 100644
@@ -8,6 +8,7 @@
 #ifndef _CLK_H_
 #define _CLK_H_
 
+#include <dm/ofnode.h>
 #include <linux/errno.h>
 #include <linux/types.h>

@@ -98,6 +99,20 @@ int clk_get_by_index_platdata(struct udevice *dev, int index,
  */
 int clk_get_by_index(struct udevice *dev, int index, struct clk *clk);
 
+/**
+ * clock_get_by_index_nodev - Get/request a clock by integer index
+ * without a device.
+ *
+ * This is a version of clk_get_by_index() that does not use a device.
+ *
+ * @node:	The client ofnode.
+ * @index:	The index of the clock to request, within the client's list of
+ *		clocks.
+ * @clock	A pointer to a clock struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk);
+
 /**
  * clock_get_bulk - Get/request all clocks of a device.
  *

Signature · 1 line

2.18.0.321.gffc6fa0e3

Simon Glass

2018-08-23 10:45 UTC #79 lore raw

PATCH v3 53/58 clk: Get the CLK by index without device

+Stephen

Quoted 9 lines · Jagan Teki

Getting a CLK by index with device is not straight forward for some use-cases like handling clock operations for child node in parent driver. So we need to process the child node in parent probe via ofnode and process CLK operation for child without udevice but with ofnode.
So add clk_get_by_index_nodev() and move the common code in clk_get_by_index_tail() to use for clk_get_by_index()

Quoted 7 lines

Cc Simon Glass <[email protected]>
Cc Joe Hershberger <[email protected]>
Signed-off-by Jagan Teki <[email protected]>
---
 drivers/clk/clk-uclass.c | 61 +++++++++++++++++++++++++++++++++++++++-
 include/clk.h            | 15 ++++++++++
 2 files changed, 75 insertions(+), 1 deletion(-)

Can you please add a test for the new function you add?

Regards,
Simon

Jagan Teki

author

2018-08-19 13:57 UTC #80 lore raw

PATCH v3 54/58 clk: Use clk_get_by_index_tail()

In reply to Jagan Teki

clk_get_by_index_tail() now handle common clk get by index code so use it in relevant places.

Cc Simon Glass <[email protected]>

Cc Joe Hershberger <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/clk-uclass.c | 77 +++++++++++++---------------------------
 1 file changed, 25 insertions(+), 52 deletions(-)

drivers/clk/clk-uclass.c +25 ~~-52~~

index 8bb41a4de5..d439d216f2 100644
@@ -54,50 +54,6 @@ static int clk_of_xlate_default(struct clk *clk,
 	return 0;
 }
 
-static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
-				   int index, struct clk *clk)
-{
-	int ret;
-	struct ofnode_phandle_args args;
-	struct udevice *dev_clk;
-	const struct clk_ops *ops;
-
-	debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
-
-	assert(clk);
-	clk->dev = NULL;
-
-	ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
-					 index, &args);
-	if (ret) {
-		debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
-		      __func__, ret);
-		return ret;
-	}
-
-	ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &dev_clk);
-	if (ret) {
-		debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
-		      __func__, ret);
-		return ret;
-	}
-
-	clk->dev = dev_clk;
-
-	ops = clk_dev_ops(dev_clk);
-
-	if (ops->of_xlate)
-		ret = ops->of_xlate(clk, &args);
-	else
-		ret = clk_of_xlate_default(clk, &args);
-	if (ret) {
-		debug("of_xlate() failed: %d\n", ret);
-		return ret;
-	}
-
-	return clk_request(dev_clk, clk);
-}
-
 static int clk_get_by_index_tail(int ret, ofnode node,
 				 struct ofnode_phandle_args *args,
 				 const char *list_name, int index,

@@ -197,10 +153,11 @@ bulk_get_err:
 
 static int clk_set_default_parents(struct udevice *dev)
 {
+	struct ofnode_phandle_args args;
 	struct clk clk, parent_clk;
 	int index;
 	int num_parents;
-	int ret;
+	int ret, err;
 
 	num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
 						  "#clock-cells");

@@ -211,8 +168,13 @@ static int clk_set_default_parents(struct udevice *dev)
 	}
 
 	for (index = 0; index < num_parents; index++) {
-		ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
-					      index, &parent_clk);
+		err = dev_read_phandle_with_args(dev, "assigned-clock-parents",
+						 "#clock-cells", 0,
+						 index, &args);
+
+		ret = clk_get_by_index_tail(err, dev_ofnode(dev), &args,
+					    "assigned-clock-parents",
+					    index > 0, &parent_clk);
 		/* If -ENOENT, this is a no-op entry */
 		if (ret == -ENOENT)
 			continue;

@@ -223,8 +185,13 @@ static int clk_set_default_parents(struct udevice *dev)
 			return ret;
 		}
 
-		ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
-					      index, &clk);
+		err = dev_read_phandle_with_args(dev, "assigned-clocks",
+						 "#clock-cells", 0,
+						 index, &args);
+
+		ret = clk_get_by_index_tail(err, dev_ofnode(dev), &args,
+					    "assigned-clocks",
+					    index > 0, &clk);
 		if (ret) {
 			debug("%s: could not get assigned clock %d for %s\n",
 			      __func__, index, dev_read_name(dev));

@@ -252,11 +219,12 @@ static int clk_set_default_parents(struct udevice *dev)
 
 static int clk_set_default_rates(struct udevice *dev)
 {
+	struct ofnode_phandle_args args;
 	struct clk clk;
 	int index;
 	int num_rates;
 	int size;
-	int ret = 0;
+	int err, ret = 0;
 	u32 *rates = NULL;
 
 	size = dev_read_size(dev, "assigned-clock-rates");

@@ -277,8 +245,13 @@ static int clk_set_default_rates(struct udevice *dev)
 		if (!rates[index])
 			continue;
 
-		ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
-					      index, &clk);
+		err = dev_read_phandle_with_args(dev, "assigned-clocks",
+						 "#clock-cells", 0,
+						 index, &args);
+
+		ret = clk_get_by_index_tail(err, dev_ofnode(dev), &args,
+					    "assigned-clocks",
+					    index > 0, &clk);
 		if (ret) {
 			debug("%s: could not get assigned clock %d for %s\n",
 			      __func__, index, dev_read_name(dev));

Signature · 1 line

2.18.0.321.gffc6fa0e3

Simon Glass

2018-08-23 10:45 UTC #81 lore raw

PATCH v3 54/58 clk: Use clk_get_by_index_tail()

+Stephen

Quoted 9 lines · Jagan Teki

clk_get_by_index_tail() now handle common clk get by index code so use it in relevant places.
Cc Simon Glass <[email protected]>
Cc Joe Hershberger <[email protected]>
Signed-off-by Jagan Teki <[email protected]>
---
 drivers/clk/clk-uclass.c | 77 +++++++++++++---------------------------
 1 file changed, 25 insertions(+), 52 deletions(-)

Reviewed-by Simon Glass <[email protected]>

Jagan Teki

author

2018-08-19 13:57 UTC #82 lore raw

PATCH v3 55/58 reset: Get the RESET by index without device

In reply to Jagan Teki

Getting a RESET by index with device is not straight forward for some use-cases like handling clock operations for child node in parent driver. So we need to process the child node in parent probe via ofnode and process RESET operation for child without udevice but with ofnode.

So add reset_get_by_index_nodev() and move the common code in reset_get_by_index_tail() to use for reset_get_by_index()

Cc Simon Glass <[email protected]>

Cc Joe Hershberger <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/reset/reset-uclass.c | 53 ++++++++++++++++++++++++------------
 include/reset.h              | 16 +++++++++++
 2 files changed, 52 insertions(+), 17 deletions(-)

drivers/reset/reset-uclass.c +36 ~~-17~~

index 6320efcb49..755bbf7a5e 100644
@@ -34,41 +34,34 @@ static int reset_of_xlate_default(struct reset_ctl *reset_ctl,
 	return 0;
 }
 
-int reset_get_by_index(struct udevice *dev, int index,
-		       struct reset_ctl *reset_ctl)
+static int reset_get_by_index_tail(int ret, ofnode node,
+				   struct ofnode_phandle_args *args,
+				   const char *list_name, int index,
+				   struct reset_ctl *reset_ctl)
 {
-	struct ofnode_phandle_args args;
-	int ret;
 	struct udevice *dev_reset;
 	struct reset_ops *ops;
 
-	debug("%s(dev=%p, index=%d, reset_ctl=%p)\n", __func__, dev, index,
-	      reset_ctl);
+	assert(reset_ctl);
 	reset_ctl->dev = NULL;
-
-	ret = dev_read_phandle_with_args(dev, "resets", "#reset-cells", 0,
-					  index, &args);
-	if (ret) {
-		debug("%s: fdtdec_parse_phandle_with_args() failed: %d\n",
-		      __func__, ret);
+	if (ret)
 		return ret;
-	}
 
-	ret = uclass_get_device_by_ofnode(UCLASS_RESET, args.node,
+	ret = uclass_get_device_by_ofnode(UCLASS_RESET, args->node,
 					  &dev_reset);
 	if (ret) {
 		debug("%s: uclass_get_device_by_ofnode() failed: %d\n",
 		      __func__, ret);
-		debug("%s %d\n", ofnode_get_name(args.node), args.args[0]);
+		debug("%s %d\n", ofnode_get_name(args->node), args->args[0]);
 		return ret;
 	}
 	ops = reset_dev_ops(dev_reset);
 
 	reset_ctl->dev = dev_reset;
 	if (ops->of_xlate)
-		ret = ops->of_xlate(reset_ctl, &args);
+		ret = ops->of_xlate(reset_ctl, args);
 	else
-		ret = reset_of_xlate_default(reset_ctl, &args);
+		ret = reset_of_xlate_default(reset_ctl, args);
 	if (ret) {
 		debug("of_xlate() failed: %d\n", ret);
 		return ret;

@@ -86,6 +79,32 @@ int reset_get_by_index(struct udevice *dev, int index,
 	return 0;
 }
 
+int reset_get_by_index(struct udevice *dev, int index,
+		       struct reset_ctl *reset_ctl)
+{
+	struct ofnode_phandle_args args;
+	int ret;
+
+	ret = dev_read_phandle_with_args(dev, "resets", "#reset-cells", 0,
+					 index, &args);
+
+	return reset_get_by_index_tail(ret, dev_ofnode(dev), &args, "resets",
+				       index > 0, reset_ctl);
+}
+
+int reset_get_by_index_nodev(ofnode node, int index,
+			     struct reset_ctl *reset_ctl)
+{
+	struct ofnode_phandle_args args;
+	int ret;
+
+	ret = ofnode_parse_phandle_with_args(node, "resets", "#reset-cells", 0,
+					     index > 0, &args);
+
+	return reset_get_by_index_tail(ret, node, &args, "resets",
+				       index > 0, reset_ctl);
+}
+
 int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk)
 {
 	int i, ret, err, count;

include/reset.h +16 -0

index 70130bb886..581cc2579b 100644
@@ -6,6 +6,7 @@
 #ifndef _RESET_H
 #define _RESET_H
 
+#include <dm/ofnode.h>
 #include <linux/errno.h>
 
 /**

@@ -97,6 +98,21 @@ struct reset_ctl_bulk {
 int reset_get_by_index(struct udevice *dev, int index,
 		       struct reset_ctl *reset_ctl);
 
+/**
+ * reset_get_by_index_nodev - Get/request a reset signal by integer index
+ * without a device.
+ *
+ * This is a version of reset_get_by_index() that does not use a device.
+ *
+ * @node:	The client ofnode.
+ * @index:	The index of the reset signal to request, within the client's
+ *		list of reset signals.
+ * @reset_ctl	A pointer to a reset control struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_get_by_index_nodev(ofnode node, int index,
+			     struct reset_ctl *reset_ctl);
+
 /**
  * reset_get_bulk - Get/request all reset signals of a device.
  *

Signature · 1 line

2.18.0.321.gffc6fa0e3

Simon Glass

2018-08-23 10:45 UTC #83 lore raw

PATCH v3 55/58 reset: Get the RESET by index without device

Hi Jagan,

Quoted 9 lines · Jagan Teki

Getting a RESET by index with device is not straight forward for some use-cases like handling clock operations for child node in parent driver. So we need to process the child node in parent probe via ofnode and process RESET operation for child without udevice but with ofnode.
So add reset_get_by_index_nodev() and move the common code in reset_get_by_index_tail() to use for reset_get_by_index()

Quoted 8 lines

Cc Simon Glass <[email protected]>
Cc Joe Hershberger <[email protected]>
Signed-off-by Jagan Teki <[email protected]>
---
 drivers/reset/reset-uclass.c | 53 ++++++++++++++++++++++++------------
 include/reset.h              | 16 +++++++++++
 2 files changed, 52 insertions(+), 17 deletions(-)

Please add a test for the new function you add.

Regards,
Simon

Jagan Teki

author

2018-08-19 13:57 UTC #84 lore raw

PATCH v3 56/58 clk: sunxi: h3: Implement EPHY CLK and RESET

In reply to Jagan Teki

EPHY CLK and RESET is availble in Allwinner H3 EMAC via mdio-mux node of internal PHY. Add the respetive clock and reset reg and bits.

Cc Joe Hershberger <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/clk_h3.c | 4 ++++
 1 file changed, 4 insertions(+)

drivers/clk/sunxi/clk_h3.c +4 -0

index 88086580f4..3d5dc2cbed 100644
@@ -34,6 +34,8 @@ static struct ccu_clk_map h3_clks[] = {
 	[CLK_BUS_UART2]		= { 0x06c, BIT(18), NULL },
 	[CLK_BUS_UART3]		= { 0x06c, BIT(19), NULL },
 
+	[CLK_BUS_EPHY]		= { 0x070, BIT(0), NULL },
+
 	[CLK_MMC0]		= { 0x088, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC1]		= { 0x08c, BIT(31), &mmc_clk_set_rate },
 	[CLK_MMC2]		= { 0x090, BIT(31), &mmc_clk_set_rate },

@@ -73,6 +75,8 @@ static struct ccu_reset_map h3_resets[] = {
 	[RST_BUS_OHCI2]		= { 0x2c0, BIT(30) },
 	[RST_BUS_OHCI3]		= { 0x2c0, BIT(31) },
 
+	[RST_BUS_EPHY]		= { 0x2c8, BIT(2) },
+
 	[RST_BUS_UART0]		= { 0x2d8, BIT(16) },
 	[RST_BUS_UART1]		= { 0x2d8, BIT(17) },
 	[RST_BUS_UART2]		= { 0x2d8, BIT(18) },

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:57 UTC #85 lore raw

PATCH v3 57/58 net: sun8i_emac: Add EPHY CLK and RESET support

In reply to Jagan Teki

Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework.

Cc Joe Hershberger <[email protected]>

Cc Lothar Felten <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/net/sun8i_emac.c | 72 ++++++++++++++++++++++++++++++----------
 1 file changed, 55 insertions(+), 17 deletions(-)

drivers/net/sun8i_emac.c +55 ~~-17~~

index ad2d390f4e..bb97e6d7e9 100644
@@ -134,7 +134,9 @@ struct emac_eth_dev {
 	struct phy_device *phydev;
 	struct mii_dev *bus;
 	struct clk tx_clk;
+	struct clk ephy_clk;
 	struct reset_ctl tx_rst;
+	struct reset_ctl ephy_rst;
 #ifdef CONFIG_DM_GPIO
 	struct gpio_desc reset_gpio;
 #endif

@@ -638,7 +640,6 @@ static int sun8i_eth_write_hwaddr(struct udevice *dev)
 
 static int sun8i_emac_board_setup(struct emac_eth_dev *priv)
 {
-	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 	int ret;
 
 	ret = clk_enable(&priv->tx_clk);

@@ -655,16 +656,20 @@ static int sun8i_emac_board_setup(struct emac_eth_dev *priv)
 		}
 	}
 
-	if (priv->variant == H3_EMAC) {
-		/* Only H3/H5 have clock controls for internal EPHY */
-		if (priv->use_internal_phy) {
-			/* Set clock gating for ephy */
-			setbits_le32(&ccm->bus_gate4,
-				     BIT(AHB_GATE_OFFSET_EPHY));
-
-			/* Deassert EPHY */
-			setbits_le32(&ccm->ahb_reset2_cfg,
-				     BIT(AHB_RESET_OFFSET_EPHY));
+	/* Only H3/H5 have clock controls for internal EPHY */
+	if (clk_valid(&priv->ephy_clk)) {
+		ret = clk_enable(&priv->ephy_clk);
+		if (ret) {
+			dev_err(dev, "failed to enable EPHY TX clock\n");
+			return ret;
+		}
+	}
+
+	if (reset_valid(&priv->ephy_rst)) {
+		ret = reset_deassert(&priv->ephy_rst);
+		if (ret) {
+			dev_err(dev, "failed to deassert EPHY TX clock\n");
+			return ret;
 		}
 	}

@@ -819,6 +824,42 @@ static const struct eth_ops sun8i_emac_eth_ops = {
 	.stop                   = sun8i_emac_eth_stop,
 };
 
+static int sun8i_get_ephy_nodes(struct emac_eth_dev *priv)
+{
+	int node, ret;
+
+	/* look for mdio-mux node for internal PHY node */
+	node = fdt_path_offset(gd->fdt_blob,
+			"/soc/ethernet at 1c30000/mdio-mux/mdio at 1/ethernet-phy at 1");
+	if (node < 0) {
+		debug("failed to get mdio-mux with internal PHY\n");
+		return node;
+	}
+
+	ret = fdt_node_check_compatible(gd->fdt_blob, node,
+					"allwinner,sun8i-h3-mdio-internal");
+	if (ret < 0) {
+		debug("failed to find mdio-internal node\n");
+		return ret;
+	}
+
+	ret = clk_get_by_index_nodev(offset_to_ofnode(node), 0, &priv->ephy_clk);
+	if (ret) {
+		dev_err(dev, "failed to get EPHY TX clock\n");
+		return ret;
+	}
+
+	ret = reset_get_by_index_nodev(offset_to_ofnode(node), 0, &priv->ephy_rst);
+	if (ret) {
+		dev_err(dev, "failed to get EPHY TX reset\n");
+		return ret;
+	}
+
+	priv->use_internal_phy = true;
+
+	return 0;
+}
+
 static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
 {
 	struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);

@@ -901,12 +942,9 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
 	}
 
 	if (priv->variant == H3_EMAC) {
-		int parent = fdt_parent_offset(gd->fdt_blob, offset);
-
-		if (parent >= 0 &&
-		    !fdt_node_check_compatible(gd->fdt_blob, parent,
-				"allwinner,sun8i-h3-mdio-internal"))
-			priv->use_internal_phy = true;
+		ret = sun8i_get_ephy_nodes(priv);
+		if (ret)
+			return ret;
 	}
 
 	priv->interface = pdata->phy_interface;

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2018-08-19 13:57 UTC #86 lore raw

PATCH v3 58/58 board: sunxi: gmac: Remove Ethernet clock and reset

In reply to Jagan Teki

Since Ethernet clock and reset is now handling via CLK and RESET frameworks via driver API's remove explicit ccm writes.

Signed-off-by Jagan Teki <[email protected]>

---
 board/sunxi/gmac.c | 8 --------
 1 file changed, 8 deletions(-)

board/sunxi/gmac.c +0 -8

index 826650c89b..d8fdf7728e 100644
@@ -12,14 +12,6 @@ void eth_init_board(void)
 	struct sunxi_ccm_reg *const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
-	/* Set up clock gating */
-#ifdef CONFIG_SUNXI_GEN_SUN6I
-	setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
-	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
-#else
-	setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
-#endif
-
 	/* Set MII clock */
 #ifdef CONFIG_RGMII
 	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |

Signature · 1 line

2.18.0.321.gffc6fa0e3