clk: tegra: Return the exact clock rate from clk_round_rate
Subsystems (3)
PATCH 1/1 clk: tegra: Return the exact clock rate from clk_round_rate
The current behavior is that clk_round_rate would return the same clock rate passed to it for valid PLL configurations. This change will return the exact rate the PLL will provide in accordance with clk API.
--- drivers/clk/tegra/clk-pll.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)
drivers/clk/tegra/clk-pll.c +6 -1
@@ -595,7 +595,12 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,return -EINVAL ; } - cfg->output_rate >>= p_div; +if (cfg->m ==0 ) { + cfg->output_rate =0 ; + }else { + cfg->output_rate = cfg->n *DIV_ROUND_UP (parent_rate, cfg->m); + cfg->output_rate >>= p_div; + }if (pll->params->pdiv_tohw) { ret =_p_div_to_hw (hw,1 << p_div);
Signature · 1 line
2.17.1
Quoted 14 lines · ryang
The current behavior is that
clk_round_ratewould return the same clock rate passed to it for valid PLL configurations. This change will return the exact rate the PLL will provide in accordance with clk API.Signed-off-by ryang <[email protected]>--- drivers/clk/tegra/clk-pll.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)drivers/clk/tegra/clk-pll.c +0
-0
drivers/clk/tegra/clk-pll.c static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, · line 599
Quoted 6 lines
drivers/clk/tegra/clk-pll.c +2
-1@@ -595,7 +595,12 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,return -EINVAL ; } - cfg->output_rate >>= p_div; +if (cfg->m ==0 ) { + cfg->output_rate =0 ;
I think a WARN_ON() is appropriate here. the input divider should never be 0.
Peter.
Quoted 10 lines
drivers/clk/tegra/clk-pll.c +4
-0+ }else { + cfg->output_rate = cfg->n *DIV_ROUND_UP (parent_rate, cfg->m); + cfg->output_rate >>= p_div; + }if (pll->params->pdiv_tohw) { ret =_p_div_to_hw (hw,1 << p_div);Signature · 1 line
2.17.1
Quoted 18 lines · Peter De Schrijver
Quoted 17 lines · ryang
The current behavior is that
clk_round_ratewould return the same clock rate passed to it for valid PLL configurations. This change will return the exact rate the PLL will provide in accordance with clk API.Signed-off-by ryang <[email protected]>--- drivers/clk/tegra/clk-pll.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)drivers/clk/tegra/clk-pll.c +0
-0@@ -595,7 +595,12 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,return -EINVAL ; }
Quoted 8 lines
drivers/clk/tegra/clk-pll.c static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, · line 599
Quoted 3 lines
drivers/clk/tegra/clk-pll.c +2
-1- cfg->output_rate >>= p_div; +if (cfg->m ==0 ) { + cfg->output_rate =0 ;I think a
WARN_ON()is appropriate here. the input divider should never be 0.Peter.
Should it return -EINVAL (or some error) too? _calc_rate is also in the clk_set_rate code path. I think we want to avoid programming the register to 0 input divider all together?
Quoted 10 lines
Quoted 10 lines
drivers/clk/tegra/clk-pll.c +4
-0+ }else { + cfg->output_rate = cfg->n *DIV_ROUND_UP (parent_rate, cfg->m); + cfg->output_rate >>= p_div; + }if (pll->params->pdiv_tohw) { ret =_p_div_to_hw (hw,1 << p_div);Signature · 1 line
2.17.1
Quoted 25 lines · r yang
Quoted 24 lines · Peter De Schrijver
Quoted 14 lines · ryang
The current behavior is that
clk_round_ratewould return the same clock rate passed to it for valid PLL configurations. This change will return the exact rate the PLL will provide in accordance with clk API.Signed-off-by ryang <[email protected]>--- drivers/clk/tegra/clk-pll.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)drivers/clk/tegra/clk-pll.c +0
-0drivers/clk/tegra/clk-pll.c static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, · line 599
Quoted 6 lines
drivers/clk/tegra/clk-pll.c +2
-1@@ -595,7 +595,12 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,return -EINVAL ; } - cfg->output_rate >>= p_div; +if (cfg->m ==0 ) { + cfg->output_rate =0 ;I think a
WARN_ON()is appropriate here. the input divider should never be 0.
Quoted 7 lines
Quoted 2 lines
Peter.
Should it return
-EINVAL(or some error) too?_calc_rateis also in theclk_set_ratecode path. I think we want to avoid programming the register to 0 input divider all together?
Yes. writing 0 to the input divider is usually not allowed. In some cases it's equivalent to writing 1, but better not count on that.
Peter.
Quoted 10 lines
Quoted 10 lines
Quoted 10 lines
drivers/clk/tegra/clk-pll.c +4
-0+ }else { + cfg->output_rate = cfg->n *DIV_ROUND_UP (parent_rate, cfg->m); + cfg->output_rate >>= p_div; + }if (pll->params->pdiv_tohw) { ret =_p_div_to_hw (hw,1 << p_div);Signature · 1 line
2.17.1
Quoted 8 lines · ryang
The current behavior is that
clk_round_ratewould return the same clock rate passed to it for valid PLL configurations. This change will return the exact rate the PLL will provide in accordance with clk API.Signed-off-by ryang <[email protected]>--- drivers/clk/tegra/clk-pll.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)
With Peter's comment addressed:
Quoted 5 lines · ryang
The current behavior is that
clk_round_ratewould return the same clock rate passed to it for valid PLL configurations. This change will return the exact rate the PLL will provide in accordance with clk API.Signed-off-by ryang <[email protected]>
A minor comment.. [0] require a real name, it's not even obvious whether you're "Ryan G" or "R Yang".