initial support for "suniv" Allwinner new ARM9 SoC

Allwinner also has some ARMv5 SoCs.

In order to add support for them, add a CONFIG_ARCH_SUNXI_V7 bool config which is selected when a ARMv7 soc is selected, and make CONFIG_ARCH_SUNXI a common option which is selected by both V7 and V5 sunxi option.

Signed-off-by Mesih Kilinc <[email protected]>

---
 arch/arm/mach-sunxi/Kconfig | 23 ++++++++++++++++-------
 1 file changed, 16 insertions(+), 7 deletions(-)

arch/arm/mach-sunxi/Kconfig +1 -1

index d9c8ecf..7e5f173 100644
@@ -6,31 +6,38 @@ menuconfig ARCH_SUNXI
 	select GENERIC_IRQ_CHIP
 	select GPIOLIB
 	select PINCTRL
-	select PM_OPP
 	select SUN4I_TIMER
 	select RESET_CONTROLLER
+	help

Quoted 27 lines · Mesih Kilinc

Allwinner also has some ARMv5 SoCs.

In order to add support for them, add a CONFIG_ARCH_SUNXI_V7 bool config which is selected when a ARMv7 soc is selected, and make CONFIG_ARCH_SUNXI a common option which is selected by both V7 and V5 sunxi option.

Signed-off-by Mesih Kilinc <[email protected]>

---
 arch/arm/mach-sunxi/Kconfig | 23 ++++++++++++++++-------
 1 file changed, 16 insertions(+), 7 deletions(-)

arch/arm/mach-sunxi/Kconfig +2 -1

index d9c8ecf..7e5f173 100644
@@ -6,31 +6,38 @@ menuconfig ARCH_SUNXI
 	select GENERIC_IRQ_CHIP
 	select GPIOLIB
 	select PINCTRL
-	select PM_OPP
 	select SUN4I_TIMER
 	select RESET_CONTROLLER
+	help
+	  Support for Allwinner ARM-based family of processors
 
 if ARCH_SUNXI
 

arch/arm/mach-sunxi/Kconfig menuconfig ARCH_SUNXI · line 21

Quoted 6 lines

arch/arm/mach-sunxi/Kconfig +6 -0

+if ARCH_MULTI_V7
+
+config ARCH_SUNXI_V7
+	bool
+	select PM_OPP
+

Actually, thinking more about this, I don't see why the PM_OPP config option should be made specific to the ARMv7 sunxi SoCs, you will have things cpufreq enabled at some point as well on the armv5 support.

arch/arm/mach-sunxi/Kconfig menuconfig ARCH_SUNXI · line 24

Quoted 4 lines

arch/arm/mach-sunxi/Kconfig +1 -1

 config MACH_SUN4I
 	bool "Allwinner A10 (sun4i) SoCs support"
-	default ARCH_SUNXI
+	select ARCH_SUNXI_V7

The option is still changed from being on by default to being off by default. This breaks all the defconfig, and we really shouldn't change that.

Quoted 28 lines · Maxime Ripard

Quoted 27 lines · Mesih Kilinc

Allwinner also has some ARMv5 SoCs.

In order to add support for them, add a CONFIG_ARCH_SUNXI_V7 bool config which is selected when a ARMv7 soc is selected, and make CONFIG_ARCH_SUNXI a common option which is selected by both V7 and V5 sunxi option.

Signed-off-by Mesih Kilinc <[email protected]>

---
 arch/arm/mach-sunxi/Kconfig | 23 ++++++++++++++++-------
 1 file changed, 16 insertions(+), 7 deletions(-)

arch/arm/mach-sunxi/Kconfig +2 -1

index d9c8ecf..7e5f173 100644
@@ -6,31 +6,38 @@ menuconfig ARCH_SUNXI
 	select GENERIC_IRQ_CHIP
 	select GPIOLIB
 	select PINCTRL
-	select PM_OPP
 	select SUN4I_TIMER
 	select RESET_CONTROLLER
+	help
+	  Support for Allwinner ARM-based family of processors
 
 if ARCH_SUNXI
 

Quoted 11 lines

arch/arm/mach-sunxi/Kconfig menuconfig ARCH_SUNXI · line 21

Quoted 6 lines

arch/arm/mach-sunxi/Kconfig +6 -0

+if ARCH_MULTI_V7
+
+config ARCH_SUNXI_V7
+	bool
+	select PM_OPP
+

Actually, thinking more about this, I don't see why the PM_OPP config option should be made specific to the ARMv7 sunxi SoCs, you will have things cpufreq enabled at some point as well on the armv5 support.

OK. I was basing this code to the first patch series.
So there will be no need for ARCH_SUNXI_VX configs. Should I drop them and differantiate IC's by only ARCH_MULTI_VX?

Add new Allwinner ARMv5 F1C100s SoC's compatible string

Signed-off-by Mesih Kilinc <[email protected]>

Add option for Allwinner ARMv5 SoCs and SoC F1C100s (which has a die used for many new F-series products, including F1C100A, F1C100s, F1C200s, F1C500, F1C600).

Signed-off-by Mesih Kilinc <[email protected]>

Add compatible string for Alwinner suniv F1C100s SoC interrupt controller which is stripped version of sun4i

Signed-off-by Mesih Kilinc <[email protected]>

The new F-series SoCs (suniv) from Allwinner use an stripped version of the interrupt controller in A10/A13

Add support for it in irq-sun4i driver.

Signed-off-by Mesih Kilinc <[email protected]>

---
 drivers/irqchip/irq-sun4i.c | 104 +++++++++++++++++++++++++++++++-------------
 1 file changed, 74 insertions(+), 30 deletions(-)

drivers/irqchip/irq-sun4i.c +0 -0

index e3e5b91..7ca4a4d 100644

drivers/irqchip/irq-sun4i.c +46 -22

 static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs);
 

@@ -43,7 +53,7 @@ static void sun4i_irq_ack(struct irq_data *irqd)
 	if (irq != 0)
 		return; /* Only IRQ 0 / the ENMI needs to be acked */
 
-	writel(BIT(0), sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0));
+	writel(BIT(0), irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0));
 }
 
 static void sun4i_irq_mask(struct irq_data *irqd)

@@ -53,9 +63,9 @@ static void sun4i_irq_mask(struct irq_data *irqd)
 	int reg = irq / 32;
 	u32 val;
 
-	val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
+	val = readl(irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg));
 	writel(val & ~(1 << irq_off),
-	       sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
+	       irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg));
 }
 
 static void sun4i_irq_unmask(struct irq_data *irqd)

@@ -65,9 +75,9 @@ static void sun4i_irq_unmask(struct irq_data *irqd)
 	int reg = irq / 32;
 	u32 val;
 
-	val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
+	val = readl(irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg));
 	writel(val | (1 << irq_off),
-	       sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
+	       irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg));
 }
 
 static struct irq_chip sun4i_irq_chip = {

@@ -95,42 +105,76 @@ static const struct irq_domain_ops sun4i_irq_ops = {
 static int __init sun4i_of_init(struct device_node *node,
 				struct device_node *parent)
 {
-	sun4i_irq_base = of_iomap(node, 0);
-	if (!sun4i_irq_base)
+	irq_ic_data->irq_base = of_iomap(node, 0);
+	if (!irq_ic_data->irq_base)
 		panic("%pOF: unable to map IC registers\n",
 			node);
 
 	/* Disable all interrupts */
-	writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(0));
-	writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(1));
-	writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(2));
+	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(0));
+	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(1));
+	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(2));
 
 	/* Unmask all the interrupts, ENABLE_REG(x) is used for masking */
-	writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(0));
-	writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(1));
-	writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(2));
+	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(0));
+	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(1));
+	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(2));
 
 	/* Clear all the pending interrupts */
-	writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0));
-	writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(1));
-	writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(2));
+	writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0));
+	writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(1));
+	writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(2));
 
-	/* Enable protection mode */
-	writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG);
+	/* Enable protection mode (not available in suniv) */
+	if (of_device_is_compatible(node, "allwinner,sun4i-a10-ic"))
+		writel(0x01, irq_ic_data->irq_base + SUN4I_IRQ_PROTECTION_REG);
 
 	/* Configure the external interrupt source type */
-	writel(0x00, sun4i_irq_base + SUN4I_IRQ_NMI_CTRL_REG);
+	writel(0x00, irq_ic_data->irq_base + SUN4I_IRQ_NMI_CTRL_REG);
 
-	sun4i_irq_domain = irq_domain_add_linear(node, 3 * 32,
+	irq_ic_data->irq_domain = irq_domain_add_linear(node, 3 * 32,
 						 &sun4i_irq_ops, NULL);
-	if (!sun4i_irq_domain)
+	if (!irq_ic_data->irq_domain)
 		panic("%pOF: unable to create IRQ domain\n", node);
 
 	set_handle_irq(sun4i_handle_irq);
 
 	return 0;
 }
-IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_of_init);
+
+static int __init sun4i_ic_of_init(struct device_node *node,
+				   struct device_node *parent)
+{
+	irq_ic_data = kzalloc(sizeof(struct sunxi_irq_chip_data), GFP_KERNEL);
+	if (!irq_ic_data) {
+		pr_err("kzalloc failed!\n");
+		return -ENOMEM;
+	}
+
+	irq_ic_data->enable_req_offset = SUN4I_IRQ_ENABLE_REG_OFFSET;
+	irq_ic_data->mask_req_offset = SUN4I_IRQ_MASK_REG_OFFSET;
+
+	return sun4i_of_init(node, parent);
+}
+
+IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_ic_of_init);
+
+static int __init suniv_ic_of_init(struct device_node *node,
+				   struct device_node *parent)
+{
+	irq_ic_data = kzalloc(sizeof(struct sunxi_irq_chip_data), GFP_KERNEL);
+	if (!irq_ic_data) {
+		pr_err("kzalloc failed!\n");

Hi Mesih,

Quoted 10 lines

The new F-series SoCs (suniv) from Allwinner use an stripped version of the interrupt controller in A10/A13

Add support for it in irq-sun4i driver.

Signed-off-by Mesih Kilinc <[email protected]>

---
 drivers/irqchip/irq-sun4i.c | 104 +++++++++++++++++++++++++++++++-------------
 1 file changed, 74 insertions(+), 30 deletions(-)

drivers/irqchip/irq-sun4i.c line 32

Quoted 12 lines

drivers/irqchip/irq-sun4i.c +2 -2

index e3e5b91..7ca4a4d 100644
@@ -28,11 +28,21 @@
 #define SUN4I_IRQ_NMI_CTRL_REG		0x0c
 #define SUN4I_IRQ_PENDING_REG(x)	(0x10 + 0x4 * x)
 #define SUN4I_IRQ_FIQ_PENDING_REG(x)	(0x20 + 0x4 * x)
-#define SUN4I_IRQ_ENABLE_REG(x)		(0x40 + 0x4 * x)
-#define SUN4I_IRQ_MASK_REG(x)		(0x50 + 0x4 * x)
+#define SUN4I_IRQ_ENABLE_REG(x)		(irq_ic_data->enable_req_offset + 0x4 * x)
+#define SUN4I_IRQ_MASK_REG(x)		(irq_ic_data->mask_req_offset + 0x4 * x)

You shouldn't have all the values you use passed as argument, so irq_ic_data should be one of them here.

drivers/irqchip/irq-sun4i.c line 38

Quoted 6 lines

drivers/irqchip/irq-sun4i.c +6 -0

+#define SUN4I_IRQ_ENABLE_REG_OFFSET	0x40
+#define SUN4I_IRQ_MASK_REG_OFFSET	0x50
+#define SUNIV_IRQ_ENABLE_REG_OFFSET	0x20
+#define SUNIV_IRQ_MASK_REG_OFFSET	0x30
+
+struct sunxi_irq_chip_data{

^ a space here

drivers/irqchip/irq-sun4i.c line 42

Quoted 4 lines

drivers/irqchip/irq-sun4i.c +4 -0

+	void __iomem *irq_base;
+	struct irq_domain *irq_domain;
+	u32 enable_req_offset;
+	u32 mask_req_offset;

s/req/reg/ ?

Quoted 11 lines

drivers/irqchip/irq-sun4i.c +11 -0

+
+static int __init suniv_ic_of_init(struct device_node *node,
+				   struct device_node *parent)
+{
+	irq_ic_data = kzalloc(sizeof(struct sunxi_irq_chip_data), GFP_KERNEL);
+	if (!irq_ic_data) {
+		pr_err("kzalloc failed!\n");
+		return -ENOMEM;
+	}
+
+	irq_ic_data->enable_req_offset = SUNIV_IRQ_ENABLE_REG_OFFSET;

drivers/irqchip/irq-sun4i.c static const struct irq_domain_ops sun4i_irq_ops = { · line 177

Quoted 6 lines

drivers/irqchip/irq-sun4i.c +6 -0

+	irq_ic_data->mask_req_offset = SUNIV_IRQ_MASK_REG_OFFSET;
+
+	return sun4i_of_init(node, parent);
+}
+
+IRQCHIP_DECLARE(allwinner_sunvi_ic, "allwinner,suniv-f1c100s-ic", suniv_ic_of_init);

You can even split that addition to a new patch as well.

Quoted 7 lines

Quoted 7 lines

drivers/irqchip/irq-sun4i.c +0 -0

index e3e5b91..7ca4a4d 100644
@@ -28,11 +28,21 @@
 #define SUN4I_IRQ_NMI_CTRL_REG		0x0c
 #define SUN4I_IRQ_PENDING_REG(x)	(0x10 + 0x4 * x)

Quoted 9 lines

drivers/irqchip/irq-sun4i.c line 32

Quoted 5 lines

drivers/irqchip/irq-sun4i.c +2 -2

 #define SUN4I_IRQ_FIQ_PENDING_REG(x)	(0x20 + 0x4 * x)
-#define SUN4I_IRQ_ENABLE_REG(x)		(0x40 + 0x4 * x)
-#define SUN4I_IRQ_MASK_REG(x)		(0x50 + 0x4 * x)
+#define SUN4I_IRQ_ENABLE_REG(x)		(irq_ic_data->enable_req_offset + 0x4 * x)
+#define SUN4I_IRQ_MASK_REG(x)		(irq_ic_data->mask_req_offset + 0x4 * x)

You shouldn't have all the values you use passed as argument, so irq_ic_data should be one of them here.

Could you elaborate it a little bit?

Quoted 11 lines

Quoted 11 lines

drivers/irqchip/irq-sun4i.c +11 -0

+
+static int __init suniv_ic_of_init(struct device_node *node,
+				   struct device_node *parent)
+{
+	irq_ic_data = kzalloc(sizeof(struct sunxi_irq_chip_data), GFP_KERNEL);
+	if (!irq_ic_data) {
+		pr_err("kzalloc failed!\n");
+		return -ENOMEM;
+	}
+
+	irq_ic_data->enable_req_offset = SUNIV_IRQ_ENABLE_REG_OFFSET;

Quoted 8 lines

drivers/irqchip/irq-sun4i.c static const struct irq_domain_ops sun4i_irq_ops = { · line 177

Quoted 6 lines

drivers/irqchip/irq-sun4i.c +6 -0

+	irq_ic_data->mask_req_offset = SUNIV_IRQ_MASK_REG_OFFSET;
+
+	return sun4i_of_init(node, parent);
+}
+
+IRQCHIP_DECLARE(allwinner_sunvi_ic, "allwinner,suniv-f1c100s-ic", suniv_ic_of_init);

You can even split that addition to a new patch as well.

OK. I will do 3 patches. First one will add a struct that holds only base and domain. Second one will add register offsets to that struct. Third one will add f1c100s support. Is that ok?

Add compatible string for Allwinner suniv timer which is similar to sun4i timer.

Signed-off-by Mesih Kilinc <[email protected]>

The suniv (new F-series) chip has a timer with less functionality than the A10 timer, e.g. it has only 3 channels.

Add a new compatible for it. As we didn't use the extra channels on A10 either now, the code needn't to be changed.

The suniv chip is based on ARM926EJ-S CPU, thus it has no architecture timer.

Register sun4i_timer as sched_clock on it.

Signed-off-by Mesih Kilinc <[email protected]>

The suniv (new F-series) chip has a timer with less functionality than the A10 timer, e.g. it has only 3 channels.

Add a new compatible for it. As we didn't use the extra channels on A10 either now, the code needn't to be changed.

The suniv chip is based on ARM926EJ-S CPU, thus it has no architecture timer.

Register sun4i_timer as sched_clock on it.

Signed-off-by Mesih Kilinc <[email protected]>

---
 drivers/clocksource/sun4i_timer.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

drivers/clocksource/sun4i_timer.c +4 -1

index 6e0180a..65f38f6 100644
@@ -186,7 +186,8 @@ static int __init sun4i_timer_init(struct device_node *node)
 	 */
 	if (of_machine_is_compatible("allwinner,sun4i-a10") ||
 	    of_machine_is_compatible("allwinner,sun5i-a13") ||
-	    of_machine_is_compatible("allwinner,sun5i-a10s"))
+	    of_machine_is_compatible("allwinner,sun5i-a10s") ||
+	    of_machine_is_compatible("allwinner,suniv-f1c100s"))
 		sched_clock_register(sun4i_timer_sched_read, 32,
 				     timer_of_rate(&to));
 

@@ -218,3 +219,5 @@ static int __init sun4i_timer_init(struct device_node *node)
 }
 TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
 		       sun4i_timer_init);
+TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer",
+		       sun4i_timer_init);

Add compatible string for Allwinner suniv F1C100s SoC's pinctrl.

Signed-off-by Mesih Kilinc <[email protected]>

The suniv F1C100s chip (several new F-series SoCs) of Allwinner has a pin
controller like other SoCs from Allwinner.

Add support for it.

Signed-off-by Mesih Kilinc <[email protected]>

Add compatiple string for Allwinner suniv F1C100s CCU. Add clock and reset definitions.

Signed-off-by Mesih Kilinc <[email protected]>

The suniv F1C100s SoC (the chip in some new F-series products of Allwinner)
has a CCU which seems to be a stripped version of the CCU in SoCs after sun6i.

Add support for the CCU.

Signed-off-by Mesih Kilinc <[email protected]>

The suniv ARMv5 F1C100s chip has similar sram controller to sun4i A10. Add compatible string for it.

Signed-off-by Mesih Kilinc <[email protected]>

Allwinner ARMv5 F1C100s has similar sram controller to sun4i A10 Add compatible strings for it.

Signed-off-by Mesih Kilinc <[email protected]>

Allwinner ARMv5 F1C100s has similar watchdog timer to sun6i A31. Add definition for it.

Signed-off-by Mesih Kilinc <[email protected]>

F1C100s is one product with the suniv die, which has a 32MiB co-packaged DDR1 DRAM chip. As we have the support for suniv pin controller and CCU now, add a initial DTSI for it.

Signed-off-by Mesih Kilinc <[email protected]>

---
 arch/arm/boot/dts/suniv-f1c100s.dtsi | 151 +++++++++++++++++++++++++++++++++++
 1 file changed, 151 insertions(+)
 create mode 100644 arch/arm/boot/dts/suniv-f1c100s.dtsi

arch/arm/boot/dts/suniv-f1c100s.dtsi new file +27 -0

new file mode 100644
index 0000000..3ad64ee
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright 2018 Icenowy Zheng <[email protected]>
+ * Copyright 2018 Mesih Kilinc <[email protected]>
+ */
+
+#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
+#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&intc>;
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		osc24M: clk-24M {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "osc24M";
+		};
+
+		osc32k: clk-32k {

arch/arm/boot/dts/suniv-f1c100s.dtsi new file +66 -0

+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		sram-controller at 1c00000 {
+			compatible = "allwinner,suniv-f1c100s-system-control";
+			reg = <0x01c00000 0x30>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			sram_d: sram at 10000 {
+				compatible = "mmio-sram";
+				reg = <0x00010000 0x1000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x00010000 0x1000>;
+
+				otg_sram: sram-section at 0 {
+					compatible = "allwinner,suniv-f1c100s-sram-d";
+					reg = <0x0000 0x1000>;
+					status = "disabled";
+				};
+			};
+		};
+
+		ccu: clock at 1c20000 {
+			compatible = "allwinner,suniv-f1c100s-ccu";
+			reg = <0x01c20000 0x400>;
+			clocks = <&osc24M>, <&osc32k>;
+			clock-names = "hosc", "losc";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		intc: interrupt-controller at 1c20400 {
+			compatible = "allwinner,suniv-f1c100s-ic";
+			reg = <0x01c20400 0x400>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+
+		pio: pinctrl at 1c20800 {
+			compatible = "allwinner,suniv-f1c100s-pinctrl";
+			reg = <0x01c20800 0x400>;
+			interrupts = <38>, <39>, <40>;
+			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
+			clock-names = "apb", "hosc", "losc";
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			#gpio-cells = <3>;
+
+			uart0_pins_a: uart-pins-pe {
+				pins = "PE0", "PE1";
+				function = "uart0";
+			};
+		};