arm64: dts: Add sdm845 GPU/GMU and SMMU
Subsystems (6)
v5 cover arm64: dts: Add sdm845 GPU/GMU and SMMU
Now that more of the dependent bindings are headed upstream this a refresh of of https://patchwork.freedesktop.org/series/39308/ to add bindings and nodes for the GPU/GMU and GPU SMMU for sdm845.
This change requires the following dependencies:
gpucc:git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git e431c92188a9
include/dt-bindings/power/qcom-rpmpd.h:
https://patchwork.kernel.org/patch/10711119/
qcom,smmu-v2 binding:
https://patchwork.kernel.org/patch/10581911/
v5: Use symbolic names for the RPMH power levels defined in OPP table,
move the opp tables as children of their respective nodes and rename the iommu device.
v4: Rebase
v3: Split GMU PDC region into two GPU specific sections, fix indentation,
really use qcom,gmu for the phandle name
v2: changed qcom,arc-level to qcom,level following discussion with Viresh;
change gmu phandle to qcom,gmu per Rob
Jordan Crouse (2):
dt-bindings: Document,qcom,adreno-gmu
arm64: dts: sdm845: Add gpu and gmu device nodes
.../devicetree/bindings/display/msm/gmu.txt | 54 ++++++++ .../devicetree/bindings/display/msm/gpu.txt | 2 + arch/arm64/boot/dts/qcom/sdm845.dtsi | 123 ++++++++++++++++++ 3 files changed, 179 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt
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PATCH v5 1/2 dt-bindings: Document,qcom,adreno-gmu
Document the device tree bindings for the Adreno GMU device available on Adreno a6xx targets.
--- .../devicetree/bindings/display/msm/gmu.txt | 54 +++++++++++++++++++ .../devicetree/bindings/display/msm/gpu.txt | 2 + 2 files changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt
Documentation/devicetree/bindings/display/msm/gmu.txt new file +54 -0
@@ -0,0 +1,54 @@ +Qualcomm adreno/snapdragon GMU (Graphics management unit) + +The GMU is a programmable power controller for the GPU. the CPU controls the +GMU which in turn handles power controls for the GPU. + +Required properties: +- compatible: + * "qcom,adreno-gmu" +- reg: Physical base address and length of the GMU registers. +- reg-names: Matching names for the register regions + * "gmu" + * "gmu_pdc" +- interrupts: The interrupt signals from the GMU. +- interrupt-names: Matching names for the interrupts + * "hfi" + * "gmu" +- clocks: phandles to the device clocks +- clock-names: Matching names for the clocks + * "gmu" + * "cxo" + * "axi" + * "mnoc" +- power-domains: should be <&clock_gpucc GPU_CX_GDSC> +- iommus: phandle to the adreno iommu +- operating-points-v2: phandle to the OPP operating points + +Example: + +/ { + ... + + gmu: gmu@506a000 { + compatible="qcom,adreno-gmu"; + + reg = <0x506a000 0x30000>, + <0xb200000 0x300000>; + reg-names = "gmu", "gmu_pdc"; + + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + + clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>, + <&clock_gpucc GPU_CC_CXO_CLK>, + <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, + <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + + power-domains = <&clock_gpucc GPU_CX_GDSC>; + iommus = <&adreno_smmu 5>; + + i operating-points-v2 = <&gmu_opp_table>; + }; +};
Documentation/devicetree/bindings/display/msm/gpu.txt +2 -0
@@ -14,6 +14,8 @@ Required properties: * "core" * "iface" * "mem_iface" +- qcom,gmu: For a6xx and newer targets a phandle to the GMU device that will + control the power for the GPU Example:
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Re: [PATCH v5 1/2] dt-bindings: Document, qcom, adreno-gmu
Hi,
Quoted 10 lines · Jordan Crouse
Document the device tree bindings for the Adreno GMU device available on Adreno a6xx targets.
Reviewed-by Rob Herring <[email protected]>Signed-off-by Jordan Crouse <[email protected]>--- .../devicetree/bindings/display/msm/gmu.txt | 54 +++++++++++++++++++ .../devicetree/bindings/display/msm/gpu.txt | 2 + 2 files changed, 56 insertions(+)
nit: Why does subject have a "," after "Document"?
nit: Should subject start "dt-bindings: drm/msm/a6xx" or something like that? I thought you wanted not just "dt-bindings" but also a subsystem prefix?
Quoted 35 lines
create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txtDocumentation/devicetree/bindings/display/msm/gmu.txt new file +27
-0@@ -0,0 +1,54 @@ +Qualcomm adreno/snapdragon GMU (Graphics management unit) + +The GMU is a programmable power controller for the GPU. the CPU controls the +GMU which in turn handles power controls for the GPU. + +Required properties: +- compatible: + * "qcom,adreno-gmu" +- reg: Physical base address and length of the GMU registers. +- reg-names: Matching names for the register regions + * "gmu" + * "gmu_pdc" +- interrupts: The interrupt signals from the GMU. +- interrupt-names: Matching names for the interrupts + * "hfi" + * "gmu" +- clocks: phandles to the device clocks +- clock-names: Matching names for the clocks + * "gmu" + * "cxo" + * "axi" + * "mnoc" +- power-domains: should be <&clock_gpucc GPU_CX_GDSC> +- iommus: phandle to the adreno iommu +- operating-points-v2: phandle to the OPP operating points + +Example:
Documentation/devicetree/bindings/display/msm/gmu.txt line 37
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/gmu.txt new file +10
-0+ +/ { + ... + + gmu: gmu@506a000 { + compatible="qcom,adreno-gmu"; + + reg = <0x506a000 0x30000>, + <0xb200000 0x300000>; + reg-names = "gmu", "gmu_pdc";
Your implementation has 3 register ranges but your bindings have 2. You also have a different address for "gmu_pdc" even though it looks like your examples are supposed to be based on sdm845.
(you'd want to not only change the example but also the bindings above)
Documentation/devicetree/bindings/display/msm/gmu.txt line 46
Quoted 9 lines
Documentation/devicetree/bindings/display/msm/gmu.txt new file +9
-0+ + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + + clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>, + <&clock_gpucc GPU_CC_CXO_CLK>, + <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, + <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>;
nit: might as well update to "&gpucc" to match the style of clock controller labels used in sdm845.dts.
Documentation/devicetree/bindings/display/msm/gmu.txt line 52
Quoted 6 lines
Documentation/devicetree/bindings/display/msm/gmu.txt new file +6
-0+ clock-names = "gmu", "cxo", "axi", "memnoc"; + + power-domains = <&clock_gpucc GPU_CX_GDSC>; + iommus = <&adreno_smmu 5>; + + i operating-points-v2 = <&gmu_opp_table>;
Why "i"?
...also: worth actually including the operating table here in the example?
Documentation/devicetree/bindings/display/msm/gpu.txt Required properties: · line 18
Quoted 12 lines
Documentation/devicetree/bindings/display/msm/gmu.txt new file +2
-0+ }; +};Documentation/devicetree/bindings/display/msm/gpu.txt +2
-0@@ -14,6 +14,8 @@ Required properties: * "core" * "iface" * "mem_iface" +- qcom,gmu: For a6xx and newer targets a phandle to the GMU device that will + control the power for the GPU
You seem to have lost something between the previous version of this and the latest. In the last version (and the version Rob gave his review to) you added some extra text. Diffing your old patch to your new one:
-Optional properties.
-- clocks: device clocks. Required for a3xx, a4xx and a5xx targets. a6xx and
- newer with a GMU attached do not have direct clock control from the CPU and
- do not need to provide clock properties.
+- clocks: device clocks
See ../clocks/clock-bindings.txt for details.
-- clock-names: the following clocks can be provided:
+- clock-names: the following clocks are required:
Did you mean to remove that? Your current bindings now say that the clocks are required but then your device tree patch for sdm845 says they're not.
Documentation/devicetree/bindings/display/msm/gpu.txt Required properties: · line 20
Quoted 1 line
Documentation/devicetree/bindings/display/msm/gpu.txt +0
-0Example:
While you're touching this file, maybe update the "Example" so instead of saying "qcom,kgsl-3d0@" it says "gpu@"
-Doug
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Re: [PATCH v5 1/2] dt-bindings: Document,qcom,adreno-gmu
Quoted 7 lines · Doug Anderson
Hi,
Quoted 4 lines · Jordan Crouse
Document the device tree bindings for the Adreno GMU device available on Adreno a6xx targets.
Quoted 8 lines
Quoted 6 lines
Reviewed-by Rob Herring <[email protected]>Signed-off-by Jordan Crouse <[email protected]>--- .../devicetree/bindings/display/msm/gmu.txt | 54 +++++++++++++++++++ .../devicetree/bindings/display/msm/gpu.txt | 2 + 2 files changed, 56 insertions(+)nit: Why does subject have a "," after "Document"?
Typo.
Quoted 3 lines
nit: Should subject start "dt-bindings: drm/msm/a6xx" or something like that? I thought you wanted not just "dt-bindings" but also a subsystem prefix?
I was trying to reuse the subject from the previous versions, but I would be happy to change it.
Quoted 51 lines
Quoted 36 lines
create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txtDocumentation/devicetree/bindings/display/msm/gmu.txt new file +27
-0@@ -0,0 +1,54 @@ +Qualcomm adreno/snapdragon GMU (Graphics management unit) + +The GMU is a programmable power controller for the GPU. the CPU controls the +GMU which in turn handles power controls for the GPU. + +Required properties: +- compatible: + * "qcom,adreno-gmu" +- reg: Physical base address and length of the GMU registers. +- reg-names: Matching names for the register regions + * "gmu" + * "gmu_pdc" +- interrupts: The interrupt signals from the GMU. +- interrupt-names: Matching names for the interrupts + * "hfi" + * "gmu" +- clocks: phandles to the device clocks +- clock-names: Matching names for the clocks + * "gmu" + * "cxo" + * "axi" + * "mnoc" +- power-domains: should be <&clock_gpucc GPU_CX_GDSC> +- iommus: phandle to the adreno iommu +- operating-points-v2: phandle to the OPP operating points + +Example:Documentation/devicetree/bindings/display/msm/gmu.txt line 37
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/gmu.txt new file +10
-0+ +/ { + ... + + gmu: gmu@506a000 { + compatible="qcom,adreno-gmu"; + + reg = <0x506a000 0x30000>, + <0xb200000 0x300000>; + reg-names = "gmu", "gmu_pdc";Your implementation has 3 register ranges but your bindings have 2. You also have a different address for "
gmu_pdc" even though it looks like your examples are supposed to be based on sdm845.
Quoted 1 line
(you'd want to not only change the example but also the bindings above)
I'll update the settings - a new region has indeed been added since the last time we were here.
Quoted 15 lines
Documentation/devicetree/bindings/display/msm/gmu.txt line 46
Quoted 10 lines
Documentation/devicetree/bindings/display/msm/gmu.txt new file +9
-0+ + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + + clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>, + <&clock_gpucc GPU_CC_CXO_CLK>, + <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, + <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>;nit: might as well update to "&gpucc" to match the style of clock controller labels used in
sdm845.dts.
Quoted 8 lines
Documentation/devicetree/bindings/display/msm/gmu.txt line 52
Quoted 6 lines
Documentation/devicetree/bindings/display/msm/gmu.txt new file +6
-0+ clock-names = "gmu", "cxo", "axi", "memnoc"; + + power-domains = <&clock_gpucc GPU_CX_GDSC>; + iommus = <&adreno_smmu 5>; + + i operating-points-v2 = <&gmu_opp_table>;Why "i"?
Also a typo.
Quoted 1 line
...also: worth actually including the operating table here in the example?
I say no. It might good practice to have the opp tables in the child node but I don't think it is mandatory from a bindings perspective.
The bindings are documented elsewhere and to me that seems enough for our purposes - at least thats our story for smmu and gpucc and other phandles.
Quoted 19 lines
Documentation/devicetree/bindings/display/msm/gpu.txt Required properties: · line 18
Quoted 13 lines
Documentation/devicetree/bindings/display/msm/gmu.txt new file +2
-0+ }; +};Documentation/devicetree/bindings/display/msm/gpu.txt +2
-0@@ -14,6 +14,8 @@ Required properties: * "core" * "iface" * "mem_iface" +- qcom,gmu: For a6xx and newer targets a phandle to the GMU device that will + control the power for the GPUYou seem to have lost something between the previous version of this and the latest. In the last version (and the version Rob gave his review to) you added some extra text. Diffing your old patch to your new one:
Review
Quoted 8 lines
(quoted diff) +2
-5-Optional properties. -- clocks: device clocks. Required for a3xx, a4xx and a5xx targets. a6xx and - newer with a GMU attached do not have direct clock control from the CPU and - do not need to provide clock properties. +- clocks: device clocks See ../clocks/clock-bindings.txt for details. -- clock-names: the following clocks can be provided: +- clock-names: the following clocks are required:
You are right that "can be provided" is correct.
Quoted 8 lines
Did you mean to remove that? Your current bindings now say that the clocks are required but then your device tree patch for sdm845 says they're not.
Documentation/devicetree/bindings/display/msm/gpu.txt Required properties: · line 20
Quoted 1 line
Documentation/devicetree/bindings/display/msm/gpu.txt +0
-0Example:While you're touching this file, maybe update the "Example" so instead of saying "qcom,kgsl-3d0@" it says "gpu@"
I don't want to much with the example too much lest we "break" it for older targets. I'll see what generic stuff we can change without breaking the original intent.
Jordan
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PATCH v5 2/2 arm64: dts: sdm845: Add gpu and gmu device nodes
In reply to a message not in the archiveAdd the nodes to describe the Adreno GPU and GMU devices.
--- arch/arm64/boot/dts/qcom/sdm845.dtsi | 123 +++++++++++++++++++++++++++ 1 file changed, 123 insertions(+)
arch/arm64/boot/dts/qcom/sdm845.dtsi +123 -0
@@ -7,9 +7,11 @@ #include <dt-bindings/clock/qcom,dispcc-sdm845.h> #include <dt-bindings/clock/qcom,gcc-sdm845.h> +#include <dt-bindings/clock/qcom,gpucc-sdm845.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/phy/phy-qcom-qusb2.h> +#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/reset/qcom,sdm845-aoss.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/clock/qcom,gcc-sdm845.h>
@@ -1348,6 +1350,127 @@ }; }; + gpu@5000000 { + compatible = "qcom,adreno-630.2", "qcom,adreno"; + #stream-id-cells = <16>; + + reg = <0x5000000 0x40000>, <0x509e000 0x10>; + reg-names = "kgsl_3d0_reg_memory", "cx_mem"; + + /* + * Look ma, no clocks! The GPU clocks and power are + * controlled entirely by the GMU + */ + + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + + iommus = <&adreno_smmu 0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + gpu_opp_table: adreno-opp-table { + compatible = "operating-points-v2-qcom-level"; + + opp-710000000 { + opp-hz = /bits/ 64 <710000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + }; + + opp-675000000 { + opp-hz = /bits/ 64 <675000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + opp-596000000 { + opp-hz = /bits/ 64 <596000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + opp-520000000 { + opp-hz = /bits/ 64 <520000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + opp-414000000 { + opp-hz = /bits/ 64 <414000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + opp-342000000 { + opp-hz = /bits/ 64 <342000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + opp-257000000 { + opp-hz = /bits/ 64 <257000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + }; + }; + + adreno_smmu: iommu@5040000 { + compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; + reg = <0x5040000 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "bus", "iface"; + + power-domains = <&gpucc GPU_CX_GDSC>; + }; + + gmu: gmu@506a000 { + compatible="qcom,adreno-gmu"; + + reg = <0x506a000 0x30000>, + <0xb280000 0x10000>, + <0xb480000 0x10000>; + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; + + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + + power-domains = <&gpucc GPU_CX_GDSC>; + iommus = <&adreno_smmu 5>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: adreno-gmu-opp-table { + compatible = "operating-points-v2-qcom-level"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + }; + }; + usb_1_hsphy: phy@88e2000 { compatible = "qcom,sdm845-qusb2-phy"; reg = <0x88e2000 0x400>;
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Re: [PATCH v5 2/2] arm64: dts: sdm845: Add gpu and gmu device nodes
Hi,
Quoted 13 lines · Jordan Crouse
Add the nodes to describe the Adreno GPU and GMU devices.
Signed-off-by Jordan Crouse <[email protected]>--- arch/arm64/boot/dts/qcom/sdm845.dtsi | 123 +++++++++++++++++++++++++++ 1 file changed, 123 insertions(+)arch/arm64/boot/dts/qcom/sdm845.dtsi +0
-0
arch/arm64/boot/dts/qcom/sdm845.dtsi line 10
Quoted 4 lines
arch/arm64/boot/dts/qcom/sdm845.dtsi +1
-0@@ -7,9 +7,11 @@ #include <dt-bindings/clock/qcom,dispcc-sdm845.h> #include <dt-bindings/clock/qcom,gcc-sdm845.h> +#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
Probably don't need to add this in your patch since (presumably) your patch needs to be based atop
<https://lore.kernel.org/patchwork/patch/1018365/> and that already adds the #include (and also the node that you depend on).
Quoted 8 lines
arch/arm64/boot/dts/qcom/sdm845.dtsi +1
-0#include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/phy/phy-qcom-qusb2.h> +#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/reset/qcom,sdm845-aoss.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/clock/qcom,gcc-sdm845.h>
arch/arm64/boot/dts/qcom/sdm845.dtsi line 1358
Quoted 9 lines
arch/arm64/boot/dts/qcom/sdm845.dtsi +6
-0@@ -1348,6 +1350,127 @@ }; }; + gpu@5000000 { + compatible = "qcom,adreno-630.2", "qcom,adreno"; + #stream-id-cells = <16>; + + reg = <0x5000000 0x40000>, <0x509e000 0x10>; + reg-names = "kgsl_3d0_reg_memory", "cx_mem";
The second register range isn't in your bindings patch. Can you add it?
arch/arm64/boot/dts/qcom/sdm845.dtsi line 1368
Quoted 9 lines
arch/arm64/boot/dts/qcom/sdm845.dtsi +9
-0+ /* + * Look ma, no clocks! The GPU clocks and power are + * controlled entirely by the GMU + */ + + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + + iommus = <&adreno_smmu 0>;
It it worth mentioning the iommus and #stream-id-cells in the bindings?
arch/arm64/boot/dts/qcom/sdm845.dtsi line 1370
Quoted 1 line
arch/arm64/boot/dts/qcom/sdm845.dtsi +1
-0+ operating-points-v2 = <&gpu_opp_table>;
Is it worth mentioning the operating-points-v2 in the bindings patch?
arch/arm64/boot/dts/qcom/sdm845.dtsi line 1374
Quoted 4 lines
arch/arm64/boot/dts/qcom/sdm845.dtsi +4
-0+ + qcom,gmu = <&gmu>; + + gpu_opp_table: adreno-opp-table {
nit: since this is no longer at the top level you can just call it "opp-table" now. That matches what the latest RPMh PD node looks like.
Quoted 75 lines
arch/arm64/boot/dts/qcom/sdm845.dtsi +75
-0+ compatible = "operating-points-v2-qcom-level"; + + opp-710000000 { + opp-hz = /bits/ 64 <710000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + }; + + opp-675000000 { + opp-hz = /bits/ 64 <675000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + opp-596000000 { + opp-hz = /bits/ 64 <596000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + opp-520000000 { + opp-hz = /bits/ 64 <520000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + opp-414000000 { + opp-hz = /bits/ 64 <414000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + opp-342000000 { + opp-hz = /bits/ 64 <342000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + opp-257000000 { + opp-hz = /bits/ 64 <257000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + }; + }; + + adreno_smmu: iommu@5040000 { + compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; + reg = <0x5040000 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "bus", "iface"; + + power-domains = <&gpucc GPU_CX_GDSC>; + }; + + gmu: gmu@506a000 { + compatible="qcom,adreno-gmu"; + + reg = <0x506a000 0x30000>, + <0xb280000 0x10000>, + <0xb480000 0x10000>; + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; + + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>,
arch/arm64/boot/dts/qcom/sdm845.dtsi line 1459
Quoted 10 lines
arch/arm64/boot/dts/qcom/sdm845.dtsi +10
-0+ <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + + power-domains = <&gpucc GPU_CX_GDSC>; + iommus = <&adreno_smmu 5>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: adreno-gmu-opp-table {
Same here that this can just be called "opp-table".
Quoted 5 lines
arch/arm64/boot/dts/qcom/sdm845.dtsi +5
-0+ compatible = "operating-points-v2-qcom-level"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
arch/arm64/boot/dts/qcom/sdm845.dtsi line 1474
Quoted 10 lines
arch/arm64/boot/dts/qcom/sdm845.dtsi +9
-0+ }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + }; + }; + usb_1_hsphy: phy@88e2000 {
Since you won't compile without the gpucc patch maybe pick it before sending out your patch? Then context diff would show gpucc right here and it will avoid merge conflicts.
-Doug
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