ppc: support for the XIVE interrupt controller (POWER9)

PATCH Applied Cédric Le Goater 2 participants 15 messages Dec 17, 2018 – Dec 18, 2018

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Cédric Le Goater

author

2018-12-17 22:35 UTC #0 lore raw

v9 cover ppc: support for the XIVE interrupt controller (POWER9)

Hello,

Here is the version 9 of the QEMU models adding support for the XIVE interrupt controller to the sPAPR machine, under TCG only.

The 'dual' machine, supporting both interrupt modes, is nearly complete, only remains the question on the qirq array, which will be addressed in early 2019 with the support for KVM.

Thanks,

Changes in v9 (sPAPR only) :

- fixed compile breakage on windows
- reworked XIVE capability in ibm,arch-vec-5-platform-support
- fixed default CPU type on 3.1 machines
- updated MAINTAINERS file

* GitHub trees

QEMU sPAPR:

https://github.com/legoater/qemu/commits/xive-v9-4.0

QEMU PowerNV:

https://github.com/legoater/qemu/commits/powernv-3.1

Linux/KVM:

https://github.com/legoater/linux/commits/xive-4.20

OPAL:

https://github.com/legoater/skiboot/commits/xive

Cédric Le Goater (7):
target/ppc: fix the PPC_BIT definitions
target/ppc: replace __builtin_ffssl() by the equivalent ctz routines spapr/xive: fix compilation breakage on windows
spapr: add an extra OV5 field to the sPAPR IRQ backend
spapr: introduce an 'ic-mode' machine option
spapr: change default CPU type to POWER9
MAINTAINERS: PPC: add a XIVE section

 include/hw/ppc/spapr.h     |  7 ++++
 include/hw/ppc/spapr_irq.h |  1 +
 target/ppc/cpu.h           | 21 +++++-----
 hw/intc/spapr_xive.c       | 46 +++++++++++++---------
 hw/ppc/spapr.c             | 80 ++++++++++++++++++++++++++++++++------
 hw/ppc/spapr_cpu_core.c    |  3 +-
 hw/ppc/spapr_irq.c         | 37 +++++++-----------
 MAINTAINERS                |  8 ++++
 8 files changed, 138 insertions(+), 65 deletions(-)

Signature · 1 line

2.17.2

Cédric Le Goater

author

2018-12-17 22:35 UTC #1 lore raw

PATCH v9 1/7 target/ppc: fix the PPC_BIT definitions

Change the PPC_BIT macro to use ULL instead of UL and the PPC_BIT32 and PPC_BIT8 not to use any suffix.

This fixes a compile breakage on windows.

Signed-off-by Cédric Le Goater <[email protected]>

---
 target/ppc/cpu.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

target/ppc/cpu.h +3 -3

index ab68abe8a23c..527181c0f09f 100644
@@ -70,9 +70,9 @@
 #define PPC_ELF_MACHINE     EM_PPC
 #endif
 
-#define PPC_BIT(bit)            (0x8000000000000000UL >> (bit))
-#define PPC_BIT32(bit)          (0x80000000UL >> (bit))
-#define PPC_BIT8(bit)           (0x80UL >> (bit))
+#define PPC_BIT(bit)            (0x8000000000000000ULL >> (bit))
+#define PPC_BIT32(bit)          (0x80000000 >> (bit))
+#define PPC_BIT8(bit)           (0x80 >> (bit))
 #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
 #define PPC_BITMASK32(bs, be)   ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
                                  PPC_BIT32(bs))

Signature · 1 line

2.17.2

David Gibson

2018-12-18 02:23 UTC #2 lore raw

Re: [Qemu-devel] [PATCH v9 1/7] target/ppc: fix the PPC_BIT definitions

Quoted 6 lines · Cédric Le Goater

Change the PPC_BIT macro to use ULL instead of UL and the PPC_BIT32 and PPC_BIT8 not to use any suffix.
This fixes a compile breakage on windows.
Signed-off-by Cédric Le Goater <[email protected]>

Applied (before the rest of the XIVE patches), thanks.

Quoted 21 lines

---
 target/ppc/cpu.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

target/ppc/cpu.h +3 -3

index ab68abe8a23c..527181c0f09f 100644
@@ -70,9 +70,9 @@
 #define PPC_ELF_MACHINE     EM_PPC
 #endif
 
-#define PPC_BIT(bit)            (0x8000000000000000UL >> (bit))
-#define PPC_BIT32(bit)          (0x80000000UL >> (bit))
-#define PPC_BIT8(bit)           (0x80UL >> (bit))
+#define PPC_BIT(bit)            (0x8000000000000000ULL >> (bit))
+#define PPC_BIT32(bit)          (0x80000000 >> (bit))
+#define PPC_BIT8(bit)           (0x80 >> (bit))
 #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
 #define PPC_BITMASK32(bs, be)   ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
                                  PPC_BIT32(bs))

Signature · 4 lines

David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Cédric Le Goater

author

2018-12-17 22:35 UTC #3 lore raw

PATCH v9 2/7 target/ppc: replace __builtin_ffssl() by the equivalent ctz routines

In reply to Cédric Le Goater

And remove the intermediate MASK_TO_LSH macro which does not add any value.

This fixes a compile breakage on windows.

Signed-off-by Cédric Le Goater <[email protected]>

---
 target/ppc/cpu.h | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

target/ppc/cpu.h +9 -6

index 527181c0f09f..f4ef4f214564 100644
@@ -78,18 +78,21 @@
                                  PPC_BIT32(bs))
 #define PPC_BITMASK8(bs, be)    ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
 
+/*
+ * OPAL PPC bitmask field manipulation, used in XIVE, PHB3 and PHB4
+ */
 #if HOST_LONG_BITS == 32
-# define MASK_TO_LSH(m)          (__builtin_ffsll(m) - 1)
+#  define GETFIELD(m, v)        (((v) & (m)) >> ctz32(m))
+#  define SETFIELD(m, v, val)                                   \
+    (((v) & ~(m)) | ((((typeof(v))(val)) << ctz32(m)) & (m)))
 #elif HOST_LONG_BITS == 64
-# define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
+#  define GETFIELD(m, v)        (((v) & (m)) >> ctz64(m))
+#  define SETFIELD(m, v, val)                                   \
+    (((v) & ~(m)) | ((((typeof(v))(val)) << ctz64(m)) & (m)))
 #else
 # error Unknown sizeof long
 #endif
 
-#define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
-#define SETFIELD(m, v, val)                             \
-        (((v) & ~(m)) | ((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m)))
-
 /*****************************************************************************/
 /* Exception vectors definitions                                             */
 enum {

Signature · 1 line

2.17.2

David Gibson

2018-12-18 02:23 UTC #4 lore raw

Re: [Qemu-devel] [PATCH v9 2/7] target/ppc: replace __builtin_ffssl() by the equivalent ctz routines

Quoted 5 lines · Cédric Le Goater

And remove the intermediate MASK_TO_LSH macro which does not add any value.
This fixes a compile breakage on windows.
Signed-off-by Cédric Le Goater <[email protected]>

It's an improvement over what's there, but it still leaves macros whose primary use would be for guest registers, but are typed according to host values, which doesn't make much sense.

I think instead we should redefine your BE64 / BE32 variants in terms of the existing extract*() and deposit*() primitives, and get rid of the GETFIELD / SETFIELD macros.

Quoted 36 lines

---
 target/ppc/cpu.h | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

target/ppc/cpu.h +9 -6

index 527181c0f09f..f4ef4f214564 100644
@@ -78,18 +78,21 @@
                                  PPC_BIT32(bs))
 #define PPC_BITMASK8(bs, be)    ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
 
+/*
+ * OPAL PPC bitmask field manipulation, used in XIVE, PHB3 and PHB4
+ */
 #if HOST_LONG_BITS == 32
-# define MASK_TO_LSH(m)          (__builtin_ffsll(m) - 1)
+#  define GETFIELD(m, v)        (((v) & (m)) >> ctz32(m))
+#  define SETFIELD(m, v, val)                                   \
+    (((v) & ~(m)) | ((((typeof(v))(val)) << ctz32(m)) & (m)))
 #elif HOST_LONG_BITS == 64
-# define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
+#  define GETFIELD(m, v)        (((v) & (m)) >> ctz64(m))
+#  define SETFIELD(m, v, val)                                   \
+    (((v) & ~(m)) | ((((typeof(v))(val)) << ctz64(m)) & (m)))
 #else
 # error Unknown sizeof long
 #endif
 
-#define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
-#define SETFIELD(m, v, val)                             \
-        (((v) & ~(m)) | ((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m)))
-
 /*****************************************************************************/
 /* Exception vectors definitions                                             */
 enum {

Signature · 4 lines

David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Cédric Le Goater

author

2018-12-18 08:08 UTC #5 lore raw

Re: [Qemu-devel] [PATCH v9 2/7] target/ppc: replace __builtin_ffssl() by the equivalent ctz routines

Quoted 7 lines · David Gibson

Quoted 5 lines · Cédric Le Goater
And remove the intermediate MASK_TO_LSH macro which does not add any value.
This fixes a compile breakage on windows.
Signed-off-by Cédric Le Goater <[email protected]>

Quoted 7 lines

It's an improvement over what's there, but it still leaves macros whose primary use would be for guest registers, but are typed according to host values, which doesn't make much sense.
I think instead we should redefine your BE64 / BE32 variants in terms of the existing extract*() and deposit*() primitives, and get rid of the GETFIELD / SETFIELD macros.

I will get rid of the GETFIELD/SETFIELD macros and rewrite the BE64/BE32 variants but I won't use the extract*() and deposit*(). I prefer to keep the same pattern, which is similar to shpc_get/set_status(). I will make the code clearer with static inlines.

I don't really like the names also. what about xive_(get/set)_field(32/64) ?

Quoted 37 lines

Quoted 36 lines

---
 target/ppc/cpu.h | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

target/ppc/cpu.h +9 -6

index 527181c0f09f..f4ef4f214564 100644
@@ -78,18 +78,21 @@
                                  PPC_BIT32(bs))
 #define PPC_BITMASK8(bs, be)    ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
 
+/*
+ * OPAL PPC bitmask field manipulation, used in XIVE, PHB3 and PHB4
+ */
 #if HOST_LONG_BITS == 32
-# define MASK_TO_LSH(m)          (__builtin_ffsll(m) - 1)
+#  define GETFIELD(m, v)        (((v) & (m)) >> ctz32(m))
+#  define SETFIELD(m, v, val)                                   \
+    (((v) & ~(m)) | ((((typeof(v))(val)) << ctz32(m)) & (m)))
 #elif HOST_LONG_BITS == 64
-# define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
+#  define GETFIELD(m, v)        (((v) & (m)) >> ctz64(m))
+#  define SETFIELD(m, v, val)                                   \
+    (((v) & ~(m)) | ((((typeof(v))(val)) << ctz64(m)) & (m)))
 #else
 # error Unknown sizeof long
 #endif
 
-#define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
-#define SETFIELD(m, v, val)                             \
-        (((v) & ~(m)) | ((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m)))
-
 /*****************************************************************************/
 /* Exception vectors definitions                                             */
 enum {

David Gibson

2018-12-18 09:45 UTC #6 lore raw

Re: [Qemu-devel] [PATCH v9 2/7] target/ppc: replace __builtin_ffssl() by the equivalent ctz routines

Quoted 12 lines · Cédric Le Goater

Quoted 11 lines · David Gibson
Quoted 5 lines · Cédric Le Goater
And remove the intermediate MASK_TO_LSH macro which does not add any value.
This fixes a compile breakage on windows.
Signed-off-by Cédric Le Goater <[email protected]>
It's an improvement over what's there, but it still leaves macros whose primary use would be for guest registers, but are typed according to host values, which doesn't make much sense.

Quoted 8 lines

Quoted 3 lines
I think instead we should redefine your BE64 / BE32 variants in terms of the existing extract*() and deposit*() primitives, and get rid of the GETFIELD / SETFIELD macros.
I will get rid of the GETFIELD/SETFIELD macros and rewrite the BE64/BE32 variants but I won't use the extract*() and deposit*(). I prefer to keep the same pattern, which is similar to shpc_get/set_status(). I will make the code clearer with static inlines.

That's fine.

Quoted 2 lines

I don't really like the names also. what about
xive_(get/set)_field(32/64) ?

Sure, works for me. Since these will now be strictly fixed width, you can probably make them inlines instead of macros too, so we get type checking.

Signature · 4 lines

David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Cédric Le Goater

author

2018-12-17 22:35 UTC #7 lore raw

PATCH v9 3/7 spapr/xive: fix compilation breakage on windows

In reply to Cédric Le Goater

Signed-off-by Cédric Le Goater <[email protected]>

---
 hw/intc/spapr_xive.c | 46 +++++++++++++++++++++++++++-----------------
 1 file changed, 28 insertions(+), 18 deletions(-)

hw/intc/spapr_xive.c +28 ~~-18~~

index aaa5865c4080..3ceabe668b16 100644
@@ -589,12 +589,14 @@ static target_ulong h_int_get_source_info(PowerPCCPU *cpu,
     }
 
     if (lisn >= xive->nr_irqs) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %lx\n", lisn);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n",
+                      lisn);
         return H_P2;
     }
 
     if (!xive_eas_is_valid(&xive->eat[lisn])) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %lx\n", lisn);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n",
+                      lisn);
         return H_P2;
     }

@@ -701,13 +703,15 @@ static target_ulong h_int_set_source_config(PowerPCCPU *cpu,
     }
 
     if (lisn >= xive->nr_irqs) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %lx\n", lisn);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n",
+                      lisn);
         return H_P2;
     }
 
     eas = xive->eat[lisn];
     if (!xive_eas_is_valid(&eas)) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %lx\n", lisn);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n",
+                      lisn);
         return H_P2;
     }

@@ -724,8 +728,8 @@ static target_ulong h_int_set_source_config(PowerPCCPU *cpu,
     }
 
     if (spapr_xive_priority_is_reserved(priority)) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority %ld is reserved\n",
-                      priority);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld
+                      " is reserved\n", priority);
         return H_P4;
     }

@@ -793,13 +797,15 @@ static target_ulong h_int_get_source_config(PowerPCCPU *cpu,
     }
 
     if (lisn >= xive->nr_irqs) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %lx\n", lisn);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n",
+                      lisn);
         return H_P2;
     }
 
     eas = xive->eat[lisn];
     if (!xive_eas_is_valid(&eas)) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %lx\n", lisn);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n",
+                      lisn);
         return H_P2;
     }

@@ -870,8 +876,8 @@ static target_ulong h_int_get_queue_info(PowerPCCPU *cpu,
      */
 
     if (spapr_xive_priority_is_reserved(priority)) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority %ld is reserved\n",
-                      priority);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld
+                      " is reserved\n", priority);
         return H_P3;
     }

@@ -956,8 +962,8 @@ static target_ulong h_int_set_queue_config(PowerPCCPU *cpu,
      */
 
     if (spapr_xive_priority_is_reserved(priority)) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority %ld is reserved\n",
-                      priority);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld
+                      " is reserved\n", priority);
         return H_P3;
     }

@@ -1102,8 +1108,8 @@ static target_ulong h_int_get_queue_config(PowerPCCPU *cpu,
      */
 
     if (spapr_xive_priority_is_reserved(priority)) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority %ld is reserved\n",
-                      priority);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld
+                      " is reserved\n", priority);
         return H_P3;
     }

@@ -1268,13 +1274,15 @@ static target_ulong h_int_esb(PowerPCCPU *cpu,
     }
 
     if (lisn >= xive->nr_irqs) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %lx\n", lisn);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n",
+                      lisn);
         return H_P2;
     }
 
     eas = xive->eat[lisn];
     if (!xive_eas_is_valid(&eas)) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %lx\n", lisn);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n",
+                      lisn);
         return H_P2;
     }

@@ -1330,13 +1338,15 @@ static target_ulong h_int_sync(PowerPCCPU *cpu,
     }
 
     if (lisn >= xive->nr_irqs) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %lx\n", lisn);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n",
+                      lisn);
         return H_P2;
     }
 
     eas = xive->eat[lisn];
     if (!xive_eas_is_valid(&eas)) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %lx\n", lisn);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n",
+                      lisn);
         return H_P2;
     }

Signature · 1 line

2.17.2

David Gibson

Applied

2018-12-18 03:47 UTC #8 lore raw

Re: [Qemu-devel] [PATCH v9 3/7] spapr/xive: fix compilation breakage on windows

Quoted 1 line · Cédric Le Goater

Signed-off-by Cédric Le Goater <[email protected]>

Applied, and folded into "spapr: add hcalls support for the XIVE exploitation interrupt mode".

Quoted 141 lines

---
 hw/intc/spapr_xive.c | 46 +++++++++++++++++++++++++++-----------------
 1 file changed, 28 insertions(+), 18 deletions(-)

hw/intc/spapr_xive.c +28 ~~-18~~

index aaa5865c4080..3ceabe668b16 100644
@@ -589,12 +589,14 @@ static target_ulong h_int_get_source_info(PowerPCCPU *cpu,
     }
 
     if (lisn >= xive->nr_irqs) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %lx\n", lisn);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n",
+                      lisn);
         return H_P2;
     }
 
     if (!xive_eas_is_valid(&xive->eat[lisn])) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %lx\n", lisn);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n",
+                      lisn);
         return H_P2;
     }

@@ -701,13 +703,15 @@ static target_ulong h_int_set_source_config(PowerPCCPU *cpu,
     }
 
     if (lisn >= xive->nr_irqs) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %lx\n", lisn);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n",
+                      lisn);
         return H_P2;
     }
 
     eas = xive->eat[lisn];
     if (!xive_eas_is_valid(&eas)) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %lx\n", lisn);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n",
+                      lisn);
         return H_P2;
     }

@@ -724,8 +728,8 @@ static target_ulong h_int_set_source_config(PowerPCCPU *cpu,
     }
 
     if (spapr_xive_priority_is_reserved(priority)) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority %ld is reserved\n",
-                      priority);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld
+                      " is reserved\n", priority);
         return H_P4;
     }

@@ -793,13 +797,15 @@ static target_ulong h_int_get_source_config(PowerPCCPU *cpu,
     }
 
     if (lisn >= xive->nr_irqs) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %lx\n", lisn);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n",
+                      lisn);
         return H_P2;
     }
 
     eas = xive->eat[lisn];
     if (!xive_eas_is_valid(&eas)) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %lx\n", lisn);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n",
+                      lisn);
         return H_P2;
     }

@@ -870,8 +876,8 @@ static target_ulong h_int_get_queue_info(PowerPCCPU *cpu,
      */
 
     if (spapr_xive_priority_is_reserved(priority)) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority %ld is reserved\n",
-                      priority);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld
+                      " is reserved\n", priority);
         return H_P3;
     }

@@ -956,8 +962,8 @@ static target_ulong h_int_set_queue_config(PowerPCCPU *cpu,
      */
 
     if (spapr_xive_priority_is_reserved(priority)) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority %ld is reserved\n",
-                      priority);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld
+                      " is reserved\n", priority);
         return H_P3;
     }

@@ -1102,8 +1108,8 @@ static target_ulong h_int_get_queue_config(PowerPCCPU *cpu,
      */
 
     if (spapr_xive_priority_is_reserved(priority)) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority %ld is reserved\n",
-                      priority);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld
+                      " is reserved\n", priority);
         return H_P3;
     }

@@ -1268,13 +1274,15 @@ static target_ulong h_int_esb(PowerPCCPU *cpu,
     }
 
     if (lisn >= xive->nr_irqs) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %lx\n", lisn);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n",
+                      lisn);
         return H_P2;
     }
 
     eas = xive->eat[lisn];
     if (!xive_eas_is_valid(&eas)) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %lx\n", lisn);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n",
+                      lisn);
         return H_P2;
     }

@@ -1330,13 +1338,15 @@ static target_ulong h_int_sync(PowerPCCPU *cpu,
     }
 
     if (lisn >= xive->nr_irqs) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %lx\n", lisn);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n",
+                      lisn);
         return H_P2;
     }
 
     eas = xive->eat[lisn];
     if (!xive_eas_is_valid(&eas)) {
-        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %lx\n", lisn);
+        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n",
+                      lisn);
         return H_P2;
     }

Signature · 4 lines

David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Cédric Le Goater

author

2018-12-17 22:35 UTC #9 lore raw

PATCH v9 4/7 spapr: add an extra OV5 field to the sPAPR IRQ backend

In reply to Cédric Le Goater

The interrupt modes supported by the hypervisor are advertised to the guest with new bits definitions of the option vector 5 of property "ibm,arch-vec-5-platform-support. The byte 23 bits 0-1 of the OV5 are defined as follow :

  0b00   PAPR 2.7 and earlier (Legacy systems)
  0b01   XIVE Exploitation mode only
  0b10   Either available

If the client/guest selects the XIVE interrupt mode, it informs the hypervisor by returning the value 0b01 in byte 23 bits 0-1. A 0b00 value indicates the use of the XICS interrupt mode (Legacy systems).

The sPAPR IRQ backend is extended with these definitions and the values are directly used to populate the "ibm,arch-vec-5-platform-support" property. The interrupt mode is advertised under TCG and under KVM. Although a KVM XIVE device is not yet available, the machine can still operate with kernel_irqchip=off. However, we apply a restriction on the CPU which is required to be a POWER9 when a XIVE interrupt controller is in use.

Signed-off-by Cédric Le Goater <[email protected]>

---

Changes since v8 :

- reworked XIVE capability in ibm,arch-vec-5-platform-support

 include/hw/ppc/spapr.h     |  6 ++++++
 include/hw/ppc/spapr_irq.h |  1 +
 hw/ppc/spapr.c             | 33 ++++++++++++++++++++++++++-------
 hw/ppc/spapr_irq.c         |  3 +++
 4 files changed, 36 insertions(+), 7 deletions(-)

include/hw/ppc/spapr.h +6 -0

index b1a2515107da..c3a04d5fc13d 100644
@@ -829,5 +829,11 @@ int spapr_caps_post_migration(sPAPRMachineState *spapr);
 
 void spapr_check_pagesize(sPAPRMachineState *spapr, hwaddr pagesize,
                           Error **errp);
+/*
+ * XIVE definitions
+ */
+#define SPAPR_OV5_XIVE_LEGACY   0x0
+#define SPAPR_OV5_XIVE_EXPLOIT  0x40
+#define SPAPR_OV5_XIVE_BOTH     0x80 /* Only to advertise on the platform */
 
 #endif /* HW_SPAPR_H */

include/hw/ppc/spapr_irq.h +1 -0

index 63061a009b4c..b34d5a00381b 100644
@@ -33,6 +33,7 @@ void spapr_irq_msi_reset(sPAPRMachineState *spapr);
 typedef struct sPAPRIrq {
     uint32_t    nr_irqs;
     uint32_t    nr_msis;
+    uint8_t     ov5;
 
     void (*init)(sPAPRMachineState *spapr, Error **errp);
     int (*claim)(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp);

hw/ppc/spapr.c +26 -7

index 7a0ab2da5488..51f254866006 100644
@@ -1095,15 +1095,19 @@ static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt)
     spapr_dt_rtas_tokens(fdt, rtas);
 }
 
-/* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features
- * that the guest may request and thus the valid values for bytes 24..26 of
- * option vector 5: */
-static void spapr_dt_ov5_platform_support(void *fdt, int chosen)
+/*
+ * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU
+ * and the XIVE features that the guest may request and thus the valid
+ * values for bytes 23..26 of option vector 5:
+ */
+static void spapr_dt_ov5_platform_support(sPAPRMachineState *spapr, void *fdt,
+                                          int chosen)
 {
     PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
+    sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
 
     char val[2 * 4] = {
-        23, 0x00, /* Xive mode, filled in below. */
+        23, smc->irq->ov5, /* Xive mode. */
         24, 0x00, /* Hash/Radix, filled in below. */
         25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
         26, 0x40, /* Radix options: GTSE == yes. */

@@ -1111,7 +1115,11 @@ static void spapr_dt_ov5_platform_support(void *fdt, int chosen)
 
     if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
                           first_ppc_cpu->compat_pvr)) {
-        /* If we're in a pre POWER9 compat mode then the guest should do hash */
+        /*
+         * If we're in a pre POWER9 compat mode then the guest should
+         * do hash and use the legacy interrupt mode
+         */
+        val[1] = 0x00; /* XICS */
         val[3] = 0x00; /* Hash */
     } else if (kvm_enabled()) {
         if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {

@@ -1189,7 +1197,7 @@ static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt)
         _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path));
     }
 
-    spapr_dt_ov5_platform_support(fdt, chosen);
+    spapr_dt_ov5_platform_support(spapr, fdt, chosen);
 
     g_free(stdout_path);
     g_free(bootlist);

@@ -2659,6 +2667,17 @@ static void spapr_machine_init(MachineState *machine)
     /* advertise support for ibm,dyamic-memory-v2 */
     spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2);
 
+    /* advertise XIVE on POWER9 machines */
+    if (smc->irq->ov5 & SPAPR_OV5_XIVE_EXPLOIT) {
+        if (ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00,
+                                  0, spapr->max_compat_pvr)) {
+            spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT);
+        } else {
+            error_report("XIVE-only machines require a POWER9 CPU");
+            exit(1);
+        }
+    }
+
     /* init CPUs */
     spapr_init_cpus(spapr);

hw/ppc/spapr_irq.c +3 -0

index f835ea939cbf..79f06308995b 100644
@@ -216,6 +216,7 @@ static int spapr_irq_post_load_xics(sPAPRMachineState *spapr, int version_id)
 sPAPRIrq spapr_irq_xics = {
     .nr_irqs     = SPAPR_IRQ_XICS_NR_IRQS,
     .nr_msis     = SPAPR_IRQ_XICS_NR_MSIS,
+    .ov5         = SPAPR_OV5_XIVE_LEGACY,
 
     .init        = spapr_irq_init_xics,
     .claim       = spapr_irq_claim_xics,

@@ -342,6 +343,7 @@ static void spapr_irq_reset_xive(sPAPRMachineState *spapr, Error **errp)
 sPAPRIrq spapr_irq_xive = {
     .nr_irqs     = SPAPR_IRQ_XIVE_NR_IRQS,
     .nr_msis     = SPAPR_IRQ_XIVE_NR_MSIS,
+    .ov5         = SPAPR_OV5_XIVE_EXPLOIT,
 
     .init        = spapr_irq_init_xive,
     .claim       = spapr_irq_claim_xive,

@@ -466,6 +468,7 @@ int spapr_irq_find(sPAPRMachineState *spapr, int num, bool align, Error **errp)
 sPAPRIrq spapr_irq_xics_legacy = {
     .nr_irqs     = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
     .nr_msis     = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
+    .ov5         = SPAPR_OV5_XIVE_LEGACY,
 
     .init        = spapr_irq_init_xics,
     .claim       = spapr_irq_claim_xics,

Signature · 1 line

2.17.2

Cédric Le Goater

author

2018-12-17 22:35 UTC #10 lore raw

PATCH v9 5/7 spapr: introduce an 'ic-mode' machine option

In reply to Cédric Le Goater

This option is used to select the interrupt controller mode (XICS or XIVE) with which the machine will operate. XICS being the default mode for now.

When running a machine with the XIVE interrupt mode backend, the guest OS is required to have support for the XIVE exploitation mode. In the case of legacy OS, the mode selected by CAS should be XICS and the OS should fail to boot. However, QEMU could possibly detect it, terminate the boot process and reset to stop in the SLOF firmware. This is not yet handled.

Signed-off-by Cédric Le Goater <[email protected]>

Reviewed-by David Gibson <[email protected]>

---
 include/hw/ppc/spapr.h  |  1 +
 hw/ppc/spapr.c          | 50 +++++++++++++++++++++++++++++++++++------
 hw/ppc/spapr_cpu_core.c |  3 +--
 hw/ppc/spapr_irq.c      | 34 +++++++++-------------------
 4 files changed, 55 insertions(+), 33 deletions(-)

include/hw/ppc/spapr.h +1 -0

index c3a04d5fc13d..36033b89d31a 100644
@@ -181,6 +181,7 @@ struct sPAPRMachineState {
     int32_t irq_map_nr;
     unsigned long *irq_map;
     sPAPRXive  *xive;
+    sPAPRIrq *irq;
 
     bool cmd_line_caps[SPAPR_CAP_NUM];
     sPAPRCapabilities def, eff, mig;

hw/ppc/spapr.c +43 -7

98 lines not on this page · raw message

hw/ppc/spapr_cpu_core.c +1 -2

index 1811cd48db90..82666436e9b4 100644
@@ -214,7 +214,6 @@ static void spapr_cpu_core_unrealize(DeviceState *dev, Error **errp)
 static void spapr_realize_vcpu(PowerPCCPU *cpu, sPAPRMachineState *spapr,
                                sPAPRCPUCore *sc, Error **errp)
 {
-    sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
     CPUPPCState *env = &cpu->env;
     CPUState *cs = CPU(cpu);
     Error *local_err = NULL;

@@ -233,7 +232,7 @@ static void spapr_realize_vcpu(PowerPCCPU *cpu, sPAPRMachineState *spapr,
     qemu_register_reset(spapr_cpu_reset, cpu);
     spapr_cpu_reset(cpu);
 
-    cpu->intc = smc->irq->cpu_intc_create(spapr, OBJECT(cpu), &local_err);
+    cpu->intc = spapr->irq->cpu_intc_create(spapr, OBJECT(cpu), &local_err);
     if (local_err) {
         goto error_unregister;
     }

hw/ppc/spapr_irq.c +10 ~~-24~~

index 79f06308995b..0999a2b2d69c 100644
@@ -94,8 +94,7 @@ error:
 static void spapr_irq_init_xics(sPAPRMachineState *spapr, Error **errp)
 {
     MachineState *machine = MACHINE(spapr);
-    sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
-    int nr_irqs = smc->irq->nr_irqs;
+    int nr_irqs = spapr->irq->nr_irqs;
     Error *local_err = NULL;
 
     if (kvm_enabled()) {

@@ -234,7 +233,6 @@ sPAPRIrq spapr_irq_xics = {
 static void spapr_irq_init_xive(sPAPRMachineState *spapr, Error **errp)
 {
     MachineState *machine = MACHINE(spapr);
-    sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
     uint32_t nr_servers = spapr_max_server_number(spapr);
     DeviceState *dev;
     int i;

@@ -248,7 +246,7 @@ static void spapr_irq_init_xive(sPAPRMachineState *spapr, Error **errp)
     }
 
     dev = qdev_create(NULL, TYPE_SPAPR_XIVE);
-    qdev_prop_set_uint32(dev, "nr-irqs", smc->irq->nr_irqs);
+    qdev_prop_set_uint32(dev, "nr-irqs", spapr->irq->nr_irqs);
     /*
      * 8 XIVE END structures per CPU. One for each available priority
      */

@@ -361,50 +359,38 @@ sPAPRIrq spapr_irq_xive = {
  */
 void spapr_irq_init(sPAPRMachineState *spapr, Error **errp)
 {
-    sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
-
     /* Initialize the MSI IRQ allocator. */
     if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
-        spapr_irq_msi_init(spapr, smc->irq->nr_msis);
+        spapr_irq_msi_init(spapr, spapr->irq->nr_msis);
     }
 
-    smc->irq->init(spapr, errp);
+    spapr->irq->init(spapr, errp);
 }
 
 int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp)
 {
-    sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
-
-    return smc->irq->claim(spapr, irq, lsi, errp);
+    return spapr->irq->claim(spapr, irq, lsi, errp);
 }
 
 void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num)
 {
-    sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
-
-    smc->irq->free(spapr, irq, num);
+    spapr->irq->free(spapr, irq, num);
 }
 
 qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq)
 {
-    sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
-
-    return smc->irq->qirq(spapr, irq);
+    return spapr->irq->qirq(spapr, irq);
 }
 
 int spapr_irq_post_load(sPAPRMachineState *spapr, int version_id)
 {
-    sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
-
-    return smc->irq->post_load(spapr, version_id);
+    return spapr->irq->post_load(spapr, version_id);
 }
 
 void spapr_irq_reset(sPAPRMachineState *spapr, Error **errp)
 {
-    sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
-
-    if (smc->irq->reset) {
-        smc->irq->reset(spapr, errp);
+    if (spapr->irq->reset) {
+        spapr->irq->reset(spapr, errp);
     }
 }

Signature · 1 line

2.17.2

Cédric Le Goater

author

2018-12-17 22:35 UTC #11 lore raw

PATCH v9 6/7 spapr: change default CPU type to POWER9

In reply to Cédric Le Goater

Signed-off-by Cédric Le Goater <[email protected]>

---
 hw/ppc/spapr.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

hw/ppc/spapr.c +2 -1

index aefa0f4ea430..8ea680fcde1e 100644
@@ -3967,7 +3967,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
 
     smc->dr_lmb_enabled = true;
     smc->update_dt_enabled = true;
-    mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
+    mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
     mc->has_hotpluggable_cpus = true;
     smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
     fwc->get_dev_path = spapr_get_fw_dev_path;

@@ -4066,6 +4066,7 @@ static void spapr_machine_3_1_class_options(MachineClass *mc)
 
     spapr_machine_4_0_class_options(mc);
     SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_3_1);
+    mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
     smc->update_dt_enabled = false;
 }

Signature · 1 line

2.17.2

David Gibson

2018-12-18 04:16 UTC #12 lore raw

Re: [Qemu-devel] [PATCH v9 6/7] spapr: change default CPU type to POWER9

Quoted 1 line · Cédric Le Goater

Signed-off-by Cédric Le Goater <[email protected]>

Fixed up for my removal of the update_dt patch, and applied.

Quoted 25 lines

---
 hw/ppc/spapr.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

hw/ppc/spapr.c +2 -1

index aefa0f4ea430..8ea680fcde1e 100644
@@ -3967,7 +3967,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
 
     smc->dr_lmb_enabled = true;
     smc->update_dt_enabled = true;
-    mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
+    mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
     mc->has_hotpluggable_cpus = true;
     smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
     fwc->get_dev_path = spapr_get_fw_dev_path;

@@ -4066,6 +4066,7 @@ static void spapr_machine_3_1_class_options(MachineClass *mc)
 
     spapr_machine_4_0_class_options(mc);
     SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_3_1);
+    mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
     smc->update_dt_enabled = false;
 }

Signature · 4 lines

David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Cédric Le Goater

author

2018-12-17 22:35 UTC #13 lore raw

PATCH v9 7/7 MAINTAINERS: PPC: add a XIVE section

In reply to Cédric Le Goater

Signed-off-by Cédric Le Goater <[email protected]>

---
 MAINTAINERS | 8 ++++++++
 1 file changed, 8 insertions(+)

MAINTAINERS +8 -0

index 83c127f0d6e4..6a648d29a9bd 100644
@@ -1009,6 +1009,14 @@ F: tests/libqos/*spapr*
 F: tests/rtas*
 F: tests/libqos/rtas*
 
+XIVE
+M: David Gibson <[email protected]>
+M: Cédric Le Goater <[email protected]>
+L: [email protected]
+S: Supported
+F: hw/*/*xive*
+F: include/hw/*/*xive*
+
 virtex_ml507
 M: Edgar E. Iglesias <[email protected]>
 L: [email protected]

Signature · 1 line

2.17.2

David Gibson

2018-12-18 04:16 UTC #14 lore raw

In reply to Cédric Le Goater

Quoted 8 lines · Cédric Le Goater

Hello,
Here is the version 9 of the QEMU models adding support for the XIVE interrupt controller to the sPAPR machine, under TCG only.
The 'dual' machine, supporting both interrupt modes, is nearly complete, only remains the question on the qirq array, which will be addressed in early 2019 with the support for KVM.

Ok, I've applied most of this lot. I think that leaves my next pull request just waiting on the GETFIELD stuff.

Signature · 4 lines

David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson