Add initial RISC-V architecture support
Subsystems (5)
v3 cover Add initial RISC-V architecture support
This patchseries adds initial RISC-V architecture support for barebox.
See Documentation/boards/riscv.rst for instructions.
You can obtain this patchseries from github:
$ git clone -b 20181218.riscv https://github.com/frantony/barebox
Changes since PATCH v2 (20180628)
(http://lists.infradead.org/pipermail/barebox/2018-June/033879.html)
* eliminate arch/riscv/boards/erizo-generic;
* use obj-dtb-y to include the dtb;
* simplify barebox.lds.S (see http://lists.infradead.org/pipermail/barebox/2018-June/033901.html);
* add SPDX-License-Identifier;
* rebase over latest master.
Changes since PATCH v1 (20170415)
(http://lists.infradead.org/pipermail/barebox/2018-April/032647.html)
* drop skeleton.dtsi;
* drop SPI GPIO bindings for erizo_generic;
* improve erizo-nmon-image;
* generic linker script is dropped;
* use generic GCC library routines from lib.
Changes since RFC v4 (20170927)
(http://lists.infradead.org/pipermail/barebox/2017-September/031226.html)
* drop 64-bit support;
* sync with RISC-V linux;
* RISC-V in barebox now is little endian only;
* fix according to notes by Oleksij Rempel.
Changes since RFC v3 (20161212)
(http://lists.infradead.org/pipermail/barebox/2016-December/028716.html)
* drop SiFive support, add support for custom Erizo SoC;
* barebox runs on real hardware (e.g. DE0-Nano FPGA board, see https://github.com/miet-riscv-workgroup/rv32-simple-soc for
details);
* introduce NMON for RISC-V;
* add relocator to start.S.
Changes since RFC v2 (20161113)
(http://lists.infradead.org/pipermail/barebox/2016-November/028533.html):
* add RV32 support.
Changes since RFC v1 (20161013)
(http://lists.infradead.org/pipermail/barebox/2016-October/028309.html):
* drop spike pk support;
* add qemu-sifive board support;
* add Documentation/boards/riscv.rst;
* fix guard macro names.
Antony Pavlov (10):
Add initial RISC-V architecture support
RISC-V: add Erizo SoC support
RISC-V: add low-level debug macros for ns16550
RISC-V: add nmon nano-monitor
RISC-V: erizo: add DEBUG_LL support
RISC-V: erizo: enable nmon
RISC-V: erizo: add nmon image creation
RISC-V: add erizo_generic_defconfig
scripts: add nmon-loader
Documentation: add RISC-V docs
Documentation/boards/riscv.rst | 91 +++++++ arch/riscv/Kconfig | 91 +++++++ arch/riscv/Makefile | 67 +++++ arch/riscv/boot/Makefile | 3 + arch/riscv/boot/dtb.c | 37 +++ arch/riscv/boot/main_entry.c | 35 +++ arch/riscv/boot/start.S | 68 +++++ arch/riscv/configs/erizo_generic_defconfig | 51 ++++ arch/riscv/dts/.gitignore | 1 + arch/riscv/dts/Makefile | 13 + arch/riscv/dts/erizo-generic.dts | 14 ++ arch/riscv/dts/erizo.dtsi | 46 ++++ arch/riscv/include/asm/barebox.h | 1 + arch/riscv/include/asm/bitops.h | 32 +++ arch/riscv/include/asm/bitsperlong.h | 10 + arch/riscv/include/asm/byteorder.h | 6 + arch/riscv/include/asm/common.h | 6 + arch/riscv/include/asm/debug_ll_ns16550.h | 182 ++++++++++++++ arch/riscv/include/asm/elf.h | 11 + arch/riscv/include/asm/io.h | 8 + arch/riscv/include/asm/mmu.h | 6 + arch/riscv/include/asm/posix_types.h | 1 + arch/riscv/include/asm/riscv_nmon.h | 234 ++++++++++++++++++ arch/riscv/include/asm/sections.h | 1 + arch/riscv/include/asm/string.h | 1 + arch/riscv/include/asm/swab.h | 6 + arch/riscv/include/asm/types.h | 60 +++++ arch/riscv/include/asm/unaligned.h | 19 ++ arch/riscv/lib/.gitignore | 1 + arch/riscv/lib/Makefile | 3 + arch/riscv/lib/asm-offsets.c | 12 + arch/riscv/lib/barebox.lds.S | 79 ++++++ arch/riscv/lib/riscv_timer.c | 63 +++++ arch/riscv/mach-erizo/Kconfig | 11 + arch/riscv/mach-erizo/Makefile | 3 + arch/riscv/mach-erizo/include/mach/debug_ll.h | 33 +++ drivers/of/Kconfig | 2 +- scripts/erizo-nmon-image | 10 + scripts/nmon-loader | 31 +++ 39 files changed, 1348 insertions(+), 1 deletion(-) create mode 100644 Documentation/boards/riscv.rst create mode 100644 arch/riscv/Kconfig create mode 100644 arch/riscv/Makefile create mode 100644 arch/riscv/boot/Makefile create mode 100644 arch/riscv/boot/dtb.c create mode 100644 arch/riscv/boot/main_entry.c create mode 100644 arch/riscv/boot/start.S create mode 100644 arch/riscv/configs/erizo_generic_defconfig create mode 100644 arch/riscv/dts/.gitignore create mode 100644 arch/riscv/dts/Makefile create mode 100644 arch/riscv/dts/erizo-generic.dts create mode 100644 arch/riscv/dts/erizo.dtsi create mode 100644 arch/riscv/include/asm/barebox.h create mode 100644 arch/riscv/include/asm/bitops.h create mode 100644 arch/riscv/include/asm/bitsperlong.h create mode 100644 arch/riscv/include/asm/byteorder.h create mode 100644 arch/riscv/include/asm/common.h create mode 100644 arch/riscv/include/asm/debug_ll_ns16550.h create mode 100644 arch/riscv/include/asm/elf.h create mode 100644 arch/riscv/include/asm/io.h create mode 100644 arch/riscv/include/asm/mmu.h create mode 100644 arch/riscv/include/asm/posix_types.h create mode 100644 arch/riscv/include/asm/riscv_nmon.h create mode 100644 arch/riscv/include/asm/sections.h create mode 100644 arch/riscv/include/asm/string.h create mode 100644 arch/riscv/include/asm/swab.h create mode 100644 arch/riscv/include/asm/types.h create mode 100644 arch/riscv/include/asm/unaligned.h create mode 100644 arch/riscv/lib/.gitignore create mode 100644 arch/riscv/lib/Makefile create mode 100644 arch/riscv/lib/asm-offsets.c create mode 100644 arch/riscv/lib/barebox.lds.S create mode 100644 arch/riscv/lib/riscv_timer.c create mode 100644 arch/riscv/mach-erizo/Kconfig create mode 100644 arch/riscv/mach-erizo/Makefile create mode 100644 arch/riscv/mach-erizo/include/mach/debug_ll.h create mode 100755 scripts/erizo-nmon-image create mode 100755 scripts/nmon-loader
Signature · 7 lines
2.20.0 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH v3 1/10 Add initial RISC-V architecture support
Signed-off-by Antony Pavlov <[email protected]>
--- arch/riscv/Kconfig | 54 +++++++++++++++++++ arch/riscv/Makefile | 54 +++++++++++++++++++ arch/riscv/boot/Makefile | 3 ++ arch/riscv/boot/dtb.c | 37 +++++++++++++ arch/riscv/boot/main_entry.c | 35 ++++++++++++ arch/riscv/boot/start.S | 60 +++++++++++++++++++++ arch/riscv/dts/.gitignore | 1 + arch/riscv/dts/Makefile | 11 ++++ arch/riscv/include/asm/barebox.h | 1 + arch/riscv/include/asm/bitops.h | 32 +++++++++++ arch/riscv/include/asm/bitsperlong.h | 10 ++++ arch/riscv/include/asm/byteorder.h | 6 +++ arch/riscv/include/asm/common.h | 6 +++ arch/riscv/include/asm/elf.h | 11 ++++ arch/riscv/include/asm/io.h | 8 +++ arch/riscv/include/asm/mmu.h | 6 +++ arch/riscv/include/asm/posix_types.h | 1 + arch/riscv/include/asm/sections.h | 1 + arch/riscv/include/asm/string.h | 1 + arch/riscv/include/asm/swab.h | 6 +++ arch/riscv/include/asm/types.h | 60 +++++++++++++++++++++ arch/riscv/include/asm/unaligned.h | 19 +++++++ arch/riscv/lib/.gitignore | 1 + arch/riscv/lib/Makefile | 3 ++ arch/riscv/lib/asm-offsets.c | 12 +++++ arch/riscv/lib/barebox.lds.S | 79 ++++++++++++++++++++++++++++ arch/riscv/lib/riscv_timer.c | 63 ++++++++++++++++++++++ drivers/of/Kconfig | 2 +- 28 files changed, 582 insertions(+), 1 deletion(-)
arch/riscv/Kconfig new file +54 -0
@@ -0,0 +1,54 @@ +config RISCV + def_bool y + select GENERIC_FIND_NEXT_BIT + select HAVE_CONFIGURABLE_MEMORY_LAYOUT + select HAVE_CONFIGURABLE_TEXT_BASE + select GPIOLIB + select OFTREE + select COMMON_CLK + select COMMON_CLK_OF_PROVIDER + select CLKDEV_LOOKUP + +config ARCH_TEXT_BASE + hex + default 0x0 + +menu "Machine selection" + +choice + prompt "Base ISA" + default ARCH_RV32I + +config ARCH_RV32I + bool "RV32I" + select CPU_SUPPORTS_32BIT_KERNEL + select GENERIC_LIB_ASHLDI3 + select GENERIC_LIB_ASHRDI3 + select GENERIC_LIB_LSHRDI3 + +endchoice + +config CPU_SUPPORTS_32BIT_KERNEL + bool + +choice + prompt "barebox code model" + default 32BIT + +config 32BIT + bool "32-bit barebox" + depends on CPU_SUPPORTS_32BIT_KERNEL + help + Select this option to build a 32-bit barebox. + +endchoice + +config BUILTIN_DTB + bool "link a DTB into the barebox image" + depends on OFTREE + +config BUILTIN_DTB_NAME + string "DTB to build into the barebox image" + depends on BUILTIN_DTB + +endmenu
arch/riscv/Makefile new file +54 -0
54 lines not on this page · raw message
arch/riscv/boot/Makefile new file +3 -0
@@ -0,0 +1,3 @@ +obj-y += start.o +obj-y += main_entry.o +obj-$(CONFIG_OFDEVICE) += dtb.o
arch/riscv/boot/dtb.c new file +37 -0
@@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* +* Copyright (C) 2016, 2018 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ +#include <common.h> +#include <init.h> +#include <of.h> + +extern char __dtb_start[]; + +static int of_riscv_init (void ) +{ +struct device_node *root; + + root =of_get_root_node (); +if (root) +return 0 ; + + root =of_unflatten_dtb (__dtb_start); +if (!IS_ERR (root)) { +pr_debug ("using internal DTB\n" ); +of_set_root_node (root); +if (IS_ENABLED (CONFIG_OFDEVICE )) +of_probe (); + } + +return 0 ; +} +core_initcall (of_riscv_init);
arch/riscv/boot/main_entry.c new file +35 -0
@@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* +* Copyright (C) 2016 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +#include <common.h> +#include <memory.h> +#include <asm-generic/memory_layout.h> +#include <asm/sections.h> + +void main_entry (void ); + +/** +* Called plainly from assembler code +* +* @note The C environment isn't initialized yet +*/ +void main_entry (void ) +{ +/* clear the BSS first */ +memset (__bss_start,0x00 , __bss_stop - __bss_start); + +mem_malloc_init ((void *)MALLOC_BASE , + (void *)(MALLOC_BASE +MALLOC_SIZE -1 )); + +start_barebox (); +}
arch/riscv/boot/start.S new file +60 -0
60 lines not on this page · raw message
arch/riscv/dts/.gitignore new file +1 -0
@@ -0,0 +1 @@ +*dtb*
arch/riscv/dts/Makefile new file +11 -0
@@ -0,0 +1,11 @@ +BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME)) +ifneq ($(BUILTIN_DTB),) +obj-dtb-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o +endif + +# just to build a built-in.o. Otherwise compilation fails when no devicetree is +# created. +obj- += dummy.o + +always := $(dtb-y) +clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts
arch/riscv/include/asm/barebox.h new file +1 -0
@@ -0,0 +1 @@ +/* dummy */
arch/riscv/include/asm/bitops.h new file +32 -0
@@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* +* This file is part of barebox. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +#ifndef _ASM_BITOPS_H_ +#define _ASM_BITOPS_H_ + +#include <asm-generic/bitops/__ffs.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/ffs.h> +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/ffz.h> +#include <asm-generic/bitops/hweight.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/find.h> +#include <asm-generic/bitops/ops.h> + +#define set_bit (x, y) __set_bit(x, y) +#define clear_bit (x, y) __clear_bit(x, y) +#define change_bit (x, y) __change_bit(x, y) +#define test_and_set_bit (x, y) __test_and_set_bit(x, y) +#define test_and_clear_bit (x, y) __test_and_clear_bit(x, y) +#define test_and_change_bit (x, y) __test_and_change_bit(x, y) + +#endif /* _ASM_BITOPS_H_ */
arch/riscv/include/asm/bitsperlong.h new file +10 -0
@@ -0,0 +1,10 @@ +#ifndef __ASM_BITSPERLONG_H +#define __ASM_BITSPERLONG_H + +#ifdef __riscv64 +#define BITS_PER_LONG 64 +#else +#define BITS_PER_LONG 32 +#endif + +#endif /* __ASM_BITSPERLONG_H */
arch/riscv/include/asm/byteorder.h new file +6 -0
@@ -0,0 +1,6 @@ +#ifndef _ASM_RISCV_BYTEORDER_H +#define _ASM_RISCV_BYTEORDER_H + +#include <linux/byteorder/little_endian.h> + +#endif /* _ASM_RISCV_BYTEORDER_H */
arch/riscv/include/asm/common.h new file +6 -0
@@ -0,0 +1,6 @@ +#ifndef ASM_RISCV_COMMON_H +#define ASM_RISCV_COMMON_H + +/* nothing special yet */ + +#endif /* ASM_RISCV_COMMON_H */
arch/riscv/include/asm/elf.h new file +11 -0
@@ -0,0 +1,11 @@ +#ifndef __ASM_RISCV_ELF_H__ +#define __ASM_RISCV_ELF_H__ + +#if __SIZEOF_POINTER__ ==8 +#define ELF_CLASS ELFCLASS64 +#define CONFIG_PHYS_ADDR_T_64BIT +#else +#define ELF_CLASS ELFCLASS32 +#endif + +#endif /* __ASM_RISCV_ELF_H__ */
arch/riscv/include/asm/io.h new file +8 -0
@@ -0,0 +1,8 @@ +#ifndef __ASM_RISCV_IO_H +#define __ASM_RISCV_IO_H + +#define IO_SPACE_LIMIT 0 + +#include <asm-generic/io.h> + +#endif /* __ASM_RISCV_IO_H */
arch/riscv/include/asm/mmu.h new file +6 -0
@@ -0,0 +1,6 @@ +#ifndef __ASM_MMU_H +#define __ASM_MMU_H + +#define MAP_ARCH_DEFAULT MAP_UNCACHED + +#endif /* __ASM_MMU_H */
arch/riscv/include/asm/posix_types.h new file +1 -0
@@ -0,0 +1 @@ +#include <asm-generic/posix_types.h>
arch/riscv/include/asm/sections.h new file +1 -0
@@ -0,0 +1 @@ +#include <asm-generic/sections.h>
arch/riscv/include/asm/string.h new file +1 -0
@@ -0,0 +1 @@ +/* dummy */
arch/riscv/include/asm/swab.h new file +6 -0
@@ -0,0 +1,6 @@ +#ifndef _ASM_SWAB_H +#define _ASM_SWAB_H + +/* nothing. use generic functions */ + +#endif /* _ASM_SWAB_H */
arch/riscv/include/asm/types.h new file +60 -0
60 lines not on this page · raw message
arch/riscv/include/asm/unaligned.h new file +19 -0
@@ -0,0 +1,19 @@ +#ifndef _ASM_RISCV_UNALIGNED_H +#define _ASM_RISCV_UNALIGNED_H + +/* +* FIXME: this file is copy-n-pasted from sandbox's unaligned.h +*/ + +#include <linux/unaligned/access_ok.h> +#include <linux/unaligned/generic.h> + +#if __BYTE_ORDER == __LITTLE_ENDIAN +#define get_unaligned __get_unaligned_le +#define put_unaligned __put_unaligned_le +#else +#define get_unaligned __get_unaligned_be +#define put_unaligned __put_unaligned_be +#endif + +#endif /* _ASM_RISCV_UNALIGNED_H */
arch/riscv/lib/.gitignore new file +1 -0
@@ -0,0 +1 @@ +barebox.lds
arch/riscv/lib/Makefile new file +3 -0
@@ -0,0 +1,3 @@ +extra-y += barebox.lds + +obj-y += riscv_timer.o
arch/riscv/lib/asm-offsets.c new file +12 -0
@@ -0,0 +1,12 @@ +/* +* Generate definitions needed by assembly language modules. +* This code generates raw asm output which is post-processed to extract +* and format the required data. +*/ + +#include <linux/kbuild.h> + +int main (void ) +{ +return 0 ; +}
arch/riscv/lib/barebox.lds.S new file +79 -0
79 lines not on this page · raw message
arch/riscv/lib/riscv_timer.c new file +63 -0
63 lines not on this page · raw message
drivers/of/Kconfig +1 -1
@@ -4,7 +4,7 @@ config OFTREE config OFTREE_MEM_GENERIC depends on OFTREE - depends on PPC || ARM || EFI_BOOTUP || OPENRISC || SANDBOX + depends on PPC || ARM || EFI_BOOTUP || OPENRISC || SANDBOX || RISCV def_bool y config DTC
Signature · 7 lines
2.20.0 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH v3 2/10 RISC-V: add Erizo SoC support
In reply to Antony PavlovErizo is an opensource hardware SoC for FPGA.
Signed-off-by Antony Pavlov <[email protected]>
--- arch/riscv/Kconfig | 11 ++++++++ arch/riscv/Makefile | 2 ++ arch/riscv/dts/Makefile | 2 ++ arch/riscv/dts/erizo-generic.dts | 14 ++++++++++ arch/riscv/dts/erizo.dtsi | 46 ++++++++++++++++++++++++++++++++ arch/riscv/mach-erizo/Kconfig | 11 ++++++++ arch/riscv/mach-erizo/Makefile | 3 +++ 7 files changed, 89 insertions(+)
arch/riscv/Kconfig +11 -0
@@ -15,6 +15,15 @@ config ARCH_TEXT_BASE menu "Machine selection" +choice + prompt "System type" + default MACH_ERIZO + +config MACH_ERIZO + bool "erizo family" + +endchoice + choice prompt "Base ISA" default ARCH_RV32I
@@ -51,4 +60,6 @@ config BUILTIN_DTB_NAME string "DTB to build into the barebox image" depends on BUILTIN_DTB +source arch/riscv/mach-erizo/Kconfig + endmenu
arch/riscv/Makefile +2 -0
@@ -11,6 +11,8 @@ cflags-y += -Wall -Wstrict-prototypes \ LDFLAGS += $(ldflags-y) LDFLAGS_barebox += -nostdlib +machine-$(CONFIG_MACH_ERIZO) := erizo + TEXT_BASE = $(CONFIG_TEXT_BASE) CPPFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE)
arch/riscv/dts/Makefile +2 -0
@@ -3,6 +3,8 @@ ifneq ($(BUILTIN_DTB),) obj-dtb-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o endif +obj-dtb-$(CONFIG_BOARD_ERIZO_GENERIC) += erizo-generic.dtb.o + # just to build a built-in.o. Otherwise compilation fails when no devicetree is # created. obj- += dummy.o
arch/riscv/dts/erizo-generic.dts new file +14 -0
@@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "erizo.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "generic Erizo SoC board"; + compatible = "miet-riscv-workgroup,erizo-generic-board"; + + memory@0 { + device_type = "memory"; + reg = <0x80000000 0x00800000>; + }; +};
arch/riscv/dts/erizo.dtsi new file +46 -0
46 lines not on this page · raw message
arch/riscv/mach-erizo/Kconfig new file +11 -0
@@ -0,0 +1,11 @@ +if MACH_ERIZO + +choice + prompt "Board type" + +config BOARD_ERIZO_GENERIC + bool "erizo generic board" + +endchoice + +endif
arch/riscv/mach-erizo/Makefile new file +3 -0
@@ -0,0 +1,3 @@ +# just to build a built-in.o. Otherwise compilation fails when no o-files is +# created. +obj- += dummy.o
Signature · 7 lines
2.20.0 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH v3 3/10 RISC-V: add low-level debug macros for ns16550
In reply to Antony PavlovThis patch adds macros for ns16550 port initialization and single char output. The macros can be used in MIPS asm pbl code.
Signed-off-by Antony Pavlov <[email protected]>
--- arch/riscv/include/asm/debug_ll_ns16550.h | 182 ++++++++++++++++++++++ 1 file changed, 182 insertions(+)
arch/riscv/include/asm/debug_ll_ns16550.h new file +182 -0
@@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +* Copyright (C) 2016, 2017 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +/** @file +* This file contains declaration for early output support +*/ +#ifndef __INCLUDE_RISCV_ASM_DEBUG_LL_NS16550_H__ +#define __INCLUDE_RISCV_ASM_DEBUG_LL_NS16550_H__ + +#include <linux/kconfig.h> + +#ifdef CONFIG_DEBUG_LL + +#ifndef DEBUG_LL_UART_ADDR +#error DEBUG_LL_UART_ADDR is undefined! +#endif + +#ifndef DEBUG_LL_UART_SHIFT +#error DEBUG_LL_UART_SHIFT is undefined! +#endif + +#ifndef DEBUG_LL_UART_DIVISOR +#error DEBUG_LL_UART_DIVISOR is undefined! +#endif + +#endif /* CONFIG_DEBUG_LL */ + +#define UART_THR (0x0 << DEBUG_LL_UART_SHIFT) +#define UART_RBR (0x0 << DEBUG_LL_UART_SHIFT) +#define UART_DLL (0x0 << DEBUG_LL_UART_SHIFT) +#define UART_DLM (0x1 << DEBUG_LL_UART_SHIFT) +#define UART_LCR (0x3 << DEBUG_LL_UART_SHIFT) +#define UART_LSR (0x5 << DEBUG_LL_UART_SHIFT) + +#define UART_LCR_W 0x07/* Set UART to 8,N,2 & DLAB = 0 */ +#define UART_LCR_DLAB 0x87/* Set UART to 8,N,2 & DLAB = 1 */ + +#define UART_LSR_DR 0x01/* UART received data present */ +#define UART_LSR_THRE 0x20/* Xmit holding register empty */ + +#if defined(DEBUG_LL_UART_IOSIZE32 ) +#define UART_REG_L lw +#define UART_REG_S sw +#elif defined(DEBUG_LL_UART_IOSIZE8 ) +#define UART_REG_L lbu +#define UART_REG_S sb +#else +#error "Please define DEBUG_LL_UART_IOSIZE{8,32}" +#endif + +#ifndef __ASSEMBLY__ +/* +* C macros +*/ + +#include <asm/io.h> + +static inline void PUTC_LL (char ch) +{ +#ifdef CONFIG_DEBUG_LL +while (!(__raw_readl ((u8 *)DEBUG_LL_UART_ADDR +UART_LSR ) &UART_LSR_THRE )) + ; +__raw_writel (ch, (u8 *)DEBUG_LL_UART_ADDR +UART_THR ); +#endif /* CONFIG_DEBUG_LL */ +} + +static inline void debug_ll_ns16550_init (void ) +{ +#ifdef CONFIG_DEBUG_LL +__raw_writel (UART_LCR_DLAB , (u8 *)DEBUG_LL_UART_ADDR +UART_LCR ); +__raw_writel (DEBUG_LL_UART_DIVISOR &0xff , (u8 *)DEBUG_LL_UART_ADDR +UART_DLL ); +__raw_writel ((DEBUG_LL_UART_DIVISOR >>8 ) &0xff , (u8 *)DEBUG_LL_UART_ADDR +UART_DLM ); +__raw_writel (UART_LCR_W , (u8 *)DEBUG_LL_UART_ADDR +UART_LCR ); +#endif /* CONFIG_DEBUG_LL */ +} +#else /* __ASSEMBLY__ */ +/* +* Macros for use in assembly language code +*/ + +.macro debug_ll_ns16550_init +#ifdef CONFIG_DEBUG_LL + li t0, DEBUG_LL_UART_ADDR + + li t1, UART_LCR_DLAB /* DLAB on */ + UART_REG_S t1, UART_LCR(t0) /* Write it out */ + + li t1, DEBUG_LL_UART_DIVISOR + UART_REG_S t1, UART_DLL(t0) /* write low order byte */ + srl t1, t1, 8 + UART_REG_S t1, UART_DLM(t0) /* write high order byte */ + + li t1, UART_LCR_W /* DLAB off */ + UART_REG_S t1, UART_LCR(t0) /* Write it out */ +#endif /* CONFIG_DEBUG_LL */ +.endm + +/* + * output a character in a0 + */ +.macro debug_ll_outc_a0 +#ifdef CONFIG_DEBUG_LL + + li t0, DEBUG_LL_UART_ADDR + +201: + UART_REG_L t1, UART_LSR(t0) /* get line status */ + andi t1, t1, UART_LSR_THRE /* check for transmitter empty */ + beqz t1, 201b /* try again */ + + UART_REG_S a0, UART_THR(t0) /* write the character */ + +#endif /* CONFIG_DEBUG_LL */ +.endm + +/* + * output a character + */ +.macro debug_ll_outc chr +#ifdef CONFIG_DEBUG_LL + li a0, \chr + debug_ll_outc_a0 +#endif /* CONFIG_DEBUG_LL */ +.endm + +/* + * output CR + NL + */ +.macro debug_ll_ns16550_outnl +#ifdef CONFIG_DEBUG_LL + debug_ll_outc '\r' + debug_ll_outc '\n' +#endif /* CONFIG_DEBUG_LL */ +.endm + +/* + * check character in input buffer + * return value: + * v0 = 0 no character in input buffer + * v0 != 0 character in input buffer + */ +.macro debug_ll_tstc +#ifdef CONFIG_DEBUG_LL + li t0, DEBUG_LL_UART_ADDR + + /* get line status and check for data present */ + UART_REG_L s0, UART_LSR(t0) + andi s0, s0, UART_LSR_DR + +#endif /* CONFIG_DEBUG_LL */ +.endm + +/* + * get character to v0 + */ +.macro debug_ll_getc +#ifdef CONFIG_DEBUG_LL + +204: + debug_ll_tstc + + /* try again */ + beqz s0, 204b + + /* read a character */ + UART_REG_L s0, UART_RBR(t0) + +#endif /* CONFIG_DEBUG_LL */ +.endm +#endif /* __ASSEMBLY__ */ + +#endif /* __INCLUDE_RISCV_ASM_DEBUG_LL_NS16550_H__ */
Signature · 7 lines
2.20.0 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH v3 03/10] RISC-V: add low-level debug macros for ns16550
Quoted 17 lines · Antony Pavlov
This patch adds macros for ns16550 port initialization and single char output. The macros can be used in MIPS asm pbl code.
Signed-off-by Antony Pavlov <[email protected]>--- arch/riscv/include/asm/debug_ll_ns16550.h | 182 ++++++++++++++++++++++ 1 file changed, 182 insertions(+)arch/riscv/include/asm/debug_ll_ns16550.h new file +2
-0@@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/*
arch/riscv/include/asm/debug_ll_ns16550.h line 12
Quoted 10 lines
arch/riscv/include/asm/debug_ll_ns16550.h new file +10
-0+* Copyright (C) 2016, 2017 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/
Just SPDX-License-Identifier and Copyright should be enough
Quoted 160 lines
arch/riscv/include/asm/debug_ll_ns16550.h new file +159
-0+/** @file +* This file contains declaration for early output support +*/ +#ifndef __INCLUDE_RISCV_ASM_DEBUG_LL_NS16550_H__ +#define __INCLUDE_RISCV_ASM_DEBUG_LL_NS16550_H__ + +#include <linux/kconfig.h> + +#ifdef CONFIG_DEBUG_LL + +#ifndef DEBUG_LL_UART_ADDR +#error DEBUG_LL_UART_ADDR is undefined! +#endif + +#ifndef DEBUG_LL_UART_SHIFT +#error DEBUG_LL_UART_SHIFT is undefined! +#endif + +#ifndef DEBUG_LL_UART_DIVISOR +#error DEBUG_LL_UART_DIVISOR is undefined! +#endif + +#endif /* CONFIG_DEBUG_LL */ + +#define UART_THR (0x0 << DEBUG_LL_UART_SHIFT) +#define UART_RBR (0x0 << DEBUG_LL_UART_SHIFT) +#define UART_DLL (0x0 << DEBUG_LL_UART_SHIFT) +#define UART_DLM (0x1 << DEBUG_LL_UART_SHIFT) +#define UART_LCR (0x3 << DEBUG_LL_UART_SHIFT) +#define UART_LSR (0x5 << DEBUG_LL_UART_SHIFT) + +#define UART_LCR_W 0x07/* Set UART to 8,N,2 & DLAB = 0 */ +#define UART_LCR_DLAB 0x87/* Set UART to 8,N,2 & DLAB = 1 */ + +#define UART_LSR_DR 0x01/* UART received data present */ +#define UART_LSR_THRE 0x20/* Xmit holding register empty */ + +#if defined(DEBUG_LL_UART_IOSIZE32 ) +#define UART_REG_L lw +#define UART_REG_S sw +#elif defined(DEBUG_LL_UART_IOSIZE8 ) +#define UART_REG_L lbu +#define UART_REG_S sb +#else +#error "Please define DEBUG_LL_UART_IOSIZE{8,32}" +#endif + +#ifndef __ASSEMBLY__ +/* +* C macros +*/ + +#include <asm/io.h> + +static inline void PUTC_LL (char ch) +{ +#ifdef CONFIG_DEBUG_LL +while (!(__raw_readl ((u8 *)DEBUG_LL_UART_ADDR +UART_LSR ) &UART_LSR_THRE )) + ; +__raw_writel (ch, (u8 *)DEBUG_LL_UART_ADDR +UART_THR ); +#endif /* CONFIG_DEBUG_LL */ +} + +static inline void debug_ll_ns16550_init (void ) +{ +#ifdef CONFIG_DEBUG_LL +__raw_writel (UART_LCR_DLAB , (u8 *)DEBUG_LL_UART_ADDR +UART_LCR ); +__raw_writel (DEBUG_LL_UART_DIVISOR &0xff , (u8 *)DEBUG_LL_UART_ADDR +UART_DLL ); +__raw_writel ((DEBUG_LL_UART_DIVISOR >>8 ) &0xff , (u8 *)DEBUG_LL_UART_ADDR +UART_DLM ); +__raw_writel (UART_LCR_W , (u8 *)DEBUG_LL_UART_ADDR +UART_LCR ); +#endif /* CONFIG_DEBUG_LL */ +} +#else /* __ASSEMBLY__ */ +/* +* Macros for use in assembly language code +*/ + +.macro debug_ll_ns16550_init +#ifdef CONFIG_DEBUG_LL +li t0,DEBUG_LL_UART_ADDR + + li t1, UART_LCR_DLAB /* DLAB on */ + UART_REG_S t1, UART_LCR(t0) /* Write it out */ + + li t1, DEBUG_LL_UART_DIVISOR + UART_REG_S t1, UART_DLL(t0) /* write low order byte */ + srl t1, t1, 8 + UART_REG_S t1, UART_DLM(t0) /* write high order byte */ + + li t1, UART_LCR_W /* DLAB off */ + UART_REG_S t1, UART_LCR(t0) /* Write it out */ +#endif /* CONFIG_DEBUG_LL */ +.endm + +/* + * output a character in a0 + */ +.macro debug_ll_outc_a0 +#ifdef CONFIG_DEBUG_LL + + li t0, DEBUG_LL_UART_ADDR + +201: + UART_REG_L t1, UART_LSR(t0) /* get line status */ + andi t1, t1, UART_LSR_THRE /* check for transmitter empty */ + beqz t1, 201b /* try again */ + + UART_REG_S a0, UART_THR(t0) /* write the character */ + +#endif /* CONFIG_DEBUG_LL */ +.endm + +/* + * output a character + */ +.macro debug_ll_outc chr +#ifdef CONFIG_DEBUG_LL + li a0, \chr + debug_ll_outc_a0 +#endif /* CONFIG_DEBUG_LL */ +.endm + +/* + * output CR + NL + */ +.macro debug_ll_ns16550_outnl +#ifdef CONFIG_DEBUG_LL + debug_ll_outc '\r' + debug_ll_outc '\n' +#endif /* CONFIG_DEBUG_LL */ +.endm + +/* + * check character in input buffer + * return value: + * v0 = 0 no character in input buffer + * v0 != 0 character in input buffer + */ +.macro debug_ll_tstc +#ifdef CONFIG_DEBUG_LL + li t0, DEBUG_LL_UART_ADDR + + /* get line status and check for data present */ + UART_REG_L s0, UART_LSR(t0) + andi s0, s0, UART_LSR_DR + +#endif /* CONFIG_DEBUG_LL */ +.endm + +/* + * get character to v0 + */ +.macro debug_ll_getc +#ifdef CONFIG_DEBUG_LL + +204: + debug_ll_tstc + +/* try again */
arch/riscv/include/asm/debug_ll_ns16550.h line 182
Quoted 10 lines
arch/riscv/include/asm/debug_ll_ns16550.h new file +10
-0+ beqz s0, 204b + + /* read a character */ + UART_REG_L s0, UART_RBR(t0) + +#endif /* CONFIG_DEBUG_LL */ +.endm +#endif /* __ASSEMBLY__ */ + +#endif /* __INCLUDE_RISCV_ASM_DEBUG_LL_NS16550_H__ */
_______________________________________________
barebox mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/barebox
PATCH v3 4/10 RISC-V: add nmon nano-monitor
In reply to Antony Pavlovnmon is a tiny (<1024 bytes) monitor program
for the RV32I processors.
It can operate with NO working RAM at all!
It uses only the processor registers and NS16550-compatible UART port for operation, so it can be used for a memory controller setup code debugging.
Signed-off-by Antony Pavlov <[email protected]>
--- arch/riscv/Kconfig | 24 +++ arch/riscv/boot/start.S | 8 + arch/riscv/include/asm/riscv_nmon.h | 234 ++++++++++++++++++++++++++++ 3 files changed, 266 insertions(+)
arch/riscv/Kconfig +24 -0
@@ -63,3 +63,27 @@ config BUILTIN_DTB_NAME source arch/riscv/mach-erizo/Kconfig endmenu + +menu "RISC-V specific settings" + +config HAS_NMON + bool + +config NMON + bool "nmon" + depends on HAS_NMON + depends on DEBUG_LL + help + Say yes here to add the nmon to pbl. + nmon -- nano-monitor program for the RISC-V processors. + It can operate with NO working RAM, using only + the processor registers. + +config NMON_HELP + bool "nmon help message" + depends on NMON + help + Say yes here to get the nmon commands message on + every nmon start. + +endmenu
arch/riscv/boot/start.S +8 -0
@@ -18,12 +18,20 @@ #include <asm-generic/memory_layout.h> +#include "mach/debug_ll.h" + +#include "asm/riscv_nmon.h" + .text .section ".text_entry" .align 2 .globl _start _start: + debug_ll_ns16550_init + + riscv_nmon + li sp, STACK_BASE + STACK_SIZE /* copy barebox to link location */
arch/riscv/include/asm/riscv_nmon.h new file +234 -0
234 lines not on this page · raw message
Signature · 7 lines
2.20.0 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH v3 5/10 RISC-V: erizo: add DEBUG_LL support
In reply to Antony PavlovSigned-off-by Antony Pavlov <[email protected]>
--- arch/riscv/Kconfig | 1 + arch/riscv/mach-erizo/include/mach/debug_ll.h | 33 +++++++++++++++++++ 2 files changed, 34 insertions(+)
arch/riscv/Kconfig +1 -0
@@ -21,6 +21,7 @@ choice config MACH_ERIZO bool "erizo family" + select HAS_DEBUG_LL endchoice
arch/riscv/mach-erizo/include/mach/debug_ll.h new file +33 -0
@@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +* Copyright (C) 2017 Antony Pavlov <[email protected]> +* +* This file is part of barebox. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ + +#ifndef __MACH_ERIZO_DEBUG_LL__ +#define __MACH_ERIZO_DEBUG_LL__ + +/** @file +* This File contains declaration for early output support +*/ + +#include <linux/kconfig.h> + +#define DEBUG_LL_UART_ADDR 0x90000000 +#define DEBUG_LL_UART_SHIFT 2 +#define DEBUG_LL_UART_IOSIZE32 + +#define DEBUG_LL_UART_CLK (24000000 / 16) +#define DEBUG_LL_UART_BPS CONFIG_BAUDRATE +#define DEBUG_LL_UART_DIVISOR (DEBUG_LL_UART_CLK / DEBUG_LL_UART_BPS) + +#include <asm/debug_ll_ns16550.h> + +#endif /* __MACH_ERIZO_DEBUG_LL__ */
Signature · 7 lines
2.20.0 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH v3 6/10 RISC-V: erizo: enable nmon
In reply to Antony PavlovSigned-off-by Antony Pavlov <[email protected]>
--- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+)
arch/riscv/Kconfig +1 -0
@@ -22,6 +22,7 @@ choice config MACH_ERIZO bool "erizo family" select HAS_DEBUG_LL + select HAS_NMON endchoice
Signature · 7 lines
2.20.0 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH v3 7/10 RISC-V: erizo: add nmon image creation
In reply to Antony PavlovSigned-off-by Antony Pavlov <[email protected]>
--- arch/riscv/Makefile | 11 +++++++++++ scripts/erizo-nmon-image | 10 ++++++++++ 2 files changed, 21 insertions(+)
arch/riscv/Makefile +11 -0
@@ -54,3 +54,14 @@ CFLAGS += $(cflags-y) lds-y := arch/riscv/lib/barebox.lds CLEAN_FILES += arch/riscv/lib/barebox.lds + +ifeq ($(CONFIG_MACH_ERIZO),y) +KBUILD_IMAGE := barebox.erizo.nmon +endif + +quiet_cmd_erizo_nmon_image = MKIMAGE $@ + cmd_erizo_nmon_image = $(srctree)/scripts/erizo-nmon-image $< $@ || \ + echo "WARNING: Couldn't create erizo nmon image due to previous errors." + +barebox.erizo.nmon: $(KBUILD_BINARY) FORCE + $(call if_changed,erizo_nmon_image)
scripts/erizo-nmon-image new file +10 -0
@@ -0,0 +1,10 @@ +#!/bin/sh + +if [ $# != 2 ]; then + echo "Usage:" + echo " erizo-nmon-image <input-binary-file> <output-expect-file>" + + exit 1 +fi + +hexdump -v -e '/4 "%08x\n"' $1 | perl -e '$a = 0x80000000; while (<>) { chop; printf("expect \"nmon> \"\n"); printf("send \"w%08x$_\"\n", $a); $a = $a + 4; }' > $2
Signature · 7 lines
2.20.0 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH v3 8/10 RISC-V: add erizo_generic_defconfig
In reply to Antony PavlovSigned-off-by Antony Pavlov <[email protected]>
--- arch/riscv/configs/erizo_generic_defconfig | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+)
arch/riscv/configs/erizo_generic_defconfig new file +51 -0
@@ -0,0 +1,51 @@ +# CONFIG_GLOBALVAR is not set +CONFIG_TEXT_BASE=0x80000000 +CONFIG_MEMORY_LAYOUT_FIXED=y +CONFIG_STACK_BASE=0x800e0000 +CONFIG_STACK_SIZE=0x20000 +CONFIG_MALLOC_BASE=0x80100000 +CONFIG_MALLOC_SIZE=0x100000 +CONFIG_MALLOC_TLSF=y +CONFIG_PANIC_HANG=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +# CONFIG_ERRNO_MESSAGES is not set +# CONFIG_TIMESTAMP is not set +# CONFIG_BOOTM is not set +# CONFIG_ENV_HANDLING is not set +CONFIG_POLLER=y +CONFIG_DEBUG_LL=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_IMD=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_GO=y +CONFIG_CMD_LOADY=y +CONFIG_CMD_CMP=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MM=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SPI=y +CONFIG_CMD_OF_DUMP=y +CONFIG_CMD_TIME=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_OFDEVICE=y +CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_DRIVER_SPI_GPIO=y +CONFIG_I2C=y +CONFIG_I2C_GPIO=y +CONFIG_MTD=y +# CONFIG_MTD_OOB_DEVICE is not set +CONFIG_MTD_M25P80=y +CONFIG_CLOCKSOURCE_DUMMY_RATE=60000 +CONFIG_EEPROM_AT24=y +CONFIG_GPIO_GENERIC_PLATFORM=y +# CONFIG_PINCTRL is not set +CONFIG_DIGEST_CRC32_GENERIC=y
Signature · 7 lines
2.20.0 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH v3 9/10 scripts: add nmon-loader
In reply to Antony PavlovSigned-off-by Antony Pavlov <[email protected]>
--- scripts/nmon-loader | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+)
scripts/nmon-loader new file +31 -0
@@ -0,0 +1,31 @@ +#!/usr/bin/expect -f + +# device +set image [lindex $argv 0]; +set modem [lindex $argv 1]; +set speed [lindex $argv 2]; + +if {$argc != 3} { + puts "Usage:" + puts " nmon-loader.expect <file> <device> <speed>" + exit 2 +} + +# keep it open +exec sh -c "sleep 3 < $modem" & + +# serial port parameters +exec stty -F $modem $speed raw -clocal -echo -istrip -hup + +# connect +send_user "connecting to $modem, exit with ~.\n" +spawn -open [open $modem w+] +send_user "connected\n" +send "\r" + +source $image + +interact { + ~- exit + ~~ {send "\034"} +}
Signature · 7 lines
2.20.0 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH v3 09/10] scripts: add nmon-loader
On Tue, 18 Dec 2018 10:19:42 +0300
Antony Pavlov <[email protected]> wrote:
Hi Sascha!
It looks like this patch is missed in the master branch. Please apply the patch!
Quoted 45 lines
Signed-off-by Antony Pavlov <[email protected]>--- scripts/nmon-loader | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+)scripts/nmon-loader new file +31
-0@@ -0,0 +1,31 @@ +#!/usr/bin/expect -f + +# device +set image [lindex $argv 0]; +set modem [lindex $argv 1]; +set speed [lindex $argv 2]; + +if {$argc != 3} { + puts "Usage:" + puts " nmon-loader.expect <file> <device> <speed>" + exit 2 +} + +# keep it open +exec sh -c "sleep 3 < $modem" & + +# serial port parameters +exec stty -F $modem $speed raw -clocal -echo -istrip -hup + +# connect +send_user "connecting to $modem, exit with ~.\n" +spawn -open [open $modem w+] +send_user "connected\n" +send "\r" + +source $image + +interact { + ~- exit + ~~ {send "\034"} +}Signature · 1 line
2.20.0
Signature · 7 lines
Best regards, Antony Pavlov _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH v3 09/10] scripts: add nmon-loader
Hi Antony,
Quoted 7 lines · Antony Pavlov
On Tue, 18 Dec 2018 10:19:42 +0300
Antony Pavlov <[email protected]> wrote:Hi Sascha!
It looks like this patch is missed in the master branch. Please apply the patch!
I was about to apply it when I just saw that neither the commit message nor a comment in the script give a hint what this all about. Could you add something?
Quoted 3 lines
scripts/nmon-loader line 10
Quoted 3 lines
scripts/nmon-loader new file +3
-0+if {$argc != 3} { + puts "Usage:" + puts " nmon-loader.expect <file> <device> <speed>"
The script is named just nmon-loader, not nmon-loader.expect.
Sascha
Signature · 9 lines
Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH v3 09/10] scripts: add nmon-loader
Quoted 15 lines · On Mon, 12 Aug 2019 09:41:21 +0200 Sascha Hauer <[email protected]> wrote:
Hi Antony,
Quoted 7 lines · Antony Pavlov
On Tue, 18 Dec 2018 10:19:42 +0300
Antony Pavlov <[email protected]> wrote:Hi Sascha!
It looks like this patch is missed in the master branch. Please apply the patch!
I was about to apply it when I just saw that neither the commit message nor a comment in the script give a hint what this all about. Could you add something?
Quoted 5 lines
Quoted 3 lines
scripts/nmon-loader line 10
Quoted 3 lines
scripts/nmon-loader new file +3
-0+if {$argc != 3} { + puts "Usage:" + puts " nmon-loader.expect <file> <device> <speed>"The script is named just nmon-loader, not nmon-loader.expect.
Ok, I'll add a comment to the script itself and resend the updated patch.
Signature · 7 lines
Best regards, Antony Pavlov _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH v3 10/10 Documentation: add RISC-V docs
In reply to Antony PavlovSigned-off-by Antony Pavlov <[email protected]>
--- Documentation/boards/riscv.rst | 91 ++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+)
Documentation/boards/riscv.rst new file +91 -0
@@ -0,0 +1,91 @@ +RISC-V +====== + +Running RISC-V barebox on qemu +------------------------------ + +Obtain RISC-V GCC/Newlib Toolchain, +see https://github.com/riscv/riscv-tools/blob/master/README.md +for details. The ``build.sh`` script from ``riscv-tools`` should +create toolchain. + +Next compile qemu emulator:: + + $ git clone -b 20180409.erizo https://github.com/miet-riscv-workgroup/riscv-qemu + $ cd riscv-qemu + $ cap="no" ./configure \ + --extra-cflags="-Wno-maybe-uninitialized" \ + --audio-drv-list="" \ + --disable-attr \ + --disable-blobs \ + --disable-bluez \ + --disable-brlapi \ + --disable-curl \ + --disable-curses \ + --disable-docs \ + --disable-kvm \ + --disable-spice \ + --disable-sdl \ + --disable-vde \ + --disable-vnc-sasl \ + --disable-werror \ + --enable-trace-backend=simple \ + --disable-stack-protector \ + --target-list=riscv32-softmmu,riscv64-softmmu + $ make + + +Next compile barebox:: + + $ make erizo_generic_defconfig ARCH=riscv + ... + $ make ARCH=riscv CROSS_COMPILE=<path to your riscv toolchain>/riscv32-unknown-elf- + +Run barebox:: + + $ <path to riscv-qemu source>/riscv32-softmmu/qemu-system-riscv32 \ + -nographic -M erizo -bios <path to barebox sources >/barebox.bin \ + -serial stdio -monitor none -trace file=/dev/null + Switch to console [cs0] + + + barebox 2018.12.0-00148-g60e49c4e16 #1 Tue Dec 18 01:12:29 MSK 2018 + + + Board: generic Erizo SoC board + malloc space: 0x80100000 -> 0x801fffff (size 1 MiB) + running /env/bin/init... + /env/bin/init not found + barebox:/ + + +Running RISC-V barebox on DE0-Nano FPGA board +--------------------------------------------- + +See https://github.com/open-design/riscv-soc-cores/ for instructions +on DE0-Nano bitstream generation and loading. + +Connect to board's UART with your favorite serial communication software +(e.g. minicom) and check 'nmon> ' prompt (nmon runs from onchip ROM). + +Next close your communication software and use ./scripts/nmon-loader +to load barebox image into board's DRAM, e.g. + + # ./scripts/nmon-loader barebox.erizo.nmon /dev/ttyUSB0 115200 + +Wait several munutes for 'nmon> ' prompt. + +Next, start barebox from DRAM: + + nmon> g 80000000 + Switch to console [cs0] + + + barebox 2018.12.0-00148-g60e49c4e16 #1 Tue Dec 18 01:12:29 MSK 2018 + + + Board: generic Erizo SoC board + malloc space: 0x80100000 -> 0x801fffff (size 1 MiB) + running /env/bin/init... + /env/bin/init not found + barebox:/
Signature · 7 lines
2.20.0 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Hi Antony,
Quoted 2 lines · Antony Pavlov
This patchseries adds initial RISC-V architecture support for barebox.
It's very nice to get RISC-V support for barebox.
The code looks fine from a first glance. I would prefer using multi image support from the start of course, but I think I can live without it.
I do not have the bandwidth to look at the code so closely to give any valuable input though. I am fine to apply it if you want to, or you could continue to develop it out of tree if that's more convenient for you. Your choice.
Sascha
Signature · 9 lines
Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Quoted 5 lines · On Thu, 3 Jan 2019 12:18:09 +0100 Sascha Hauer <[email protected]> wrote:
Quoted 1 line · Antony Pavlov
This patchseries adds initial RISC-V architecture support for barebox.
It's very nice to get RISC-V support for barebox.
Quoted 7 lines
The code looks fine from a first glance. I would prefer using multi image support from the start of course, but I think I can live without it.
I do not have the bandwidth to look at the code so closely to give any valuable input though. I am fine to apply it if you want to, or you could continue to develop it out of tree if that's more convenient for you. Your choice.
Hi Sascha!
Please apply RISC-V patchseries.
It's looks like people need a good bootloader for RISC-V ;) E.g.:
https://www.mail-archive.com/[email protected]/msg52977.html
https://forums.sifive.com/t/coreboot-or-u-boot/1186
I'm planning to add linux-capable 64-bit SiFive Unleashed board support in the next RISC-V patchseries. See https://www.sifive.com/boards/hifive-unleashed for details.
At least current qemu supports Unleashed-class boards.
Signature · 7 lines
Best regards, Antony Pavlov _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Quoted 16 lines · Antony Pavlov
Quoted 5 lines · On Thu, 3 Jan 2019 12:18:09 +0100 Sascha Hauer <[email protected]> wrote:
Quoted 1 line · Antony Pavlov
This patchseries adds initial RISC-V architecture support for barebox.
It's very nice to get RISC-V support for barebox.
Quoted 7 lines
The code looks fine from a first glance. I would prefer using multi image support from the start of course, but I think I can live without it.
I do not have the bandwidth to look at the code so closely to give any valuable input though. I am fine to apply it if you want to, or you could continue to develop it out of tree if that's more convenient for you. Your choice.
Quoted 3 lines
Hi Sascha!
Please apply RISC-V patchseries.
Ok, just did that.
Sascha
Signature · 9 lines
Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox