arm64: dts: Add sdm845 GPU/GMU and SMMU

Every GPU core only has one interrupt so there isn't any value in looking up the interrupt by name. Remove the name (which is legacy anyway) and use platform_get_irq() instead.

Signed-off-by Jordan Crouse <[email protected]>

---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 -
 drivers/gpu/drm/msm/msm_gpu.c           | 2 +-
 drivers/gpu/drm/msm/msm_gpu.h           | 1 -
 3 files changed, 1 insertion(+), 3 deletions(-)

Each GPU core only uses one interrupt so we don't to look up an interrupt by name and thereby we don't need interrupt-names.

Signed-off-by Jordan Crouse <[email protected]>

---
 Documentation/devicetree/bindings/display/msm/gpu.txt | 1 -
 1 file changed, 1 deletion(-)

'interrupt-names' shouldn't be used in cases when there is only one interrupt and it is not otherwise used in the driver.

Signed-off-by Jordan Crouse <[email protected]>

---
 arch/arm/boot/dts/qcom-apq8064.dtsi | 1 -
 1 file changed, 1 deletion(-)

Hi,

Quoted 8 lines · Jordan Crouse

'interrupt-names' shouldn't be used in cases when there is only one interrupt and it is not otherwise used in the driver.

Signed-off-by Jordan Crouse <[email protected]>

---
 arch/arm/boot/dts/qcom-apq8064.dtsi | 1 -
 1 file changed, 1 deletion(-)

Looks good to me. It should be noted that Andy shouldn't land this until he has a tree that contains ("drm/msm/gpu: Remove hardcoded interrupt name"). ...or he should Ack this and it should go through the same tree as that patch.

I'm curious: is there a reason you didn't remove it from the other two users?

linuxnext/master:arch/arm/boot/dts/imx51.dtsi:
interrupt-names = "kgsl_3d0_irq";
linuxnext/master:arch/arm/boot/dts/imx53.dtsi:
interrupt-names = "kgsl_3d0_irq";

...also: if this really is only for "apq8064" and not globally for all qcom devices it'd be nice to mention "apq8064" somewhere in the subject.

-Doug

'interrupt-names' shouldn't be used in cases when there is only one interrupt and it is not otherwise used in the driver.

Signed-off-by Jordan Crouse <[email protected]>

---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 -
 1 file changed, 1 deletion(-)

Update the GPU bindings and document the new bindings for the GMU device found with Adreno a6xx targets.

Signed-off-by Jordan Crouse <[email protected]>

---

v7: Updated the GMU compatible string and clarified details about when clocks can be optional on the GPU

 .../devicetree/bindings/display/msm/gmu.txt   | 59 +++++++++++++++++++
 .../devicetree/bindings/display/msm/gpu.txt   | 42 ++++++++++++-
 2 files changed, 98 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt

Add the nodes to describe the Adreno GPU and GMU devices.

Signed-off-by Jordan Crouse <[email protected]>

---

v7: Updated the GMU compatible string and removed interrupt-names

 arch/arm64/boot/dts/qcom/sdm845.dtsi | 122 +++++++++++++++++++++++++++
 1 file changed, 122 insertions(+)

arch/arm64/boot/dts/qcom/sdm845.dtsi +1 -0

index 233a5898ebc2..4779014e4a05 100644
@@ -11,6 +11,7 @@
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/phy/phy-qcom-qusb2.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 #include <dt-bindings/clock/qcom,gcc-sdm845.h>

arch/arm64/boot/dts/qcom/sdm845.dtsi +11 -0

+                       compatible = "qcom,adreno-630.2", "qcom,adreno";
+                       #stream-id-cells = <16>;
+
+                       reg = <0x5000000 0x40000>, <0x509e000 0x10>;
+                       reg-names = "kgsl_3d0_reg_memory", "cx_mem";
+
+                       /*
+                        * Look ma, no clocks! The GPU clocks and power are
+                        * controlled entirely by the GMU
+                        */
+

Hi,

Quoted 24 lines · Jordan Crouse

Add the nodes to describe the Adreno GPU and GMU devices.

Signed-off-by Jordan Crouse <[email protected]>

---

v7: Updated the GMU compatible string and removed interrupt-names

 arch/arm64/boot/dts/qcom/sdm845.dtsi | 122 +++++++++++++++++++++++++++
 1 file changed, 122 insertions(+)

arch/arm64/boot/dts/qcom/sdm845.dtsi +1 -0

index 233a5898ebc2..4779014e4a05 100644
@@ -11,6 +11,7 @@
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/phy/phy-qcom-qusb2.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 #include <dt-bindings/clock/qcom,gcc-sdm845.h>

arch/arm64/boot/dts/qcom/sdm845.dtsi line 1354

Quoted 5 lines

arch/arm64/boot/dts/qcom/sdm845.dtsi +2 -0

@@ -1349,6 +1350,127 @@
                        };
                };
 
+
+               gpu@5000000 {

Repeating my comments from v6:

nit that you're adding an extra blank line here that you don't need. Given the quantity of outstanding dts patches though, it's almost certain that Andy will need to manually resolve conflicts when applying this patch so presumably he can fix up when he lands.

In any case, feel free to add:

Reviewed-by Douglas Anderson <[email protected]>

Tested-by Douglas Anderson <[email protected]>

Quoted 11 lines

arch/arm64/boot/dts/qcom/sdm845.dtsi +11 -0

+                       compatible = "qcom,adreno-630.2", "qcom,adreno";
+                       #stream-id-cells = <16>;
+
+                       reg = <0x5000000 0x40000>, <0x509e000 0x10>;
+                       reg-names = "kgsl_3d0_reg_memory", "cx_mem";
+
+                       /*
+                        * Look ma, no clocks! The GPU clocks and power are
+                        * controlled entirely by the GMU
+                        */
+

arch/arm64/boot/dts/qcom/sdm845.dtsi line 1375

Quoted 10 lines

arch/arm64/boot/dts/qcom/sdm845.dtsi +10 -0

+                       interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+                       iommus = <&adreno_smmu 0>;
+
+                       operating-points-v2 = <&gpu_opp_table>;
+
+                       qcom,gmu = <&gmu>;
+
+                       gpu_opp_table: opp-table {
+                               compatible = "operating-points-v2-qcom-level";

I believe that the consensus from the v2 comments at
<https://patchwork.kernel.org/patch/10727121/> are that this should be:

compatible = "operating-points-v2-qcom-level", "operating-points-v2";

...same with the other one below...

Now that more of the sdm845 bindings are headed upstream this a refresh of of https://patchwork.freedesktop.org/series/39308/ to add bindings and nodes for the GPU/GMU and GPU SMMU for sdm845. v7 of this patchset also removes interrupt-names from the driver and the existing DT changes per feedback from Rob Herring.

This is based on :
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git for-next

with:
https://lore.kernel.org/patchwork/patch/1018365/

This change requires the following dependencies:

include/dt-bindings/power/qcom-rpmpd.h:
https://patchwork.kernel.org/patch/10711119/

qcom,smmu-v2 binding:
https://patchwork.kernel.org/patch/10581911/

v7: Add patches to remove interrupt-names, add version specific compatible
string for gmu
v6: Update GPU bindings for a6xx and make the examples match the nodes and vice
versa. Clean up types and rebase on
https://lore.kernel.org/patchwork/patch/1018365/ to help facilitate merging.
v5: Use symbolic names for the RPMH power levels defined in OPP table,
move the opp tables as children of their respective nodes and rename the iommu device.
v4: Rebase
v3: Split GMU PDC region into two GPU specific sections, fix indentation,
really use qcom,gmu for the phandle name
v2: changed qcom,arc-level to qcom,level following discussion with Viresh;
change gmu phandle to qcom,gmu per Rob

Jordan Crouse (6):
drm/msm/gpu: Remove hardcoded interrupt name
drm/msm: drop interrupt-names
ARM: dts: qcom: Removed unused interrupt-names from GPU node
arm64: dts: qcom: msm8916: Remove unused interrupt-names from GPU
dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings
arm64: dts: sdm845: Add gpu and gmu device nodes

Hi Rob,

Quoted 35 lines · Jordan Crouse

Now that more of the sdm845 bindings are headed upstream this a refresh of of https://patchwork.freedesktop.org/series/39308/ to add bindings and nodes for the GPU/GMU and GPU SMMU for sdm845. v7 of this patchset also removes interrupt-names from the driver and the existing DT changes per feedback from Rob Herring.

This is based on :
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git for-next

with:
https://lore.kernel.org/patchwork/patch/1018365/

This change requires the following dependencies:

include/dt-bindings/power/qcom-rpmpd.h:
https://patchwork.kernel.org/patch/10711119/

qcom,smmu-v2 binding:
https://patchwork.kernel.org/patch/10581911/

v7: Add patches to remove interrupt-names, add version specific compatible
string for gmu
v6: Update GPU bindings for a6xx and make the examples match the nodes and vice
versa. Clean up types and rebase on
https://lore.kernel.org/patchwork/patch/1018365/ to help facilitate merging.
v5: Use symbolic names for the RPMH power levels defined in OPP table,
move the opp tables as children of their respective nodes and rename the iommu device.
v4: Rebase
v3: Split GMU PDC region into two GPU specific sections, fix indentation,
really use qcom,gmu for the phandle name
v2: changed qcom,arc-level to qcom,level following discussion with Viresh;
change gmu phandle to qcom,gmu per Rob

Quoted 7 lines

Jordan Crouse (6):
drm/msm/gpu: Remove hardcoded interrupt name
drm/msm: drop interrupt-names
ARM: dts: qcom: Removed unused interrupt-names from GPU node
arm64: dts: qcom: msm8916: Remove unused interrupt-names from GPU
dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings
arm64: dts: sdm845: Add gpu and gmu device nodes

I know it's been holidays and everyone (including me) has been on vacation, but just wanted to make sure the current status of this series was explicitly called out. :-)

I believe patches #1 and #2 are ready to land and will go through your tree.

Patches #3 and #4 should probably go through Andy's tree and are not urgent (they are just cleanup). They can sit on the back burner until patches #1 and #2 have hit mainline. That's a good reason to land #1 and #2 sooner. ;-)

I think patch #5 is also ready to land. There's been some bikeshedding about the exact format for the opp table, but none of that bikeshedding affects the bindings that Jordan wrote. If you agree that this is OK to land, it would also be nice to get in.

...then Jordan can spin patch #6 (once Rob H Acks Rajendra's opp bindings) alone at a future date.