clk: Add Allwinner CLK, RESET support

---
 arch/arm/include/asm/arch-sunxi/ccu.h | 65 +++++++++++++++++++++++
 drivers/clk/Kconfig                   |  1 +
 drivers/clk/Makefile                  |  1 +
 drivers/clk/sunxi/Kconfig             | 18 +++++++
 drivers/clk/sunxi/Makefile            |  9 ++++
 drivers/clk/sunxi/clk_a64.c           | 46 +++++++++++++++++
 drivers/clk/sunxi/clk_sunxi.c         | 74 +++++++++++++++++++++++++++
 7 files changed, 214 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-sunxi/ccu.h
 create mode 100644 drivers/clk/sunxi/Kconfig
 create mode 100644 drivers/clk/sunxi/Makefile
 create mode 100644 drivers/clk/sunxi/clk_a64.c
 create mode 100644 drivers/clk/sunxi/clk_sunxi.c

arch/arm/include/asm/arch-sunxi/ccu.h new file +65 -0

new file mode 100644
index 0000000000..24efe0ab0a
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Amarula Solutions.
+ * Author: Jagan Teki <[email protected]>
+ */
+
+#ifndef _ASM_ARCH_CCU_H
+#define _ASM_ARCH_CCU_H
+
+/**
+ * enum ccu_flags - ccu clock flags
+ *
+ * @CCU_CLK_F_IS_VALID:		is given clock gate is valid?
+ */
+enum ccu_flags {
+	CCU_CLK_F_IS_VALID		= BIT(0),
+};
+
+/**
+ * struct ccu_clk_gate - ccu clock gate
+ * @off:	gate offset
+ * @bit:	gate bit
+ * @flags:	ccu clock gate flags
+ */
+struct ccu_clk_gate {
+	u16 off;
+	u32 bit;
+	enum ccu_flags flags;
+};
+
+#define GATE(_off, _bit) {			\
+	.off = _off,				\
+	.bit = _bit,				\
+	.flags = CCU_CLK_F_IS_VALID,		\
+}
+
+/**
+ * struct ccu_desc - clock control unit descriptor
+ *
+ * @gates:	clock gates
+ */
+struct ccu_desc {
+	const struct ccu_clk_gate *gates;
+};
+
+/**
+ * struct ccu_priv - sunxi clock control unit
+ *
+ * @base:	base address
+ * @desc:	ccu descriptor
+ */
+struct ccu_priv {
+	void *base;
+	const struct ccu_desc *desc;
+};
+
+/**
+ * sunxi_clk_probe - common sunxi clock probe
+ * @dev:	clock device
+ */
+int sunxi_clk_probe(struct udevice *dev);
+
+extern struct clk_ops sunxi_clk_ops;
+
+#endif /* _ASM_ARCH_CCU_H */

drivers/clk/Kconfig +1 -0

index eadf7f8250..51c931b906 100644
@@ -104,6 +104,7 @@ source "drivers/clk/imx/Kconfig"
 source "drivers/clk/mvebu/Kconfig"
 source "drivers/clk/owl/Kconfig"
 source "drivers/clk/renesas/Kconfig"
+source "drivers/clk/sunxi/Kconfig"
 source "drivers/clk/tegra/Kconfig"
 source "drivers/clk/uniphier/Kconfig"

drivers/clk/Makefile +1 -0

index 9acbb1a650..6a4ff9143b 100644
@@ -22,6 +22,7 @@ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
 obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
 obj-$(CONFIG_CLK_OWL) += owl/
 obj-$(CONFIG_CLK_RENESAS) += renesas/
+obj-$(CONFIG_ARCH_SUNXI) += sunxi/
 obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
 obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
 obj-$(CONFIG_CLK_UNIPHIER) += uniphier/

drivers/clk/sunxi/Kconfig new file +18 -0

new file mode 100644
index 0000000000..bf5ecb3801
@@ -0,0 +1,18 @@
+config CLK_SUNXI
+	bool "Clock support for Allwinner SoCs"
+	depends on CLK && ARCH_SUNXI
+	default y
+	help
+	  This enables support for common clock driver API on Allwinner
+	  SoCs.
+
+if CLK_SUNXI
+
+config CLK_SUN50I_A64
+	bool "Clock driver for Allwinner A64"
+	default MACH_SUN50I
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner A64 SoC.
+
+endif # CLK_SUNXI

drivers/clk/sunxi/Makefile new file +9 -0

new file mode 100644
index 0000000000..fb20d28333
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2018 Amarula Solutions.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
+
+obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o

drivers/clk/sunxi/clk_a64.c new file +46 -0

46 lines not on this page · raw message

drivers/clk/sunxi/clk_sunxi.c new file +74 -0

74 lines not on this page · raw message

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2019-01-10 18:39 UTC #2 lore raw

PATCH v6 2/20 reset: Add Allwinner RESET driver

Add common reset driver for all Allwinner SoC's.

Since CLK and RESET share common DT compatible, it is CLK driver job is to bind the reset driver. So add CLK bind call on respective SoC driver by passing ccu map descriptor so-that reset deassert, deassert operations held based on ccu reset table defined from CLK driver.

Select DM_RESET via CLK_SUNXI, this make hidden section of RESET since CLK and RESET share common DT compatible and code.

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/include/asm/arch-sunxi/ccu.h |  33 ++++++-
 drivers/clk/sunxi/Kconfig             |   1 +
 drivers/clk/sunxi/clk_a64.c           |  20 +++++
 drivers/reset/Kconfig                 |   8 ++
 drivers/reset/Makefile                |   1 +
 drivers/reset/reset-sunxi.c           | 124 ++++++++++++++++++++++++++
 6 files changed, 186 insertions(+), 1 deletion(-)
 create mode 100644 drivers/reset/reset-sunxi.c

arch/arm/include/asm/arch-sunxi/ccu.h +32 -1

index 24efe0ab0a..5dd97ab227 100644
@@ -8,12 +8,14 @@
 #define _ASM_ARCH_CCU_H
 
 /**
- * enum ccu_flags - ccu clock flags
+ * enum ccu_flags - ccu clock/reset flags
  *
  * @CCU_CLK_F_IS_VALID:		is given clock gate is valid?
+ * @CCU_RST_F_IS_VALID:		is given reset control is valid?
  */
 enum ccu_flags {
 	CCU_CLK_F_IS_VALID		= BIT(0),
+	CCU_RST_F_IS_VALID		= BIT(1),
 };
 
 /**

@@ -34,13 +36,33 @@ struct ccu_clk_gate {
 	.flags = CCU_CLK_F_IS_VALID,		\
 }
 
+/**
+ * struct ccu_reset - ccu reset
+ * @off:	reset offset
+ * @bit:	reset bit
+ * @flags:	ccu reset control flags
+ */
+struct ccu_reset {
+	u16 off;
+	u32 bit;
+	enum ccu_flags flags;
+};
+
+#define RESET(_off, _bit) {			\
+	.off = _off,				\
+	.bit = _bit,				\
+	.flags = CCU_RST_F_IS_VALID,		\
+}
+
 /**
  * struct ccu_desc - clock control unit descriptor
  *
  * @gates:	clock gates
+ * @resets:	reset unit
  */
 struct ccu_desc {
 	const struct ccu_clk_gate *gates;
+	const struct ccu_reset *resets;
 };
 
 /**

@@ -62,4 +84,13 @@ int sunxi_clk_probe(struct udevice *dev);
 
 extern struct clk_ops sunxi_clk_ops;
 
+/**
+ * sunxi_reset_bind() - reset binding
+ *
+ * @dev:       reset device
+ * @count:     reset count
+ * @return 0 success, or error value
+ */
+int sunxi_reset_bind(struct udevice *dev, ulong count);
+
 #endif /* _ASM_ARCH_CCU_H */

drivers/clk/sunxi/Kconfig +1 -0

index bf5ecb3801..041d711e58 100644
@@ -1,6 +1,7 @@
 config CLK_SUNXI
 	bool "Clock support for Allwinner SoCs"
 	depends on CLK && ARCH_SUNXI
+	select DM_RESET
 	default y
 	help
 	  This enables support for common clock driver API on Allwinner

drivers/clk/sunxi/clk_a64.c +20 -0

index 803a2f711d..eb0a45d97f 100644
@@ -10,6 +10,7 @@
 #include <errno.h>
 #include <asm/arch/ccu.h>
 #include <dt-bindings/clock/sun50i-a64-ccu.h>
+#include <dt-bindings/reset/sun50i-a64-ccu.h>
 
 static const struct ccu_clk_gate a64_gates[] = {
 	[CLK_BUS_OTG]		= GATE(0x060, BIT(23)),

@@ -26,10 +27,28 @@ static const struct ccu_clk_gate a64_gates[] = {
 	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(17)),
 };
 
+static const struct ccu_reset a64_resets[] = {
+	[RST_USB_PHY0]          = RESET(0x0cc, BIT(0)),
+	[RST_USB_PHY1]          = RESET(0x0cc, BIT(1)),
+	[RST_USB_HSIC]          = RESET(0x0cc, BIT(2)),
+
+	[RST_BUS_OTG]           = RESET(0x2c0, BIT(23)),
+	[RST_BUS_EHCI0]         = RESET(0x2c0, BIT(24)),
+	[RST_BUS_EHCI1]         = RESET(0x2c0, BIT(25)),
+	[RST_BUS_OHCI0]         = RESET(0x2c0, BIT(28)),
+	[RST_BUS_OHCI1]         = RESET(0x2c0, BIT(29)),
+};
+
 static const struct ccu_desc a64_ccu_desc = {
 	.gates = a64_gates,
+	.resets = a64_resets,
 };
 
+static int a64_clk_bind(struct udevice *dev)
+{
+	return sunxi_reset_bind(dev, ARRAY_SIZE(a64_resets));
+}
+
 static const struct udevice_id a64_ccu_ids[] = {
 	{ .compatible = "allwinner,sun50i-a64-ccu",
 	  .data = (ulong)&a64_ccu_desc },

@@ -43,4 +62,5 @@ U_BOOT_DRIVER(clk_sun50i_a64) = {
 	.priv_auto_alloc_size	= sizeof(struct ccu_priv),
 	.ops		= &sunxi_clk_ops,
 	.probe		= sunxi_clk_probe,
+	.bind		= a64_clk_bind,
 };

drivers/reset/Kconfig +8 -0

index 9c5208b7da..b6b40b6ce9 100644
@@ -106,4 +106,12 @@ config RESET_SOCFPGA
 	help
 	  Support for reset controller on SoCFPGA platform.
 
+config RESET_SUNXI
+	bool "RESET support for Allwinner SoCs"
+	depends on DM_RESET && ARCH_SUNXI
+	default y
+	help
+	  This enables support for common reset driver for
+	  Allwinner SoCs.
+
 endmenu

drivers/reset/Makefile +1 -0

index f4520878b7..377c038163 100644
@@ -17,3 +17,4 @@ obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
 obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
 obj-$(CONFIG_RESET_MESON) += reset-meson.o
 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
+obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o

drivers/reset/reset-sunxi.c new file +124 -0

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Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2019-01-10 18:39 UTC #3 lore raw

PATCH v6 3/20 clk: sunxi: Add Allwinner H3/H5 CLK driver

Add initial clock driver for Allwinner H3/H5.

- Implement USB bus and USB clocks via ccu_clk_gate table for H3/H5, so it can accessed in common clk enable and disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table for H3/H5, so it can accessed in common reset deassert and assert functions from reset-sunxi.c

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/Kconfig  |  7 ++++
 drivers/clk/sunxi/Makefile |  1 +
 drivers/clk/sunxi/clk_h3.c | 79 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 87 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk_h3.c

drivers/clk/sunxi/Kconfig +7 -0

index 041d711e58..c3713bbac2 100644
@@ -9,6 +9,13 @@ config CLK_SUNXI
 
 if CLK_SUNXI
 
+config CLK_SUN8I_H3
+	bool "Clock driver for Allwinner H3/H5"
+	default MACH_SUNXI_H3_H5
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner H3/H5 SoC.
+
 config CLK_SUN50I_A64
 	bool "Clock driver for Allwinner A64"
 	default MACH_SUN50I

drivers/clk/sunxi/Makefile +1 -0

index fb20d28333..dec49f27a1 100644
@@ -6,4 +6,5 @@
 
 obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
 
+obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o

drivers/clk/sunxi/clk_h3.c new file +79 -0

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2.18.0.321.gffc6fa0e3

Jagan Teki

author

2019-01-10 18:40 UTC #4 lore raw

PATCH v6 4/20 clk: sunxi: Add Allwinner A10/A20 CLK driver

Add initial clock driver for Allwinner A10/A20.

- Implement USB ahb and USB clocks via ccu_clk_gate table for A10/A20, so it can accessed in common clk enable and disable functions from clk_sunxi.c
- Implement USB resets via ccu_reset table for A10/A20, so it can accessed in common reset deassert and assert functions from reset-sunxi.c

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/Kconfig   |  7 +++++
 drivers/clk/sunxi/Makefile  |  1 +
 drivers/clk/sunxi/clk_a10.c | 59 +++++++++++++++++++++++++++++++++++++
 3 files changed, 67 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk_a10.c

drivers/clk/sunxi/Kconfig +7 -0

index c3713bbac2..fbbf94ef55 100644
@@ -9,6 +9,13 @@ config CLK_SUNXI
 
 if CLK_SUNXI
 
+config CLK_SUN4I_A10
+	bool "Clock driver for Allwinner A10/A20"
+	default MACH_SUN4I || MACH_SUN7I
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner A10/A20 SoC.
+
 config CLK_SUN8I_H3
 	bool "Clock driver for Allwinner H3/H5"
 	default MACH_SUNXI_H3_H5

drivers/clk/sunxi/Makefile +1 -0

index dec49f27a1..bba830922f 100644
@@ -6,5 +6,6 @@
 
 obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
 
+obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
 obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o

drivers/clk/sunxi/clk_a10.c new file +59 -0

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2.18.0.321.gffc6fa0e3

Jagan Teki

author

2019-01-10 18:40 UTC #5 lore raw

PATCH v6 5/20 clk: sunxi: Add Allwinner A10s/A13 CLK driver

Add initial clock driver for Allwinner A10s/A13.

- Implement USB ahb and USB clocks via ccu_clk_gate table for A10s/A13, so it can accessed in common clk enable and disable functions from clk_sunxi.c
- Implement USB resets via ccu_reset table for A10s/A13, so it can accessed in common reset deassert and assert functions from reset-sunxi.c

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/Kconfig    |  7 +++++
 drivers/clk/sunxi/Makefile   |  1 +
 drivers/clk/sunxi/clk_a10s.c | 56 ++++++++++++++++++++++++++++++++++++
 3 files changed, 64 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk_a10s.c

drivers/clk/sunxi/Kconfig +7 -0

index fbbf94ef55..b228c2fa3a 100644
@@ -16,6 +16,13 @@ config CLK_SUN4I_A10
 	  This enables common clock driver support for platforms based
 	  on Allwinner A10/A20 SoC.
 
+config CLK_SUN5I_A10S
+	bool "Clock driver for Allwinner A10s/A13"
+	default MACH_SUN5I
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner A10s/A13 SoC.
+
 config CLK_SUN8I_H3
 	bool "Clock driver for Allwinner H3/H5"
 	default MACH_SUNXI_H3_H5

drivers/clk/sunxi/Makefile +1 -0

index bba830922f..466d4b79d6 100644
@@ -7,5 +7,6 @@
 obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
 
 obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
+obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
 obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o

drivers/clk/sunxi/clk_a10s.c new file +56 -0

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2.18.0.321.gffc6fa0e3

Jagan Teki

author

2019-01-10 18:40 UTC #6 lore raw

PATCH v6 6/20 clk: sunxi: Add Allwinner A31 CLK driver

Add initial clock driver for Allwinner A31.

- Implement USB ahb1 and USB clocks via ccu_clk_gate table for A31, so it can accessed in common clk enable and disable functions from clk_sunxi.c
- Implement USB ahb1 and USB resets via ccu_reset table for A31, so it can accessed in common reset deassert and assert functions from reset-sunxi.c

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/Kconfig   |  7 ++++
 drivers/clk/sunxi/Makefile  |  1 +
 drivers/clk/sunxi/clk_a31.c | 68 +++++++++++++++++++++++++++++++++++++
 3 files changed, 76 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk_a31.c

drivers/clk/sunxi/Kconfig +7 -0

index b228c2fa3a..535b0dc02c 100644
@@ -23,6 +23,13 @@ config CLK_SUN5I_A10S
 	  This enables common clock driver support for platforms based
 	  on Allwinner A10s/A13 SoC.
 
+config CLK_SUN6I_A31
+	bool "Clock driver for Allwinner A31/A31s"
+	default MACH_SUN6I
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner A31/A31s SoC.
+
 config CLK_SUN8I_H3
 	bool "Clock driver for Allwinner H3/H5"
 	default MACH_SUNXI_H3_H5

drivers/clk/sunxi/Makefile +1 -0

index 466d4b79d6..3cf0071b0c 100644
@@ -8,5 +8,6 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
 
 obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
 obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
+obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
 obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o

drivers/clk/sunxi/clk_a31.c new file +68 -0

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2.18.0.321.gffc6fa0e3

Jagan Teki

author

2019-01-10 18:40 UTC #7 lore raw

PATCH v6 7/20 clk: sunxi: Add Allwinner A23/A33 CLK driver

Add initial clock driver for Allwinner A23/A33.

- Implement USB bus and USB clocks via ccu_clk_gate table for A23/A33, so it can accessed in common clk enable and disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table for A23/A33, so it can accessed in common reset deassert and assert functions from reset-sunxi.c

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/Kconfig   |  7 +++++
 drivers/clk/sunxi/Makefile  |  1 +
 drivers/clk/sunxi/clk_a23.c | 63 +++++++++++++++++++++++++++++++++++++
 3 files changed, 71 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk_a23.c

drivers/clk/sunxi/Kconfig +7 -0

index 535b0dc02c..38ff99d345 100644
@@ -30,6 +30,13 @@ config CLK_SUN6I_A31
 	  This enables common clock driver support for platforms based
 	  on Allwinner A31/A31s SoC.
 
+config CLK_SUN8I_A23
+	bool "Clock driver for Allwinner A23/A33"
+	default MACH_SUN8I_A23 || MACH_SUN8I_A33
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner A23/A33 SoC.
+
 config CLK_SUN8I_H3
 	bool "Clock driver for Allwinner H3/H5"
 	default MACH_SUNXI_H3_H5

drivers/clk/sunxi/Makefile +1 -0

index 3cf0071b0c..6924897036 100644
@@ -9,5 +9,6 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
 obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
 obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
 obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
+obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
 obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o

drivers/clk/sunxi/clk_a23.c new file +63 -0

63 lines not on this page · raw message

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2019-01-10 18:40 UTC #8 lore raw

PATCH v6 8/20 clk: sunxi: Add Allwinner A83T CLK driver

Add initial clock driver for Allwinner A83T.

- Implement USB bus and USB clocks via ccu_clk_gate table for A83T, so it can accessed in common clk enable and disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table for A83T, so it can accessed in common reset deassert and assert functions from reset-sunxi.c

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/Kconfig    |  7 ++++
 drivers/clk/sunxi/Makefile   |  1 +
 drivers/clk/sunxi/clk_a83t.c | 63 ++++++++++++++++++++++++++++++++++++
 3 files changed, 71 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk_a83t.c

drivers/clk/sunxi/Kconfig +7 -0

index 38ff99d345..90af70d171 100644
@@ -37,6 +37,13 @@ config CLK_SUN8I_A23
 	  This enables common clock driver support for platforms based
 	  on Allwinner A23/A33 SoC.
 
+config CLK_SUN8I_A83T
+	bool "Clock driver for Allwinner A83T"
+	default MACH_SUN8I_A83T
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner A83T SoC.
+
 config CLK_SUN8I_H3
 	bool "Clock driver for Allwinner H3/H5"
 	default MACH_SUNXI_H3_H5

drivers/clk/sunxi/Makefile +1 -0

index 6924897036..4a254c8671 100644
@@ -10,5 +10,6 @@ obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
 obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
 obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
 obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
+obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
 obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o

drivers/clk/sunxi/clk_a83t.c new file +63 -0

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2.18.0.321.gffc6fa0e3

Jagan Teki

author

2019-01-10 18:40 UTC #9 lore raw

PATCH v6 9/20 clk: sunxi: Add Allwinner R40 CLK driver

Add initial clock driver for Allwinner R40.

- Implement USB bus and USB clocks via ccu_clk_gate for R40, so it can accessed in common clk enable and disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table for R40, so it can accessed in common reset deassert and assert functions from reset-sunxi.c

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/Kconfig   |  7 ++++
 drivers/clk/sunxi/Makefile  |  1 +
 drivers/clk/sunxi/clk_r40.c | 70 +++++++++++++++++++++++++++++++++++++
 3 files changed, 78 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk_r40.c

drivers/clk/sunxi/Kconfig +7 -0

index 90af70d171..c45a4ba378 100644
@@ -44,6 +44,13 @@ config CLK_SUN8I_A83T
 	  This enables common clock driver support for platforms based
 	  on Allwinner A83T SoC.
 
+config CLK_SUN8I_R40
+	bool "Clock driver for Allwinner R40"
+	default MACH_SUN8I_R40
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner R40 SoC.
+
 config CLK_SUN8I_H3
 	bool "Clock driver for Allwinner H3/H5"
 	default MACH_SUNXI_H3_H5

drivers/clk/sunxi/Makefile +1 -0

index 4a254c8671..61f8b87396 100644
@@ -11,5 +11,6 @@ obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
 obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
 obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
 obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
+obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
 obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o

drivers/clk/sunxi/clk_r40.c new file +70 -0

70 lines not on this page · raw message

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2019-01-10 18:40 UTC #10 lore raw

PATCH v6 10/20 clk: sunxi: Add Allwinner V3S CLK driver

Add initial clock driver for Allwinner V3S.

- Implement USB bus and USB clocks via ccu_clk_gate table for V3S, so it can accessed in common clk enable and disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table for V3S, so it can accessed in common reset deassert and assert functions from reset-sunxi.c

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/Kconfig   |  7 +++++
 drivers/clk/sunxi/Makefile  |  1 +
 drivers/clk/sunxi/clk_v3s.c | 51 +++++++++++++++++++++++++++++++++++++
 3 files changed, 59 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk_v3s.c

drivers/clk/sunxi/Kconfig +7 -0

index c45a4ba378..a6f84e9e56 100644
@@ -51,6 +51,13 @@ config CLK_SUN8I_R40
 	  This enables common clock driver support for platforms based
 	  on Allwinner R40 SoC.
 
+config CLK_SUN8I_V3S
+	bool "Clock driver for Allwinner V3S"
+	default MACH_SUN8I_V3S
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner V3S SoC.
+
 config CLK_SUN8I_H3
 	bool "Clock driver for Allwinner H3/H5"
 	default MACH_SUNXI_H3_H5

drivers/clk/sunxi/Makefile +1 -0

index 61f8b87396..fbd43527a6 100644
@@ -12,5 +12,6 @@ obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
 obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
 obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
 obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
+obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o
 obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o

drivers/clk/sunxi/clk_v3s.c new file +51 -0

51 lines not on this page · raw message

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2019-01-10 18:40 UTC #11 lore raw

PATCH v6 11/20 clk: sunxi: Implement UART clocks

Implement UART clocks for all Allwinner SoC
clock drivers via ccu clock gate table.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/clk_a10.c  | 9 +++++++++
 drivers/clk/sunxi/clk_a10s.c | 5 +++++
 drivers/clk/sunxi/clk_a23.c  | 6 ++++++
 drivers/clk/sunxi/clk_a31.c  | 7 +++++++
 drivers/clk/sunxi/clk_a64.c  | 6 ++++++
 drivers/clk/sunxi/clk_a83t.c | 6 ++++++
 drivers/clk/sunxi/clk_h3.c   | 5 +++++
 drivers/clk/sunxi/clk_r40.c  | 9 +++++++++
 drivers/clk/sunxi/clk_v3s.c  | 4 ++++
 9 files changed, 57 insertions(+)

drivers/clk/sunxi/clk_a10.c +9 -0

index a8a7b7d41e..b00f51af8b 100644
@@ -19,6 +19,15 @@ static struct ccu_clk_gate a10_gates[] = {
 	[CLK_AHB_EHCI1]		= GATE(0x060, BIT(3)),
 	[CLK_AHB_OHCI1]		= GATE(0x060, BIT(4)),
 
+	[CLK_APB1_UART0]	= GATE(0x06c, BIT(16)),
+	[CLK_APB1_UART1]	= GATE(0x06c, BIT(17)),
+	[CLK_APB1_UART2]	= GATE(0x06c, BIT(18)),
+	[CLK_APB1_UART3]	= GATE(0x06c, BIT(19)),
+	[CLK_APB1_UART4]	= GATE(0x06c, BIT(20)),
+	[CLK_APB1_UART5]	= GATE(0x06c, BIT(21)),
+	[CLK_APB1_UART6]	= GATE(0x06c, BIT(22)),
+	[CLK_APB1_UART7]	= GATE(0x06c, BIT(23)),
+
 	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(6)),
 	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(7)),
 	[CLK_USB_PHY]		= GATE(0x0cc, BIT(8)),

drivers/clk/sunxi/clk_a10s.c +5 -0

index bf91018fc2..aa904ce067 100644
@@ -17,6 +17,11 @@ static struct ccu_clk_gate a10s_gates[] = {
 	[CLK_AHB_EHCI]		= GATE(0x060, BIT(1)),
 	[CLK_AHB_OHCI]		= GATE(0x060, BIT(2)),
 
+	[CLK_APB1_UART0]	= GATE(0x06c, BIT(16)),
+	[CLK_APB1_UART1]	= GATE(0x06c, BIT(17)),
+	[CLK_APB1_UART2]	= GATE(0x06c, BIT(18)),
+	[CLK_APB1_UART3]	= GATE(0x06c, BIT(19)),
+
 	[CLK_USB_OHCI]		= GATE(0x0cc, BIT(6)),
 	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
 	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),

drivers/clk/sunxi/clk_a23.c +6 -0

index 2a504ebdad..ebe8d0002c 100644
@@ -17,6 +17,12 @@ static struct ccu_clk_gate a23_gates[] = {
 	[CLK_BUS_EHCI]		= GATE(0x060, BIT(26)),
 	[CLK_BUS_OHCI]		= GATE(0x060, BIT(29)),
 
+	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
+	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
+	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
+	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
+	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
+
 	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
 	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
 	[CLK_USB_HSIC]		= GATE(0x0cc, BIT(10)),

drivers/clk/sunxi/clk_a31.c +7 -0

index 723d17dff2..145df5c19f 100644
@@ -20,6 +20,13 @@ static struct ccu_clk_gate a31_gates[] = {
 	[CLK_AHB1_OHCI1]	= GATE(0x060, BIT(30)),
 	[CLK_AHB1_OHCI2]	= GATE(0x060, BIT(31)),
 
+	[CLK_APB2_UART0]	= GATE(0x06c, BIT(16)),
+	[CLK_APB2_UART1]	= GATE(0x06c, BIT(17)),
+	[CLK_APB2_UART2]	= GATE(0x06c, BIT(18)),
+	[CLK_APB2_UART3]	= GATE(0x06c, BIT(19)),
+	[CLK_APB2_UART4]	= GATE(0x06c, BIT(20)),
+	[CLK_APB2_UART5]	= GATE(0x06c, BIT(21)),
+
 	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
 	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
 	[CLK_USB_PHY2]		= GATE(0x0cc, BIT(10)),

drivers/clk/sunxi/clk_a64.c +6 -0

index eb0a45d97f..63424a9e2d 100644
@@ -19,6 +19,12 @@ static const struct ccu_clk_gate a64_gates[] = {
 	[CLK_BUS_OHCI0]		= GATE(0x060, BIT(28)),
 	[CLK_BUS_OHCI1]		= GATE(0x060, BIT(29)),
 
+	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
+	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
+	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
+	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
+	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
+
 	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
 	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
 	[CLK_USB_HSIC]		= GATE(0x0cc, BIT(10)),

drivers/clk/sunxi/clk_a83t.c +6 -0

index 3160f7f700..76099fd154 100644
@@ -18,6 +18,12 @@ static struct ccu_clk_gate a83t_gates[] = {
 	[CLK_BUS_EHCI1]		= GATE(0x060, BIT(27)),
 	[CLK_BUS_OHCI0]		= GATE(0x060, BIT(29)),
 
+	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
+	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
+	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
+	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
+	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
+
 	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
 	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
 	[CLK_USB_HSIC]		= GATE(0x0cc, BIT(10)),

drivers/clk/sunxi/clk_h3.c +5 -0

index 9ee5c33b87..69c2aa34a3 100644
@@ -23,6 +23,11 @@ static struct ccu_clk_gate h3_gates[] = {
 	[CLK_BUS_OHCI2]		= GATE(0x060, BIT(30)),
 	[CLK_BUS_OHCI3]		= GATE(0x060, BIT(31)),
 
+	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
+	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
+	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
+	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
+
 	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
 	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
 	[CLK_USB_PHY2]		= GATE(0x0cc, BIT(10)),

drivers/clk/sunxi/clk_r40.c +9 -0

index cdf54da027..9a632b2603 100644
@@ -21,6 +21,15 @@ static struct ccu_clk_gate r40_gates[] = {
 	[CLK_BUS_OHCI1]		= GATE(0x060, BIT(30)),
 	[CLK_BUS_OHCI2]		= GATE(0x060, BIT(31)),
 
+	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
+	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
+	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
+	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
+	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
+	[CLK_BUS_UART5]		= GATE(0x06c, BIT(21)),
+	[CLK_BUS_UART6]		= GATE(0x06c, BIT(22)),
+	[CLK_BUS_UART7]		= GATE(0x06c, BIT(23)),
+
 	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
 	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
 	[CLK_USB_PHY2]		= GATE(0x0cc, BIT(10)),

drivers/clk/sunxi/clk_v3s.c +4 -0

index 623b1601d4..a268786b2d 100644
@@ -15,6 +15,10 @@
 static struct ccu_clk_gate v3s_gates[] = {
 	[CLK_BUS_OTG]		= GATE(0x060, BIT(24)),
 
+	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
+	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
+	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
+
 	[CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
 };

Signature · 1 line

2.18.0.321.gffc6fa0e3

André Przywara

2019-01-10 22:52 UTC #12 lore raw

PATCH v6 11/20 clk: sunxi: Implement UART clocks

Quoted 4 lines · Jagan Teki

Implement UART clocks for all Allwinner SoC
clock drivers via ccu clock gate table.
Signed-off-by Jagan Teki <[email protected]>

Compared against each manual:

Thanks,
Andre

Quoted 169 lines

---
 drivers/clk/sunxi/clk_a10.c  | 9 +++++++++
 drivers/clk/sunxi/clk_a10s.c | 5 +++++
 drivers/clk/sunxi/clk_a23.c  | 6 ++++++
 drivers/clk/sunxi/clk_a31.c  | 7 +++++++
 drivers/clk/sunxi/clk_a64.c  | 6 ++++++
 drivers/clk/sunxi/clk_a83t.c | 6 ++++++
 drivers/clk/sunxi/clk_h3.c   | 5 +++++
 drivers/clk/sunxi/clk_r40.c  | 9 +++++++++
 drivers/clk/sunxi/clk_v3s.c  | 4 ++++
 9 files changed, 57 insertions(+)

drivers/clk/sunxi/clk_a10.c +9 -0

index a8a7b7d41e..b00f51af8b 100644
@@ -19,6 +19,15 @@ static struct ccu_clk_gate a10_gates[] = {
 	[CLK_AHB_EHCI1]		= GATE(0x060, BIT(3)),
 	[CLK_AHB_OHCI1]		= GATE(0x060, BIT(4)),
 
+	[CLK_APB1_UART0]	= GATE(0x06c, BIT(16)),
+	[CLK_APB1_UART1]	= GATE(0x06c, BIT(17)),
+	[CLK_APB1_UART2]	= GATE(0x06c, BIT(18)),
+	[CLK_APB1_UART3]	= GATE(0x06c, BIT(19)),
+	[CLK_APB1_UART4]	= GATE(0x06c, BIT(20)),
+	[CLK_APB1_UART5]	= GATE(0x06c, BIT(21)),
+	[CLK_APB1_UART6]	= GATE(0x06c, BIT(22)),
+	[CLK_APB1_UART7]	= GATE(0x06c, BIT(23)),
+
 	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(6)),
 	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(7)),
 	[CLK_USB_PHY]		= GATE(0x0cc, BIT(8)),

drivers/clk/sunxi/clk_a10s.c +5 -0

index bf91018fc2..aa904ce067 100644
@@ -17,6 +17,11 @@ static struct ccu_clk_gate a10s_gates[] = {
 	[CLK_AHB_EHCI]		= GATE(0x060, BIT(1)),
 	[CLK_AHB_OHCI]		= GATE(0x060, BIT(2)),
 
+	[CLK_APB1_UART0]	= GATE(0x06c, BIT(16)),
+	[CLK_APB1_UART1]	= GATE(0x06c, BIT(17)),
+	[CLK_APB1_UART2]	= GATE(0x06c, BIT(18)),
+	[CLK_APB1_UART3]	= GATE(0x06c, BIT(19)),
+
 	[CLK_USB_OHCI]		= GATE(0x0cc, BIT(6)),
 	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
 	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),

drivers/clk/sunxi/clk_a23.c +6 -0

index 2a504ebdad..ebe8d0002c 100644
@@ -17,6 +17,12 @@ static struct ccu_clk_gate a23_gates[] = {
 	[CLK_BUS_EHCI]		= GATE(0x060, BIT(26)),
 	[CLK_BUS_OHCI]		= GATE(0x060, BIT(29)),
 
+	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
+	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
+	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
+	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
+	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
+
 	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
 	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
 	[CLK_USB_HSIC]		= GATE(0x0cc, BIT(10)),

drivers/clk/sunxi/clk_a31.c +7 -0

index 723d17dff2..145df5c19f 100644
@@ -20,6 +20,13 @@ static struct ccu_clk_gate a31_gates[] = {
 	[CLK_AHB1_OHCI1]	= GATE(0x060, BIT(30)),
 	[CLK_AHB1_OHCI2]	= GATE(0x060, BIT(31)),
 
+	[CLK_APB2_UART0]	= GATE(0x06c, BIT(16)),
+	[CLK_APB2_UART1]	= GATE(0x06c, BIT(17)),
+	[CLK_APB2_UART2]	= GATE(0x06c, BIT(18)),
+	[CLK_APB2_UART3]	= GATE(0x06c, BIT(19)),
+	[CLK_APB2_UART4]	= GATE(0x06c, BIT(20)),
+	[CLK_APB2_UART5]	= GATE(0x06c, BIT(21)),
+
 	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
 	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
 	[CLK_USB_PHY2]		= GATE(0x0cc, BIT(10)),

drivers/clk/sunxi/clk_a64.c +6 -0

index eb0a45d97f..63424a9e2d 100644
@@ -19,6 +19,12 @@ static const struct ccu_clk_gate a64_gates[] = {
 	[CLK_BUS_OHCI0]		= GATE(0x060, BIT(28)),
 	[CLK_BUS_OHCI1]		= GATE(0x060, BIT(29)),
 
+	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
+	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
+	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
+	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
+	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
+
 	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
 	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
 	[CLK_USB_HSIC]		= GATE(0x0cc, BIT(10)),

drivers/clk/sunxi/clk_a83t.c +6 -0

index 3160f7f700..76099fd154 100644
@@ -18,6 +18,12 @@ static struct ccu_clk_gate a83t_gates[] = {
 	[CLK_BUS_EHCI1]		= GATE(0x060, BIT(27)),
 	[CLK_BUS_OHCI0]		= GATE(0x060, BIT(29)),
 
+	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
+	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
+	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
+	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
+	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
+
 	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
 	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
 	[CLK_USB_HSIC]		= GATE(0x0cc, BIT(10)),

drivers/clk/sunxi/clk_h3.c +5 -0

index 9ee5c33b87..69c2aa34a3 100644
@@ -23,6 +23,11 @@ static struct ccu_clk_gate h3_gates[] = {
 	[CLK_BUS_OHCI2]		= GATE(0x060, BIT(30)),
 	[CLK_BUS_OHCI3]		= GATE(0x060, BIT(31)),
 
+	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
+	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
+	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
+	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
+
 	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
 	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
 	[CLK_USB_PHY2]		= GATE(0x0cc, BIT(10)),

drivers/clk/sunxi/clk_r40.c +9 -0

index cdf54da027..9a632b2603 100644
@@ -21,6 +21,15 @@ static struct ccu_clk_gate r40_gates[] = {
 	[CLK_BUS_OHCI1]		= GATE(0x060, BIT(30)),
 	[CLK_BUS_OHCI2]		= GATE(0x060, BIT(31)),
 
+	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
+	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
+	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
+	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
+	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
+	[CLK_BUS_UART5]		= GATE(0x06c, BIT(21)),
+	[CLK_BUS_UART6]		= GATE(0x06c, BIT(22)),
+	[CLK_BUS_UART7]		= GATE(0x06c, BIT(23)),
+
 	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
 	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
 	[CLK_USB_PHY2]		= GATE(0x0cc, BIT(10)),

drivers/clk/sunxi/clk_v3s.c +4 -0

index 623b1601d4..a268786b2d 100644
@@ -15,6 +15,10 @@
 static struct ccu_clk_gate v3s_gates[] = {
 	[CLK_BUS_OTG]		= GATE(0x060, BIT(24)),
 
+	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
+	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
+	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
+
 	[CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
 };

Jagan Teki

author

2019-01-10 18:40 UTC #13 lore raw

PATCH v6 12/20 clk: sunxi: Implement UART resets

Implement UART resets for all relevant Allwinner SoC clock drivers via ccu reset table.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/clk_a23.c  | 6 ++++++
 drivers/clk/sunxi/clk_a31.c  | 7 +++++++
 drivers/clk/sunxi/clk_a64.c  | 6 ++++++
 drivers/clk/sunxi/clk_a83t.c | 6 ++++++
 drivers/clk/sunxi/clk_h3.c   | 5 +++++
 drivers/clk/sunxi/clk_r40.c  | 9 +++++++++
 drivers/clk/sunxi/clk_v3s.c  | 4 ++++
 7 files changed, 43 insertions(+)

drivers/clk/sunxi/clk_a23.c +6 -0

index ebe8d0002c..854259bf81 100644
@@ -38,6 +38,12 @@ static struct ccu_reset a23_resets[] = {
 	[RST_BUS_OTG]		= RESET(0x2c0, BIT(24)),
 	[RST_BUS_EHCI]		= RESET(0x2c0, BIT(26)),
 	[RST_BUS_OHCI]		= RESET(0x2c0, BIT(29)),
+
+	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
+	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
+	[RST_BUS_UART3]		= RESET(0x2d8, BIT(19)),
+	[RST_BUS_UART4]		= RESET(0x2d8, BIT(20)),
 };
 
 static const struct ccu_desc a23_ccu_desc = {

drivers/clk/sunxi/clk_a31.c +7 -0

index 145df5c19f..a38d76cb7c 100644
@@ -46,6 +46,13 @@ static struct ccu_reset a31_resets[] = {
 	[RST_AHB1_OHCI0]	= RESET(0x2c0, BIT(29)),
 	[RST_AHB1_OHCI1]	= RESET(0x2c0, BIT(30)),
 	[RST_AHB1_OHCI2]	= RESET(0x2c0, BIT(31)),
+
+	[RST_APB2_UART0]	= RESET(0x2d8, BIT(16)),
+	[RST_APB2_UART1]	= RESET(0x2d8, BIT(17)),
+	[RST_APB2_UART2]	= RESET(0x2d8, BIT(18)),
+	[RST_APB2_UART3]	= RESET(0x2d8, BIT(19)),
+	[RST_APB2_UART4]	= RESET(0x2d8, BIT(20)),
+	[RST_APB2_UART5]	= RESET(0x2d8, BIT(21)),
 };
 
 static const struct ccu_desc a31_ccu_desc = {

drivers/clk/sunxi/clk_a64.c +6 -0

index 63424a9e2d..a2ba6eefc5 100644
@@ -43,6 +43,12 @@ static const struct ccu_reset a64_resets[] = {
 	[RST_BUS_EHCI1]         = RESET(0x2c0, BIT(25)),
 	[RST_BUS_OHCI0]         = RESET(0x2c0, BIT(28)),
 	[RST_BUS_OHCI1]         = RESET(0x2c0, BIT(29)),
+
+	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
+	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
+	[RST_BUS_UART3]		= RESET(0x2d8, BIT(19)),
+	[RST_BUS_UART4]		= RESET(0x2d8, BIT(20)),
 };
 
 static const struct ccu_desc a64_ccu_desc = {

drivers/clk/sunxi/clk_a83t.c +6 -0

index 76099fd154..1ef6ac5b25 100644
@@ -40,6 +40,12 @@ static struct ccu_reset a83t_resets[] = {
 	[RST_BUS_EHCI0]		= RESET(0x2c0, BIT(26)),
 	[RST_BUS_EHCI1]		= RESET(0x2c0, BIT(27)),
 	[RST_BUS_OHCI0]		= RESET(0x2c0, BIT(29)),
+
+	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
+	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
+	[RST_BUS_UART3]		= RESET(0x2d8, BIT(19)),
+	[RST_BUS_UART4]		= RESET(0x2d8, BIT(20)),
 };
 
 static const struct ccu_desc a83t_ccu_desc = {

drivers/clk/sunxi/clk_h3.c +5 -0

index 69c2aa34a3..f82949b3b6 100644
@@ -53,6 +53,11 @@ static struct ccu_reset h3_resets[] = {
 	[RST_BUS_OHCI1]		= RESET(0x2c0, BIT(29)),
 	[RST_BUS_OHCI2]		= RESET(0x2c0, BIT(30)),
 	[RST_BUS_OHCI3]		= RESET(0x2c0, BIT(31)),
+
+	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
+	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
+	[RST_BUS_UART3]		= RESET(0x2d8, BIT(19)),
 };
 
 static const struct ccu_desc h3_ccu_desc = {

drivers/clk/sunxi/clk_r40.c +9 -0

index 9a632b2603..fd7aae97ea 100644
@@ -50,6 +50,15 @@ static struct ccu_reset r40_resets[] = {
 	[RST_BUS_OHCI0]		= RESET(0x2c0, BIT(29)),
 	[RST_BUS_OHCI1]		= RESET(0x2c0, BIT(30)),
 	[RST_BUS_OHCI2]		= RESET(0x2c0, BIT(31)),
+
+	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
+	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
+	[RST_BUS_UART3]		= RESET(0x2d8, BIT(19)),
+	[RST_BUS_UART4]		= RESET(0x2d8, BIT(20)),
+	[RST_BUS_UART5]		= RESET(0x2d8, BIT(21)),
+	[RST_BUS_UART6]		= RESET(0x2d8, BIT(22)),
+	[RST_BUS_UART7]		= RESET(0x2d8, BIT(23)),
 };
 
 static const struct ccu_desc r40_ccu_desc = {

drivers/clk/sunxi/clk_v3s.c +4 -0

index a268786b2d..25ad87500e 100644
@@ -26,6 +26,10 @@ static struct ccu_reset v3s_resets[] = {
 	[RST_USB_PHY0]		= RESET(0x0cc, BIT(0)),
 
 	[RST_BUS_OTG]		= RESET(0x2c0, BIT(24)),
+
+	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
+	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
 };
 
 static const struct ccu_desc v3s_ccu_desc = {

Signature · 1 line

2.18.0.321.gffc6fa0e3

André Przywara

2019-01-10 22:50 UTC #14 lore raw

PATCH v6 12/20 clk: sunxi: Implement UART resets

Quoted 4 lines · Jagan Teki

Implement UART resets for all relevant Allwinner SoC clock drivers via ccu reset table.
Signed-off-by Jagan Teki <[email protected]>

Compared against each manual:

Cheers,
Andre.

Quoted 131 lines

---
 drivers/clk/sunxi/clk_a23.c  | 6 ++++++
 drivers/clk/sunxi/clk_a31.c  | 7 +++++++
 drivers/clk/sunxi/clk_a64.c  | 6 ++++++
 drivers/clk/sunxi/clk_a83t.c | 6 ++++++
 drivers/clk/sunxi/clk_h3.c   | 5 +++++
 drivers/clk/sunxi/clk_r40.c  | 9 +++++++++
 drivers/clk/sunxi/clk_v3s.c  | 4 ++++
 7 files changed, 43 insertions(+)

drivers/clk/sunxi/clk_a23.c +6 -0

index ebe8d0002c..854259bf81 100644
@@ -38,6 +38,12 @@ static struct ccu_reset a23_resets[] = {
 	[RST_BUS_OTG]		= RESET(0x2c0, BIT(24)),
 	[RST_BUS_EHCI]		= RESET(0x2c0, BIT(26)),
 	[RST_BUS_OHCI]		= RESET(0x2c0, BIT(29)),
+
+	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
+	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
+	[RST_BUS_UART3]		= RESET(0x2d8, BIT(19)),
+	[RST_BUS_UART4]		= RESET(0x2d8, BIT(20)),
 };
 
 static const struct ccu_desc a23_ccu_desc = {

drivers/clk/sunxi/clk_a31.c +7 -0

index 145df5c19f..a38d76cb7c 100644
@@ -46,6 +46,13 @@ static struct ccu_reset a31_resets[] = {
 	[RST_AHB1_OHCI0]	= RESET(0x2c0, BIT(29)),
 	[RST_AHB1_OHCI1]	= RESET(0x2c0, BIT(30)),
 	[RST_AHB1_OHCI2]	= RESET(0x2c0, BIT(31)),
+
+	[RST_APB2_UART0]	= RESET(0x2d8, BIT(16)),
+	[RST_APB2_UART1]	= RESET(0x2d8, BIT(17)),
+	[RST_APB2_UART2]	= RESET(0x2d8, BIT(18)),
+	[RST_APB2_UART3]	= RESET(0x2d8, BIT(19)),
+	[RST_APB2_UART4]	= RESET(0x2d8, BIT(20)),
+	[RST_APB2_UART5]	= RESET(0x2d8, BIT(21)),
 };
 
 static const struct ccu_desc a31_ccu_desc = {

drivers/clk/sunxi/clk_a64.c +6 -0

index 63424a9e2d..a2ba6eefc5 100644
@@ -43,6 +43,12 @@ static const struct ccu_reset a64_resets[] = {
 	[RST_BUS_EHCI1]         = RESET(0x2c0, BIT(25)),
 	[RST_BUS_OHCI0]         = RESET(0x2c0, BIT(28)),
 	[RST_BUS_OHCI1]         = RESET(0x2c0, BIT(29)),
+
+	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
+	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
+	[RST_BUS_UART3]		= RESET(0x2d8, BIT(19)),
+	[RST_BUS_UART4]		= RESET(0x2d8, BIT(20)),
 };
 
 static const struct ccu_desc a64_ccu_desc = {

drivers/clk/sunxi/clk_a83t.c +6 -0

index 76099fd154..1ef6ac5b25 100644
@@ -40,6 +40,12 @@ static struct ccu_reset a83t_resets[] = {
 	[RST_BUS_EHCI0]		= RESET(0x2c0, BIT(26)),
 	[RST_BUS_EHCI1]		= RESET(0x2c0, BIT(27)),
 	[RST_BUS_OHCI0]		= RESET(0x2c0, BIT(29)),
+
+	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
+	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
+	[RST_BUS_UART3]		= RESET(0x2d8, BIT(19)),
+	[RST_BUS_UART4]		= RESET(0x2d8, BIT(20)),
 };
 
 static const struct ccu_desc a83t_ccu_desc = {

drivers/clk/sunxi/clk_h3.c +5 -0

index 69c2aa34a3..f82949b3b6 100644
@@ -53,6 +53,11 @@ static struct ccu_reset h3_resets[] = {
 	[RST_BUS_OHCI1]		= RESET(0x2c0, BIT(29)),
 	[RST_BUS_OHCI2]		= RESET(0x2c0, BIT(30)),
 	[RST_BUS_OHCI3]		= RESET(0x2c0, BIT(31)),
+
+	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
+	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
+	[RST_BUS_UART3]		= RESET(0x2d8, BIT(19)),
 };
 
 static const struct ccu_desc h3_ccu_desc = {

drivers/clk/sunxi/clk_r40.c +9 -0

index 9a632b2603..fd7aae97ea 100644
@@ -50,6 +50,15 @@ static struct ccu_reset r40_resets[] = {
 	[RST_BUS_OHCI0]		= RESET(0x2c0, BIT(29)),
 	[RST_BUS_OHCI1]		= RESET(0x2c0, BIT(30)),
 	[RST_BUS_OHCI2]		= RESET(0x2c0, BIT(31)),
+
+	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
+	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
+	[RST_BUS_UART3]		= RESET(0x2d8, BIT(19)),
+	[RST_BUS_UART4]		= RESET(0x2d8, BIT(20)),
+	[RST_BUS_UART5]		= RESET(0x2d8, BIT(21)),
+	[RST_BUS_UART6]		= RESET(0x2d8, BIT(22)),
+	[RST_BUS_UART7]		= RESET(0x2d8, BIT(23)),
 };
 
 static const struct ccu_desc r40_ccu_desc = {

drivers/clk/sunxi/clk_v3s.c +4 -0

index a268786b2d..25ad87500e 100644
@@ -26,6 +26,10 @@ static struct ccu_reset v3s_resets[] = {
 	[RST_USB_PHY0]		= RESET(0x0cc, BIT(0)),
 
 	[RST_BUS_OTG]		= RESET(0x2c0, BIT(24)),
+
+	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
+	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
 };
 
 static const struct ccu_desc v3s_ccu_desc = {

Jagan Teki

author

2019-01-10 18:40 UTC #15 lore raw

PATCH v6 13/20 clk: sunxi: Add Allwinner H6 CLK driver

Add initial clock driver for Allwinner H6.

- Implement UART bus clocks via ccu_clk_gate table for H6, so it can accessed in common clk enable and disable functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for H6, so it can accessed in common reset deassert and assert functions from reset-sunxi.c

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/clk/sunxi/Kconfig  |  7 +++++
 drivers/clk/sunxi/Makefile |  1 +
 drivers/clk/sunxi/clk_h6.c | 53 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 61 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk_h6.c

drivers/clk/sunxi/Kconfig +7 -0

index a6f84e9e56..cb11c7c21e 100644
@@ -65,6 +65,13 @@ config CLK_SUN8I_H3
 	  This enables common clock driver support for platforms based
 	  on Allwinner H3/H5 SoC.
 
+config CLK_SUN50I_H6
+	bool "Clock driver for Allwinner H6"
+	default MACH_SUN50I_H6
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner H6 SoC.
+
 config CLK_SUN50I_A64
 	bool "Clock driver for Allwinner A64"
 	default MACH_SUN50I

drivers/clk/sunxi/Makefile +1 -0

index fbd43527a6..794aa2461c 100644
@@ -14,4 +14,5 @@ obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
 obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
 obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o
 obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
+obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o

drivers/clk/sunxi/clk_h6.c new file +53 -0

53 lines not on this page · raw message

Signature · 1 line

2.18.0.321.gffc6fa0e3

André Przywara

2019-01-10 23:55 UTC #16 lore raw

PATCH v6 13/20 clk: sunxi: Add Allwinner H6 CLK driver

Quoted 10 lines · Jagan Teki

Add initial clock driver for Allwinner H6.
- Implement UART bus clocks via ccu_clk_gate table for H6, so it can accessed in common clk enable and disable functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for H6, so it can accessed in common reset deassert and assert functions from reset-sunxi.c
Signed-off-by Jagan Teki <[email protected]>

Compared against the manual, boot tested on Pine H64.

Cheers,
Andre.

Quoted 95 lines

---
 drivers/clk/sunxi/Kconfig  |  7 +++++
 drivers/clk/sunxi/Makefile |  1 +
 drivers/clk/sunxi/clk_h6.c | 53 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 61 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk_h6.c

drivers/clk/sunxi/Kconfig +7 -0

index a6f84e9e56..cb11c7c21e 100644
@@ -65,6 +65,13 @@ config CLK_SUN8I_H3
 	  This enables common clock driver support for platforms based
 	  on Allwinner H3/H5 SoC.
 
+config CLK_SUN50I_H6
+	bool "Clock driver for Allwinner H6"
+	default MACH_SUN50I_H6
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner H6 SoC.
+
 config CLK_SUN50I_A64
 	bool "Clock driver for Allwinner A64"
 	default MACH_SUN50I

drivers/clk/sunxi/Makefile +1 -0

index fbd43527a6..794aa2461c 100644
@@ -14,4 +14,5 @@ obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
 obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
 obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o
 obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
+obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o

drivers/clk/sunxi/clk_h6.c new file +53 -0

new file mode 100644
index 0000000000..0da3a40e3d
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions.
+ * Author: Jagan Teki <[email protected]>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/arch/ccu.h>
+#include <dt-bindings/clock/sun50i-h6-ccu.h>
+#include <dt-bindings/reset/sun50i-h6-ccu.h>
+
+static struct ccu_clk_gate h6_gates[] = {
+	[CLK_BUS_UART0]		= GATE(0x90c, BIT(0)),
+	[CLK_BUS_UART1]		= GATE(0x90c, BIT(1)),
+	[CLK_BUS_UART2]		= GATE(0x90c, BIT(2)),
+	[CLK_BUS_UART3]		= GATE(0x90c, BIT(3)),
+};
+
+static struct ccu_reset h6_resets[] = {
+	[RST_BUS_UART0]		= RESET(0x90c, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x90c, BIT(17)),
+	[RST_BUS_UART2]		= RESET(0x90c, BIT(18)),
+	[RST_BUS_UART3]		= RESET(0x90c, BIT(19)),
+};
+
+static const struct ccu_desc h6_ccu_desc = {
+	.gates = h6_gates,
+	.resets = h6_resets,
+};
+
+static int h6_clk_bind(struct udevice *dev)
+{
+	return sunxi_reset_bind(dev, ARRAY_SIZE(h6_resets));
+}
+
+static const struct udevice_id h6_ccu_ids[] = {
+	{ .compatible = "allwinner,sun50i-h6-ccu",
+	  .data = (ulong)&h6_ccu_desc },
+	{ }
+};
+
+U_BOOT_DRIVER(clk_sun50i_h6) = {
+	.name		= "sun50i_h6_ccu",
+	.id		= UCLASS_CLK,
+	.of_match	= h6_ccu_ids,
+	.priv_auto_alloc_size	= sizeof(struct ccu_priv),
+	.ops		= &sunxi_clk_ops,
+	.probe		= sunxi_clk_probe,
+	.bind		= h6_clk_bind,
+};

Jagan Teki

author

2019-01-10 18:40 UTC #17 lore raw

PATCH v6 14/20 sunxi: A64: Update sun50i-a64-ccu.h

Update sun50i-a64-ccu.h from the Linux sunxi/dt64-for-4.20 tree:
commit 679294497be31596e1c9c61507746d72b6b05f26

Author: Rodrigo Exterckötter Tjäder <[email protected]>
Date:   Wed Sep 26 19:48:24 2018 +0000

arm64: dts: allwinner: a64: a64-olinuxino: set the PHY TX delay

This should be a part of previous sync patch from
commit 1b39a1834ed182bbd8036a5cd74a9ea111fa4691

Author: Andre Przywara <[email protected]>
Date:   Mon Oct 29 00:56:47 2018 +0000

sunxi: A64: Update .dts/.dtsi files

Signed-off-by Jagan Teki <[email protected]>

---
 include/dt-bindings/clock/sun50i-a64-ccu.h | 2 ++
 1 file changed, 2 insertions(+)

include/dt-bindings/clock/sun50i-a64-ccu.h +2 -0

index 370c0a0473..d66432c6e6 100644
@@ -43,6 +43,8 @@
 #ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_
 #define _DT_BINDINGS_CLK_SUN50I_A64_H_
 
+#define CLK_PLL_PERIPH0		11
+
 #define CLK_BUS_MIPI_DSI	28
 #define CLK_BUS_CE		29
 #define CLK_BUS_DMA		30

Signature · 1 line

2.18.0.321.gffc6fa0e3

André Przywara

2019-01-10 23:58 UTC #18 lore raw

PATCH v6 14/20 sunxi: A64: Update sun50i-a64-ccu.h

Quoted 6 lines · Jagan Teki

Update sun50i-a64-ccu.h from the Linux sunxi/dt64-for-4.20 tree:
commit 679294497be31596e1c9c61507746d72b6b05f26
Author: Rodrigo Exterckötter Tjäder <[email protected]>
Date:   Wed Sep 26 19:48:24 2018 +0000
arm64: dts: allwinner: a64: a64-olinuxino: set the PHY TX delay

Quoted 8 lines

This should be a part of previous sync patch from
commit 1b39a1834ed182bbd8036a5cd74a9ea111fa4691
Author: Andre Przywara <[email protected]>
Date:   Mon Oct 29 00:56:47 2018 +0000
sunxi: A64: Update .dts/.dtsi files
Signed-off-by Jagan Teki <[email protected]>

Cheers,
Andre.

Quoted 18 lines

---
 include/dt-bindings/clock/sun50i-a64-ccu.h | 2 ++
 1 file changed, 2 insertions(+)

include/dt-bindings/clock/sun50i-a64-ccu.h +2 -0

index 370c0a0473..d66432c6e6 100644
@@ -43,6 +43,8 @@
 #ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_
 #define _DT_BINDINGS_CLK_SUN50I_A64_H_
 
+#define CLK_PLL_PERIPH0		11
+
 #define CLK_BUS_MIPI_DSI	28
 #define CLK_BUS_CE		29
 #define CLK_BUS_DMA		30

Jagan Teki

author

2019-01-10 18:40 UTC #19 lore raw

PATCH v6 15/20 sunxi: Enable CLK

CLK and DM_RESET drivers are now available for most of the Allwinner platforms, so enable in mach-sunxi/Kconfig

Enabling CLK will select DM_RESET by default.

Signed-off-by Jagan Teki <[email protected]>

---
 arch/arm/mach-sunxi/Kconfig | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/arm/mach-sunxi/Kconfig +12 -0

index 3c54f5106d..5f51bbbed0 100644
@@ -132,6 +132,7 @@ endif
 
 config MACH_SUNXI_H3_H5
 	bool
+	select CLK
 	select DM_I2C
 	select PHY_SUN4I_USB
 	select SUNXI_DE2

@@ -154,6 +155,7 @@ config MACH_SUN4I
 	bool "sun4i (Allwinner A10)"
 	select CPU_V7A
 	select ARM_CORTEX_CPU_IS_UP
+	select CLK
 	select DM_MMC if MMC
 	select DM_SCSI if SCSI
 	select PHY_SUN4I_USB

@@ -165,6 +167,7 @@ config MACH_SUN5I
 	bool "sun5i (Allwinner A13)"
 	select CPU_V7A
 	select ARM_CORTEX_CPU_IS_UP
+	select CLK
 	select DRAM_SUN4I
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN4I

@@ -177,6 +180,7 @@ config MACH_SUN6I
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
+	select CLK
 	select DRAM_SUN6I
 	select PHY_SUN4I_USB
 	select SUN6I_P2WI

@@ -191,6 +195,7 @@ config MACH_SUN7I
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
+	select CLK
 	select DRAM_SUN4I
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN4I

@@ -203,6 +208,7 @@ config MACH_SUN8I_A23
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
+	select CLK
 	select DRAM_SUN8I_A23
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN6I

@@ -216,6 +222,7 @@ config MACH_SUN8I_A33
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
+	select CLK
 	select DRAM_SUN8I_A33
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN6I

@@ -226,6 +233,7 @@ config MACH_SUN8I_A33
 config MACH_SUN8I_A83T
 	bool "sun8i (Allwinner A83T)"
 	select CPU_V7A
+	select CLK
 	select DRAM_SUN8I_A83T
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN6I

@@ -248,6 +256,7 @@ config MACH_SUN8I_R40
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
+	select CLK
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
 	select SUNXI_DRAM_DW

@@ -259,6 +268,7 @@ config MACH_SUN8I_V3S
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
+	select CLK
 	select SUNXI_GEN_SUN6I
 	select SUNXI_DRAM_DW
 	select SUNXI_DRAM_DW_16BIT

@@ -277,6 +287,7 @@ config MACH_SUN9I
 config MACH_SUN50I
 	bool "sun50i (Allwinner A64)"
 	select ARM64
+	select CLK
 	select DM_I2C
 	select PHY_SUN4I_USB
 	select SUN6I_PRCM

@@ -300,6 +311,7 @@ config MACH_SUN50I_H5
 config MACH_SUN50I_H6
 	bool "sun50i (Allwinner H6)"
 	select ARM64
+	select CLK
 	select SUPPORT_SPL
 	select FIT
 	select SPL_LOAD_FIT

Signature · 1 line

2.18.0.321.gffc6fa0e3

André Przywara

2019-01-11 00:09 UTC #20 lore raw

PATCH v6 15/20 sunxi: Enable CLK

Quoted 4 lines · Jagan Teki

CLK and DM_RESET drivers are now available for most of the Allwinner platforms, so enable in mach-sunxi/Kconfig
Enabling CLK will select DM_RESET by default.

Shame we don't have the new A80 DTs in our tree, otherwise we would have got away with a one-liner instead ...

Quoted 1 line

Signed-off-by Jagan Teki <[email protected]>

Cheers,
Andre.

Quoted 105 lines

---
 arch/arm/mach-sunxi/Kconfig | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/arm/mach-sunxi/Kconfig +12 -0

index 3c54f5106d..5f51bbbed0 100644
@@ -132,6 +132,7 @@ endif
 
 config MACH_SUNXI_H3_H5
 	bool
+	select CLK
 	select DM_I2C
 	select PHY_SUN4I_USB
 	select SUNXI_DE2

@@ -154,6 +155,7 @@ config MACH_SUN4I
 	bool "sun4i (Allwinner A10)"
 	select CPU_V7A
 	select ARM_CORTEX_CPU_IS_UP
+	select CLK
 	select DM_MMC if MMC
 	select DM_SCSI if SCSI
 	select PHY_SUN4I_USB

@@ -165,6 +167,7 @@ config MACH_SUN5I
 	bool "sun5i (Allwinner A13)"
 	select CPU_V7A
 	select ARM_CORTEX_CPU_IS_UP
+	select CLK
 	select DRAM_SUN4I
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN4I

@@ -177,6 +180,7 @@ config MACH_SUN6I
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
+	select CLK
 	select DRAM_SUN6I
 	select PHY_SUN4I_USB
 	select SUN6I_P2WI

@@ -191,6 +195,7 @@ config MACH_SUN7I
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
+	select CLK
 	select DRAM_SUN4I
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN4I

@@ -203,6 +208,7 @@ config MACH_SUN8I_A23
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
+	select CLK
 	select DRAM_SUN8I_A23
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN6I

@@ -216,6 +222,7 @@ config MACH_SUN8I_A33
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
+	select CLK
 	select DRAM_SUN8I_A33
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN6I

@@ -226,6 +233,7 @@ config MACH_SUN8I_A33
 config MACH_SUN8I_A83T
 	bool "sun8i (Allwinner A83T)"
 	select CPU_V7A
+	select CLK
 	select DRAM_SUN8I_A83T
 	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN6I

@@ -248,6 +256,7 @@ config MACH_SUN8I_R40
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
+	select CLK
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
 	select SUNXI_DRAM_DW

@@ -259,6 +268,7 @@ config MACH_SUN8I_V3S
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
+	select CLK
 	select SUNXI_GEN_SUN6I
 	select SUNXI_DRAM_DW
 	select SUNXI_DRAM_DW_16BIT

@@ -277,6 +287,7 @@ config MACH_SUN9I
 config MACH_SUN50I
 	bool "sun50i (Allwinner A64)"
 	select ARM64
+	select CLK
 	select DM_I2C
 	select PHY_SUN4I_USB
 	select SUN6I_PRCM

@@ -300,6 +311,7 @@ config MACH_SUN50I_H5
 config MACH_SUN50I_H6
 	bool "sun50i (Allwinner H6)"
 	select ARM64
+	select CLK
 	select SUPPORT_SPL
 	select FIT
 	select SPL_LOAD_FIT

Jagan Teki

author

2019-01-10 18:40 UTC #21 lore raw

PATCH v6 16/20 phy: sun4i-usb: Use CLK and RESET support

Now clock and reset drivers are available for respective SoC's so use clk and reset ops on phy driver.

Signed-off-by Jagan Teki <[email protected]>

Reviewed-by Marek Vasut <[email protected]>

---
 drivers/phy/allwinner/phy-sun4i-usb.c | 77 ++++++++++++++++++++-------
 1 file changed, 57 insertions(+), 20 deletions(-)

drivers/phy/allwinner/phy-sun4i-usb.c +57 ~~-20~~

index a7d7e3f044..f206fa3f5d 100644
@@ -11,10 +11,12 @@
  */
 
 #include <common.h>
+#include <clk.h>
 #include <dm.h>
 #include <dm/device.h>
 #include <generic-phy.h>
 #include <phy-sun4i-usb.h>
+#include <reset.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>

@@ -80,6 +82,7 @@ struct sun4i_usb_phy_cfg {
 	enum sun4i_usb_phy_type type;
 	u32 disc_thresh;
 	u8 phyctl_offset;
+	bool dedicated_clocks;
 	bool enable_pmu_unk1;
 	bool phy0_dual_route;
 };

@@ -88,30 +91,21 @@ struct sun4i_usb_phy_info {
 	const char *gpio_vbus;
 	const char *gpio_vbus_det;
 	const char *gpio_id_det;
-	int rst_mask;
 } phy_info[] = {
 	{
 		.gpio_vbus = CONFIG_USB0_VBUS_PIN,
 		.gpio_vbus_det = CONFIG_USB0_VBUS_DET,
 		.gpio_id_det = CONFIG_USB0_ID_DET,
-		.rst_mask = (CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK),
 	},
 	{
 		.gpio_vbus = CONFIG_USB1_VBUS_PIN,
 		.gpio_vbus_det = NULL,
 		.gpio_id_det = NULL,
-		.rst_mask = (CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK),
 	},
 	{
 		.gpio_vbus = CONFIG_USB2_VBUS_PIN,
 		.gpio_vbus_det = NULL,
 		.gpio_id_det = NULL,
-#ifdef CONFIG_MACH_SUN8I_A83T
-		.rst_mask = (CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK |
-			     CCM_USB_CTRL_12M_CLK),
-#else
-		.rst_mask = (CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK),
-#endif
 	},
 	{
 		.gpio_vbus = CONFIG_USB3_VBUS_PIN,

@@ -126,13 +120,13 @@ struct sun4i_usb_phy_plat {
 	int gpio_vbus;
 	int gpio_vbus_det;
 	int gpio_id_det;
-	int rst_mask;
+	struct clk clocks;
+	struct reset_ctl resets;
 	int id;
 };
 
 struct sun4i_usb_phy_data {
 	void __iomem *base;
-	struct sunxi_ccm_reg *ccm;
 	const struct sun4i_usb_phy_cfg *cfg;
 	struct sun4i_usb_phy_plat *usb_phy;
 };

@@ -266,8 +260,19 @@ static int sun4i_usb_phy_init(struct phy *phy)
 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 	u32 val;
+	int ret;
 
-	setbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask);
+	ret = clk_enable(&usb_phy->clocks);
+	if (ret) {
+		dev_err(dev, "failed to enable usb_%ldphy clock\n", phy->id);
+		return ret;
+	}
+
+	ret = reset_deassert(&usb_phy->resets);
+	if (ret) {
+		dev_err(dev, "failed to deassert usb_%ldreset reset\n", phy->id);
+		return ret;
+	}
 
 	if (data->cfg->type == sun8i_a83t_phy) {
 		if (phy->id == 0) {

@@ -308,6 +313,7 @@ static int sun4i_usb_phy_exit(struct phy *phy)
 {
 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
+	int ret;
 
 	if (phy->id == 0) {
 		if (data->cfg->type == sun8i_a83t_phy) {

@@ -320,7 +326,17 @@ static int sun4i_usb_phy_exit(struct phy *phy)
 
 	sun4i_usb_phy_passby(phy, false);
 
-	clrbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask);
+	ret = clk_disable(&usb_phy->clocks);
+	if (ret) {
+		dev_err(dev, "failed to disable usb_%ldphy clock\n", phy->id);
+		return ret;
+	}
+
+	ret = reset_assert(&usb_phy->resets);
+	if (ret) {
+		dev_err(dev, "failed to assert usb_%ldreset reset\n", phy->id);
+		return ret;
+	}
 
 	return 0;
 }

@@ -407,10 +423,6 @@ static int sun4i_usb_phy_probe(struct udevice *dev)
 	if (IS_ERR(data->base))
 		return PTR_ERR(data->base);
 
-	data->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-	if (IS_ERR(data->ccm))
-		return PTR_ERR(data->ccm);
-
 	data->usb_phy = plat;
 	for (i = 0; i < data->cfg->num_phys; i++) {
 		struct sun4i_usb_phy_plat *phy = &plat[i];

@@ -448,6 +460,24 @@ static int sun4i_usb_phy_probe(struct udevice *dev)
 			sunxi_gpio_set_pull(phy->gpio_id_det, SUNXI_GPIO_PULL_UP);
 		}
 
+		if (data->cfg->dedicated_clocks)
+			snprintf(name, sizeof(name), "usb%d_phy", i);
+		else
+			strlcpy(name, "usb_phy", sizeof(name));
+
+		ret = clk_get_by_name(dev, name, &phy->clocks);
+		if (ret) {
+			dev_err(dev, "failed to get usb%d_phy clock phandle\n", i);
+			return ret;
+		}
+
+		snprintf(name, sizeof(name), "usb%d_reset", i);
+		ret = reset_get_by_name(dev, name, &phy->resets);
+		if (ret) {
+			dev_err(dev, "failed to get usb%d_reset reset phandle\n", i);
+			return ret;
+		}
+
 		if (i || data->cfg->phy0_dual_route) {
 			snprintf(name, sizeof(name), "pmu%d", i);
 			phy->pmu = (void __iomem *)devfdt_get_addr_name(dev, name);

@@ -456,9 +486,6 @@ static int sun4i_usb_phy_probe(struct udevice *dev)
 		}
 
 		phy->id = i;
-		phy->rst_mask = info->rst_mask;
-		if ((data->cfg->type == sun8i_h3_phy) && (phy->id == 3))
-			phy->rst_mask = (BIT(3) | BIT(11));
 	};
 
 	debug("Allwinner Sun4I USB PHY driver loaded\n");

@@ -470,6 +497,7 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
 	.type = sun4i_a10_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A10,
+	.dedicated_clocks = false,
 	.enable_pmu_unk1 = false,
 };

@@ -478,6 +506,7 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
 	.type = sun4i_a10_phy,
 	.disc_thresh = 2,
 	.phyctl_offset = REG_PHYCTL_A10,
+	.dedicated_clocks = false,
 	.enable_pmu_unk1 = false,
 };

@@ -486,6 +515,7 @@ static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
 	.type = sun6i_a31_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A10,
+	.dedicated_clocks = true,
 	.enable_pmu_unk1 = false,
 };

@@ -494,6 +524,7 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
 	.type = sun4i_a10_phy,
 	.disc_thresh = 2,
 	.phyctl_offset = REG_PHYCTL_A10,
+	.dedicated_clocks = false,
 	.enable_pmu_unk1 = false,
 };

@@ -502,6 +533,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
 	.type = sun4i_a10_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A10,
+	.dedicated_clocks = true,
 	.enable_pmu_unk1 = false,
 };

@@ -510,6 +542,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
 	.type = sun8i_a33_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
 	.enable_pmu_unk1 = false,
 };

@@ -517,6 +550,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
 	.num_phys = 3,
 	.type = sun8i_a83t_phy,
 	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
 };
 
 static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {

@@ -524,6 +558,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
 	.type = sun8i_h3_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
 	.enable_pmu_unk1 = true,
 	.phy0_dual_route = true,
 };

@@ -533,6 +568,7 @@ static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
 	.type = sun8i_v3s_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
 	.enable_pmu_unk1 = true,
 	.phy0_dual_route = true,
 };

@@ -542,6 +578,7 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 	.type = sun50i_a64_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
 	.enable_pmu_unk1 = true,
 	.phy0_dual_route = true,
 };

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2019-01-10 18:40 UTC #22 lore raw

PATCH v6 17/20 reset: Add reset valid

Add reset_valid to check whether given reset is valid or not.

Cc Simon Glass <[email protected]>

Signed-off-by Jagan Teki <[email protected]>

---
 include/reset.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

include/reset.h +11 -0

index bc495a90c2..65aa7a4ce5 100644
@@ -306,4 +306,15 @@ static inline int reset_release_bulk(struct reset_ctl_bulk *bulk)
 }
 #endif
 
+/**
+ * reset_valid() - check if reset is valid
+ *
+ * @reset_ctl:		the reset to check
+ * @return TRUE if valid, or FALSE
+ */
+static inline bool reset_valid(struct reset_ctl *reset_ctl)
+{
+	return !!reset_ctl->dev;
+}
+
 #endif

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2019-01-10 18:40 UTC #23 lore raw

PATCH v6 18/20 musb-new: sunxi: Use CLK and RESET support

Now clock and reset drivers are available for respective SoC's so use clk and reset ops on musb driver.

Signed-off-by Jagan Teki <[email protected]>

Reviewed-by Marek Vasut <[email protected]>

---
 drivers/usb/musb-new/sunxi.c | 79 ++++++++++++++++++------------------
 1 file changed, 39 insertions(+), 40 deletions(-)

drivers/usb/musb-new/sunxi.c +39 ~~-40~~

index f3deb9bc66..906c08ece9 100644
@@ -16,9 +16,11 @@
  * This file is part of the Inventra Controller Driver for Linux.
  */
 #include <common.h>
+#include <clk.h>
 #include <dm.h>
 #include <generic-phy.h>
 #include <phy-sun4i-usb.h>
+#include <reset.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>

@@ -80,16 +82,12 @@
 
 struct sunxi_musb_config {
 	struct musb_hdrc_config *config;
-	bool has_reset;
-	u8 rst_bit;
-	u8 clkgate_bit;
-	u32 off_reset0;
 };
 
 struct sunxi_glue {
 	struct musb_host_data mdata;
-	struct sunxi_ccm_reg *ccm;
-	u32 *reg_reset0;
+	struct clk clk;
+	struct reset_ctl rst;
 	struct sunxi_musb_config *cfg;
 	struct device dev;
 	struct phy phy;

@@ -296,24 +294,27 @@ static int sunxi_musb_init(struct musb *musb)
 
 	pr_debug("%s():\n", __func__);
 
-	ret = generic_phy_init(&glue->phy);
+	ret = clk_enable(&glue->clk);
 	if (ret) {
-		pr_err("failed to init USB PHY\n");
+		dev_err(dev, "failed to enable clock\n");
 		return ret;
 	}
 
-	musb->isr = sunxi_musb_interrupt;
-
-	setbits_le32(&glue->ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_USB0));
-	if (glue->cfg->clkgate_bit)
-		setbits_le32(&glue->ccm->ahb_gate0,
-			     BIT(glue->cfg->clkgate_bit));
+	if (reset_valid(&glue->rst)) {
+		ret = reset_deassert(&glue->rst);
+		if (ret) {
+			dev_err(dev, "failed to deassert reset\n");
+			goto err_clk;
+		}
+	}
 
-	if (glue->cfg->has_reset)
-		setbits_le32(glue->reg_reset0, BIT(AHB_GATE_OFFSET_USB0));
+	ret = generic_phy_init(&glue->phy);
+	if (ret) {
+		dev_err(dev, "failed to init USB PHY\n");
+		goto err_rst;
+	}
 
-	if (glue->cfg->rst_bit)
-		setbits_le32(glue->reg_reset0, BIT(glue->cfg->rst_bit));
+	musb->isr = sunxi_musb_interrupt;
 
 	USBC_ConfigFIFO_Base();
 	USBC_EnableDpDmPullUp(musb->mregs);

@@ -329,6 +330,13 @@ static int sunxi_musb_init(struct musb *musb)
 	USBC_ForceVbusValidToHigh(musb->mregs);
 
 	return 0;
+
+err_rst:
+	if (reset_valid(&glue->rst))
+		reset_assert(&glue->rst);
+err_clk:
+	clk_disable(&glue->clk);
+	return ret;
 }
 
 static int sunxi_musb_exit(struct musb *musb)

@@ -344,16 +352,9 @@ static int sunxi_musb_exit(struct musb *musb)
 		}
 	}
 
-	if (glue->cfg->has_reset)
-		clrbits_le32(glue->reg_reset0, BIT(AHB_GATE_OFFSET_USB0));
-
-	if (glue->cfg->rst_bit)
-		clrbits_le32(glue->reg_reset0, BIT(glue->cfg->rst_bit));
-
-	clrbits_le32(&glue->ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_USB0));
-	if (glue->cfg->clkgate_bit)
-		clrbits_le32(&glue->ccm->ahb_gate0,
-			     BIT(glue->cfg->clkgate_bit));
+	if (reset_valid(&glue->rst))
+		reset_assert(&glue->rst);
+	clk_disable(&glue->clk);
 
 	return 0;
 }

@@ -450,11 +451,17 @@ static int musb_usb_probe(struct udevice *dev)
 	if (!glue->cfg)
 		return -EINVAL;
 
-	glue->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-	if (IS_ERR(glue->ccm))
-		return PTR_ERR(glue->ccm);
+	ret = clk_get_by_index(dev, 0, &glue->clk);
+	if (ret) {
+		dev_err(dev, "failed to get clock\n");
+		return ret;
+	}
 
-	glue->reg_reset0 = (void *)glue->ccm + glue->cfg->off_reset0;
+	ret = reset_get_by_index(dev, 0, &glue->rst);
+	if (ret && ret != -ENOENT) {
+		dev_err(dev, "failed to get reset\n");
+		return ret;
+	}
 
 	ret = generic_phy_get_by_name(dev, "usb", &glue->phy);
 	if (ret) {

@@ -462,7 +469,6 @@ static int musb_usb_probe(struct udevice *dev)
 		return ret;
 	}
 
-
 	memset(&pdata, 0, sizeof(pdata));
 	pdata.power = 250;
 	pdata.platform_ops = &sunxi_musb_ops;

@@ -505,21 +511,14 @@ static int musb_usb_remove(struct udevice *dev)
 
 static const struct sunxi_musb_config sun4i_a10_cfg = {
 	.config = &musb_config,
-	.has_reset = false,
 };
 
 static const struct sunxi_musb_config sun6i_a31_cfg = {
 	.config = &musb_config,
-	.has_reset = true,
-	.off_reset0 = OFF_SUN6I_AHB_RESET0,
 };
 
 static const struct sunxi_musb_config sun8i_h3_cfg = {
 	.config = &musb_config_h3,
-	.has_reset = true,
-	.rst_bit = 23,
-	.clkgate_bit = 23,
-	.off_reset0 = OFF_SUN6I_AHB_RESET0,
 };
 
 static const struct udevice_id sunxi_musb_ids[] = {

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2019-01-10 18:40 UTC #24 lore raw

PATCH v6 19/20 sunxi: usb: Switch to Generic host controllers

Onc of key blocker for using USB Generic host controller drivers in Allwinner are CLK and RESET drivers, now these available for USB usage.

So switch sunxi USB use EHCI and OHCI Generic controllers.

Enabling USB is wisely a board choise, So Enable USB_OHCI_HCD where it already have USB_EHCI_HCD

Signed-off-by Jagan Teki <[email protected]>

---
 configs/A10-OLinuXino-Lime_defconfig          | 1 +
 configs/A10s-OLinuXino-M_defconfig            | 1 +
 configs/A13-OLinuXinoM_defconfig              | 1 +
 configs/A13-OLinuXino_defconfig               | 1 +
 configs/A20-OLinuXino-Lime2-eMMC_defconfig    | 1 +
 configs/A20-OLinuXino-Lime2_defconfig         | 1 +
 configs/A20-OLinuXino-Lime_defconfig          | 1 +
 configs/A20-OLinuXino_MICRO-eMMC_defconfig    | 1 +
 configs/A20-OLinuXino_MICRO_defconfig         | 1 +
 configs/A20-Olimex-SOM-EVB_defconfig          | 1 +
 configs/A20-Olimex-SOM204-EVB-eMMC_defconfig  | 1 +
 configs/A20-Olimex-SOM204-EVB_defconfig       | 1 +
 configs/Auxtek-T003_defconfig                 | 1 +
 configs/Auxtek-T004_defconfig                 | 1 +
 configs/Bananapi_defconfig                    | 1 +
 configs/Bananapi_m2m_defconfig                | 1 +
 configs/Bananapro_defconfig                   | 1 +
 configs/CHIP_defconfig                        | 1 +
 configs/CHIP_pro_defconfig                    | 1 +
 configs/CSQ_CS908_defconfig                   | 1 +
 configs/Colombus_defconfig                    | 1 +
 configs/Cubieboard2_defconfig                 | 1 +
 configs/Cubieboard_defconfig                  | 1 +
 configs/Cubietruck_defconfig                  | 1 +
 configs/Cubietruck_plus_defconfig             | 1 +
 configs/Hummingbird_A31_defconfig             | 1 +
 configs/Itead_Ibox_A20_defconfig              | 1 +
 configs/Lamobo_R1_defconfig                   | 1 +
 configs/Linksprite_pcDuino3_Nano_defconfig    | 1 +
 configs/Linksprite_pcDuino3_defconfig         | 1 +
 configs/Linksprite_pcDuino_defconfig          | 1 +
 configs/MK808C_defconfig                      | 1 +
 configs/Marsboard_A10_defconfig               | 1 +
 configs/Mele_A1000G_quad_defconfig            | 1 +
 configs/Mele_A1000_defconfig                  | 1 +
 configs/Mele_I7_defconfig                     | 1 +
 configs/Mele_M3_defconfig                     | 1 +
 configs/Mele_M5_defconfig                     | 1 +
 configs/Mele_M9_defconfig                     | 1 +
 configs/Mini-X_defconfig                      | 1 +
 configs/Orangepi_defconfig                    | 1 +
 configs/Orangepi_mini_defconfig               | 1 +
 configs/Sinlinx_SinA31s_defconfig             | 1 +
 configs/Sinlinx_SinA33_defconfig              | 1 +
 configs/Sinovoip_BPI_M2_Plus_defconfig        | 1 +
 configs/Sinovoip_BPI_M2_defconfig             | 1 +
 configs/Sinovoip_BPI_M3_defconfig             | 1 +
 configs/Wexler_TAB7200_defconfig              | 1 +
 configs/Wits_Pro_A20_DKT_defconfig            | 1 +
 configs/Wobo_i5_defconfig                     | 1 +
 configs/a64-olinuxino_defconfig               | 1 +
 configs/ba10_tv_box_defconfig                 | 1 +
 configs/bananapi_m1_plus_defconfig            | 1 +
 configs/bananapi_m64_defconfig                | 1 +
 configs/ga10h_v1_1_defconfig                  | 1 +
 configs/h8_homlet_v2_defconfig                | 1 +
 configs/i12-tvbox_defconfig                   | 1 +
 configs/icnova-a20-swac_defconfig             | 1 +
 configs/inet1_defconfig                       | 1 +
 configs/inet_q972_defconfig                   | 1 +
 configs/jesurun_q5_defconfig                  | 1 +
 configs/libretech_all_h3_cc_h2_plus_defconfig | 1 +
 configs/libretech_all_h3_cc_h3_defconfig      | 1 +
 configs/libretech_all_h3_cc_h5_defconfig      | 1 +
 configs/mixtile_loftq_defconfig               | 1 +
 configs/mk802_a10s_defconfig                  | 1 +
 configs/mk802_defconfig                       | 1 +
 configs/mk802ii_defconfig                     | 1 +
 configs/nanopi_a64_defconfig                  | 1 +
 configs/nanopi_m1_defconfig                   | 1 +
 configs/nanopi_m1_plus_defconfig              | 1 +
 configs/nanopi_neo2_defconfig                 | 1 +
 configs/nanopi_neo_air_defconfig              | 1 +
 configs/nanopi_neo_defconfig                  | 1 +
 configs/nanopi_neo_plus2_defconfig            | 1 +
 configs/orangepi_2_defconfig                  | 1 +
 configs/orangepi_lite_defconfig               | 1 +
 configs/orangepi_one_defconfig                | 1 +
 configs/orangepi_pc2_defconfig                | 1 +
 configs/orangepi_pc_defconfig                 | 1 +
 configs/orangepi_pc_plus_defconfig            | 1 +
 configs/orangepi_plus2e_defconfig             | 1 +
 configs/orangepi_plus_defconfig               | 1 +
 configs/orangepi_prime_defconfig              | 1 +
 configs/orangepi_r1_defconfig                 | 1 +
 configs/orangepi_win_defconfig                | 1 +
 configs/orangepi_zero_defconfig               | 1 +
 configs/orangepi_zero_plus2_defconfig         | 1 +
 configs/orangepi_zero_plus_defconfig          | 1 +
 configs/parrot_r16_defconfig                  | 1 +
 configs/pine64_plus_defconfig                 | 1 +
 configs/pinebook_defconfig                    | 1 +
 configs/r7-tv-dongle_defconfig                | 1 +
 configs/sopine_baseboard_defconfig            | 1 +
 configs/sun8i_a23_evb_defconfig               | 1 +
 configs/sunxi_Gemei_G9_defconfig              | 1 +
 configs/tbs_a711_defconfig                    | 1 +
 drivers/usb/host/Kconfig                      | 2 ++
 include/configs/sun4i.h                       | 4 ----
 include/configs/sun50i.h                      | 5 -----
 include/configs/sun5i.h                       | 4 ----
 include/configs/sun6i.h                       | 4 ----
 include/configs/sun7i.h                       | 4 ----
 include/configs/sun8i.h                       | 4 ----
 include/configs/sunxi-common.h                | 1 -
 105 files changed, 99 insertions(+), 26 deletions(-)

configs/A10-OLinuXino-Lime_defconfig +1 -0

index 55134a9002..9b8891eed5 100644
@@ -22,5 +22,6 @@ CONFIG_SUN4I_EMAC=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/A10s-OLinuXino-M_defconfig +1 -0

index d0fb4d7860..fcf4890c3a 100644
@@ -18,5 +18,6 @@ CONFIG_MII=y
 CONFIG_SUN4I_EMAC=y
 CONFIG_AXP152_POWER=y
 CONFIG_CONS_INDEX=2
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/A13-OLinuXinoM_defconfig +1 -0

index 88374551e3..aedb0c3f0a 100644
@@ -19,5 +19,6 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino-micro"
 CONFIG_SUNXI_NO_PMIC=y
 CONFIG_CONS_INDEX=2
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/A13-OLinuXino_defconfig +1 -0

index 7b836ddf9c..eb76bf8fea 100644
@@ -26,6 +26,7 @@ CONFIG_DFU_RAM=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_CONS_INDEX=2
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/A20-OLinuXino-Lime2-eMMC_defconfig +1 -0

index 3e9f57446c..d74afd5959 100644
@@ -31,6 +31,7 @@ CONFIG_AXP_ALDO3_VOLT_SLOPE_08=y
 CONFIG_AXP_ALDO3_INRUSH_QUIRK=y
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/A20-OLinuXino-Lime2_defconfig +1 -0

index e7ca33576a..a10cc0bd97 100644
@@ -30,6 +30,7 @@ CONFIG_AXP_ALDO3_VOLT_SLOPE_08=y
 CONFIG_AXP_ALDO3_INRUSH_QUIRK=y
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/A20-OLinuXino-Lime_defconfig +1 -0

index 91f5210762..9e13792f1a 100644
@@ -21,5 +21,6 @@ CONFIG_SUN7I_GMAC=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/A20-OLinuXino_MICRO-eMMC_defconfig +1 -0

index 20964c5546..73e6f7c4e0 100644
@@ -24,5 +24,6 @@ CONFIG_SUN7I_GMAC_FORCE_TXERR=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/A20-OLinuXino_MICRO_defconfig +1 -0

index cf9bf3347b..bd68511d6b 100644
@@ -25,5 +25,6 @@ CONFIG_SUN7I_GMAC_FORCE_TXERR=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/A20-Olimex-SOM-EVB_defconfig +1 -0

index a31f96ce14..c38025a9c2 100644
@@ -26,5 +26,6 @@ CONFIG_SUN7I_GMAC=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/A20-Olimex-SOM204-EVB-eMMC_defconfig +1 -0

index c9e9475215..778c2ee72b 100644
@@ -30,6 +30,7 @@ CONFIG_SUN7I_GMAC=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/A20-Olimex-SOM204-EVB_defconfig +1 -0

index 1181832b2e..e853c9301c 100644
@@ -29,6 +29,7 @@ CONFIG_SUN7I_GMAC=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Auxtek-T003_defconfig +1 -0

index a693cfdd41..c2a681c569 100644
@@ -15,5 +15,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t003"
 CONFIG_AXP152_POWER=y
 CONFIG_CONS_INDEX=2
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Auxtek-T004_defconfig +1 -0

index 5c88b2bec0..bc5fc8cee8 100644
@@ -13,5 +13,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t004"
 CONFIG_AXP152_POWER=y
 CONFIG_CONS_INDEX=2
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Bananapi_defconfig +1 -0

index 41cb9fc225..67daec6d7f 100644
@@ -21,5 +21,6 @@ CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Bananapi_m2m_defconfig +1 -0

index 990c791b76..c8dfa7d51f 100644
@@ -15,6 +15,7 @@ CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-bananapi-m2m"
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_FUNCTION_MASS_STORAGE=y

configs/Bananapro_defconfig +1 -0

index 41fc6a6eee..cd5d8b6cdd 100644
@@ -24,5 +24,6 @@ CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_AXP_ALDO4_VOLT=2500
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/CHIP_defconfig +1 -0

index ffdffcdb06..67fe58b21f 100644
@@ -17,6 +17,7 @@ CONFIG_DFU_RAM=y
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_AXP_ALDO4_VOLT=3300
 CONFIG_CONS_INDEX=2
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/CHIP_pro_defconfig +1 -0

index c607adb65b..618f113ff6 100644
@@ -22,6 +22,7 @@ CONFIG_SYS_NAND_OOBSIZE=0x100
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_AXP_ALDO4_VOLT=3300
 CONFIG_CONS_INDEX=2
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/CSQ_CS908_defconfig +1 -0

index ffc64d6aa4..9036ffc96a 100644
@@ -16,6 +16,7 @@ CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Colombus_defconfig +1 -0

index 77c7e9ee29..cb65647c7a 100644
@@ -26,5 +26,6 @@ CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_AXP_ALDO1_VOLT=3300
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Cubieboard2_defconfig +1 -0

index 366f55b815..7fe5b83fa2 100644
@@ -18,5 +18,6 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Cubieboard_defconfig +1 -0

index efc3e2567a..ccb612a9c7 100644
@@ -17,5 +17,6 @@ CONFIG_SCSI_AHCI=y
 CONFIG_MII=y
 CONFIG_SUN4I_EMAC=y
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Cubietruck_defconfig +1 -0

index 86bef3d54f..3beb515075 100644
@@ -28,6 +28,7 @@ CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Cubietruck_plus_defconfig +1 -0

index 2f43bbd947..cecb428b02 100644
@@ -23,6 +23,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-cubietruck-plus"
 CONFIG_AXP_DLDO3_VOLT=2500
 CONFIG_AXP_DLDO4_VOLT=3300
 CONFIG_AXP_FLDO1_VOLT=1200
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Hummingbird_A31_defconfig +1 -0

index b3e9d0a530..0f0b1c2251 100644
@@ -18,5 +18,6 @@ CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_AXP_ALDO1_VOLT=3300
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Itead_Ibox_A20_defconfig +1 -0

index 721bc87677..784c4de384 100644
@@ -18,5 +18,6 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Lamobo_R1_defconfig +1 -0

index 9eb3c08cb8..88f8a1577b 100644
@@ -23,5 +23,6 @@ CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Linksprite_pcDuino3_Nano_defconfig +1 -0

index 09aae78205..72d9b03929 100644
@@ -21,5 +21,6 @@ CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Linksprite_pcDuino3_defconfig +1 -0

index 00a49d1077..9156f132d1 100644
@@ -20,5 +20,6 @@ CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_SCSI=y
 CONFIG_DM_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Linksprite_pcDuino_defconfig +1 -0

index 81dbb72c75..21cfea133d 100644
@@ -13,5 +13,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino"
 CONFIG_MII=y
 CONFIG_SUN4I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/MK808C_defconfig +1 -0

index f634ac894a..367a164554 100644
@@ -10,5 +10,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-mk808c"
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Marsboard_A10_defconfig +1 -0

index ae7c26615f..c40e452aa4 100644
@@ -14,5 +14,6 @@ CONFIG_MII=y
 CONFIG_SUN4I_EMAC=y
 CONFIG_SUNXI_NO_PMIC=y
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Mele_A1000G_quad_defconfig +1 -0

index a2c613521e..feabbbf244 100644
@@ -19,6 +19,7 @@ CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_AXP_DLDO4_VOLT=3300
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Mele_A1000_defconfig +1 -0

index 49672092e2..9375c5d424 100644
@@ -17,5 +17,6 @@ CONFIG_SCSI_AHCI=y
 CONFIG_MII=y
 CONFIG_SUN4I_EMAC=y
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Mele_I7_defconfig +1 -0

index aac4fa12b2..eecf89b76e 100644
@@ -18,5 +18,6 @@ CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_AXP_DLDO4_VOLT=3300
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Mele_M3_defconfig +1 -0

index acd98bc960..9738f8ba81 100644
@@ -17,5 +17,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3"
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Mele_M5_defconfig +1 -0

index e473da772e..c76bc9f91f 100644
@@ -19,5 +19,6 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Mele_M9_defconfig +1 -0

index 63bf3fd5b2..d3136c67cb 100644
@@ -18,5 +18,6 @@ CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_AXP_DLDO4_VOLT=3300
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Mini-X_defconfig +1 -0

index 161feea519..54b40d5696 100644
@@ -12,5 +12,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus"
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Orangepi_defconfig +1 -0

index 3ea1d03d96..dae821a8d2 100644
@@ -23,5 +23,6 @@ CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Orangepi_mini_defconfig +1 -0

index 737c7a958e..e1cbbbd4e9 100644
@@ -25,5 +25,6 @@ CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Sinlinx_SinA31s_defconfig +1 -0

index dbc8c08e57..efa3b86b1f 100644
@@ -19,5 +19,6 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Sinlinx_SinA33_defconfig +1 -0

index df078c4b64..b92d62117c 100644
@@ -20,6 +20,7 @@ CONFIG_CMD_DFU=y
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33"
 CONFIG_DFU_RAM=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Sinovoip_BPI_M2_Plus_defconfig +1 -0

index 35c4718e2d..c2025ee0a4 100644
@@ -14,6 +14,7 @@ CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-bananapi-m2-plus"
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Sinovoip_BPI_M2_defconfig +1 -0

index 83ef4b4dce..fd69ac5170 100644
@@ -18,5 +18,6 @@ CONFIG_SUN7I_GMAC=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_ALDO2_VOLT=1800
 CONFIG_AXP_DLDO1_VOLT=3000
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Sinovoip_BPI_M3_defconfig +1 -0

index 9f04731543..ec59feb4e4 100644
@@ -24,6 +24,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-bananapi-m3"
 CONFIG_AXP_DCDC5_VOLT=1200
 CONFIG_AXP_DLDO3_VOLT=2500
 CONFIG_AXP_SW_ON=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Wexler_TAB7200_defconfig +1 -0

index 58c65b72bb..a2351dc925 100644
@@ -18,6 +18,7 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wexler-tab7200"
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Wits_Pro_A20_DKT_defconfig +1 -0

index 1fc7a4dbb0..cc8ba5810c 100644
@@ -23,5 +23,6 @@ CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/Wobo_i5_defconfig +1 -0

index a0dca6aa67..17f03c8579 100644
@@ -15,5 +15,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-wobo-i5"
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_AXP_ALDO4_VOLT=3300
 CONFIG_CONS_INDEX=2
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/a64-olinuxino_defconfig +1 -0

index 01fcb86599..94ac94c6ab 100644
@@ -11,5 +11,6 @@ CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-olinuxino"
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/ba10_tv_box_defconfig +1 -0

index 846fab2f5f..76a980e60f 100644
@@ -16,6 +16,7 @@ CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-ba10-tvbox"
 CONFIG_MII=y
 CONFIG_SUN4I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/bananapi_m1_plus_defconfig +1 -0

index 7286d2160b..46baf346c5 100644
@@ -21,4 +21,5 @@ CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_SCSI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y

configs/bananapi_m64_defconfig +1 -0

index aa0ad3c5f4..7dc768ff9f 100644
@@ -12,6 +12,7 @@ CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-bananapi-m64"
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/ga10h_v1_1_defconfig +1 -0

index 4c88285e24..0049982407 100644
@@ -23,6 +23,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ga10h-v1.1"
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_CONS_INDEX=5
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/h8_homlet_v2_defconfig +1 -0

index 7aad6f0cdf..6e1cc00357 100644
@@ -16,6 +16,7 @@ CONFIG_CONSOLE_MUX=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-allwinner-h8homlet-v2"
 CONFIG_AXP_DLDO4_VOLT=3300
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/i12-tvbox_defconfig +1 -0

index 4b3a8a3d50..fea490d74d 100644
@@ -15,5 +15,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox"
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/icnova-a20-swac_defconfig +1 -0

index 07c89a41e7..99cc7e889f 100644
@@ -22,5 +22,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-icnova-swac"
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/inet1_defconfig +1 -0

index 79e594bc15..b5b94d9c95 100644
@@ -19,6 +19,7 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet1"
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/inet_q972_defconfig +1 -0

index d15f71ae7a..7f3d04db6d 100644
@@ -20,6 +20,7 @@ CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-inet-q972"
 CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/jesurun_q5_defconfig +1 -0

index ce485376f3..e6f90c09f2 100644
@@ -15,6 +15,7 @@ CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5"
 CONFIG_MII=y
 CONFIG_SUN4I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/libretech_all_h3_cc_h2_plus_defconfig +1 -0

index 2c7a3ff9ef..9c2e28f1e8 100644
@@ -13,5 +13,6 @@ CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-libretech-all-h3-cc"
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/libretech_all_h3_cc_h3_defconfig +1 -0

index bd2c7083b0..9130a5980b 100644
@@ -13,5 +13,6 @@ CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-libretech-all-h3-cc"
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/libretech_all_h3_cc_h5_defconfig +1 -0

index 001f53d0fe..eb0d5dc7af 100644
@@ -13,5 +13,6 @@ CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-libretech-all-h3-cc"
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/mixtile_loftq_defconfig +1 -0

index 9ebb55c678..55d06497c9 100644
@@ -18,5 +18,6 @@ CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
 CONFIG_AXP_ALDO1_VOLT=3300
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/mk802_a10s_defconfig +1 -0

index 3fba55e70f..5a0b502145 100644
@@ -14,5 +14,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-mk802"
 CONFIG_AXP152_POWER=y
 CONFIG_CONS_INDEX=2
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/mk802_defconfig +1 -0

index 1b59348f94..14f8feee20 100644
@@ -10,5 +10,6 @@ CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802"
 CONFIG_SUNXI_NO_PMIC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/mk802ii_defconfig +1 -0

index 7a3f3d1f74..abd261db2f 100644
@@ -9,5 +9,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii"
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/nanopi_a64_defconfig +1 -0

index cd3b59f2dc..4dfd36ee3c 100644
@@ -10,5 +10,6 @@ CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-nanopi-a64"
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/nanopi_m1_defconfig +1 -0

index bf4e874b12..c8efce81e4 100644
@@ -11,5 +11,6 @@ CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1"
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/nanopi_m1_plus_defconfig +1 -0

index 66e90916f7..79b1c6913e 100644
@@ -13,5 +13,6 @@ CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1-plus"
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/nanopi_neo2_defconfig +1 -0

index ee693be1a8..8892f6cd83 100644
@@ -11,5 +11,6 @@ CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo2"
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/nanopi_neo_air_defconfig +1 -0

index 8c362fa885..149530416b 100644
@@ -13,5 +13,6 @@ CONFIG_CONSOLE_MUX=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo-air"
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/nanopi_neo_defconfig +1 -0

index ffb854b4b8..b963a28ecc 100644
@@ -14,5 +14,6 @@ CONFIG_CONSOLE_MUX=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo"
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/nanopi_neo_plus2_defconfig +1 -0

index 331dc6a8f7..efb1737a75 100644
@@ -13,4 +13,5 @@ CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo-plus2"
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y

configs/orangepi_2_defconfig +1 -0

index b86c0ab380..3ad13cb307 100644
@@ -16,5 +16,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-2"
 CONFIG_SUN8I_EMAC=y
 CONFIG_SY8106A_POWER=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_lite_defconfig +1 -0

index de08a8a2c6..e30df9be26 100644
@@ -11,5 +11,6 @@ CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-lite"
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_one_defconfig +1 -0

index 003f2cc7cb..346a55f1d1 100644
@@ -12,5 +12,6 @@ CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one"
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_pc2_defconfig +1 -0

index 7f7e6d3264..a74fedda3f 100644
@@ -13,6 +13,7 @@ CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-pc2"
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_pc_defconfig +1 -0

index fd41e1a45b..14fcb66113 100644
@@ -14,5 +14,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
 CONFIG_SUN8I_EMAC=y
 CONFIG_SY8106A_POWER=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_pc_plus_defconfig +1 -0

index 1f0bf73149..0e7b4d3b1b 100644
@@ -15,5 +15,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc-plus"
 CONFIG_SUN8I_EMAC=y
 CONFIG_SY8106A_POWER=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_plus2e_defconfig +1 -0

index 9baccdef78..3e79c848c3 100644
@@ -16,5 +16,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus2e"
 CONFIG_SUN8I_EMAC=y
 CONFIG_SY8106A_POWER=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_plus_defconfig +1 -0

index 0588799b59..26bd9c439a 100644
@@ -18,5 +18,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus"
 CONFIG_SUN8I_EMAC=y
 CONFIG_SY8106A_POWER=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_prime_defconfig +1 -0

index 7e10ebe796..d2429b767b 100644
@@ -11,6 +11,7 @@ CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-prime"
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_r1_defconfig +1 -0

index f587bec2ec..cd3355153c 100644
@@ -13,5 +13,6 @@ CONFIG_CONSOLE_MUX=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-r1"
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_win_defconfig +1 -0

index ab889ea8f5..78c55326c6 100644
@@ -11,5 +11,6 @@ CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-orangepi-win"
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_zero_defconfig +1 -0

index 0da9c65093..e5a4c1d9fc 100644
@@ -13,5 +13,6 @@ CONFIG_CONSOLE_MUX=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-zero"
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_zero_plus2_defconfig +1 -0

index 3c6ee03a53..7ae922774c 100644
@@ -13,5 +13,6 @@ CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-zero-plus2"
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/orangepi_zero_plus_defconfig +1 -0

index 5d783c5981..74133fa03b 100644
@@ -13,5 +13,6 @@ CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-zero-plus"
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/parrot_r16_defconfig +1 -0

index a6071612c4..80c1bf1fbe 100644
@@ -18,6 +18,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-parrot"
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_CONS_INDEX=5
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/pine64_plus_defconfig +1 -0

index a5b87b9063..ded4d134f1 100644
@@ -14,5 +14,6 @@ CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus"
 CONFIG_PHY_REALTEK=y
 CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/pinebook_defconfig +1 -0

index 5294dbd2eb..935644dfaf 100644
@@ -15,6 +15,7 @@ CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_PWM=y
 CONFIG_PWM_SUNXI=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
 # CONFIG_USB_GADGET is not set

configs/r7-tv-dongle_defconfig +1 -0

index 9c797c5512..d993b5d256 100644
@@ -13,5 +13,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-r7-tv-dongle"
 CONFIG_AXP152_POWER=y
 CONFIG_CONS_INDEX=2
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/sopine_baseboard_defconfig +1 -0

index 9ede081c08..0a189fc03d 100644
@@ -16,5 +16,6 @@ CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-sopine-baseboard"
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/sun8i_a23_evb_defconfig +1 -0

index 70c4072e22..563275b65f 100644
@@ -14,5 +14,6 @@ CONFIG_NR_DRAM_BANKS=1
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-evb"
 CONFIG_CONS_INDEX=5
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/sunxi_Gemei_G9_defconfig +1 -0

index e07d7c7d9e..06a07df051 100644
@@ -16,5 +16,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-gemei-g9"
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

configs/tbs_a711_defconfig +1 -0

index b2bcf3be57..103ce9be46 100644
@@ -19,6 +19,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-tbs-a711"
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_AXP_DCDC5_VOLT=1200
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_FUNCTION_MASS_STORAGE=y

drivers/usb/host/Kconfig +2 -0

index a213c918bc..60f37f40fd 100644
@@ -190,6 +190,7 @@ config USB_EHCI_GENERIC
 	bool "Support for generic EHCI USB controller"
 	depends on OF_CONTROL
 	depends on DM_USB
+	default ARCH_SUNXI
 	default n
 	---help---
 	  Enables support for generic EHCI controller.

@@ -220,6 +221,7 @@ config USB_OHCI_GENERIC
 	bool "Support for generic OHCI USB controller"
 	depends on OF_CONTROL
 	depends on DM_USB
+	default ARCH_SUNXI
 	select USB_HOST
 	---help---
 	  Enables support for generic OHCI controller.

include/configs/sun4i.h +0 -4

index af079a71ee..6033760583 100644
@@ -11,10 +11,6 @@
  * A10 specific configuration
  */
 
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_SUNXI
-#endif
-
 /*
  * Include common sunxi configuration where most the settings are
  */

include/configs/sun50i.h +0 -5

index 2d73c75b8c..e050a5299f 100644
@@ -10,11 +10,6 @@
  * A64 specific configuration
  */
 
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_SUNXI
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#endif
-
 #ifndef CONFIG_MACH_SUN50I_H6
 #define GICD_BASE		0x1c81000
 #define GICC_BASE		0x1c82000

include/configs/sun5i.h +0 -4

index c3692caa73..ee42af80d4 100644
@@ -11,10 +11,6 @@
  * High Level Configuration Options
  */
 
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_SUNXI
-#endif
-
 /*
  * Include common sunxi configuration where most the settings are
  */

include/configs/sun6i.h +0 -4

index 1523684fad..1e490daac1 100644
@@ -14,10 +14,6 @@
  * A31 specific configuration
  */
 
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_SUNXI
-#endif
-
 #define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
 #define CONFIG_ARMV7_SECURE_MAX_SIZE    (64 * 1024) /* 64 KB */

include/configs/sun7i.h +0 -4

index bb8f217b25..d2fd586672 100644
@@ -12,10 +12,6 @@
  * A20 specific configuration
  */
 
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_SUNXI
-#endif
-
 #define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
 #define CONFIG_ARMV7_SECURE_MAX_SIZE	(64 * 1024) /* 64 KB */

include/configs/sun8i.h +0 -4

index 7dc8693b76..9b4675e4c3 100644
@@ -12,10 +12,6 @@
  * A23 specific configuration
  */
 
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_USB_EHCI_SUNXI
-#endif
-
 /*
  * Include common sunxi configuration where most the settings are
  */

include/configs/sunxi-common.h +0 -1

index 9819d9980c..ed0cfc24f5 100644
@@ -295,7 +295,6 @@ extern int soft_i2c_gpio_scl;
 
 #ifdef CONFIG_USB_EHCI_HCD
 #define CONFIG_USB_OHCI_NEW
-#define CONFIG_USB_OHCI_SUNXI
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
 #endif

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2019-01-10 18:40 UTC #25 lore raw

PATCH v6 20/20 usb: host: Drop [e-o]hci-sunxi drivers

Now Allwinner platform is all set to use Generic USB controller drivers, so remove the legacy sunxi drivers.

Signed-off-by Jagan Teki <[email protected]>

---
 drivers/usb/host/Makefile     |   2 -
 drivers/usb/host/ehci-sunxi.c | 204 -----------------------------
 drivers/usb/host/ohci-sunxi.c | 233 ----------------------------------
 scripts/config_whitelist.txt  |   2 -
 4 files changed, 441 deletions(-)
 delete mode 100644 drivers/usb/host/ehci-sunxi.c
 delete mode 100644 drivers/usb/host/ohci-sunxi.c

drivers/usb/host/Makefile +0 -2

index 948683a52b..6aa574f6f7 100644
@@ -15,7 +15,6 @@ obj-$(CONFIG_USB_OHCI_DA8XX) += ohci-da8xx.o
 obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
 obj-$(CONFIG_USB_SL811HS) += sl811-hcd.o
 obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o
-obj-$(CONFIG_USB_OHCI_SUNXI) += ohci-sunxi.o
 obj-$(CONFIG_USB_OHCI_LPC32XX) += ohci-lpc32xx.o
 obj-$(CONFIG_USB_OHCI_GENERIC) += ohci-generic.o

@@ -37,7 +36,6 @@ obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
 obj-$(CONFIG_USB_EHCI_MSM) += ehci-msm.o
 obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
 obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
-obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o
 obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
 obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
 obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o

drivers/usb/host/ehci-sunxi.c deleted +0 ~~-204~~

204 lines not on this page · raw message

drivers/usb/host/ohci-sunxi.c deleted +0 ~~-233~~

233 lines not on this page · raw message

scripts/config_whitelist.txt +0 -2

index 527050de97..ed651c2348 100644
@@ -4542,7 +4542,6 @@ CONFIG_USB_EHCI_MX5
 CONFIG_USB_EHCI_MXC
 CONFIG_USB_EHCI_MXS
 CONFIG_USB_EHCI_SPEAR
-CONFIG_USB_EHCI_SUNXI
 CONFIG_USB_EHCI_TEGRA
 CONFIG_USB_EHCI_TXFIFO_THRESH
 CONFIG_USB_EHCI_VCT

@@ -4580,7 +4579,6 @@ CONFIG_USB_MUSB_TUSB6010
 CONFIG_USB_OHCI_EP93XX
 CONFIG_USB_OHCI_LPC32XX
 CONFIG_USB_OHCI_NEW
-CONFIG_USB_OHCI_SUNXI
 CONFIG_USB_OTG
 CONFIG_USB_OTG_BLACKLIST_HUB
 CONFIG_USB_PHY_TYPE

Signature · 1 line

2.18.0.321.gffc6fa0e3

Jagan Teki

author

2019-01-18 16:52 UTC #26 lore raw

v6 cover clk: Add Allwinner CLK, RESET support