arm64: dts: allwinner: h6: Enable CPU DVFS(cpufreq)

The original orangepi use the dcdca to supply the CPU cores. According to the axp805 spec, the range of dcdca is 0.6 to 1.1v, 1.12 to 1.52v. In order to support more CPU frequency, slightly increase the voltage maximum and minimum.

Signed-off-by Yangtao Li <[email protected]>

---
 arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +0 -0

index b2526dac2fcf..e7aebaf91ede 100644

Hi!

Thanks for your patches

Quoted 16 lines · Yangtao Li

The original orangepi use the dcdca to supply the CPU cores. According to the axp805 spec, the range of dcdca is 0.6 to 1.1v, 1.12 to 1.52v. In order to support more CPU frequency, slightly increase the voltage maximum and minimum.

Signed-off-by Yangtao Li <[email protected]>

---
 arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +0 -0

index b2526dac2fcf..e7aebaf91ede 100644
@@ -159,8 +159,8 @@
 

arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi line 163

Quoted 6 lines

arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +2 -2

                      reg_dcdca: dcdca {
                              regulator-always-on;
-                             regulator-min-microvolt = <810000>;
-                             regulator-max-microvolt = <1080000>;
+                             regulator-min-microvolt = <800000>;
+                             regulator-max-microvolt = <1160000>;

This violates the minimum and maximum recommended voltages in the H6 datasheet. Could you clarify why you are doing so (ideally in the commit log)?

Thanks!
Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Quoted 19 lines · Maxime Ripard

Thanks for your patches

Quoted 16 lines · Yangtao Li

The original orangepi use the dcdca to supply the CPU cores. According to the axp805 spec, the range of dcdca is 0.6 to 1.1v, 1.12 to 1.52v. In order to support more CPU frequency, slightly increase the voltage maximum and minimum.

Signed-off-by Yangtao Li <[email protected]>

---
 arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +0 -0

index b2526dac2fcf..e7aebaf91ede 100644
@@ -159,8 +159,8 @@
 

Quoted 10 lines

arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi line 163

Quoted 6 lines

arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +2 -2

                      reg_dcdca: dcdca {
                              regulator-always-on;
-                             regulator-min-microvolt = <810000>;
-                             regulator-max-microvolt = <1080000>;
+                             regulator-min-microvolt = <800000>;
+                             regulator-max-microvolt = <1160000>;

This violates the minimum and maximum recommended voltages in the H6 datasheet. Could you clarify why you are doing so (ideally in the commit log)?

In fact, in sunxi's sdk, the actual minimum and maximum voltage of the cpu is smaller or larger than the datasheet.

For some better quality ic, the minimum voltage can be smaller. For some poor quality ic, the maximum voltage needs to be increased a little.

Add an OPP (Operating Performance Points) table for the CPU cores to enable DVFS (Dynamic Voltage & Frequency Scaling) on the H6. This information comes from github.

Signed-off-by Yangtao Li <[email protected]>

---
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 61 ++++++++++++++++++++
 1 file changed, 61 insertions(+)

arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +51 -0

index 57a1390ecdc2..46a4a69eb38f 100644
@@ -28,6 +28,8 @@
 			enable-method = "psci";
 			clocks = <&ccu CLK_CPUX>; 
 			clock-latency-ns = <244144>; /* 8 32k periods */
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
 		};
 
 		cpu1: cpu@1 {

@@ -37,6 +39,8 @@
 			enable-method = "psci";
 			clocks = <&ccu CLK_CPUX>; 
 			clock-latency-ns = <244144>; /* 8 32k periods */
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
 		};
 
 		cpu2: cpu@2 {

@@ -46,6 +50,8 @@
 			enable-method = "psci";
 			clocks = <&ccu CLK_CPUX>; 
 			clock-latency-ns = <244144>; /* 8 32k periods */
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
 		};
 
 		cpu3: cpu@3 {

@@ -55,6 +61,61 @@
 			enable-method = "psci";
 			clocks = <&ccu CLK_CPUX>; 
 			clock-latency-ns = <244144>; /* 8 32k periods */
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
+		};
+	};
+
+	cpu_opp_table: opp_table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@480000000 {
+			opp-hz = /bits/ 64 <480000000>;
+			opp-microvolt = <800000 800000 880000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@720000000 {
+			opp-hz = /bits/ 64 <720000000>;
+			opp-microvolt = <800000 800000 880000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@816000000 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <800000 800000 880000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@888000000 {
+			opp-hz = /bits/ 64 <888000000>;
+			opp-microvolt = <800000 800000 940000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@1080000000 {
+			opp-hz = /bits/ 64 <1080000000>;
+			opp-microvolt = <840000 840000 1060000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@1320000000 {
+			opp-hz = /bits/ 64 <1320000000>;
+			opp-microvolt = <900000 900000 1160000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+

Hi,

Quoted 89 lines · Yangtao Li

Add an OPP (Operating Performance Points) table for the CPU cores to enable DVFS (Dynamic Voltage & Frequency Scaling) on the H6. This information comes from github.

Signed-off-by Yangtao Li <[email protected]>

---
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 61 ++++++++++++++++++++
 1 file changed, 61 insertions(+)

arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +51 -0

index 57a1390ecdc2..46a4a69eb38f 100644
@@ -28,6 +28,8 @@
                      enable-method = "psci";
                      clocks = <&ccu CLK_CPUX>;
                      clock-latency-ns = <244144>; /* 8 32k periods */
+                     operating-points-v2 = <&cpu_opp_table>;
+                     #cooling-cells = <2>;
              };
 
              cpu1: cpu@1 {

@@ -37,6 +39,8 @@
                      enable-method = "psci";
                      clocks = <&ccu CLK_CPUX>;
                      clock-latency-ns = <244144>; /* 8 32k periods */
+                     operating-points-v2 = <&cpu_opp_table>;
+                     #cooling-cells = <2>;
              };
 
              cpu2: cpu@2 {

@@ -46,6 +50,8 @@
                      enable-method = "psci";
                      clocks = <&ccu CLK_CPUX>;
                      clock-latency-ns = <244144>; /* 8 32k periods */
+                     operating-points-v2 = <&cpu_opp_table>;
+                     #cooling-cells = <2>;
              };
 
              cpu3: cpu@3 {

@@ -55,6 +61,61 @@
                      enable-method = "psci";
                      clocks = <&ccu CLK_CPUX>;
                      clock-latency-ns = <244144>; /* 8 32k periods */
+                     operating-points-v2 = <&cpu_opp_table>;
+                     #cooling-cells = <2>;
+             };
+     };
+
+     cpu_opp_table: opp_table {
+             compatible = "operating-points-v2";
+             opp-shared;
+
+             opp@480000000 {
+                     opp-hz = /bits/ 64 <480000000>;
+                     opp-microvolt = <800000 800000 880000>;
+                     clock-latency-ns = <244144>; /* 8 32k periods */
+             };
+
+             opp@720000000 {
+                     opp-hz = /bits/ 64 <720000000>;
+                     opp-microvolt = <800000 800000 880000>;
+                     clock-latency-ns = <244144>; /* 8 32k periods */
+             };
+
+             opp@816000000 {
+                     opp-hz = /bits/ 64 <816000000>;
+                     opp-microvolt = <800000 800000 880000>;
+                     clock-latency-ns = <244144>; /* 8 32k periods */
+             };
+
+             opp@888000000 {
+                     opp-hz = /bits/ 64 <888000000>;
+                     opp-microvolt = <800000 800000 940000>;
+                     clock-latency-ns = <244144>; /* 8 32k periods */
+             };
+
+             opp@1080000000 {
+                     opp-hz = /bits/ 64 <1080000000>;
+                     opp-microvolt = <840000 840000 1060000>;
+                     clock-latency-ns = <244144>; /* 8 32k periods */
+             };
+
+             opp@1320000000 {
+                     opp-hz = /bits/ 64 <1320000000>;
+                     opp-microvolt = <900000 900000 1160000>;
+                     clock-latency-ns = <244144>; /* 8 32k periods */
+             };
+

arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi line 118

Quoted 10 lines

arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +10 -0

+             opp@1488000000 {
+                     opp-hz = /bits/ 64 <1488000000>;
+                     opp-microvolt = <960000 960000 1160000>;
+                     clock-latency-ns = <244144>; /* 8 32k periods */
+             };
+
+             opp@1800000000 {
+                     opp-hz = /bits/ 64 <1800000000>;
+                     opp-microvolt = <1060000 1060000 1160000>;
+                     clock-latency-ns = <244144>; /* 8 32k periods */

So we definitely want to have that tested, especially since cpufreq can lead to all kind of hard to debug errors (brown-outs, CPU lockups, cache corruption, etc.). I good way to test that would be to use cpufreq-ljt-stress-test here:
https://github.com/ssvb/cpuburn-arm/blob/master/cpufreq-ljt-stress-test

I'm especially worried about the higher frequencies that will probably make the SoC heat too much

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

How about to implement a thermal driver that is not integrated with gpadc ？

GPADC on soc is rarely used now.

Hi

Quoted 3 lines · Frank Lee

How about to implement a thermal driver that is not integrated with gpadc ？

Quoted 1 line

GPADC on soc is rarely used now.

You mean GPADC in general, or the gpadc driver in particular? Otherwise, yes, having a driver for the thermal sensor in the H6 sounds like a good plan for thermal throttling, but I don't see it as a dependency for that whole series.

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Quoted 7 lines · Maxime Ripard

Hi

Quoted 3 lines · Frank Lee

How about to implement a thermal driver that is not integrated with gpadc ？

Quoted 6 lines

Quoted 1 line

GPADC on soc is rarely used now.

You mean GPADC in general, or the gpadc driver in particular? Otherwise, yes, having a driver for the thermal sensor in the H6 sounds like a good plan for thermal throttling, but I don't see it as a dependency for that whole series.

At present, sunxi's thermal driver is integrated with the gpadc driver. I have a idea to implement the thermal driver alone. I haven't started yet, and it may take a while to do it.

How about the plan to implement a thermal drive alone and put i under drivers/thermal?

Quoted 110 lines · Maxime Ripard

Hi,

Quoted 89 lines · Yangtao Li

Add an OPP (Operating Performance Points) table for the CPU cores to enable DVFS (Dynamic Voltage & Frequency Scaling) on the H6. This information comes from github.

Signed-off-by Yangtao Li <[email protected]>

---
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 61 ++++++++++++++++++++
 1 file changed, 61 insertions(+)

arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +51 -0

index 57a1390ecdc2..46a4a69eb38f 100644
@@ -28,6 +28,8 @@
                      enable-method = "psci";
                      clocks = <&ccu CLK_CPUX>;
                      clock-latency-ns = <244144>; /* 8 32k periods */
+                     operating-points-v2 = <&cpu_opp_table>;
+                     #cooling-cells = <2>;
              };
 
              cpu1: cpu@1 {

@@ -37,6 +39,8 @@
                      enable-method = "psci";
                      clocks = <&ccu CLK_CPUX>;
                      clock-latency-ns = <244144>; /* 8 32k periods */
+                     operating-points-v2 = <&cpu_opp_table>;
+                     #cooling-cells = <2>;
              };
 
              cpu2: cpu@2 {

@@ -46,6 +50,8 @@
                      enable-method = "psci";
                      clocks = <&ccu CLK_CPUX>;
                      clock-latency-ns = <244144>; /* 8 32k periods */
+                     operating-points-v2 = <&cpu_opp_table>;
+                     #cooling-cells = <2>;
              };
 
              cpu3: cpu@3 {

@@ -55,6 +61,61 @@
                      enable-method = "psci";
                      clocks = <&ccu CLK_CPUX>;
                      clock-latency-ns = <244144>; /* 8 32k periods */
+                     operating-points-v2 = <&cpu_opp_table>;
+                     #cooling-cells = <2>;
+             };
+     };
+
+     cpu_opp_table: opp_table {
+             compatible = "operating-points-v2";
+             opp-shared;
+
+             opp@480000000 {
+                     opp-hz = /bits/ 64 <480000000>;
+                     opp-microvolt = <800000 800000 880000>;
+                     clock-latency-ns = <244144>; /* 8 32k periods */
+             };
+
+             opp@720000000 {
+                     opp-hz = /bits/ 64 <720000000>;
+                     opp-microvolt = <800000 800000 880000>;
+                     clock-latency-ns = <244144>; /* 8 32k periods */
+             };
+
+             opp@816000000 {
+                     opp-hz = /bits/ 64 <816000000>;
+                     opp-microvolt = <800000 800000 880000>;
+                     clock-latency-ns = <244144>; /* 8 32k periods */
+             };
+
+             opp@888000000 {
+                     opp-hz = /bits/ 64 <888000000>;
+                     opp-microvolt = <800000 800000 940000>;
+                     clock-latency-ns = <244144>; /* 8 32k periods */
+             };
+
+             opp@1080000000 {
+                     opp-hz = /bits/ 64 <1080000000>;
+                     opp-microvolt = <840000 840000 1060000>;
+                     clock-latency-ns = <244144>; /* 8 32k periods */
+             };
+
+             opp@1320000000 {
+                     opp-hz = /bits/ 64 <1320000000>;
+                     opp-microvolt = <900000 900000 1160000>;
+                     clock-latency-ns = <244144>; /* 8 32k periods */
+             };
+

arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi line 118

Quoted 10 lines

arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +10 -0

+             opp@1488000000 {
+                     opp-hz = /bits/ 64 <1488000000>;
+                     opp-microvolt = <960000 960000 1160000>;
+                     clock-latency-ns = <244144>; /* 8 32k periods */
+             };
+
+             opp@1800000000 {
+                     opp-hz = /bits/ 64 <1800000000>;
+                     opp-microvolt = <1060000 1060000 1160000>;
+                     clock-latency-ns = <244144>; /* 8 32k periods */

So we definitely want to have that tested, especially since cpufreq can lead to all kind of hard to debug errors (brown-outs, CPU lockups, cache corruption, etc.). I good way to test that would be to use cpufreq-ljt-stress-test here:
https://github.com/ssvb/cpuburn-arm/blob/master/cpufreq-ljt-stress-test

Quoted 2 lines

I'm especially worried about the higher frequencies that will probably make the SoC heat too much

Indeed, in order to avoid this situation, it is best to have cpu cooling support(But now it does not support thermal driver? ).

In this case, perhaps we should remove the frequency beyond a certain range to avoid the CPU being too hot?