memory: Introduce NVIDIA Tegra30 EMC driver
cover memory: Introduce NVIDIA Tegra30 EMC driver
Hello,
This patchset adds driver for the External Memory Controller of NVIDIA Tegra30 SoC's. It performs memory hardware configuration that is required for changing DRAM frequency, thus providing facility for the memory frequency scaling on Tegra30. The memory scaling was tested using the Tegra's devfreq driver which is available in upstream, it dynamically changes memory clock rate based on memory clients activity.
Dmitry Osipenko (3):
dt-bindings: memory: Add binding for NVIDIA Tegra30 External Memory
Controller
memory: tegra: Introduce Tegra30 EMC driver
ARM: dts: tegra30: Add External Memory Controller node
.../memory-controllers/nvidia,tegra30-emc.txt | 257 ++++ arch/arm/boot/dts/tegra30.dtsi | 11 + drivers/memory/tegra/Kconfig | 10 + drivers/memory/tegra/Makefile | 1 + drivers/memory/tegra/mc.c | 3 - drivers/memory/tegra/mc.h | 30 +- drivers/memory/tegra/tegra30-emc.c | 1106 +++++++++++++++++ drivers/memory/tegra/tegra30.c | 44 + 8 files changed, 1450 insertions(+), 12 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.txt create mode 100644 drivers/memory/tegra/tegra30-emc.c
Signature · 1 line
2.21.0
PATCH 1/3 dt-bindings: memory: Add binding for NVIDIA Tegra30 External Memory Controller
Add device-tree binding for NVIDIA Tegra30 External Memory Controller. The binding is based on the Tegra124 EMC binding since hardware is similar, although there are couple significant differences.
Signed-off-by Dmitry Osipenko <[email protected]>
--- .../memory-controllers/nvidia,tegra30-emc.txt | 257 ++++++++++++++++++ 1 file changed, 257 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.txt
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.txt new file +257 -0
@@ -0,0 +1,257 @@ +NVIDIA Tegra30 SoC EMC (external memory controller) +==================================================== + +Required properties : +- compatible : Should be "nvidia,tegra30-emc". +- reg : physical base address and length of the controller's registers. +- #address-cells : Should be 1 +- #size-cells : Should be 0 +- interrupts : Should contain EMC General interrupt. +- clocks : Should contain EMC clock. +- nvidia,memory-controller : phandle of the MC driver. + +The node should contain a "emc-timings" subnode for each supported RAM type +(see field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address +being its RAM_CODE. + +Required properties for "emc-timings" nodes : +- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is +used for. + +Each "emc-timings" node should contain a "timing" subnode for every supported +EMC clock rate. The "timing" subnodes should have the clock rate in Hz as +their unit address. + +Required properties for "timing" nodes : +- clock-frequency : Should contain the memory clock rate in Hz. +- The following properties contain EMC timing characterization values +(specified in the board documentation) : + - nvidia,emc-auto-cal-interval : EMC_AUTO_CAL_INTERVAL + - nvidia,emc-mode-1 : Mode Register 1 + - nvidia,emc-mode-2 : Mode Register 2 + - nvidia,emc-mode-reset : Mode Register 0 + - nvidia,emc-zcal-cnt-long : EMC_ZCAL_WAIT_CNT after clock change + - nvidia,emc-cfg-dyn-self-ref : dynamic self-refresh enabled + - nvidia,emc-cfg-periodic-qrst : FBIO "read" FIFO periodic resetting enabled +- nvidia,emc-configuration : EMC timing characterization data. These are the +registers (see section "18.13.2 EMC Registers" in the TRM) whose values need to +be specified, according to the board documentation: + + EMC_RC + EMC_RFC + EMC_RAS + EMC_RP + EMC_R2W + EMC_W2R + EMC_R2P + EMC_W2P + EMC_RD_RCD + EMC_WR_RCD + EMC_RRD + EMC_REXT + EMC_WEXT + EMC_WDV + EMC_QUSE + EMC_QRST + EMC_QSAFE + EMC_RDV + EMC_REFRESH + EMC_BURST_REFRESH_NUM + EMC_PRE_REFRESH_REQ_CNT + EMC_PDEX2WR + EMC_PDEX2RD + EMC_PCHG2PDEN + EMC_ACT2PDEN + EMC_AR2PDEN + EMC_RW2PDEN + EMC_TXSR + EMC_TXSRDLL + EMC_TCKE + EMC_TFAW + EMC_TRPAB + EMC_TCLKSTABLE + EMC_TCLKSTOP + EMC_TREFBW + EMC_QUSE_EXTRA + EMC_FBIO_CFG6 + EMC_ODT_WRITE + EMC_ODT_READ + EMC_FBIO_CFG5 + EMC_CFG_DIG_DLL + EMC_CFG_DIG_DLL_PERIOD + EMC_DLL_XFORM_DQS0 + EMC_DLL_XFORM_DQS1 + EMC_DLL_XFORM_DQS2 + EMC_DLL_XFORM_DQS3 + EMC_DLL_XFORM_DQS4 + EMC_DLL_XFORM_DQS5 + EMC_DLL_XFORM_DQS6 + EMC_DLL_XFORM_DQS7 + EMC_DLL_XFORM_QUSE0 + EMC_DLL_XFORM_QUSE1 + EMC_DLL_XFORM_QUSE2 + EMC_DLL_XFORM_QUSE3 + EMC_DLL_XFORM_QUSE4 + EMC_DLL_XFORM_QUSE5 + EMC_DLL_XFORM_QUSE6 + EMC_DLL_XFORM_QUSE7 + EMC_DLI_TRIM_TXDQS0 + EMC_DLI_TRIM_TXDQS1 + EMC_DLI_TRIM_TXDQS2 + EMC_DLI_TRIM_TXDQS3 + EMC_DLI_TRIM_TXDQS4 + EMC_DLI_TRIM_TXDQS5 + EMC_DLI_TRIM_TXDQS6 + EMC_DLI_TRIM_TXDQS7 + EMC_DLL_XFORM_DQ0 + EMC_DLL_XFORM_DQ1 + EMC_DLL_XFORM_DQ2 + EMC_DLL_XFORM_DQ3 + EMC_XM2CMDPADCTRL + EMC_XM2DQSPADCTRL2 + EMC_XM2DQPADCTRL2 + EMC_XM2CLKPADCTRL + EMC_XM2COMPPADCTRL + EMC_XM2VTTGENPADCTRL + EMC_XM2VTTGENPADCTRL2 + EMC_XM2QUSEPADCTRL + EMC_XM2DQSPADCTRL3 + EMC_CTT_TERM_CTRL + EMC_ZCAL_INTERVAL + EMC_ZCAL_WAIT_CNT + EMC_MRS_WAIT_CNT + EMC_AUTO_CAL_CONFIG + EMC_CTT + EMC_CTT_DURATION + EMC_DYN_SELF_REF_CONTROL + EMC_FBIO_SPARE + EMC_CFG_RSV + +Example SoC include file: + +/ { + emc@7000f400 { + compatible = "nvidia,tegra30-emc"; + reg = <0x7000f400 0x400>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA30_CLK_EMC>; + #address-cells = <1>; + #size-cells = <0>; + + nvidia,memory-controller = <&mc>; + }; +}; + +Example board file: + +/ { + emc@7000f400 { + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref = <0x00000000>; + nvidia,emc-cfg-periodic-qrst = <0x00000001>; + + nvidia,emc-configuration = < + 0x00000020 /* EMC_RC */ + 0x0000006a /* EMC_RFC */ + 0x00000017 /* EMC_RAS */ + 0x00000007 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000c /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x00000011 /* EMC_W2P */ + 0x00000007 /* EMC_RD_RCD */ + 0x00000007 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000a /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001412 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000e /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000c /* EMC_AR2PDEN */ + 0x00000016 /* EMC_RW2PDEN */ + 0x00000072 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000015 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000007 /* EMC_TCLKSTOP */ + 0x00001453 /* EMC_TREFBW */ + 0x0000000b /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf00b0191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000008 /* EMC_DLL_XFORM_DQS0 */ + 0x00000008 /* EMC_DLL_XFORM_DQS1 */ + 0x00000008 /* EMC_DLL_XFORM_DQS2 */ + 0x00000008 /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000a /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x0c000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0155000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; + }; +};
Signature · 1 line
2.21.0
PATCH 2/3 memory: tegra: Introduce Tegra30 EMC driver
In reply to Dmitry OsipenkoIntroduce driver for the External Memory Controller (EMC) found on Tegra30 chips, it controls the external DRAM on the board. The purpose of this driver is to program memory timing for external memory on the EMC clock rate change.
Signed-off-by Dmitry Osipenko <[email protected]>
--- drivers/memory/tegra/Kconfig | 10 + drivers/memory/tegra/Makefile | 1 + drivers/memory/tegra/mc.c | 3 - drivers/memory/tegra/mc.h | 30 +- drivers/memory/tegra/tegra30-emc.c | 1105 ++++++++++++++++++++++++++++ drivers/memory/tegra/tegra30.c | 44 ++ 6 files changed, 1181 insertions(+), 12 deletions(-) create mode 100644 drivers/memory/tegra/tegra30-emc.c
drivers/memory/tegra/Kconfig +10 -0
@@ -16,6 +16,16 @@ config TEGRA20_EMC This driver is required to change memory timings / clock rate for external memory. +config TEGRA30_EMC + bool "NVIDIA Tegra30 External Memory Controller driver" + default y + depends on TEGRA_MC && ARCH_TEGRA_3x_SOC + help + This driver is for the External Memory Controller (EMC) found on + Tegra30 chips. The EMC controls the external DRAM on the board. + This driver is required to change memory timings / clock rate for + external memory. + config TEGRA124_EMC bool "NVIDIA Tegra124 External Memory Controller driver" default y
drivers/memory/tegra/Makefile +1 -0
@@ -11,5 +11,6 @@ tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o obj-$(CONFIG_TEGRA_MC) += tegra-mc.o obj-$(CONFIG_TEGRA20_EMC) += tegra20-emc.o +obj-$(CONFIG_TEGRA30_EMC) += tegra30-emc.o obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o
drivers/memory/tegra/mc.c +0 -3
@@ -51,9 +51,6 @@#define MC_EMEM_ADR_CFG 0x54#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0) -#define MC_TIMING_CONTROL 0xfc -#define MC_TIMING_UPDATE BIT(0) -static const struct of_device_id tegra_mc_of_match[] = { #ifdef CONFIG_ARCH_TEGRA_2x_SOC { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
drivers/memory/tegra/mc.h +21 -9
@@ -9,20 +9,32 @@#ifndef MEMORY_TEGRA_MC_H #define MEMORY_TEGRA_MC_H +#include <linux/bits.h> #include <linux/io.h> #include <linux/types.h> #include <soc/tegra/mc.h> -#define MC_INT_DECERR_MTS (1 << 16) -#define MC_INT_SECERR_SEC (1 << 13) -#define MC_INT_DECERR_VPR (1 << 12) -#define MC_INT_INVALID_APB_ASID_UPDATE (1 << 11) -#define MC_INT_INVALID_SMMU_PAGE (1 << 10) -#define MC_INT_ARBITRATION_EMEM (1 << 9) -#define MC_INT_SECURITY_VIOLATION (1 << 8) -#define MC_INT_INVALID_GART_PAGE (1 << 7) -#define MC_INT_DECERR_EMEM (1 << 6) +#define MC_INT_DECERR_MTS BIT(16) +#define MC_INT_SECERR_SEC BIT(13) +#define MC_INT_DECERR_VPR BIT(12) +#define MC_INT_INVALID_APB_ASID_UPDATE BIT(11) +#define MC_INT_INVALID_SMMU_PAGE BIT(10) +#define MC_INT_ARBITRATION_EMEM BIT(9) +#define MC_INT_SECURITY_VIOLATION BIT(8) +#define MC_INT_INVALID_GART_PAGE BIT(7) +#define MC_INT_DECERR_EMEM BIT(6) + +#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94 +#define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK 0x1ff +#define MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE BIT(30) +#define MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE BIT(31) + +#define MC_EMEM_ARB_OVERRIDE 0xe8 +#define MC_EMEM_ARB_OVERRIDE_EACK_MASK 0x3 + +#define MC_TIMING_CONTROL 0xfc +#define MC_TIMING_UPDATE BIT(0)static inline u32 mc_readl (struct tegra_mc *mc,unsigned long offset) {
drivers/memory/tegra/tegra30-emc.c new file +1105 -0
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drivers/memory/tegra/tegra30.c +44 -0
56 lines not on this page · raw message
Signature · 1 line
2.21.0
Re: [PATCH v1 2/3] memory: tegra: Introduce Tegra30 EMC driver
12.04.2019 2:02, Dmitry Osipenko пишет:
Quoted 6 lines
Introduce driver for the External Memory Controller (EMC) found on Tegra30 chips, it controls the external DRAM on the board. The purpose of this driver is to program memory timing for external memory on the EMC clock rate change.
Signed-off-by Dmitry Osipenko <[email protected]>
I realized that the MC_SAME_FREQ timing configuration need be properly handled for T30 and that is missed in this version. Will fix it up in v2. Although, seems it's not critical since things appear to work properly and probably only arbitration is not optimally configured because of the MC/EMC setup mismatch.
PATCH 3/3 ARM: dts: tegra30: Add External Memory Controller node
In reply to Dmitry OsipenkoAdd Add External Memory Controller node to the device-tree.
Signed-off-by Dmitry Osipenko <[email protected]>
--- arch/arm/boot/dts/tegra30.dtsi | 11 +++++++++++ drivers/memory/tegra/tegra30-emc.c | 3 ++- 2 files changed, 13 insertions(+), 1 deletion(-)
arch/arm/boot/dts/tegra30.dtsi +11 -0
@@ -732,6 +732,17 @@ #reset-cells = <1>; }; + memory-controller@7000f400 { + compatible = "nvidia,tegra30-emc"; + reg = <0x7000f400 0x400>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA30_CLK_EMC>; + #address-cells = <1>; + #size-cells = <0>; + + nvidia,memory-controller = <&mc>; + }; + fuse@7000f800 { compatible = "nvidia,tegra30-efuse"; reg = <0x7000f800 0x400>;
drivers/memory/tegra/tegra30-emc.c +2 -1
@@ -980,7 +980,8 @@ static long emc_round_rate(unsigned long rate, }if (!timing) { -dev_err (emc->dev,"no timing for rate %lu\n" , rate); +dev_err (emc->dev,"no timing for rate %lu min %lu max %lu\n" , + rate, min_rate, max_rate);return -EINVAL ; }
Signature · 1 line
2.21.0
Re: [PATCH v1 3/3] ARM: dts: tegra30: Add External Memory Controller node
Quoted 2 lines · Dmitry Osipenko
Add Add External Memory Controller node to the device-tree.
One 'Add' is enough I think :)
Peter.
Quoted 45 lines
Signed-off-by Dmitry Osipenko <[email protected]>--- arch/arm/boot/dts/tegra30.dtsi | 11 +++++++++++ drivers/memory/tegra/tegra30-emc.c | 3 ++- 2 files changed, 13 insertions(+), 1 deletion(-)arch/arm/boot/dts/tegra30.dtsi +11
-0@@ -732,6 +732,17 @@ #reset-cells = <1>; }; + memory-controller@7000f400 { + compatible = "nvidia,tegra30-emc"; + reg = <0x7000f400 0x400>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA30_CLK_EMC>; + #address-cells = <1>; + #size-cells = <0>; + + nvidia,memory-controller = <&mc>; + }; + fuse@7000f800 { compatible = "nvidia,tegra30-efuse"; reg = <0x7000f800 0x400>;drivers/memory/tegra/tegra30-emc.c +2
-1@@ -980,7 +980,8 @@ static long emc_round_rate(unsigned long rate, }if (!timing) { -dev_err (emc->dev,"no timing for rate %lu\n" , rate); +dev_err (emc->dev,"no timing for rate %lu min %lu max %lu\n" , + rate, min_rate, max_rate);return -EINVAL ; }Signature · 1 line
2.21.0
Re: [PATCH v1 3/3] ARM: dts: tegra30: Add External Memory Controller node
12.04.2019 11:01, Peter De Schrijver пишет:
Quoted 5 lines · Dmitry Osipenko
Quoted 2 lines
Add Add External Memory Controller node to the device-tree.
One 'Add' is enough I think :)
Indeed, thank you!
Re: [PATCH v1 3/3] ARM: dts: tegra30: Add External Memory Controller node
In reply to Dmitry OsipenkoQuoted 4 lines · Dmitry Osipenko
Add Add External Memory Controller node to the device-tree.
Signed-off-by Dmitry Osipenko <[email protected]>---
..
drivers/memory/tegra/tegra30-emc.c static long emc_round_rate(unsigned long rate, · line 986
Quoted 13 lines
drivers/memory/tegra/tegra30-emc.c +2
-1@@ -980,7 +980,8 @@ static long emc_round_rate(unsigned long rate, }if (!timing) { -dev_err (emc->dev,"no timing for rate %lu\n" , rate); +dev_err (emc->dev,"no timing for rate %lu min %lu max %lu\n" , + rate, min_rate, max_rate);return -EINVAL ; }
This doesn't seem to belong to this patch?
Peter.
Quoted 4 lines
Signature · 2 lines
-- 2.21.0
Re: [PATCH v1 3/3] ARM: dts: tegra30: Add External Memory Controller node
12.04.2019 11:06, Peter De Schrijver пишет:
Quoted 13 lines · Dmitry Osipenko
Quoted 4 lines
Add Add External Memory Controller node to the device-tree.
Signed-off-by Dmitry Osipenko <[email protected]>---
..
Quoted 7 lines
drivers/memory/tegra/tegra30-emc.c +0
-0@@ -980,7 +980,8 @@ static long emc_round_rate(unsigned long rate, }
Quoted 8 lines
drivers/memory/tegra/tegra30-emc.c static long emc_round_rate(unsigned long rate, · line 986
Quoted 6 lines
drivers/memory/tegra/tegra30-emc.c +2
-1if (!timing) { -dev_err (emc->dev,"no timing for rate %lu\n" , rate); +dev_err (emc->dev,"no timing for rate %lu min %lu max %lu\n" , + rate, min_rate, max_rate);return -EINVAL ; }This doesn't seem to belong to this patch?
Yes, I accidentally edited a wrong patch on rebase. Fixed it up for v2 already, thank you.