net: stmmac: Some improvements and a fix
Subsystems (5)
v2 cover net: stmmac: Some improvements and a fix
Some performace improvements (01/03 and 03/03) and a fix (02/03), all for -next.
Cc Joao Pinto <[email protected]>
Cc David S. Miller <[email protected]>
Cc Giuseppe Cavallaro <[email protected]>
Cc Alexandre Torgue <[email protected]>
Jose Abreu (3):
net: stmmac: Implement RX Coalesce Frames setting
net: stmmac: Fix descriptors address being in > 32 bits address space
net: stmmac: Introducing support for Page Pool
drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 + drivers/net/ethernet/stmicro/stmmac/common.h | 1 + drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 8 +- .../net/ethernet/stmicro/stmmac/dwmac1000_dma.c | 8 +- drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c | 8 +- drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 8 +- drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | 2 + drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 10 +- drivers/net/ethernet/stmicro/stmmac/hwif.h | 4 +- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 12 +- .../net/ethernet/stmicro/stmmac/stmmac_ethtool.c | 7 +- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 215 +++++++-------------- 12 files changed, 112 insertions(+), 172 deletions(-)
Signature · 7 lines
2.7.4 _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH v2 1/3 net: stmmac: Implement RX Coalesce Frames setting
Add support for coalescing RX path by specifying number of frames which don't need to have interrupt on completion bit set.
This is only available when RX Watchdog is enabled.
Acked-by Jakub Kicinski <[email protected]>
Signed-off-by Jose Abreu <[email protected]>
Cc Joao Pinto <[email protected]>
Cc David S. Miller <[email protected]>
Cc Giuseppe Cavallaro <[email protected]>
Cc Alexandre Torgue <[email protected]>
Cc Jakub Kicinski <[email protected]>
--- drivers/net/ethernet/stmicro/stmmac/common.h | 1 + drivers/net/ethernet/stmicro/stmmac/stmmac.h | 2 ++ drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c | 7 +++++-- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 18 ++++++++++++------ 4 files changed, 20 insertions(+), 8 deletions(-)
drivers/net/ethernet/stmicro/stmmac/common.h +1 -0
@@ -252,6 +252,7 @@ struct stmmac_safety_stats {#define STMMAC_MAX_COAL_TX_TICK 100000#define STMMAC_TX_MAX_FRAMES 256#define STMMAC_TX_FRAMES 1 +#define STMMAC_RX_FRAMES 25/* Packets types */ enum packets_types {
drivers/net/ethernet/stmicro/stmmac/stmmac.h +2 -0
@@ -55,6 +55,7 @@ struct stmmac_tx_queue { };struct stmmac_rx_queue { +u32 rx_count_frames;u32 queue_index;struct stmmac_priv *priv_data;struct dma_extended_desc *dma_erx;
@@ -110,6 +111,7 @@ struct stmmac_priv {/* Frequently used values are kept adjacent for cache effect */ u32 tx_coal_frames;u32 tx_coal_timer; +u32 rx_coal_frames;int tx_coalesce;int hwts_tx_en;
drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c +5 -2
@@ -701,8 +701,10 @@ static int stmmac_get_coalesce(struct net_device *dev, ec->tx_coalesce_usecs = priv->tx_coal_timer; ec->tx_max_coalesced_frames = priv->tx_coal_frames; -if (priv->use_riwt) +if (priv->use_riwt) { + ec->rx_max_coalesced_frames = priv->rx_coal_frames; ec->rx_coalesce_usecs =stmmac_riwt2usec (priv->rx_riwt, priv); + }return 0 ; }
@@ -715,7 +717,7 @@ static int stmmac_set_coalesce(struct net_device *dev,unsigned int rx_riwt;/* Check not supported parameters */ - if ((ec->rx_max_coalesced_frames) || (ec->rx_coalesce_usecs_irq) || + if ((ec->rx_coalesce_usecs_irq) || (ec->rx_max_coalesced_frames_irq) || (ec->tx_coalesce_usecs_irq) || (ec->use_adaptive_rx_coalesce) || (ec->use_adaptive_tx_coalesce) || (ec->pkt_rate_low) || (ec->rx_coalesce_usecs_low) ||
@@ -749,6 +751,7 @@ static int stmmac_set_coalesce(struct net_device *dev,/* Only copy relevant parameters, ignore all others. */ priv->tx_coal_frames = ec->tx_max_coalesced_frames; priv->tx_coal_timer = ec->tx_coalesce_usecs; + priv->rx_coal_frames = ec->rx_max_coalesced_frames; priv->rx_riwt = rx_riwt;stmmac_rx_watchdog (priv, priv->ioaddr, priv->rx_riwt, rx_cnt);
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +12 -6
@@ -2268,20 +2268,21 @@ static void stmmac_tx_timer(struct timer_list *t) }/** -* stmmac_init_tx_coalesce - init tx mitigation options. +* stmmac_init_coalesce - init mitigation options. * @priv: driver private structure * Description: -* This inits the transmit coalesce parameters: i.e. timer rate, +* This inits the coalesce parameters: i.e. timer rate, * timer handler and default threshold used for enabling the * interrupt on completion bit. */ -static void stmmac_init_tx_coalesce (struct stmmac_priv *priv) +static void stmmac_init_coalesce (struct stmmac_priv *priv) {u32 tx_channel_count = priv->plat->tx_queues_to_use;u32 chan; priv->tx_coal_frames =STMMAC_TX_FRAMES ; priv->tx_coal_timer =STMMAC_COAL_TX_TIMER ; + priv->rx_coal_frames =STMMAC_RX_FRAMES ;for (chan =0 ; chan < tx_channel_count; chan++) {struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
@@ -2651,7 +2652,7 @@ static int stmmac_open(struct net_device *dev) goto init_error; } -stmmac_init_tx_coalesce (priv); +stmmac_init_coalesce (priv);phylink_start (priv->phylink);
@@ -3298,6 +3299,7 @@ static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)while (dirty-- >0 ) {struct dma_desc *p; +bool use_rx_wd;if (priv->extend_desc) p = (struct dma_desc *)(rx_q->dma_erx + entry);
@@ -3340,7 +3342,11 @@ static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) }dma_wmb (); -stmmac_set_rx_owner (priv, p, priv->use_riwt); + rx_q->rx_count_frames++; + rx_q->rx_count_frames %= priv->rx_coal_frames; + use_rx_wd = priv->use_riwt && rx_q->rx_count_frames; + +stmmac_set_rx_owner (priv, p, use_rx_wd);dma_wmb ();
@@ -4623,7 +4629,7 @@ int stmmac_resume(struct device *dev)stmmac_clear_descriptors (priv);stmmac_hw_setup (ndev, false); -stmmac_init_tx_coalesce (priv); +stmmac_init_coalesce (priv);stmmac_set_rx_mode (ndev);stmmac_enable_all_queues (priv);
Signature · 1 line
2.7.4
PATCH v2 2/3 net: stmmac: Fix descriptors address being in > 32 bits address space
In reply to Jose AbreuCommit a993db88d17d ("net: stmmac: Enable support for > 32 Bits addressing in XGMAC"), introduced support for > 32 bits addressing in XGMAC but the conversion of descriptors to dma_addr_t was left out.
As some devices assing coherent memory in regions > 32 bits we need to set lower and upper value of descriptors address when initializing DMA channels.
Luckly, this was working for me because I was assigning CMA to < 4GB address space for performance reasons.
Fixes a993db88d17d ("net: stmmac: Enable support for > 32 Bits addressing in XGMAC")
Signed-off-by Jose Abreu <[email protected]>
Cc Joao Pinto <[email protected]>
Cc David S. Miller <[email protected]>
Cc Giuseppe Cavallaro <[email protected]>
Cc Alexandre Torgue <[email protected]>
Cc Maxime Coquelin <[email protected]>
Cc Maxime Ripard <[email protected]>
Cc Chen-Yu Tsai <[email protected]>
--- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 8 ++++---- drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c | 8 ++++---- drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c | 8 ++++---- drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 8 ++++---- drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | 2 ++ drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 10 ++++++---- drivers/net/ethernet/stmicro/stmmac/hwif.h | 4 ++-- 7 files changed, 26 insertions(+), 22 deletions(-)
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +4 -4
@@ -289,18 +289,18 @@ static void sun8i_dwmac_dma_init(void __iomem *ioaddr,static void sun8i_dwmac_dma_init_rx (void __iomem *ioaddr,struct stmmac_dma_cfg *dma_cfg, -u32 dma_rx_phy,u32 chan) +dma_addr_t dma_rx_phy,u32 chan) {/* Write RX descriptors address */ -writel (dma_rx_phy, ioaddr +EMAC_RX_DESC_LIST ); +writel (lower_32_bits (dma_rx_phy), ioaddr +EMAC_RX_DESC_LIST ); }static void sun8i_dwmac_dma_init_tx (void __iomem *ioaddr,struct stmmac_dma_cfg *dma_cfg, -u32 dma_tx_phy,u32 chan) +dma_addr_t dma_tx_phy,u32 chan) {/* Write TX descriptors address */ -writel (dma_tx_phy, ioaddr +EMAC_TX_DESC_LIST ); +writel (lower_32_bits (dma_tx_phy), ioaddr +EMAC_TX_DESC_LIST ); }/* sun8i_dwmac_dump_regs() - Dump EMAC address space
drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c +4 -4
@@ -112,18 +112,18 @@ static void dwmac1000_dma_init(void __iomem *ioaddr,static void dwmac1000_dma_init_rx (void __iomem *ioaddr,struct stmmac_dma_cfg *dma_cfg, -u32 dma_rx_phy,u32 chan) +dma_addr_t dma_rx_phy,u32 chan) {/* RX descriptor base address list must be written into DMA CSR3 */ -writel (dma_rx_phy, ioaddr +DMA_RCV_BASE_ADDR ); +writel (lower_32_bits (dma_rx_phy), ioaddr +DMA_RCV_BASE_ADDR ); }static void dwmac1000_dma_init_tx (void __iomem *ioaddr,struct stmmac_dma_cfg *dma_cfg, -u32 dma_tx_phy,u32 chan) +dma_addr_t dma_tx_phy,u32 chan) {/* TX descriptor base address list must be written into DMA CSR4 */ -writel (dma_tx_phy, ioaddr +DMA_TX_BASE_ADDR ); +writel (lower_32_bits (dma_tx_phy), ioaddr +DMA_TX_BASE_ADDR ); }static u32 dwmac1000_configure_fc (u32 csr6,int rxfifosz)
drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c +4 -4
@@ -31,18 +31,18 @@ static void dwmac100_dma_init(void __iomem *ioaddr,static void dwmac100_dma_init_rx (void __iomem *ioaddr,struct stmmac_dma_cfg *dma_cfg, -u32 dma_rx_phy,u32 chan) +dma_addr_t dma_rx_phy,u32 chan) {/* RX descriptor base addr lists must be written into DMA CSR3 */ -writel (dma_rx_phy, ioaddr +DMA_RCV_BASE_ADDR ); +writel (lower_32_bits (dma_rx_phy), ioaddr +DMA_RCV_BASE_ADDR ); }static void dwmac100_dma_init_tx (void __iomem *ioaddr,struct stmmac_dma_cfg *dma_cfg, -u32 dma_tx_phy,u32 chan) +dma_addr_t dma_tx_phy,u32 chan) {/* TX descriptor base addr lists must be written into DMA CSR4 */ -writel (dma_tx_phy, ioaddr +DMA_TX_BASE_ADDR ); +writel (lower_32_bits (dma_tx_phy), ioaddr +DMA_TX_BASE_ADDR ); }/* Store and Forward capability is not used at all.
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +4 -4
@@ -70,7 +70,7 @@ static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)static void dwmac4_dma_init_rx_chan (void __iomem *ioaddr,struct stmmac_dma_cfg *dma_cfg, -u32 dma_rx_phy,u32 chan) +dma_addr_t dma_rx_phy,u32 chan) {u32 value;u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
@@ -79,12 +79,12 @@ static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr, value = value | (rxpbl <<DMA_BUS_MODE_RPBL_SHIFT );writel (value, ioaddr +DMA_CHAN_RX_CONTROL (chan)); -writel (dma_rx_phy, ioaddr +DMA_CHAN_RX_BASE_ADDR (chan)); +writel (lower_32_bits (dma_rx_phy), ioaddr +DMA_CHAN_RX_BASE_ADDR (chan)); }static void dwmac4_dma_init_tx_chan (void __iomem *ioaddr,struct stmmac_dma_cfg *dma_cfg, -u32 dma_tx_phy,u32 chan) +dma_addr_t dma_tx_phy,u32 chan) {u32 value;u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
@@ -97,7 +97,7 @@ static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr,writel (value, ioaddr +DMA_CHAN_TX_CONTROL (chan)); -writel (dma_tx_phy, ioaddr +DMA_CHAN_TX_BASE_ADDR (chan)); +writel (lower_32_bits (dma_tx_phy), ioaddr +DMA_CHAN_TX_BASE_ADDR (chan)); } static void dwmac4_dma_init_channel(void __iomem *ioaddr,
drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h +2 -0
@@ -199,7 +199,9 @@#define XGMAC_RxPBL GENMASK(21, 16)#define XGMAC_RxPBL_SHIFT 16#define XGMAC_RXST BIT(0) +#define XGMAC_DMA_CH_TxDESC_HADDR (x) (0x00003110 + (0x80 * (x)))#define XGMAC_DMA_CH_TxDESC_LADDR (x) (0x00003114 + (0x80 * (x))) +#define XGMAC_DMA_CH_RxDESC_HADDR (x) (0x00003118 + (0x80 * (x)))#define XGMAC_DMA_CH_RxDESC_LADDR (x) (0x0000311c + (0x80 * (x)))#define XGMAC_DMA_CH_TxDESC_TAIL_LPTR (x) (0x00003124 + (0x80 * (x)))#define XGMAC_DMA_CH_RxDESC_TAIL_LPTR (x) (0x0000312c + (0x80 * (x)))
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c +6 -4
@@ -44,7 +44,7 @@ static void dwxgmac2_dma_init_chan(void __iomem *ioaddr,static void dwxgmac2_dma_init_rx_chan (void __iomem *ioaddr,struct stmmac_dma_cfg *dma_cfg, -u32 dma_rx_phy,u32 chan) +dma_addr_t phy,u32 chan) {u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;u32 value;
@@ -54,12 +54,13 @@ static void dwxgmac2_dma_init_rx_chan(void __iomem *ioaddr, value |= (rxpbl << XGMAC_RxPBL_SHIFT) & XGMAC_RxPBL;writel (value, ioaddr +XGMAC_DMA_CH_RX_CONTROL (chan)); -writel (dma_rx_phy, ioaddr +XGMAC_DMA_CH_RxDESC_LADDR (chan)); +writel (upper_32_bits (phy), ioaddr +XGMAC_DMA_CH_RxDESC_HADDR (chan)); +writel (lower_32_bits (phy), ioaddr +XGMAC_DMA_CH_RxDESC_LADDR (chan)); }static void dwxgmac2_dma_init_tx_chan (void __iomem *ioaddr,struct stmmac_dma_cfg *dma_cfg, -u32 dma_tx_phy,u32 chan) +dma_addr_t phy,u32 chan) {u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;u32 value;
@@ -70,7 +71,8 @@ static void dwxgmac2_dma_init_tx_chan(void __iomem *ioaddr, value |=XGMAC_OSP ;writel (value, ioaddr +XGMAC_DMA_CH_TX_CONTROL (chan)); -writel (dma_tx_phy, ioaddr +XGMAC_DMA_CH_TxDESC_LADDR (chan)); +writel (upper_32_bits (phy), ioaddr +XGMAC_DMA_CH_TxDESC_HADDR (chan)); +writel (lower_32_bits (phy), ioaddr +XGMAC_DMA_CH_TxDESC_LADDR (chan)); }static void dwxgmac2_dma_axi (void __iomem *ioaddr,struct stmmac_axi *axi)
drivers/net/ethernet/stmicro/stmmac/hwif.h +2 -2
@@ -150,10 +150,10 @@ struct stmmac_dma_ops { struct stmmac_dma_cfg *dma_cfg, u32 chan);void (*init_rx_chan)(void __iomem *ioaddr,struct stmmac_dma_cfg *dma_cfg, -u32 dma_rx_phy,u32 chan); +dma_addr_t phy,u32 chan);void (*init_tx_chan)(void __iomem *ioaddr,struct stmmac_dma_cfg *dma_cfg, -u32 dma_tx_phy,u32 chan); +dma_addr_t phy,u32 chan);/* Configure the AXI Bus Mode Register */ void (*axi)(void __iomem *ioaddr,struct stmmac_axi *axi);/* Dump DMA registers */
Signature · 1 line
2.7.4
PATCH v2 3/3 net: stmmac: Introducing support for Page Pool
In reply to Jose AbreuMapping and unmapping DMA region is an high bottleneck in stmmac driver, specially in the RX path.
This commit introduces support for Page Pool API and uses it in all RX queues. With this change, we get more stable troughput and some increase of banwidth with iperf:
- MAC1000 - 950 Mbps
- XGMAC: 9.22 Gbps
Changes from v1:
- Use page_pool_get_dma_addr() (Jesper)
- Add a comment (Jesper)
- Add page_pool_free() call (Jesper)
- Reintroduce sync_single_for_device (Arnd / Ilias)
Signed-off-by Jose Abreu <[email protected]>
Cc Joao Pinto <[email protected]>
Cc David S. Miller <[email protected]>
Cc Giuseppe Cavallaro <[email protected]>
Cc Alexandre Torgue <[email protected]>
Cc Ilias Apalodimas <[email protected]>
Cc Jesper Dangaard Brouer <[email protected]>
Cc Arnd Bergmann <[email protected]>
--- drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 + drivers/net/ethernet/stmicro/stmmac/stmmac.h | 10 +- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 201 +++++++--------------- 3 files changed, 68 insertions(+), 144 deletions(-)
drivers/net/ethernet/stmicro/stmmac/Kconfig +1 -0
@@ -3,6 +3,7 @@ config STMMAC_ETH tristate "STMicroelectronics Multi-Gigabit Ethernet driver" depends on HAS_IOMEM && HAS_DMA select MII + select PAGE_POOL select PHYLINK select CRC32 imply PTP_1588_CLOCK
drivers/net/ethernet/stmicro/stmmac/stmmac.h +8 -2
@@ -20,6 +20,7 @@#include <linux/ptp_clock_kernel.h> #include <linux/net_tstamp.h> #include <linux/reset.h> +#include <net/page_pool.h> struct stmmac_resources {void __iomem *addr;
@@ -54,14 +55,19 @@ struct stmmac_tx_queue {u32 mss; }; +struct stmmac_rx_buffer { +struct page *page; +dma_addr_t addr; +}; +struct stmmac_rx_queue {u32 rx_count_frames;u32 queue_index; +struct page_pool *page_pool; +struct stmmac_rx_buffer *buf_pool;struct stmmac_priv *priv_data;struct dma_extended_desc *dma_erx;struct dma_desc *dma_rx____cacheline_aligned_in_smp ; -struct sk_buff **rx_skbuff; -dma_addr_t *rx_skbuff_dma;unsigned int cur_rx;unsigned int dirty_rx;u32 rx_zeroc_thresh;
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +59 -142
298 lines not on this page · raw message
Signature · 1 line
2.7.4
Re: [PATCH net-next v2 3/3] net: stmmac: Introducing support for Page Pool
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c static void free_dma_rx_desc_resources(struct stmmac_priv *priv) · line 1487
Quoted 11 lines · On Thu, 4 Jul 2019 17:04:14 +0200 Jose Abreu <[email protected]> wrote:
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +3
-2@@ -1498,8 +1480,9 @@ static void free_dma_rx_desc_resources(struct stmmac_priv *priv)sizeof (struct dma_extended_desc ), rx_q->dma_erx, rx_q->dma_rx_phy); -kfree (rx_q->rx_skbuff_dma); -kfree (rx_q->rx_skbuff); +kfree (rx_q->buf_pool); +if (rx_q->page_pool &&page_pool_request_shutdown (rx_q->page_pool)) +page_pool_free (rx_q->page_pool); } }
This code is okay, but I would likely write it as:
if (rx_q->page_pool) {
page_pool_request_shutdown(rx_q->page_pool));
page_pool_free(rx_q->page_pool);}
Because (as you noticed) page_pool_free() have some API misuse checks, that will get triggered, and thus provide a warning of you forget to update this when driver evolves.
Signature · 4 lines
Best regards, Jesper Dangaard Brouer MSc.CS, Principal Kernel Engineer at Red Hat LinkedIn: http://www.linkedin.com/in/brouer
RE: [PATCH net-next v2 3/3] net: stmmac: Introducing support for Page Pool
From: Jesper Dangaard Brouer <[email protected]>
Quoted 10 lines
This code is okay, but I would likely write it as:
if (rx_q->page_pool) { page_pool_request_shutdown(rx_q->page_pool)); page_pool_free(rx_q->page_pool);}
Because (as you noticed)
page_pool_free()have some API misuse checks, that will get triggered, and thus provide a warning of you forget to update this when driver evolves.
Yeah, makes sense. I will update and resend. Thanks for the review!