drm: bridge: Add NWL MIPI DSI host controller support
Subsystems (6)
v2 cover drm: bridge: Add NWL MIPI DSI host controller support
This adds initial support for the NWL MIPI DSI Host controller found on i.MX8 SoCs.
It adds support for the i.MX8MQ but the same IP core can also be found on e.g. i.MX8QXP. I added the necessary hooks to support other imx8 variants but since I only have imx8mq boards to test I omitted the platform data for other SoCs.
The code is based on NXPs BSP so I added Robert Chiras as Co-authored-by. Robert, if this looks sane could you add your Signed-off-by:?
The most notable changes over the BSP driver are
- Calculate HS mode timing from phy_configure_opts_mipi_dphy
- Perform all clock setup via DT
- Merge nwl-imx and nwl drivers
- Add B0 silion revision quirk
- Become a bridge driver to hook into mxsfb (from what I read[0] DCSS, which also can drive the nwl on the imx8mq will likely not become part of imx-display-subsystem so it makes sense to make it drive a bridge for dsi as well).
- Use panel_bridge to attach the panel
This has been tested on a Librem 5 devkit using mxsfb with Robert's patches[1] and the rocktech-jh057n00900 panel driver on next-20190807. The DCSS can later on also act as input source too.
Changes from v1:
- Per review comments by Sam Ravnborg
https://lists.freedesktop.org/archives/dri-devel/2019-July/228130.html
- Change binding docs to YAML
- build: Don't always visit imx-nwl/
- build: Add header-test-y
- Sort headers according to DRM convention
- Use drm_display_mode instead of videmode
- Per review comments by Fabio Estevam
https://lists.freedesktop.org/archives/dri-devel/2019-July/228299.html
- Don't restrict build to ARCH_MXC
- Drop unused includes
- Drop unreachable code in imx_nwl_dsi_bridge_mode_fixup()
- Drop remaining calls of dev_err() and use DRM_DEV_ERR() consistently.
- Use devm_platform_ioremap_resource()
- Drop devm_free_irq() in probe() error path
- Use single line comments where sufficient
- Use <linux/time64.h> instead of defining USEC_PER_SEC
- Make input source select imx8 specific
- Drop <asm/unaligned.h> inclusion (after removal of get_unaligned_le32)
- Drop all EXPORT_SYMBOL_GPL() for functions used in the same module but different source files.
- Drop nwl_dsi_enable_{rx,tx}_clock() by invoking clk_prepare_enable() directly
- Remove pointless comment
- Laurent Pinchart
https://lists.freedesktop.org/archives/dri-devel/2019-July/228313.html
https://lists.freedesktop.org/archives/dri-devel/2019-July/228308.html
- Drop (on iMX8MQ) unused csr regmap
- Use NWL_MAX_PLATFORM_CLOCKS everywhere
- Drop get_unaligned_le32() usage
- remove duplicate 'for the' in binding docs
- Don't include unused <linux/clk-provider.h>
- Don't include unused <linux/component.h>
- Drop dpms_mode for tracking state, trust the drm layer on that
- Use pm_runtime_put() instead of pm_runtime_put_sync()
- Don't overwrite encoder type
- Make imx_nwl_platform_data const
- Use the reset controller API instead of open coding that platform specific part
- Use <linux/bitfield.h> intead of making up our own defines
- name mipi_dsi_transfer less generic: nwl_dsi_transfer
- ensure clean in .remove by calling mipi_dsi_host_unregister.
- prefix constants by NWL_DSI_
- properly format transfer_direction enum
- simplify platform clock handling
- Don't modify state in mode_fixup() and use mode_set() instead
- Drop bridge detach(), already handle by nwl_dsi_host_detach()
- Drop USE_*_QUIRK() macros
- Drop (for now) unused clock defnitions. 'pixel' and 'bypass' clock will be used for i.MX8 SoCs but since they're unused atm drop the definitions - but keep the logic to enable/disable several clocks in place since we know we'll need it in the future.
Changes from v0:
- Add quirk for IMQ8MQ silicon B0 revision to not mess with the system reset controller on power down since enable() won't work otherwise.
- Drop devm_free_irq() handled by the device driver core
- Disable tx esc clock after the phy power down to unbreak disable/enable (unblank/blank)
- Add ports to dt binding docs
- Select GENERIC_PHY_MIPI_DPHY instead of GENERIC_PHY for phy_mipi_dphy_get_default_config
- Select DRM_MIPI_DSI
- Include drm_print.h to fix build on next-20190408
- Drop some debugging messages
- Newline terminate all DRM_ printouts
- Turn component driver into a drm bridge
[0]: https://lists.freedesktop.org/archives/dri-devel/2019-May/219484.html
[1]: https://patchwork.freedesktop.org/series/62822/
Guido Günther (3):
arm64: imx8mq: add imx8mq iomux-gpr field defines
dt-bindings: display/bridge: Add binding for NWL mipi dsi host
controller
drm/bridge: Add NWL MIPI DSI host controller support
.../bindings/display/bridge/nwl-dsi.yaml | 155 ++++ drivers/gpu/drm/bridge/Kconfig | 2 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/nwl-dsi/Kconfig | 15 + drivers/gpu/drm/bridge/nwl-dsi/Makefile | 4 + drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.c | 484 ++++++++++++ drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.h | 66 ++ drivers/gpu/drm/bridge/nwl-dsi/nwl-dsi.c | 700 ++++++++++++++++++ drivers/gpu/drm/bridge/nwl-dsi/nwl-dsi.h | 112 +++ include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h | 62 ++ 10 files changed, 1601 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml create mode 100644 drivers/gpu/drm/bridge/nwl-dsi/Kconfig create mode 100644 drivers/gpu/drm/bridge/nwl-dsi/Makefile create mode 100644 drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.c create mode 100644 drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.h create mode 100644 drivers/gpu/drm/bridge/nwl-dsi/nwl-dsi.c create mode 100644 drivers/gpu/drm/bridge/nwl-dsi/nwl-dsi.h create mode 100644 include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h
Signature · 6 lines
2.20.1 _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
PATCH v2 1/3 arm64: imx8mq: add imx8mq iomux-gpr field defines
This adds all the gpr registers and the define needed for selecting the input source in the imx-nwl drm bridge.
--- include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h | 62 ++++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h
include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h new file +62 -0
@@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +* Copyright (C) 2017 NXP +* 2019 Purism SPC +*/ + +#ifndef __LINUX_IMX8MQ_IOMUXC_GPR_H +#define __LINUX_IMX8MQ_IOMUXC_GPR_H + +#define IOMUXC_GPR0 0x00 +#define IOMUXC_GPR1 0x04 +#define IOMUXC_GPR2 0x08 +#define IOMUXC_GPR3 0x0c +#define IOMUXC_GPR4 0x10 +#define IOMUXC_GPR5 0x14 +#define IOMUXC_GPR6 0x18 +#define IOMUXC_GPR7 0x1c +#define IOMUXC_GPR8 0x20 +#define IOMUXC_GPR9 0x24 +#define IOMUXC_GPR10 0x28 +#define IOMUXC_GPR11 0x2c +#define IOMUXC_GPR12 0x30 +#define IOMUXC_GPR13 0x34 +#define IOMUXC_GPR14 0x38 +#define IOMUXC_GPR15 0x3c +#define IOMUXC_GPR16 0x40 +#define IOMUXC_GPR17 0x44 +#define IOMUXC_GPR18 0x48 +#define IOMUXC_GPR19 0x4c +#define IOMUXC_GPR20 0x50 +#define IOMUXC_GPR21 0x54 +#define IOMUXC_GPR22 0x58 +#define IOMUXC_GPR23 0x5c +#define IOMUXC_GPR24 0x60 +#define IOMUXC_GPR25 0x64 +#define IOMUXC_GPR26 0x68 +#define IOMUXC_GPR27 0x6c +#define IOMUXC_GPR28 0x70 +#define IOMUXC_GPR29 0x74 +#define IOMUXC_GPR30 0x78 +#define IOMUXC_GPR31 0x7c +#define IOMUXC_GPR32 0x80 +#define IOMUXC_GPR33 0x84 +#define IOMUXC_GPR34 0x88 +#define IOMUXC_GPR35 0x8c +#define IOMUXC_GPR36 0x90 +#define IOMUXC_GPR37 0x94 +#define IOMUXC_GPR38 0x98 +#define IOMUXC_GPR39 0x9c +#define IOMUXC_GPR40 0xa0 +#define IOMUXC_GPR41 0xa4 +#define IOMUXC_GPR42 0xa8 +#define IOMUXC_GPR43 0xac +#define IOMUXC_GPR44 0xb0 +#define IOMUXC_GPR45 0xb4 +#define IOMUXC_GPR46 0xb8 +#define IOMUXC_GPR47 0xbc + +/* i.MX8Mq iomux gpr register field defines */ +#define IMX8MQ_GPR13_MIPI_MUX_SEL BIT(2) + +#endif /* __LINUX_IMX8MQ_IOMUXC_GPR_H */
Signature · 1 line
2.20.1
Re: [PATCH v2 1/3] arm64: imx8mq: add imx8mq iomux-gpr field defines
Quoted 8 lines · Guido Günther
This adds all the gpr registers and the define needed for selecting the input source in the imx-nwl drm bridge.
Signed-off-by Guido Günther <[email protected]>--- include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h | 62 ++++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h
I would like Arnd to look at this please.
Quoted 68 lines
include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h new file +62
-0@@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +* Copyright (C) 2017 NXP +* 2019 Purism SPC +*/ + +#ifndef __LINUX_IMX8MQ_IOMUXC_GPR_H +#define __LINUX_IMX8MQ_IOMUXC_GPR_H + +#define IOMUXC_GPR0 0x00 +#define IOMUXC_GPR1 0x04 +#define IOMUXC_GPR2 0x08 +#define IOMUXC_GPR3 0x0c +#define IOMUXC_GPR4 0x10 +#define IOMUXC_GPR5 0x14 +#define IOMUXC_GPR6 0x18 +#define IOMUXC_GPR7 0x1c +#define IOMUXC_GPR8 0x20 +#define IOMUXC_GPR9 0x24 +#define IOMUXC_GPR10 0x28 +#define IOMUXC_GPR11 0x2c +#define IOMUXC_GPR12 0x30 +#define IOMUXC_GPR13 0x34 +#define IOMUXC_GPR14 0x38 +#define IOMUXC_GPR15 0x3c +#define IOMUXC_GPR16 0x40 +#define IOMUXC_GPR17 0x44 +#define IOMUXC_GPR18 0x48 +#define IOMUXC_GPR19 0x4c +#define IOMUXC_GPR20 0x50 +#define IOMUXC_GPR21 0x54 +#define IOMUXC_GPR22 0x58 +#define IOMUXC_GPR23 0x5c +#define IOMUXC_GPR24 0x60 +#define IOMUXC_GPR25 0x64 +#define IOMUXC_GPR26 0x68 +#define IOMUXC_GPR27 0x6c +#define IOMUXC_GPR28 0x70 +#define IOMUXC_GPR29 0x74 +#define IOMUXC_GPR30 0x78 +#define IOMUXC_GPR31 0x7c +#define IOMUXC_GPR32 0x80 +#define IOMUXC_GPR33 0x84 +#define IOMUXC_GPR34 0x88 +#define IOMUXC_GPR35 0x8c +#define IOMUXC_GPR36 0x90 +#define IOMUXC_GPR37 0x94 +#define IOMUXC_GPR38 0x98 +#define IOMUXC_GPR39 0x9c +#define IOMUXC_GPR40 0xa0 +#define IOMUXC_GPR41 0xa4 +#define IOMUXC_GPR42 0xa8 +#define IOMUXC_GPR43 0xac +#define IOMUXC_GPR44 0xb0 +#define IOMUXC_GPR45 0xb4 +#define IOMUXC_GPR46 0xb8 +#define IOMUXC_GPR47 0xbc + +/* i.MX8Mq iomux gpr register field defines */ +#define IMX8MQ_GPR13_MIPI_MUX_SEL BIT(2) + +#endif /* __LINUX_IMX8MQ_IOMUXC_GPR_H */
Signature · 4 lines
Lee Jones [李琼斯] Linaro Services Technical Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog
Re: [PATCH v2 1/3] arm64: imx8mq: add imx8mq iomux-gpr field defines
In reply to Guido GüntherQuoted 5 lines · Guido Günther
This adds all the gpr registers and the define needed for selecting the input source in the imx-nwl drm bridge.
Signed-off-by Guido Günther <[email protected]>
include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h line 17
Quoted 9 lines
include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h new file +9
-0+ +#define IOMUXC_GPR0 0x00 +#define IOMUXC_GPR1 0x04 +#define IOMUXC_GPR2 0x08 +#define IOMUXC_GPR3 0x0c +#define IOMUXC_GPR4 0x10 +#define IOMUXC_GPR5 0x14 +#define IOMUXC_GPR6 0x18 +#define IOMUXC_GPR7 0x1c
(more of the same)
huh?
include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h line 60
Quoted 2 lines
include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h new file +2
-0+/* i.MX8Mq iomux gpr register field defines */ +#define IMX8MQ_GPR13_MIPI_MUX_SEL BIT(2)
I think this define should probably be local to the pinctrl driver, to ensure that no other drivers fiddle with the registers manually.
Arnd
Re: [PATCH v2 1/3] arm64: imx8mq: add imx8mq iomux-gpr field defines
Hi Arnd,
Quoted 17 lines · Arnd Bergmann
Quoted 5 lines · Guido Günther
This adds all the gpr registers and the define needed for selecting the input source in the imx-nwl drm bridge.
Signed-off-by Guido Günther <[email protected]>include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h line 17
Quoted 9 lines
include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h new file +9
-0+ +#define IOMUXC_GPR0 0x00 +#define IOMUXC_GPR1 0x04 +#define IOMUXC_GPR2 0x08 +#define IOMUXC_GPR3 0x0c +#define IOMUXC_GPR4 0x10 +#define IOMUXC_GPR5 0x14 +#define IOMUXC_GPR6 0x18 +#define IOMUXC_GPR7 0x1c(more of the same)
Quoted 1 line
huh?
These are the names from the imx8MQ reference manual (general purpose registers, they lump together all sorts of things), it's the same on imx6/imx7):
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/linux/mfd/syscon/imx7-iomuxc-gpr.h
Quoted 5 lines
include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h line 60
Quoted 2 lines
include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h new file +2
-0+/* i.MX8Mq iomux gpr register field defines */ +#define IMX8MQ_GPR13_MIPI_MUX_SEL BIT(2)I think this define should probably be local to the pinctrl driver, to ensure that no other drivers fiddle with the registers manually.
The purpose of these bits is for a driver to fiddle with them to select the input source. Similar on imx7 it's already used for e.g. the phy refclk in the pci controller:
The GPRs are not about pad configuration but gather all sorts of things (section 8.2.4 of the imx8mq reference manual): pcie setup, dsi related bits so I don't think this should be done via a pinctrl driver. Should we handle that differently than on imx6/7?
Cheers,
-- Guido
_______________________________________________
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[email protected]
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Re: [PATCH v2 1/3] arm64: imx8mq: add imx8mq iomux-gpr field defines
Quoted 33 lines · Guido Günther
Quoted 17 lines · Arnd Bergmann
Quoted 5 lines · Guido Günther
This adds all the gpr registers and the define needed for selecting the input source in the imx-nwl drm bridge.
Signed-off-by Guido Günther <[email protected]>include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h line 17
Quoted 9 lines
include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h new file +9
-0+ +#define IOMUXC_GPR0 0x00 +#define IOMUXC_GPR1 0x04 +#define IOMUXC_GPR2 0x08 +#define IOMUXC_GPR3 0x0c +#define IOMUXC_GPR4 0x10 +#define IOMUXC_GPR5 0x14 +#define IOMUXC_GPR6 0x18 +#define IOMUXC_GPR7 0x1c(more of the same)
Quoted 1 line
huh?
These are the names from the imx8MQ reference manual (general purpose registers, they lump together all sorts of things), it's the same on imx6/imx7):
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/linux/mfd/syscon/imx7-iomuxc-gpr.hQuoted 5 lines
include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h line 60
Quoted 2 lines
include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h new file +2
-0+/* i.MX8Mq iomux gpr register field defines */ +#define IMX8MQ_GPR13_MIPI_MUX_SEL BIT(2)I think this define should probably be local to the pinctrl driver, to ensure that no other drivers fiddle with the registers manually.
Quoted 5 lines
The purpose of these bits is for a driver to fiddle with them to select the input source. Similar on imx7 it's already used for e.g. the phy refclk in the pci controller:
That one should likely use either the clk interface or the phy interface instead.
Quoted 4 lines
The GPRs are not about pad configuration but gather all sorts of things (section 8.2.4 of the imx8mq reference manual): pcie setup, dsi related bits so I don't think this should be done via a pinctrl driver. Should we handle that differently than on imx6/7?
It would be nice to fix the existing code as well, but for the moment, I only think we should not add more of that.
Generally speaking, we can use syscon to do random things that don't have a subsystem of their own, but we should not use it to do things that have an existing driver framework like pinctrl, clock, reset, phy etc.
Arnd
Re: [PATCH v2 1/3] arm64: imx8mq: add imx8mq iomux-gpr field defines
Hi,
Quoted 48 lines · Arnd Bergmann
Quoted 33 lines · Guido Günther
Quoted 17 lines · Arnd Bergmann
Quoted 5 lines · Guido Günther
This adds all the gpr registers and the define needed for selecting the input source in the imx-nwl drm bridge.
Signed-off-by Guido Günther <[email protected]>include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h line 17
Quoted 9 lines
include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h new file +9
-0+ +#define IOMUXC_GPR0 0x00 +#define IOMUXC_GPR1 0x04 +#define IOMUXC_GPR2 0x08 +#define IOMUXC_GPR3 0x0c +#define IOMUXC_GPR4 0x10 +#define IOMUXC_GPR5 0x14 +#define IOMUXC_GPR6 0x18 +#define IOMUXC_GPR7 0x1c(more of the same)
Quoted 1 line
huh?
These are the names from the imx8MQ reference manual (general purpose registers, they lump together all sorts of things), it's the same on imx6/imx7):
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/linux/mfd/syscon/imx7-iomuxc-gpr.hQuoted 5 lines
include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h line 60
Quoted 2 lines
include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h new file +2
-0+/* i.MX8Mq iomux gpr register field defines */ +#define IMX8MQ_GPR13_MIPI_MUX_SEL BIT(2)I think this define should probably be local to the pinctrl driver, to ensure that no other drivers fiddle with the registers manually.
Quoted 5 lines
The purpose of these bits is for a driver to fiddle with them to select the input source. Similar on imx7 it's already used for e.g. the phy refclk in the pci controller:
That one should likely use either the clk interface or the phy interface instead.
Quoted 4 lines
The GPRs are not about pad configuration but gather all sorts of things (section 8.2.4 of the imx8mq reference manual): pcie setup, dsi related bits so I don't think this should be done via a pinctrl driver. Should we handle that differently than on imx6/7?
Quoted 7 lines
It would be nice to fix the existing code as well, but for the moment, I only think we should not add more of that.
Generally speaking, we can use syscon to do random things that don't have a subsystem of their own, but we should not use it to do things that have an existing driver framework like pinctrl, clock, reset, phy etc.
Since it's not an external pin i opted to use MUX_MMIO instead which seems like a good fit here. Does that make sense?
Cheers,
-- Guido
Re: [PATCH v2 1/3] arm64: imx8mq: add imx8mq iomux-gpr field defines
Quoted 54 lines · Guido Günther
Hi,
Quoted 52 lines · Arnd Bergmann
Quoted 34 lines · Guido Günther
Quoted 18 lines · Arnd Bergmann
Quoted 5 lines · Guido Günther
This adds all the gpr registers and the define needed for selecting the input source in the imx-nwl drm bridge.
Signed-off-by Guido Günther <[email protected]>include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h line 17
Quoted 9 lines
include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h new file +9
-0+ +#define IOMUXC_GPR0 0x00 +#define IOMUXC_GPR1 0x04 +#define IOMUXC_GPR2 0x08 +#define IOMUXC_GPR3 0x0c +#define IOMUXC_GPR4 0x10 +#define IOMUXC_GPR5 0x14 +#define IOMUXC_GPR6 0x18 +#define IOMUXC_GPR7 0x1c(more of the same)
Quoted 1 line
huh?
These are the names from the imx8MQ reference manual (general purpose registers, they lump together all sorts of things), it's the same on imx6/imx7):
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/linux/mfd/syscon/imx7-iomuxc-gpr.hQuoted 5 lines
include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h line 60
Quoted 2 lines
include/linux/mfd/syscon/imx8mq-iomuxc-gpr.h new file +2
-0+/* i.MX8Mq iomux gpr register field defines */ +#define IMX8MQ_GPR13_MIPI_MUX_SEL BIT(2)I think this define should probably be local to the pinctrl driver, to ensure that no other drivers fiddle with the registers manually.
Quoted 5 lines
The purpose of these bits is for a driver to fiddle with them to select the input source. Similar on imx7 it's already used for e.g. the phy refclk in the pci controller:
That one should likely use either the clk interface or the phy interface instead.
Quoted 4 lines
The GPRs are not about pad configuration but gather all sorts of things (section 8.2.4 of the imx8mq reference manual): pcie setup, dsi related bits so I don't think this should be done via a pinctrl driver. Should we handle that differently than on imx6/7?
It would be nice to fix the existing code as well, but for the moment, I only think we should not add more of that.
Quoted 7 lines
Quoted 4 lines
Generally speaking, we can use syscon to do random things that don't have a subsystem of their own, but we should not use it to do things that have an existing driver framework like pinctrl, clock, reset, phy etc.
Since it's not an external pin i opted to use
MUX_MMIOinstead which seems like a good fit here. Does that make sense?
Yes, I agree. The i.MX6 display subsystem predates the mux framework, otherwise I would have used it for the LVDS and HDMI muxes in the first place. We should probably switch imx-drm over as well, in a backwards compatible fashion. The &mux definitions are already there in arch/arm/boot/dts/imx6q.dtsi.
regards
Philipp
PATCH v2 2/3 dt-bindings: display/bridge: Add binding for NWL mipi dsi host controller
In reply to Guido GüntherThe Northwest Logic MIPI DSI IP core can be found in NXPs i.MX8 SoCs.
--- .../bindings/display/bridge/nwl-dsi.yaml | 155 ++++++++++++++++++ 1 file changed, 155 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +155 -0
@@ -0,0 +1,155 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/imx-nwl-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Northwest Logic MIPI-DSI on imx SoCs + +maintainers: + - Guido Gúnther <[email protected]> + - Robert Chiras <[email protected]> + +description: | + NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for + the SOCs NWL MIPI-DSI host controller. + +properties: + compatible: + oneOf: + - items: + - const: fsl,imx8mq-nwl-dsi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: DSI core clock + - description: RX_ESC clock (used in escape mode) + - description: TX_ESC clock (used in escape mode) + - description: PHY_REF clock + + clock-names: + items: + - const: core + - const: rx_esc + - const: tx_esc + - const: phy_ref + + phys: + maxItems: 1 + description: + A phandle to the phy module representing the DPHY + + phy-names: + items: + - const: dphy + + power-domains: + maxItems: 1 + description: + A phandle to the power domain + + resets: + maxItems: 4 + description: + A phandle to the reset controller + + reset-names: + items: + - const: byte + - const: dpi + - const: esc + - const: pclk + + mux-sel: + maxItems: 1 + description: + A phandle to the MUX register set + + port: + type: object + description: + A input put or output port node. + + ports: + type: object + description: + A node containing DSI input & output port nodes with endpoint + definitions as documented in + Documentation/devicetree/bindings/graph.txt. + +patternProperties: + "^panel@[0-9]+$": true + +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8mq-nwl-dsi + then: + required: + - resets + - reset-names + - mux-sel + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - phys + - phy-names + +examples: + - | + + mipi_dsi: mipi_dsi@30a00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mq-nwl-dsi"; + reg = <0x30A00000 0x300>; + clocks = <&clk 163>, <&clk 244>, <&clk 245>, <&clk 164>; + clock-names = "core", "rx_esc", "tx_esc", "phy_ref"; + interrupts = <0 34 4>; + power-domains = <&pgc_mipi>; + resets = <&src 0>, <&src 1>, <&src 2>, <&src 3>; + reset-names = "byte", "dpi", "esc", "pclk"; + mux-sel = <&iomuxc_gpr>; + phys = <&dphy>; + phy-names = "dphy"; + + panel@0 { + compatible = "..."; + port@0 { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mipi_dsi_in: endpoint { + remote-endpoint = <&lcdif_mipi_dsi>; + }; + }; + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + };
Signature · 6 lines
2.20.1 _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2 2/3] dt-bindings: display/bridge: Add binding for NWL mipi dsi host controller
Quoted 26 lines · Guido Günther
The Northwest Logic MIPI DSI IP core can be found in NXPs i.MX8 SoCs.
Signed-off-by Guido Günther <[email protected]>--- .../bindings/display/bridge/nwl-dsi.yaml | 155 ++++++++++++++++++ 1 file changed, 155 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/nwl-dsi.yamlDocumentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +11
-0@@ -0,0 +1,155 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/imx-nwl-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Northwest Logic MIPI-DSI on imx SoCs + +maintainers: + - Guido Gúnther <[email protected]> + - Robert Chiras <[email protected]>
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml line 21
Quoted 10 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +10
-0+ +description: | + NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for + the SOCs NWL MIPI-DSI host controller. + +properties: + compatible: + oneOf: + - items: + - const: fsl,imx8mq-nwl-dsi
Don't need oneOf nor items here for a single possible value:
compatible:
const: fsl,imx8mq-nwl-dsi
Or go ahead and add other compatibles because the 'if' below seems to indicate you'll have more.
Quoted 29 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +29
-0+ + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: DSI core clock + - description: RX_ESC clock (used in escape mode) + - description: TX_ESC clock (used in escape mode) + - description: PHY_REF clock + + clock-names: + items: + - const: core + - const: rx_esc + - const: tx_esc + - const: phy_ref + + phys: + maxItems: 1 + description: + A phandle to the phy module representing the DPHY + + phy-names: + items: + - const: dphy
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml line 60
Quoted 10 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +10
-0+ + power-domains: + maxItems: 1 + description: + A phandle to the power domain + + resets: + maxItems: 4 + description: + A phandle to the reset controller
Sounds like 4 phandles... This should look similar to 'clocks'.
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml line 69
Quoted 9 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +9
-0+ + reset-names: + items: + - const: byte + - const: dpi + - const: esc + - const: pclk + + mux-sel:
Needs a vendor prefix and will need a $ref to the type.
Quoted 5 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +5
-0+ maxItems: 1 + description: + A phandle to the MUX register set + + port:
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml line 84
Quoted 10 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +10
-0+ type: object + description: + A input put or output port node. + + ports: + type: object + description: + A node containing DSI input & output port nodes with endpoint + definitions as documented in + Documentation/devicetree/bindings/graph.txt.
You need to define what port@0 and port@1 are.
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml line 95
Quoted 11 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +11
-0+ +patternProperties: + "^panel@[0-9]+$": true + +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8mq-nwl-dsi
This conditional isn't needed until you have more than one compatible.
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml line 109
Quoted 13 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +13
-0+ required: + - resets + - reset-names + - mux-sel + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - phys + - phy-names
ports should be required.
Quoted 11 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +11
-0+ +examples: + - | + + mipi_dsi: mipi_dsi@30a00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mq-nwl-dsi"; + reg = <0x30A00000 0x300>; + clocks = <&clk 163>, <&clk 244>, <&clk 245>, <&clk 164>; + clock-names = "core", "rx_esc", "tx_esc", "phy_ref";
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml line 130
Quoted 10 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +10
-0+ interrupts = <0 34 4>; + power-domains = <&pgc_mipi>; + resets = <&src 0>, <&src 1>, <&src 2>, <&src 3>; + reset-names = "byte", "dpi", "esc", "pclk"; + mux-sel = <&iomuxc_gpr>; + phys = <&dphy>; + phy-names = "dphy"; + + panel@0 { + compatible = "...";
Needs to be a valid compatible. Also need 'reg' here or drop the unit-address.
Quoted 28 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +25
-1+ port@0 { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mipi_dsi_in: endpoint { + remote-endpoint = <&lcdif_mipi_dsi>; + }; + }; + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; --2.20.1
Re: [PATCH v2 2/3] dt-bindings: display/bridge: Add binding for NWL mipi dsi host controller
Hi Rob,
thanks for having a look!
Quoted 31 lines · Rob Herring
Quoted 30 lines · Guido Günther
The Northwest Logic MIPI DSI IP core can be found in NXPs i.MX8 SoCs.
Signed-off-by Guido Günther <[email protected]>--- .../bindings/display/bridge/nwl-dsi.yaml | 155 ++++++++++++++++++ 1 file changed, 155 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/nwl-dsi.yamlDocumentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +15
-0@@ -0,0 +1,155 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/imx-nwl-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Northwest Logic MIPI-DSI on imx SoCs + +maintainers: + - Guido Gúnther <[email protected]> + - Robert Chiras <[email protected]> + +description: | + NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for + the SOCs NWL MIPI-DSI host controller.
Quoted 8 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml line 21
Quoted 6 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +6
-0+ +properties: + compatible: + oneOf: + - items: + - const: fsl,imx8mq-nwl-dsiDon't need oneOf nor items here for a single possible value:
I wanted to prepare for adding other SoCs so there's less diff noise (other imx8 SoCs will be rather simple) but let's go with 'const' for now then.
Quoted 38 lines
compatible:
const: fsl,imx8mq-nwl-dsiOr go ahead and add other compatibles because the 'if' below seems to indicate you'll have more.
Quoted 32 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +32
-0+ reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: DSI core clock + - description: RX_ESC clock (used in escape mode) + - description: TX_ESC clock (used in escape mode) + - description: PHY_REF clock + + clock-names: + items: + - const: core + - const: rx_esc + - const: tx_esc + - const: phy_ref + + phys: + maxItems: 1 + description: + A phandle to the phy module representing the DPHY + + phy-names: + items: + - const: dphy + + power-domains: + maxItems: 1 + description:
Quoted 8 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml line 60
Quoted 6 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +6
-0+ A phandle to the power domain + + resets: + maxItems: 4 + description: + A phandle to the reset controllerSounds like 4 phandles... This should look similar to 'clocks'.
Added them individually, will be soc specific too later on.
Quoted 12 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml line 69
Quoted 10 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +9
-0+ + reset-names: + items: + - const: byte + - const: dpi + - const: esc + - const: pclk + + mux-sel:Needs a vendor prefix and will need a $ref to the type.
Made that fsl,mux-sel. This require me to add '$ref:
/schemas/types.yaml#definitions/phandle' as well which I hope is correct.
Quoted 9 lines
Quoted 9 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +9
-0+ maxItems: 1 + description: + A phandle to the MUX register set + + port: + type: object + description: + A input put or output port node. +
Quoted 8 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml line 84
Quoted 6 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +6
-0+ ports: + type: object + description: + A node containing DSI input & output port nodes with endpoint + definitions as documented in + Documentation/devicetree/bindings/graph.txt.You need to define what port@0 and port@1 are.
Added.
Quoted 14 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml line 95
Quoted 12 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +11
-0+ +patternProperties: + "^panel@[0-9]+$": true + +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8mq-nwl-dsiThis conditional isn't needed until you have more than one compatible.
Again intended for other upcoming SoCs but dropped for now.
Quoted 7 lines
Quoted 7 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +7
-0+ required: + - resets + - reset-names + - mux-sel + +required: + - compatible
Quoted 8 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml line 109
Quoted 6 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +6
-0+ - reg + - interrupts + - clocks + - clock-names + - phys + - phy-namesports should be required.
Added.
Quoted 16 lines
Quoted 16 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +16
-0+ +examples: + - | + + mipi_dsi: mipi_dsi@30a00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mq-nwl-dsi"; + reg = <0x30A00000 0x300>; + clocks = <&clk 163>, <&clk 244>, <&clk 245>, <&clk 164>; + clock-names = "core", "rx_esc", "tx_esc", "phy_ref"; + interrupts = <0 34 4>; + power-domains = <&pgc_mipi>; + resets = <&src 0>, <&src 1>, <&src 2>, <&src 3>; + reset-names = "byte", "dpi", "esc", "pclk"; + mux-sel = <&iomuxc_gpr>;
Quoted 8 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml line 130
Quoted 5 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +5
-0+ phys = <&dphy>; + phy-names = "dphy"; + + panel@0 { + compatible = "...";Needs to be a valid compatible. Also need 'reg' here or drop the unit-address.
Fixed.
Quoted 22 lines
Quoted 22 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +20
-0+ port@0 { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mipi_dsi_in: endpoint { + remote-endpoint = <&lcdif_mipi_dsi>; + }; + }; + port@1 { + reg = <1>; + mipi_dsi_out: endpoint {
Quoted 9 lines
Quoted 8 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +5
-1+ remote-endpoint = <&panel_in>; + }; + }; + }; + }; --2.20.1
Cheers and thanks again for having a look!
-- Guido
Laurent Pinchart
reviewerRe: [PATCH v2 2/3] dt-bindings: display/bridge: Add binding for NWL mipi dsi host controller
In reply to Guido GüntherHi Guido,
Thank you for the patch.
Quoted 76 lines · Guido Günther
The Northwest Logic MIPI DSI IP core can be found in NXPs i.MX8 SoCs.
Signed-off-by Guido Günther <[email protected]>--- .../bindings/display/bridge/nwl-dsi.yaml | 155 ++++++++++++++++++ 1 file changed, 155 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/nwl-dsi.yamlDocumentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +62
-0@@ -0,0 +1,155 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/imx-nwl-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Northwest Logic MIPI-DSI on imx SoCs + +maintainers: + - Guido Gúnther <[email protected]> + - Robert Chiras <[email protected]> + +description: | + NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for + the SOCs NWL MIPI-DSI host controller. + +properties: + compatible: + oneOf: + - items: + - const: fsl,imx8mq-nwl-dsi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: DSI core clock + - description: RX_ESC clock (used in escape mode) + - description: TX_ESC clock (used in escape mode) + - description: PHY_REF clock + + clock-names: + items: + - const: core + - const: rx_esc + - const: tx_esc + - const: phy_ref + + phys: + maxItems: 1 + description: + A phandle to the phy module representing the DPHY + + phy-names: + items: + - const: dphy + + power-domains: + maxItems: 1 + description: + A phandle to the power domain + + resets: + maxItems: 4 + description: + A phandle to the reset controller + + reset-names:
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml line 72
Quoted 10 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +10
-0+ items: + - const: byte + - const: dpi + - const: esc + - const: pclk + + mux-sel: + maxItems: 1 + description: + A phandle to the MUX register set
Did you mean the MUX syscon ? A phandle to a register set sounds a bit strange.
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml line 77
Quoted 5 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +5
-0+ + port: + type: object + description: + A input put or output port node.
s/input put/input/
Quoted 78 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +78
-0+ + ports: + type: object + description: + A node containing DSI input & output port nodes with endpoint + definitions as documented in + Documentation/devicetree/bindings/graph.txt. + +patternProperties: + "^panel@[0-9]+$": true + +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8mq-nwl-dsi + then: + required: + - resets + - reset-names + - mux-sel + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - phys + - phy-names + +examples: + - | + + mipi_dsi: mipi_dsi@30a00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mq-nwl-dsi"; + reg = <0x30A00000 0x300>; + clocks = <&clk 163>, <&clk 244>, <&clk 245>, <&clk 164>; + clock-names = "core", "rx_esc", "tx_esc", "phy_ref"; + interrupts = <0 34 4>; + power-domains = <&pgc_mipi>; + resets = <&src 0>, <&src 1>, <&src 2>, <&src 3>; + reset-names = "byte", "dpi", "esc", "pclk"; + mux-sel = <&iomuxc_gpr>; + phys = <&dphy>; + phy-names = "dphy"; + + panel@0 { + compatible = "..."; + port@0 { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mipi_dsi_in: endpoint { + remote-endpoint = <&lcdif_mipi_dsi>; + }; + }; + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + };
Signature · 7 lines
Regards, Laurent Pinchart _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2 2/3] dt-bindings: display/bridge: Add binding for NWL mipi dsi host controller
Hi Laurent,
thanks for having a look!
Quoted 86 lines · Laurent Pinchart
Hi Guido,
Thank you for the patch.
Quoted 81 lines · Guido Günther
The Northwest Logic MIPI DSI IP core can be found in NXPs i.MX8 SoCs.
Signed-off-by Guido Günther <[email protected]>--- .../bindings/display/bridge/nwl-dsi.yaml | 155 ++++++++++++++++++ 1 file changed, 155 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/nwl-dsi.yamlDocumentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +67
-0@@ -0,0 +1,155 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/imx-nwl-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Northwest Logic MIPI-DSI on imx SoCs + +maintainers: + - Guido Gúnther <[email protected]> + - Robert Chiras <[email protected]> + +description: | + NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for + the SOCs NWL MIPI-DSI host controller. + +properties: + compatible: + oneOf: + - items: + - const: fsl,imx8mq-nwl-dsi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: DSI core clock + - description: RX_ESC clock (used in escape mode) + - description: TX_ESC clock (used in escape mode) + - description: PHY_REF clock + + clock-names: + items: + - const: core + - const: rx_esc + - const: tx_esc + - const: phy_ref + + phys: + maxItems: 1 + description: + A phandle to the phy module representing the DPHY + + phy-names: + items: + - const: dphy + + power-domains: + maxItems: 1 + description: + A phandle to the power domain + + resets: + maxItems: 4 + description: + A phandle to the reset controller + + reset-names: + items: + - const: byte + - const: dpi + - const: esc + - const: pclk
Quoted 8 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml line 72
Quoted 5 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +5
-0+ + mux-sel: + maxItems: 1 + description: + A phandle to the MUX register setDid you mean the MUX syscon ? A phandle to a register set sounds a bit strange.
That one is gone in v3 in favour of mux-controls.
Quoted 8 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml line 77
Quoted 6 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +5
-0+ + port: + type: object + description: + A input put or output port node.s/input put/input/
Thanks! I've shuffled this around in v3 and added some more detail. Cheers,
-- Guido
Quoted 85 lines
Quoted 79 lines
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file +78
-0+ + ports: + type: object + description: + A node containing DSI input & output port nodes with endpoint + definitions as documented in + Documentation/devicetree/bindings/graph.txt. + +patternProperties: + "^panel@[0-9]+$": true + +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8mq-nwl-dsi + then: + required: + - resets + - reset-names + - mux-sel + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - phys + - phy-names + +examples: + - | + + mipi_dsi: mipi_dsi@30a00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mq-nwl-dsi"; + reg = <0x30A00000 0x300>; + clocks = <&clk 163>, <&clk 244>, <&clk 245>, <&clk 164>; + clock-names = "core", "rx_esc", "tx_esc", "phy_ref"; + interrupts = <0 34 4>; + power-domains = <&pgc_mipi>; + resets = <&src 0>, <&src 1>, <&src 2>, <&src 3>; + reset-names = "byte", "dpi", "esc", "pclk"; + mux-sel = <&iomuxc_gpr>; + phys = <&dphy>; + phy-names = "dphy"; + + panel@0 { + compatible = "..."; + port@0 { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mipi_dsi_in: endpoint { + remote-endpoint = <&lcdif_mipi_dsi>; + }; + }; + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + };Signature · 3 lines
Regards, Laurent Pinchart
PATCH v2 3/3 drm/bridge: Add NWL MIPI DSI host controller support
In reply to Guido GüntherThis adds initial support for the NWL MIPI DSI Host controller found on i.MX8 SoCs.
It adds support for the i.MX8MQ but the same IP can be found on e.g. the i.MX8QXP.
It has been tested on the Librem 5 devkit using mxsfb.
--- drivers/gpu/drm/bridge/Kconfig | 2 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/nwl-dsi/Kconfig | 15 + drivers/gpu/drm/bridge/nwl-dsi/Makefile | 4 + drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.c | 484 ++++++++++++++++ drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.h | 66 +++ drivers/gpu/drm/bridge/nwl-dsi/nwl-dsi.c | 700 +++++++++++++++++++++++ drivers/gpu/drm/bridge/nwl-dsi/nwl-dsi.h | 112 ++++ 8 files changed, 1384 insertions(+) create mode 100644 drivers/gpu/drm/bridge/nwl-dsi/Kconfig create mode 100644 drivers/gpu/drm/bridge/nwl-dsi/Makefile create mode 100644 drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.c create mode 100644 drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.h create mode 100644 drivers/gpu/drm/bridge/nwl-dsi/nwl-dsi.c create mode 100644 drivers/gpu/drm/bridge/nwl-dsi/nwl-dsi.h
drivers/gpu/drm/bridge/Kconfig +2 -0
@@ -154,6 +154,8 @@ source "drivers/gpu/drm/bridge/analogix/Kconfig" source "drivers/gpu/drm/bridge/adv7511/Kconfig" +source "drivers/gpu/drm/bridge/nwl-dsi/Kconfig" + source "drivers/gpu/drm/bridge/synopsys/Kconfig" endmenu
drivers/gpu/drm/bridge/Makefile +1 -0
@@ -16,4 +16,5 @@ obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/ obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/ obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o +obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi/ obj-y += synopsys/
drivers/gpu/drm/bridge/nwl-dsi/Kconfig new file +15 -0
@@ -0,0 +1,15 @@ +config DRM_NWL_MIPI_DSI + tristate "Support for Northwest Logic MIPI DSI Host controller" + depends on DRM + depends on COMMON_CLK + depends on OF && HAS_IOMEM + select DRM_KMS_HELPER + select DRM_MIPI_DSI + select DRM_PANEL_BRIDGE + select GENERIC_PHY_MIPI_DPHY + select MFD_SYSCON + select REGMAP_MMIO + help + This enables the Northwest Logic MIPI DSI Host controller as + for example found on NXP's i.MX8 Processors. +
drivers/gpu/drm/bridge/nwl-dsi/Makefile new file +4 -0
@@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +nwl-mipi-dsi-y := nwl-drv.o nwl-dsi.o +obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-mipi-dsi.o +header-test-y += nwl-drv.h nwl-dsi.h
drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.c new file +484 -0
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drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.h new file +66 -0
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drivers/gpu/drm/bridge/nwl-dsi/nwl-dsi.c new file +700 -0
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drivers/gpu/drm/bridge/nwl-dsi/nwl-dsi.h new file +112 -0
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Signature · 1 line
2.20.1