dt-bindings: riscv: Fix CPU schema errors

PATCH Superseded Rob Herring 1 participant 1 message Sep 24, 2019

Subsystems (2)

Device tree bindings RISC-V

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Rob Herring

author maintainer

2019-09-24 19:47 UTC #0 lore raw

PATCH 1/1 dt-bindings: riscv: Fix CPU schema errors

Fix the errors in the RiscV CPU DT schema:

Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@1: 'timebase-frequency' is a required property Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible:0: 'riscv' is not one of ['sifive,rocket0', 'sifive,e5', 'sifive,e51', 'sifive,u54-mc', 'sifive,u54', 'sifive,u5'] Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible: ['riscv'] is too short Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property

Fixes 4fd669a8c487 ("dt-bindings: riscv: convert cpu binding to json-schema")

Cc Paul Walmsley <[email protected]>

Cc Palmer Dabbelt <[email protected]>

Cc Albert Ou <[email protected]>

Cc [email protected]

Signed-off-by Rob Herring <[email protected]>

---
 .../devicetree/bindings/riscv/cpus.yaml       | 25 ++++++++++---------
 1 file changed, 13 insertions(+), 12 deletions(-)

Documentation/devicetree/bindings/riscv/cpus.yaml +13 ~~-12~~

index c899111aa5e3..e7321688f7b9 100644
@@ -12,15 +12,17 @@ maintainers:
 
 properties:
   compatible:
-    items:
-      - enum:
-          - sifive,rocket0
-          - sifive,e5
-          - sifive,e51
-          - sifive,u54-mc
-          - sifive,u54
-          - sifive,u5
-      - const: riscv
+    oneOf:
+      - items:
+          - enum:
+              - sifive,rocket0
+              - sifive,e5
+              - sifive,e51
+              - sifive,u54-mc
+              - sifive,u54
+              - sifive,u5
+          - const: riscv
+      - const: riscv    # Simulator only
     description:
       Identifies that the hart uses the RISC-V instruction set
       and identifies the type of the hart.

@@ -51,8 +53,6 @@ properties:
       https://riscv.org/specifications/
 
   timebase-frequency:
-    type: integer
-    minimum: 1
     description:
       Specifies the clock frequency of the system timer in Hz.
       This value is common to all harts on a single system image.

@@ -86,9 +86,9 @@ examples:
     cpus {
         #address-cells = <1>;
         #size-cells = <0>;
-        timebase-frequency = <1000000>;
         cpu@0 {
                 clock-frequency = <0>;
+                timebase-frequency = <1000000>;
                 compatible = "sifive,rocket0", "riscv";
                 device_type = "cpu";
                 i-cache-block-size = <64>;

@@ -104,6 +104,7 @@ examples:
         };
         cpu@1 {
                 clock-frequency = <0>;
+                timebase-frequency = <1000000>;
                 compatible = "sifive,rocket0", "riscv";
                 d-cache-block-size = <64>;
                 d-cache-sets = <64>;

Signature · 1 line

2.20.1