Add coresight support for SDM845, MSM8998 and MSM8996
v9 cover Add coresight support for SDM845, MSM8998 and MSM8996
This patch series adds support for coresight on SDM845, MSM8998, and MSM8996.
* Patch 1 adds device tree nodes for SDM845 coresight components.
* Patch 2 adds device tree nodes for MSM8998 coresight components.
* Patch 3 adds device tree nodes for MSM8996 coresight components.
All the previous dependencies are now merged.
This patch series has been tested on SDM845 MTP and MSM8996 based Dragonboard 820c and MSM8998 MTP.
Test results for SDM845 and MSM8996 with scatter gather are uploaded to below github link:
- https://github.com/saiprakash-ranjan/coresight-test-results
v9:
* Add test results for SDM845 and MSM8996.
* Add missing funnel node in MSM8996.
v8:
* Change to clocks instead of power domain for SDM845.
* Fix compilation with uci_id_debug struct changed to const.
* Rebase on top of linux-next.
v7:
* Change uci_id_debug struct to const.
* Update the subject as suggested by Suzuki.
v6:
* Update the UCI table with the new macro introduced by Mike.
* Rebase on top of coresight-next and provide a tree with all the dependent patches applied.
v5:
* Added coresight support for MSM8998.
* Added ETM PIDs for SDM845 and MSM8996 as suggested by Suzuki.
* Added UCI table for Coresight CPU debug module.
v4:
* Mask out the minor version as suggested by Mathieu.
* Added the dependent patch description in patch 1.
v3:
* Added arm,scatter-gather property as suggested by Suzuki.
v2:
* Added coresight support for msm8996 based on Vivek's patch. Cleaned up and added coresight cpu debug nodes for msm8996.
* Merged coresight dtsi file into sdm845.dtsi as suggested by Bjorn
* Addressed Mathieu's feedback about masking the minor version in etm4_arch_supported() and added a comment for reason to bypass the AMBA bus discovery method.
Sai Prakash Ranjan (2):
arm64: dts: qcom: sdm845: Add Coresight support
arm64: dts: qcom: msm8998: Add Coresight support
Vivek Gautam (1):
arm64: dts: qcom: msm8996: Add Coresight support
arch/arm64/boot/dts/qcom/msm8996.dtsi | 468 ++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/msm8998.dtsi | 435 ++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 451 +++++++++++++++++++++++++ 3 files changed, 1354 insertions(+)
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v9 1/3 arm64: dts: qcom: sdm845: Add Coresight support
Add coresight components found on Qualcomm SDM845 SoC.
--- arch/arm64/boot/dts/qcom/sdm845.dtsi | 451 +++++++++++++++++++++++++++ 1 file changed, 451 insertions(+)
arch/arm64/boot/dts/qcom/sdm845.dtsi +451 -0
@@ -1815,6 +1815,457 @@ clock-names = "xo"; }; + stm@6002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x06002000 0 0x1000>, + <0 0x16280000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = + <&funnel0_in7>; + }; + }; + }; + }; + + funnel@6041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06041000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = + <&merge_funnel_in0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + funnel0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + }; + + funnel@6043000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06043000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel2_out: endpoint { + remote-endpoint = + <&merge_funnel_in2>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@5 { + reg = <5>; + funnel2_in5: endpoint { + remote-endpoint = + <&apss_merge_funnel_out>; + }; + }; + }; + }; + + funnel@6045000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06045000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + merge_funnel_out: endpoint { + remote-endpoint = <&etf_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + merge_funnel_in0: endpoint { + remote-endpoint = + <&funnel0_out>; + }; + }; + + port@2 { + reg = <2>; + merge_funnel_in2: endpoint { + remote-endpoint = + <&funnel2_out>; + }; + }; + }; + }; + + replicator@6046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0 0x06046000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + replicator_out: endpoint { + remote-endpoint = <&etr_in>; + }; + }; + }; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = <&etf_out>; + }; + }; + }; + }; + + etf@6047000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x06047000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + etf_out: endpoint { + remote-endpoint = + <&replicator_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + etf_in: endpoint { + remote-endpoint = + <&merge_funnel_out>; + }; + }; + }; + }; + + etr@6048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x06048000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,scatter-gather; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = + <&replicator_out>; + }; + }; + }; + }; + + etm@7040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07040000 0 0x1000>; + + cpu = <&CPU0>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = + <&apss_funnel_in0>; + }; + }; + }; + }; + + etm@7140000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07140000 0 0x1000>; + + cpu = <&CPU1>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = + <&apss_funnel_in1>; + }; + }; + }; + }; + + etm@7240000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07240000 0 0x1000>; + + cpu = <&CPU2>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = + <&apss_funnel_in2>; + }; + }; + }; + }; + + etm@7340000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07340000 0 0x1000>; + + cpu = <&CPU3>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = + <&apss_funnel_in3>; + }; + }; + }; + }; + + etm@7440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07440000 0 0x1000>; + + cpu = <&CPU4>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = + <&apss_funnel_in4>; + }; + }; + }; + }; + + etm@7540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07540000 0 0x1000>; + + cpu = <&CPU5>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = + <&apss_funnel_in5>; + }; + }; + }; + }; + + etm@7640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07640000 0 0x1000>; + + cpu = <&CPU6>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = + <&apss_funnel_in6>; + }; + }; + }; + }; + + etm@7740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07740000 0 0x1000>; + + cpu = <&CPU7>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = + <&apss_funnel_in7>; + }; + }; + }; + }; + + funnel@7800000 { /* APSS Funnel */ + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x07800000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + apss_funnel_out: endpoint { + remote-endpoint = + <&apss_merge_funnel_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel_in0: endpoint { + remote-endpoint = + <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel_in1: endpoint { + remote-endpoint = + <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + apss_funnel_in2: endpoint { + remote-endpoint = + <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + apss_funnel_in3: endpoint { + remote-endpoint = + <&etm3_out>; + }; + }; + + port@4 { + reg = <4>; + apss_funnel_in4: endpoint { + remote-endpoint = + <&etm4_out>; + }; + }; + + port@5 { + reg = <5>; + apss_funnel_in5: endpoint { + remote-endpoint = + <&etm5_out>; + }; + }; + + port@6 { + reg = <6>; + apss_funnel_in6: endpoint { + remote-endpoint = + <&etm6_out>; + }; + }; + + port@7 { + reg = <7>; + apss_funnel_in7: endpoint { + remote-endpoint = + <&etm7_out>; + }; + }; + }; + }; + + funnel@7810000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x07810000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + apss_merge_funnel_out: endpoint { + remote-endpoint = + <&funnel2_in5>; + }; + }; + }; + + in-ports { + port { + apss_merge_funnel_in: endpoint { + remote-endpoint = + <&apss_funnel_out>; + }; + }; + }; + }; + sdhc_2: sdhci@8804000 { compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>;
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCHv9 1/3] arm64: dts: qcom: sdm845: Add Coresight support
Hi Suzuki,
Quoted 8 lines · Sai Prakash Ranjan
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by Sai Prakash Ranjan <[email protected]>Reviewed-by Mathieu Poirier <[email protected]>Acked-by Suzuki K Poulose <[email protected]>--- arch/arm64/boot/dts/qcom/sdm845.dtsi | 451 +++++++++++++++++++++++++++ 1 file changed, 451 insertions(+)
I have tested coresight with scatter gather on SDM845 MTP and MSM8996 based DB820c board and posted the results in
- https://github.com/saiprakash-ranjan/coresight-test-results
Please let me know if you need some additional testing done.
I could not perform coresight tests on MSM8998 MTP with latest build as it was resulting in crash due to some AHB timeouts. This was not due to scatter-gather and mostly likely the problem with the build. Maybe we can keep msm8998-coresight on hold?
BTW, patches are based on linux-next.
Thanks,
Sai
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCHv9 1/3] arm64: dts: qcom: sdm845: Add Coresight support
Hi Suzuki,
Quoted 17 lines · Sai Prakash Ranjan
Hi Suzuki,
Quoted 8 lines · Sai Prakash Ranjan
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by Sai Prakash Ranjan <[email protected]>Reviewed-by Mathieu Poirier <[email protected]>Acked-by Suzuki K Poulose <[email protected]>---
arch/arm64/boot/dts/qcom/sdm845.dtsi| 451 +++++++++++++++++++++++++++1 file changed, 451 insertions(+)I have tested coresight with scatter gather on SDM845 MTP and MSM8996 based DB820c board and posted the results in
- https://github.com/saiprakash-ranjan/coresight-test-results
Quoted 9 lines
Please let me know if you need some additional testing done.
I could not perform coresight tests on MSM8998 MTP with latest build as it was resulting in crash due to some AHB timeouts. This was not due to scatter-gather and mostly likely the problem with the build. Maybe we can keep msm8998-coresight on hold?
BTW, patches are based on linux-next.
Any more tests you would want me to run?
-Sai
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCHv9 1/3] arm64: dts: qcom: sdm845: Add Coresight support
Sai,
Quoted 27 lines · Sai Prakash Ranjan
Hi Suzuki,
Quoted 24 lines · Sai Prakash Ranjan
Hi Suzuki,
Quoted 8 lines · Sai Prakash Ranjan
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by Sai Prakash Ranjan <[email protected]>Reviewed-by Mathieu Poirier <[email protected]>Acked-by Suzuki K Poulose <[email protected]>--- arch/arm64/boot/dts/qcom/sdm845.dtsi | 451 +++++++++++++++++++++++++++ 1 file changed, 451 insertions(+)I have tested coresight with scatter gather on SDM845 MTP and MSM8996 based DB820c board and posted the results in
- https://github.com/saiprakash-ranjan/coresight-test-results
Please let me know if you need some additional testing done.
I could not perform coresight tests on MSM8998 MTP with latest build as it was resulting in crash due to some AHB timeouts. This was not due to scatter-gather and mostly likely the problem with the build. Maybe we can keep msm8998-coresight on hold?
Quoted 4 lines
Quoted 2 lines
BTW, patches are based on linux-next.
Any more tests you would want me to run?
Apologies for the late response. I had seen the results and they look fine. I was hitting some issues, which I have now root caused to firmware issues. So we are good to go.
Suzuki
Re: [PATCHv9 1/3] arm64: dts: qcom: sdm845: Add Coresight support
Quoted 8 lines · Suzuki K Poulose
Sai,
Quoted 1 line
Any more tests you would want me to run?
Apologies for the late response. I had seen the results and they look fine. I was hitting some issues, which I have now root caused to firmware issues. So we are good to go.
Thanks Suzuki.
Hi Bjorn, any chance you could pull these in?
Thanks,
Sai
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v9 2/3 arm64: dts: qcom: msm8998: Add Coresight support
In reply to Sai Prakash RanjanEnable coresight support by adding device nodes for the available source, sinks and channel blocks on MSM8998.
--- arch/arm64/boot/dts/qcom/msm8998.dtsi | 435 ++++++++++++++++++++++++++ 1 file changed, 435 insertions(+)
arch/arm64/boot/dts/qcom/msm8998.dtsi +435 -0
@@ -822,6 +822,441 @@ #interrupt-cells = <0x2>; }; + stm@6002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x06002000 0x1000>, + <0x16280000 0x180000>; + reg-names = "stm-base", "stm-data-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel0_in7>; + }; + }; + }; + }; + + funnel@6041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x06041000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = + <&merge_funnel_in0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + funnel0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + }; + + funnel@6042000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x06042000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + funnel1_out: endpoint { + remote-endpoint = + <&merge_funnel_in1>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@6 { + reg = <6>; + funnel1_in6: endpoint { + remote-endpoint = + <&apss_merge_funnel_out>; + }; + }; + }; + }; + + funnel@6045000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x06045000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + merge_funnel_out: endpoint { + remote-endpoint = + <&etf_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + merge_funnel_in0: endpoint { + remote-endpoint = + <&funnel0_out>; + }; + }; + + port@1 { + reg = <1>; + merge_funnel_in1: endpoint { + remote-endpoint = + <&funnel1_out>; + }; + }; + }; + }; + + replicator@6046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x06046000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + replicator_out: endpoint { + remote-endpoint = <&etr_in>; + }; + }; + }; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = <&etf_out>; + }; + }; + }; + }; + + etf@6047000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x06047000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + etf_out: endpoint { + remote-endpoint = + <&replicator_in>; + }; + }; + }; + + in-ports { + port { + etf_in: endpoint { + remote-endpoint = + <&merge_funnel_out>; + }; + }; + }; + }; + + etr@6048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x06048000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + arm,scatter-gather; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = + <&replicator_out>; + }; + }; + }; + }; + + etm@7840000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07840000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU0>; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = + <&apss_funnel_in0>; + }; + }; + }; + }; + + etm@7940000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07940000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU1>; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = + <&apss_funnel_in1>; + }; + }; + }; + }; + + etm@7a40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07a40000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU2>; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = + <&apss_funnel_in2>; + }; + }; + }; + }; + + etm@7b40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07b40000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU3>; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = + <&apss_funnel_in3>; + }; + }; + }; + }; + + funnel@7b60000 { /* APSS Funnel */ + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07b60000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + apss_funnel_out: endpoint { + remote-endpoint = + <&apss_merge_funnel_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel_in0: endpoint { + remote-endpoint = + <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel_in1: endpoint { + remote-endpoint = + <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + apss_funnel_in2: endpoint { + remote-endpoint = + <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + apss_funnel_in3: endpoint { + remote-endpoint = + <&etm3_out>; + }; + }; + + port@4 { + reg = <4>; + apss_funnel_in4: endpoint { + remote-endpoint = + <&etm4_out>; + }; + }; + + port@5 { + reg = <5>; + apss_funnel_in5: endpoint { + remote-endpoint = + <&etm5_out>; + }; + }; + + port@6 { + reg = <6>; + apss_funnel_in6: endpoint { + remote-endpoint = + <&etm6_out>; + }; + }; + + port@7 { + reg = <7>; + apss_funnel_in7: endpoint { + remote-endpoint = + <&etm7_out>; + }; + }; + }; + }; + + funnel@7b70000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x07b70000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + apss_merge_funnel_out: endpoint { + remote-endpoint = + <&funnel1_in6>; + }; + }; + }; + + in-ports { + port { + apss_merge_funnel_in: endpoint { + remote-endpoint = + <&apss_funnel_out>; + }; + }; + }; + }; + + etm@7c40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07c40000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU4>; + + port{ + etm4_out: endpoint { + remote-endpoint = <&apss_funnel_in4>; + }; + }; + }; + + etm@7d40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07d40000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU5>; + + port{ + etm5_out: endpoint { + remote-endpoint = <&apss_funnel_in5>; + }; + }; + }; + + etm@7e40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07e40000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU6>; + + port{ + etm6_out: endpoint { + remote-endpoint = <&apss_funnel_in6>; + }; + }; + }; + + etm@7f40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07f40000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU7>; + + port{ + etm7_out: endpoint { + remote-endpoint = <&apss_funnel_in7>; + }; + }; + }; + spmi_bus: spmi@800f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x800f000 0x1000>,
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCHv9 2/3] arm64: dts: qcom: msm8998: Add Coresight support
Sai,
This patch breaks boot on the 835 laptops. However, I haven't seen the same issue on the MTP. I wonder, is coresight expected to work with production fused devices? I wonder if thats the difference between the laptop and MTP that is causing the issue.
Let me know what I can do to help debug.
Quoted 466 lines · Sai Prakash Ranjan
Enable coresight support by adding device nodes for the available source, sinks and channel blocks on MSM8998.
Signed-off-by Sai Prakash Ranjan <[email protected]>Reviewed-by Mathieu Poirier <[email protected]>Acked-by Suzuki K Poulose <[email protected]>--- arch/arm64/boot/dts/qcom/msm8998.dtsi | 435 ++++++++++++++++++++++++++ 1 file changed, 435 insertions(+)arch/arm64/boot/dts/qcom/msm8998.dtsi +435
-1@@ -822,6 +822,441 @@ #interrupt-cells = <0x2>; }; + stm@6002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x06002000 0x1000>, + <0x16280000 0x180000>; + reg-names = "stm-base", "stm-data-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel0_in7>; + }; + }; + }; + }; + + funnel@6041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x06041000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = + <&merge_funnel_in0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + funnel0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + }; + + funnel@6042000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x06042000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + funnel1_out: endpoint { + remote-endpoint = + <&merge_funnel_in1>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@6 { + reg = <6>; + funnel1_in6: endpoint { + remote-endpoint = + <&apss_merge_funnel_out>; + }; + }; + }; + }; + + funnel@6045000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x06045000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + merge_funnel_out: endpoint { + remote-endpoint = + <&etf_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + merge_funnel_in0: endpoint { + remote-endpoint = + <&funnel0_out>; + }; + }; + + port@1 { + reg = <1>; + merge_funnel_in1: endpoint { + remote-endpoint = + <&funnel1_out>; + }; + }; + }; + }; + + replicator@6046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x06046000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + replicator_out: endpoint { + remote-endpoint = <&etr_in>; + }; + }; + }; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = <&etf_out>; + }; + }; + }; + }; + + etf@6047000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x06047000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + etf_out: endpoint { + remote-endpoint = + <&replicator_in>; + }; + }; + }; + + in-ports { + port { + etf_in: endpoint { + remote-endpoint = + <&merge_funnel_out>; + }; + }; + }; + }; + + etr@6048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x06048000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + arm,scatter-gather; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = + <&replicator_out>; + }; + }; + }; + }; + + etm@7840000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07840000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU0>; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = + <&apss_funnel_in0>; + }; + }; + }; + }; + + etm@7940000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07940000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU1>; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = + <&apss_funnel_in1>; + }; + }; + }; + }; + + etm@7a40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07a40000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU2>; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = + <&apss_funnel_in2>; + }; + }; + }; + }; + + etm@7b40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07b40000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU3>; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = + <&apss_funnel_in3>; + }; + }; + }; + }; + + funnel@7b60000 { /* APSS Funnel */ + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07b60000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + apss_funnel_out: endpoint { + remote-endpoint = + <&apss_merge_funnel_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel_in0: endpoint { + remote-endpoint = + <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel_in1: endpoint { + remote-endpoint = + <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + apss_funnel_in2: endpoint { + remote-endpoint = + <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + apss_funnel_in3: endpoint { + remote-endpoint = + <&etm3_out>; + }; + }; + + port@4 { + reg = <4>; + apss_funnel_in4: endpoint { + remote-endpoint = + <&etm4_out>; + }; + }; + + port@5 { + reg = <5>; + apss_funnel_in5: endpoint { + remote-endpoint = + <&etm5_out>; + }; + }; + + port@6 { + reg = <6>; + apss_funnel_in6: endpoint { + remote-endpoint = + <&etm6_out>; + }; + }; + + port@7 { + reg = <7>; + apss_funnel_in7: endpoint { + remote-endpoint = + <&etm7_out>; + }; + }; + }; + }; + + funnel@7b70000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x07b70000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + apss_merge_funnel_out: endpoint { + remote-endpoint = + <&funnel1_in6>; + }; + }; + }; + + in-ports { + port { + apss_merge_funnel_in: endpoint { + remote-endpoint = + <&apss_funnel_out>; + }; + }; + }; + }; + + etm@7c40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07c40000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU4>; + + port{ + etm4_out: endpoint { + remote-endpoint = <&apss_funnel_in4>; + }; + }; + }; + + etm@7d40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07d40000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU5>; + + port{ + etm5_out: endpoint { + remote-endpoint = <&apss_funnel_in5>; + }; + }; + }; + + etm@7e40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07e40000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU6>; + + port{ + etm6_out: endpoint { + remote-endpoint = <&apss_funnel_in6>; + }; + }; + }; + + etm@7f40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x07f40000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU7>; + + port{ + etm7_out: endpoint { + remote-endpoint = <&apss_funnel_in7>; + }; + }; + }; + spmi_bus: spmi@800f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x800f000 0x1000>, --QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
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Re: [PATCHv9 2/3] arm64: dts: qcom: msm8998: Add Coresight support
Quoted 9 lines · Jeffrey Hugo
Sai,
This patch breaks boot on the 835 laptops. However, I haven't seen the same issue on the MTP. I wonder, is coresight expected to work with production fused devices? I wonder if thats the difference between the laptop and MTP that is causing the issue.
Let me know what I can do to help debug.
I did test on MSM8998 MTP and didn't face any issue. I am guessing this is the same issue which you reported regarding cpuidle? Coresight ETM and cpuidle do not work well together since ETMs share the same power domain as CPU and they might get turned off when CPU enters idle states. Can you try with cpuidle.off=1 cmdline or just remove idle states from DT to confirm? If this is the issue, then we can try the below patch from Andrew Murray for ETM save and restore:
https://patchwork.kernel.org/patch/11097893/
It is not merged yet. They would appreciate your tested by ;)
Thanks,
Sai
Re: [PATCHv9 2/3] arm64: dts: qcom: msm8998: Add Coresight support
Quoted 9 lines · Sai Prakash Ranjan
Quoted 7 lines · Jeffrey Hugo
Sai,
This patch breaks boot on the 835 laptops. However, I haven't seen the same issue on the MTP. I wonder, is coresight expected to work with production fused devices? I wonder if thats the difference between the laptop and MTP that is causing the issue.
Quoted 5 lines
Quoted 2 lines
Let me know what I can do to help debug.
I did test on MSM8998 MTP and didn't face any issue. I am guessing this is the same issue which you reported regarding cpuidle? Coresight ETM
Yes, its the same issue. Right now, I need both patches reverted to boot.
Quoted 7 lines
and cpuidle do not work well together since ETMs share the same power domain as CPU and they might get turned off when CPU enters idle states. Can you try with cpuidle.off=1 cmdline or just remove idle states from DT to confirm? If this is the issue, then we can try the below patch from Andrew Murray for ETM save and restore:
Is there still value in testing this if the idle states are removed, yet the coresight nodes still cause issues?
Funny enough, I'm using the arm64 defconfig which doesn't seem to select CONFIG_CORESIGHT, so I'm not even sure what would be binding to the DT devices...
Quoted 5 lines
It is not merged yet. They would appreciate your tested by ;)
Thanks,
Sai
Re: [PATCHv9 2/3] arm64: dts: qcom: msm8998: Add Coresight support
Quoted 25 lines · Jeffrey Hugo
Quoted 9 lines · Sai Prakash Ranjan
Quoted 7 lines · Jeffrey Hugo
Sai,
This patch breaks boot on the 835 laptops. However, I haven't seen the same issue on the MTP. I wonder, is coresight expected to work with production fused devices? I wonder if thats the difference between the laptop and MTP that is causing the issue.
Quoted 5 lines
Quoted 2 lines
Let me know what I can do to help debug.
I did test on MSM8998 MTP and didn't face any issue. I am guessing this is the same issue which you reported regarding cpuidle? Coresight ETM
Yes, its the same issue. Right now, I need both patches reverted to boot.
Quoted 6 lines
and cpuidle do not work well together since ETMs share the same power domain as CPU and they might get turned off when CPU enters idle states. Can you try with cpuidle.off=1 cmdline or just remove idle states from DT to confirm? If this is the issue, then we can try the below patch from Andrew Murray for ETM save and restore:
Quoted 8 lines
Quoted 1 line
Is there still value in testing this if the idle states are removed, yet the coresight nodes still cause issues?
Funny enough, I'm using the arm64 defconfig which doesn't seem to select
CONFIG_CORESIGHT, so I'm not even sure what would be binding to the DT devices...
That looks like potentially missing Power domain support, either in the kernel or from the firmware.
The Coresight components are also AMBA devices (with primecell compatible) and thus the AMBA bus layer does some probing to check the PIDRx registers to match the driver. The AMBA layer does try to get the power to the component, but someone is lying that it is powered.
Suzuki
Re: [PATCHv9 2/3] arm64: dts: qcom: msm8998: Add Coresight support
In reply to Jeffrey HugoQuoted 25 lines · Jeffrey Hugo
Quoted 9 lines · Sai Prakash Ranjan
Quoted 7 lines · Jeffrey Hugo
Sai,
This patch breaks boot on the 835 laptops. However, I haven't seen the same issue on the MTP. I wonder, is coresight expected to work with production fused devices? I wonder if thats the difference between the laptop and MTP that is causing the issue.
Quoted 5 lines
Quoted 2 lines
Let me know what I can do to help debug.
I did test on MSM8998 MTP and didn't face any issue. I am guessing this is the same issue which you reported regarding cpuidle? Coresight ETM
Yes, its the same issue. Right now, I need both patches reverted to boot.
Quoted 6 lines
and cpuidle do not work well together since ETMs share the same power domain as CPU and they might get turned off when CPU enters idle states. Can you try with cpuidle.off=1 cmdline or just remove idle states from DT to confirm? If this is the issue, then we can try the below patch from Andrew Murray for ETM save and restore:
Quoted 9 lines
Quoted 1 line
Is there still value in testing this if the idle states are removed, yet the coresight nodes still cause issues?
Funny enough, I'm using the arm64 defconfig which doesn't seem to select
CONFIG_CORESIGHT, so I'm not even sure what would be binding to the DT devices...
Haan then likely it's the firmware issue.
We should probably disable coresight in soc dtsi and enable only for MTP. For now you can add a status=disabled for all coresight nodes in msm8998.dtsi and I will send the patch doing the same in a day or two(sorry I am travelling currently).
Thanks,
Sai
Jeffrey Hugo
Tested-byRe: [PATCHv9 2/3] arm64: dts: qcom: msm8998: Add Coresight support
Quoted 40 lines · Sai Prakash Ranjan
Quoted 28 lines · Jeffrey Hugo
Quoted 9 lines · Sai Prakash Ranjan
Quoted 7 lines · Jeffrey Hugo
Sai,
This patch breaks boot on the 835 laptops. However, I haven't seen the same issue on the MTP. I wonder, is coresight expected to work with production fused devices? I wonder if thats the difference between the laptop and MTP that is causing the issue.
Quoted 6 lines
Quoted 2 lines
Let me know what I can do to help debug.
I did test on MSM8998 MTP and didn't face any issue. I am guessing this
is the same issue which you reported regarding cpuidle? Coresight ETMYes, its the same issue. Right now, I need both patches reverted to boot.
Quoted 7 lines
and cpuidle do not work well together since ETMs share the same power domain as CPU and they might get turned off when CPU enters idle states.
Can you try with cpuidle.off=1 cmdline or just remove idle states from DT to confirm? If this is the issue, then we can try the below patch from Andrew Murray for ETM save and restore:Quoted 9 lines
Quoted 1 line
Is there still value in testing this if the idle states are removed, yet the coresight nodes still cause issues?
Funny enough, I'm using the arm64 defconfig which doesn't seem to select
CONFIG_CORESIGHT, so I'm not even sure what would be binding to the DT devices...
Quoted 5 lines
Haan then likely it's the firmware issue.
We should probably disable coresight in soc dtsi and enable only for MTP. For now you can add a status=disabled for all coresight nodes inmsm8998.dtsiand I will send the patch doing the same in a day or two(sorry I am travelling currently).
This sounds sane to me (and is what I did while bisecting the issue). When you do create the patch, feel free to add the following tags as you see fit.
Re: [PATCHv9 2/3] arm64: dts: qcom: msm8998: Add Coresight support
Quoted 10 lines · Jeffrey Hugo
Quoted 7 lines · Sai Prakash Ranjan
Haan then likely it's the firmware issue.
We should probably disable coresight in soc dtsi and enable only for MTP. For now you can add a status=disabled for all coresight nodes inmsm8998.dtsiand I will send the patch doing the same in a day or two(sorry I am travelling currently).
Quoted 6 lines
This sounds sane to me (and is what I did while bisecting the issue). When you do create the patch, feel free to add the following tags as you see fit.
Reported-by Jeffrey Hugo <[email protected]>Tested-by Jeffrey Hugo <[email protected]>
Thanks Jeffrey, I will add them.
Hope Mathieu and Suzuki are OK with this.
Thanks,
Sai
Re: [PATCHv9 2/3] arm64: dts: qcom: msm8998: Add Coresight support
Quoted 16 lines · Sai Prakash Ranjan
Quoted 14 lines · Jeffrey Hugo
Quoted 7 lines · Sai Prakash Ranjan
Haan then likely it's the firmware issue.
We should probably disable coresight in soc dtsi and enable only for MTP. For now you can add a status=disabled for all coresight nodes inmsm8998.dtsiand I will send the patch doing the same in a day or two(sorry I am travelling currently).This sounds sane to me (and is what I did while bisecting the issue). When you do create the patch, feel free to add the following tags as you see fit.
Quoted 5 lines
Quoted 2 lines
Reported-by Jeffrey Hugo <[email protected]>Tested-by Jeffrey Hugo <[email protected]>Thanks Jeffrey, I will add them.
Hope Mathieu and Suzuki are OK with this.
The problem here is that a debug and production device are using the same device tree, i.e msm8998.dtsi. Disabling coresight devices in the DTS file will allow the laptop to boot but completely disabled coresight blocks on the MTP board. Leaving things as is breaks the laptop but allows coresight to be used on the MTP board. One of three things can happen:
1) Nothing gets done and production board can't boot without DTS modifications.
2) Disable tags are added to the DTS file and the debug board can't use coresight without modifications.
2) The handling of the debug power domain is done properly on the MSM8998 rather than relying on the bootloader to enable it.
3) The DTS file is split or reorganised to account for debug/production devices.
Which of the above ends up being the final solution is entirely up to David and Andy.
Regards,
Mathieu
Quoted 3 lines
Thanks,
Sai
Re: [PATCHv9 2/3] arm64: dts: qcom: msm8998: Add Coresight support
Quoted 7 lines · Mathieu Poirier
The problem here is that a debug and production device are using the same device tree, i.e
msm8998.dtsi. Disabling coresight devices in the DTS file will allow the laptop to boot but completely disabled coresight blocks on the MTP board. Leaving things as is breaks the laptop but allows coresight to be used on the MTP board. One of three things can happen:
Quoted 6 lines
1) Nothing gets done and production board can't boot without DTS modifications.
2) Disable tags are added to the DTS file and the debug board can't use coresight without modifications.
2) The handling of the debug power domain is done properly on the MSM8998 rather than relying on the bootloader to enable it.
3) The DTS file is split or reorganised to account for debug/production devices.
I believe 3) is already the de facto situation.
arch/arm64/boot/dts/qcom/msm8998.dtsi is the "base" config. arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi for the MTP board. arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi for the laptops.
Quoted 2 lines
Which of the above ends up being the final solution is entirely up to David and Andy.
2498f8c1c668 ;-)
Regards.
Re: [PATCHv9 2/3] arm64: dts: qcom: msm8998: Add Coresight support
Quoted 16 lines · Marc Gonzalez
Quoted 7 lines · Mathieu Poirier
The problem here is that a debug and production device are using the same device tree, i.e
msm8998.dtsi. Disabling coresight devices in the DTS file will allow the laptop to boot but completely disabled coresight blocks on the MTP board. Leaving things as is breaks the laptop but allows coresight to be used on the MTP board. One of three things can happen:Quoted 6 lines
1) Nothing gets done and production board can't boot without DTS modifications.
2) Disable tags are added to the DTS file and the debug board can't use coresight without modifications.
2) The handling of the debug power domain is done properly on the MSM8998 rather than relying on the bootloader to enable it.
3) The DTS file is split or reorganised to account for debug/production devices.
Quoted 5 lines
I believe 3) is already the de facto situation.
arch/arm64/boot/dts/qcom/msm8998.dtsiis the "base" config.arch/arm64/boot/dts/qcom/msm8998-mtp.dtsifor the MTP board.arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsifor the laptops.
"DTS file", i.e msm8998.dtsi
Quoted 5 lines
Quoted 3 lines
Which of the above ends up being the final solution is entirely up to David and Andy.
2498f8c1c668;-)
Then it is even easier to make a decision.
Quoted 2 lines
Regards.
Re: [PATCHv9 2/3] arm64: dts: qcom: msm8998: Add Coresight support
Quoted 18 lines · Mathieu Poirier
Quoted 16 lines · Marc Gonzalez
Quoted 13 lines · Mathieu Poirier
The problem here is that a debug and production device are using the same device tree, i.e
msm8998.dtsi. Disabling coresight devices in the DTS file will allow the laptop to boot but completely disabled coresight blocks on the MTP board. Leaving things as is breaks the laptop but allows coresight to be used on the MTP board. One of three things can happen:1) Nothing gets done and production board can't boot without DTS modifications.
2) Disable tags are added to the DTS file and the debug board can't use coresight without modifications.
2) The handling of the debug power domain is done properly on the MSM8998 rather than relying on the bootloader to enable it.
3) The DTS file is split or reorganised to account for debug/production devices.
Quoted 7 lines
Quoted 5 lines
I believe 3) is already the de facto situation.
arch/arm64/boot/dts/qcom/msm8998.dtsiis the "base" config.arch/arm64/boot/dts/qcom/msm8998-mtp.dtsifor the MTP board.arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsifor the laptops."DTS file", i.e
msm8998.dtsi
Bjorn (the primary maintainer whom will likely be taking any DT patches) and I had a chat. We concluded on disabling the coresight components (by default) in the msm8998.dtsi, and then enabling them in the msm8998-mtp.dtsi. I think Bjorn would like to see some patches, which it sounds like Sai will post in a few days.
This is probably how things should be moving forward for all qcom SoCs since its standard practice to disable the coresight components via efuse or other hardware mechanism for production products.
Quoted 11 lines
Quoted 6 lines
Quoted 4 lines
Which of the above ends up being the final solution is entirely up to David and Andy.
2498f8c1c668;-)Then it is even easier to make a decision.
Quoted 2 lines
Regards.
Re: [PATCHv9 2/3] arm64: dts: qcom: msm8998: Add Coresight support
In reply to Mathieu PoirierQuoted 31 lines · Mathieu Poirier
Quoted 16 lines · Sai Prakash Ranjan
Quoted 14 lines · Jeffrey Hugo
Quoted 7 lines · Sai Prakash Ranjan
Haan then likely it's the firmware issue.
We should probably disable coresight in soc dtsi and enable only for MTP. For now you can add a status=disabled for all coresight nodes inmsm8998.dtsiand I will send the patch doing the same in a day or two(sorry I am travelling currently).This sounds sane to me (and is what I did while bisecting the issue). When you do create the patch, feel free to add the following tags as you see fit.
Quoted 5 lines
Quoted 2 lines
Reported-by Jeffrey Hugo <[email protected]>Tested-by Jeffrey Hugo <[email protected]>Thanks Jeffrey, I will add them.
Hope Mathieu and Suzuki are OK with this.The problem here is that a debug and production device are using the same device tree, i.e
msm8998.dtsi. Disabling coresight devices in the DTS file will allow the laptop to boot but completely disabled coresight blocks on the MTP board. Leaving things as is breaks the laptop but allows coresight to be used on the MTP board. One of three things can happen:
Quoted 6 lines
1) Nothing gets done and production board can't boot without DTS modifications.
2) Disable tags are added to the DTS file and the debug board can't use coresight without modifications.
2) The handling of the debug power domain is done properly on the MSM8998 rather than relying on the bootloader to enable it.
3) The DTS file is split or reorganised to account for debug/production devices.
msm8998.dtsi is a SoC include file. Can't whatever default it adopts be reversed in the board include files such as msm8998-mtp.dtsi or msm8998-clamshell.dtsi ?
Daniel.
Re: [PATCHv9 2/3] arm64: dts: qcom: msm8998: Add Coresight support
Quoted 39 lines · Daniel Thompson
Quoted 31 lines · Mathieu Poirier
Quoted 16 lines · Sai Prakash Ranjan
Quoted 14 lines · Jeffrey Hugo
Quoted 7 lines · Sai Prakash Ranjan
Haan then likely it's the firmware issue.
We should probably disable coresight in soc dtsi and enable only for MTP. For now you can add a status=disabled for all coresight nodes inmsm8998.dtsiand I will send the patch doing the same in a day or two(sorry I am travelling currently).This sounds sane to me (and is what I did while bisecting the issue). When you do create the patch, feel free to add the following tags as you see fit.
Quoted 5 lines
Quoted 2 lines
Reported-by Jeffrey Hugo <[email protected]>Tested-by Jeffrey Hugo <[email protected]>Thanks Jeffrey, I will add them.
Hope Mathieu and Suzuki are OK with this.The problem here is that a debug and production device are using the same device tree, i.e
msm8998.dtsi. Disabling coresight devices in the DTS file will allow the laptop to boot but completely disabled coresight blocks on the MTP board. Leaving things as is breaks the laptop but allows coresight to be used on the MTP board. One of three things can happen:Quoted 6 lines
1) Nothing gets done and production board can't boot without DTS modifications.
2) Disable tags are added to the DTS file and the debug board can't use coresight without modifications.
2) The handling of the debug power domain is done properly on the MSM8998 rather than relying on the bootloader to enable it.
3) The DTS file is split or reorganised to account for debug/production devices.
Quoted 3 lines
msm8998.dtsiis a SoC include file. Can't whatever default it adopts be reversed in the board include files such asmsm8998-mtp.dtsiormsm8998-clamshell.dtsi?
Or like Mathieu said, all the Coresight specific nodes could be moved in to say, msm8998-coresight.dtsi and could be included into the platforms where it actually works.
Suzuki
Re: [PATCHv9 2/3] arm64: dts: qcom: msm8998: Add Coresight support
Quoted 40 lines · Suzuki K Poulose
Quoted 39 lines · Daniel Thompson
Quoted 37 lines · Mathieu Poirier
Quoted 16 lines · Sai Prakash Ranjan
Quoted 14 lines · Jeffrey Hugo
Quoted 7 lines · Sai Prakash Ranjan
Haan then likely it's the firmware issue.
We should probably disable coresight in soc dtsi and enable only for MTP. For now you can add a status=disabled for all coresight nodes inmsm8998.dtsiand I will send the patch doing the same in a day or two(sorry I am travelling currently).This sounds sane to me (and is what I did while bisecting the issue). When you do create the patch, feel free to add the following tags as you see fit.
Quoted 5 lines
Quoted 2 lines
Reported-by Jeffrey Hugo <[email protected]>Tested-by Jeffrey Hugo <[email protected]>Thanks Jeffrey, I will add them.
Hope Mathieu and Suzuki are OK with this.The problem here is that a debug and production device are using the same device tree, i.e
msm8998.dtsi. Disabling coresight devices in the DTS file will allow the laptop to boot but completely disabled coresight blocks on the MTP board. Leaving things as is breaks the laptop but allows coresight to be used on the MTP board. One of three things can happen:1) Nothing gets done and production board can't boot without DTS modifications.
2) Disable tags are added to the DTS file and the debug board can't use coresight without modifications.
2) The handling of the debug power domain is done properly on the MSM8998 rather than relying on the bootloader to enable it.
3) The DTS file is split or reorganised to account for debug/production devices.
Quoted 7 lines
Quoted 3 lines
msm8998.dtsiis a SoC include file. Can't whatever default it adopts be reversed in the board include files such asmsm8998-mtp.dtsiormsm8998-clamshell.dtsi?Or like Mathieu said, all the Coresight specific nodes could be moved in to say,
msm8998-coresight.dtsiand could be included into the platforms where it actually works.
Sure, that works too.
Maybe it depends in you view the mtp as including the feature or as the laptops as taking it away ;-) .
Treating it as a feature a board can disable also works nicely on systems where the board include file should be setting secure-status a board (although that's probably not the case for these boards since the firmware is proprietary).
Daniel.
PATCH v9 3/3 arm64: dts: qcom: msm8996: Add Coresight support
In reply to Sai Prakash RanjanFrom: Vivek Gautam <[email protected]>
Enable coresight support by adding device nodes for the available source, sinks and channel blocks on msm8996.
This also adds coresight cpu debug nodes.
--- arch/arm64/boot/dts/qcom/msm8996.dtsi | 468 ++++++++++++++++++++++++++ 1 file changed, 468 insertions(+)
arch/arm64/boot/dts/qcom/msm8996.dtsi +468 -0
@@ -633,6 +633,474 @@ reg = <0x300000 0x90000>; }; + stm@3002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x3002000 0x1000>, + <0x8280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = + <&funnel0_in>; + }; + }; + }; + }; + + tpiu@3020000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x3020000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + port { + tpiu_in: endpoint { + remote-endpoint = + <&replicator_out1>; + }; + }; + }; + }; + + funnel@3021000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x3021000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + funnel0_in: endpoint { + remote-endpoint = + <&stm_out>; + }; + }; + }; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = + <&merge_funnel_in0>; + }; + }; + }; + }; + + funnel@3022000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x3022000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@6 { + reg = <6>; + funnel1_in: endpoint { + remote-endpoint = + <&apss_merge_funnel_out>; + }; + }; + }; + + out-ports { + port { + funnel1_out: endpoint { + remote-endpoint = + <&merge_funnel_in1>; + }; + }; + }; + }; + + funnel@3023000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x3023000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + + out-ports { + port { + funnel2_out: endpoint { + remote-endpoint = + <&merge_funnel_in2>; + }; + }; + }; + }; + + funnel@3025000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x3025000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + merge_funnel_in0: endpoint { + remote-endpoint = + <&funnel0_out>; + }; + }; + + port@1 { + reg = <1>; + merge_funnel_in1: endpoint { + remote-endpoint = + <&funnel1_out>; + }; + }; + + port@2 { + reg = <2>; + merge_funnel_in2: endpoint { + remote-endpoint = + <&funnel2_out>; + }; + }; + }; + + out-ports { + port { + merge_funnel_out: endpoint { + remote-endpoint = + <&etf_in>; + }; + }; + }; + }; + + replicator@3026000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x3026000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = + <&etf_out>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out0: endpoint { + remote-endpoint = + <&etr_in>; + }; + }; + + port@1 { + reg = <1>; + replicator_out1: endpoint { + remote-endpoint = + <&tpiu_in>; + }; + }; + }; + }; + + etf@3027000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x3027000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + port { + etf_in: endpoint { + remote-endpoint = + <&merge_funnel_out>; + }; + }; + }; + + out-ports { + port { + etf_out: endpoint { + remote-endpoint = + <&replicator_in>; + }; + }; + }; + }; + + etr@3028000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x3028000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + arm,scatter-gather; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = + <&replicator_out0>; + }; + }; + }; + }; + + debug@3810000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x3810000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU0>; + }; + + etm@3840000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x3840000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU0>; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = + <&apss_funnel0_in0>; + }; + }; + }; + }; + + debug@3910000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x3910000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU1>; + }; + + etm@3940000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x3940000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU1>; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = + <&apss_funnel0_in1>; + }; + }; + }; + }; + + funnel@39b0000 { /* APSS Funnel 0 */ + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x39b0000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel0_in0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel0_in1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + }; + + out-ports { + port { + apss_funnel0_out: endpoint { + remote-endpoint = + <&apss_merge_funnel_in0>; + }; + }; + }; + }; + + debug@3a10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x3a10000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU2>; + }; + + etm@3a40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x3a40000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU2>; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = + <&apss_funnel1_in0>; + }; + }; + }; + }; + + debug@3b10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x3b10000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU3>; + }; + + etm@3b40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x3b40000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU3>; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = + <&apss_funnel1_in1>; + }; + }; + }; + }; + + funnel@3bb0000 { /* APSS Funnel 1 */ + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x3bb0000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel1_in0: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel1_in1: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + }; + + out-ports { + port { + apss_funnel1_out: endpoint { + remote-endpoint = + <&apss_merge_funnel_in1>; + }; + }; + }; + }; + + funnel@3bc0000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x3bc0000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_merge_funnel_in0: endpoint { + remote-endpoint = + <&apss_funnel0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_merge_funnel_in1: endpoint { + remote-endpoint = + <&apss_funnel1_out>; + }; + }; + }; + + out-ports { + port { + apss_merge_funnel_out: endpoint { + remote-endpoint = + <&funnel1_in>; + }; + }; + }; + }; + kryocc: clock-controller@6400000 { compatible = "qcom,apcc-msm8996"; reg = <0x6400000 0x90000>;
Signature · 2 lines
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