add Tegra194 XUSB host and pad controller support
Subsystems (6)
JC Kuo
maintainerv2 cover add Tegra194 XUSB host and pad controller support
Hi,
This series introduces support for Tegra194 XUSB host and pad controller. Tegra194 XUSB host and pad controller are highly similar to the controllers found on Tegra186. Therefore, it's possible to resue xhci-tegra.c and xusb-tegra186.c for Tegra194.
JC Kuo (7):
xhci: tegra: Parameterize mailbox register addresses
usb: host: xhci-tegra: Add Tegra194 XHCI support
phy: tegra: xusb: Protect Tegra186 soc with config
phy: tegra: xusb: Add Tegra194 support
dt-bindings: phy: tegra: Add Tegra194 support
arm64: tegra: Add XUSB and pad controller on Tegra194
arm64: tegra: Enable XUSB host in P2972-0000 board
.../phy/nvidia,tegra124-xusb-padctl.txt | 16 ++ .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 36 ++++- .../boot/dts/nvidia/tegra194-p2972-0000.dts | 62 ++++++++ arch/arm64/boot/dts/nvidia/tegra194.dtsi | 139 +++++++++++++++++ drivers/phy/tegra/Makefile | 1 + drivers/phy/tegra/xusb-tegra186.c | 144 +++++++++++++----- drivers/phy/tegra/xusb.c | 7 + drivers/phy/tegra/xusb.h | 6 + drivers/usb/host/xhci-tegra.c | 88 +++++++++-- 9 files changed, 448 insertions(+), 51 deletions(-)
Signature · 1 line
2.17.1
JC Kuo
maintainerPATCH v2 1/7 xhci: tegra: Parameterize mailbox register addresses
Tegra194 XUSB host controller has rearranged mailbox registers. This commit makes mailbox registers address a part of "soc" data so that xhci-tegra driver can be used for Tegra194.
--- drivers/usb/host/xhci-tegra.c | 58 +++++++++++++++++++++++++---------- 1 file changed, 42 insertions(+), 16 deletions(-)
drivers/usb/host/xhci-tegra.c +42 -16
@@ -42,19 +42,18 @@#define XUSB_CFG_CSB_BASE_ADDR 0x800/* FPCI mailbox registers */ -#define XUSB_CFG_ARU_MBOX_CMD 0x0e4 +/* XUSB_CFG_ARU_MBOX_CMD */ #define MBOX_DEST_FALC BIT(27)#define MBOX_DEST_PME BIT(28)#define MBOX_DEST_SMI BIT(29)#define MBOX_DEST_XHCI BIT(30)#define MBOX_INT_EN BIT(31) -#define XUSB_CFG_ARU_MBOX_DATA_IN 0x0e8 +/* XUSB_CFG_ARU_MBOX_DATA_IN and XUSB_CFG_ARU_MBOX_DATA_OUT */ #define CMD_DATA_SHIFT 0#define CMD_DATA_MASK 0xffffff#define CMD_TYPE_SHIFT 24#define CMD_TYPE_MASK 0xff -#define XUSB_CFG_ARU_MBOX_DATA_OUT 0x0ec -#define XUSB_CFG_ARU_MBOX_OWNER 0x0f0 +/* XUSB_CFG_ARU_MBOX_OWNER */ #define MBOX_OWNER_NONE 0#define MBOX_OWNER_FW 1#define MBOX_OWNER_SW 2
@@ -146,6 +145,13 @@ struct tegra_xusb_phy_type {unsigned int num; }; +struct tega_xusb_mbox_regs { +u16 cmd; +u16 data_in; +u16 data_out; +u16 owner; +}; +struct tegra_xusb_soc {const char *firmware;const char *const *supply_names;
@@ -160,6 +166,8 @@ struct tegra_xusb_soc { } usb2, ulpi, hsic, usb3; } ports; +struct tega_xusb_mbox_regs mbox; +bool scale_ss_clock;bool has_ipfs; };
@@ -395,15 +403,15 @@ static int tegra_xusb_mbox_send(struct tegra_xusb *tegra,* ACK/NAK messages. */ if (!(msg->cmd ==MBOX_CMD_ACK || msg->cmd ==MBOX_CMD_NAK )) { - value =fpci_readl (tegra,XUSB_CFG_ARU_MBOX_OWNER ); + value =fpci_readl (tegra, tegra->soc->mbox.owner);if (value !=MBOX_OWNER_NONE ) {dev_err (tegra->dev,"mailbox is busy\n" );return -EBUSY ; } -fpci_writel (tegra,MBOX_OWNER_SW ,XUSB_CFG_ARU_MBOX_OWNER ); +fpci_writel (tegra,MBOX_OWNER_SW , tegra->soc->mbox.owner); - value =fpci_readl (tegra,XUSB_CFG_ARU_MBOX_OWNER ); + value =fpci_readl (tegra, tegra->soc->mbox.owner);if (value !=MBOX_OWNER_SW ) {dev_err (tegra->dev,"failed to acquire mailbox\n" );return -EBUSY ;
@@ -413,17 +421,17 @@ static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, } value =tegra_xusb_mbox_pack (msg); -fpci_writel (tegra, value,XUSB_CFG_ARU_MBOX_DATA_IN ); +fpci_writel (tegra, value, tegra->soc->mbox.data_in); - value =fpci_readl (tegra,XUSB_CFG_ARU_MBOX_CMD ); + value =fpci_readl (tegra, tegra->soc->mbox.cmd); value |=MBOX_INT_EN |MBOX_DEST_FALC ; -fpci_writel (tegra, value,XUSB_CFG_ARU_MBOX_CMD ); +fpci_writel (tegra, value, tegra->soc->mbox.cmd);if (wait_for_idle) {unsigned long timeout = jiffies +msecs_to_jiffies (250 );while (time_before (jiffies, timeout)) { - value =fpci_readl (tegra,XUSB_CFG_ARU_MBOX_OWNER ); + value =fpci_readl (tegra, tegra->soc->mbox.owner);if (value ==MBOX_OWNER_NONE )break ;
@@ -431,7 +439,7 @@ static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, }if (time_after (jiffies, timeout)) - value =fpci_readl (tegra,XUSB_CFG_ARU_MBOX_OWNER ); + value =fpci_readl (tegra, tegra->soc->mbox.owner);if (value !=MBOX_OWNER_NONE )return -ETIMEDOUT ;
@@ -598,16 +606,16 @@ static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data)mutex_lock (&tegra->lock); - value =fpci_readl (tegra,XUSB_CFG_ARU_MBOX_DATA_OUT ); + value =fpci_readl (tegra, tegra->soc->mbox.data_out);tegra_xusb_mbox_unpack (&msg, value); - value =fpci_readl (tegra,XUSB_CFG_ARU_MBOX_CMD ); + value =fpci_readl (tegra, tegra->soc->mbox.cmd); value &= ~MBOX_DEST_SMI ; -fpci_writel (tegra, value,XUSB_CFG_ARU_MBOX_CMD ); +fpci_writel (tegra, value, tegra->soc->mbox.cmd);/* clear mailbox owner if no ACK/NAK is required */ if (!tegra_xusb_mbox_cmd_requires_ack (msg.cmd)) -fpci_writel (tegra,MBOX_OWNER_NONE ,XUSB_CFG_ARU_MBOX_OWNER ); +fpci_writel (tegra,MBOX_OWNER_NONE , tegra->soc->mbox.owner);tegra_xusb_mbox_handle (tegra, &msg);
@@ -1375,6 +1383,12 @@ static const struct tegra_xusb_soc tegra124_soc = { }, .scale_ss_clock = true, .has_ipfs = true, + .mbox = { + .cmd = 0xe4, + .data_in = 0xe8, + .data_out = 0xec, + .owner = 0xf0, + }, };MODULE_FIRMWARE ("nvidia/tegra124/xusb.bin" );
@@ -1407,6 +1421,12 @@ static const struct tegra_xusb_soc tegra210_soc = { }, .scale_ss_clock = false, .has_ipfs = true, + .mbox = { + .cmd = 0xe4, + .data_in = 0xe8, + .data_out = 0xec, + .owner = 0xf0, + }, };MODULE_FIRMWARE ("nvidia/tegra210/xusb.bin" );
@@ -1432,6 +1452,12 @@ static const struct tegra_xusb_soc tegra186_soc = { }, .scale_ss_clock = false, .has_ipfs = false, + .mbox = { + .cmd = 0xe4, + .data_in = 0xe8, + .data_out = 0xec, + .owner = 0xf0, + }, };static const struct of_device_id tegra_xusb_of_match[] = {
Signature · 1 line
2.17.1
JC Kuo
maintainerPATCH v2 2/7 usb: host: xhci-tegra: Add Tegra194 XHCI support
In reply to JC KuoThis commit adds Tegra194 XUSB host mode controller support. This is very similar to the existing Tegra124/Tegra210/Tegra186 XHCI, except
1. the number of ports and PHYs differs
2. the IPFS wrapper being removed
3. mailbox registers address changes
--- drivers/usb/host/xhci-tegra.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)
drivers/usb/host/xhci-tegra.c +30 -0
@@ -1460,10 +1460,40 @@ static const struct tegra_xusb_soc tegra186_soc = { }, }; +static const char *const tegra194_supply_names[] = { +}; + +static const struct tegra_xusb_phy_type tegra194_phy_types[] = { + { .name ="usb3" , .num =4 , }, + { .name ="usb2" , .num =4 , }, +}; + +static const struct tegra_xusb_soc tegra194_soc = { + .firmware ="nvidia/tegra194/xusb.bin" , + .supply_names = tegra194_supply_names, + .num_supplies =ARRAY_SIZE (tegra194_supply_names), + .phy_types = tegra194_phy_types, + .num_types =ARRAY_SIZE (tegra194_phy_types), + .ports = { + .usb3 = { .offset =0 , .count =4 , }, + .usb2 = { .offset =4 , .count =4 , }, + }, + .scale_ss_clock = false, + .has_ipfs = false, + .mbox = { + .cmd =0x68 , + .data_in =0x6c , + .data_out =0x70 , + .owner =0x74 , + }, +}; +MODULE_FIRMWARE ("nvidia/tegra194/xusb.bin" ); +static const struct of_device_id tegra_xusb_of_match[] = { { .compatible ="nvidia,tegra124-xusb" , .data = &tegra124_soc }, { .compatible ="nvidia,tegra210-xusb" , .data = &tegra210_soc }, { .compatible ="nvidia,tegra186-xusb" , .data = &tegra186_soc }, + { .compatible ="nvidia,tegra194-xusb" , .data = &tegra194_soc }, { }, };MODULE_DEVICE_TABLE (of, tegra_xusb_of_match);
Signature · 1 line
2.17.1
JC Kuo
maintainerPATCH v2 3/7 phy: tegra: xusb: Protect Tegra186 soc with config
In reply to JC KuoAs xusb-tegra186.c will be reused for Tegra194, it would be good to protect Tegra186 soc data with CONFIG_ARCH_TEGRA_186_SOC. This commit also reshuffles Tegra186 soc data single CONFIG_ARCH_TEGRA_186_SOC will be sufficient.
---
Changes in v2:
- new patch to protect Tegra186 soc data with config
drivers/phy/tegra/xusb-tegra186.c | 70 ++++++++++++++++--------------- 1 file changed, 36 insertions(+), 34 deletions(-)
drivers/phy/tegra/xusb-tegra186.c +36 -34
@@ -503,19 +503,6 @@ static const char * const tegra186_usb2_functions[] = { "xusb", }; -static const struct tegra_xusb_lane_soc tegra186_usb2_lanes[] = { -TEGRA186_LANE ("usb2-0" ,0 ,0 ,0 , usb2), -TEGRA186_LANE ("usb2-1" ,0 ,0 ,0 , usb2), -TEGRA186_LANE ("usb2-2" ,0 ,0 ,0 , usb2), -}; - -static const struct tegra_xusb_pad_soc tegra186_usb2_pad = { - .name ="usb2" , - .num_lanes =ARRAY_SIZE (tegra186_usb2_lanes), - .lanes = tegra186_usb2_lanes, - .ops = &tegra186_usb2_pad_ops, -}; -static int tegra186_usb2_port_enable (struct tegra_xusb_port *port) {return 0 ;
@@ -765,27 +752,6 @@ static const char * const tegra186_usb3_functions[] = { "xusb", }; -static const struct tegra_xusb_lane_soc tegra186_usb3_lanes[] = { -TEGRA186_LANE ("usb3-0" ,0 ,0 ,0 , usb3), -TEGRA186_LANE ("usb3-1" ,0 ,0 ,0 , usb3), -TEGRA186_LANE ("usb3-2" ,0 ,0 ,0 , usb3), -}; - -static const struct tegra_xusb_pad_soc tegra186_usb3_pad = { - .name ="usb3" , - .num_lanes =ARRAY_SIZE (tegra186_usb3_lanes), - .lanes = tegra186_usb3_lanes, - .ops = &tegra186_usb3_pad_ops, -}; - -static const struct tegra_xusb_pad_soc *const tegra186_pads[] = { - &tegra186_usb2_pad, - &tegra186_usb3_pad, -#if 0 /* TODO implement */ - &tegra186_hsic_pad, -#endif -}; -static int tegra186_xusb_read_fuse_calibration (struct tegra186_xusb_padctl *padctl) {
@@ -862,6 +828,7 @@ static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = { .remove = tegra186_xusb_padctl_remove, }; +#if IS_ENABLED (CONFIG_ARCH_TEGRA_186_SOC )static const char *const tegra186_xusb_padctl_supply_names[] = {"avdd-pll-erefeut" , "avdd-usb",
@@ -869,6 +836,40 @@ static const char * const tegra186_xusb_padctl_supply_names[] = { "vddio-hsic", }; +static const struct tegra_xusb_lane_soc tegra186_usb2_lanes[] = { +TEGRA186_LANE ("usb2-0" ,0 ,0 ,0 , usb2), +TEGRA186_LANE ("usb2-1" ,0 ,0 ,0 , usb2), +TEGRA186_LANE ("usb2-2" ,0 ,0 ,0 , usb2), +}; + +static const struct tegra_xusb_pad_soc tegra186_usb2_pad = { + .name ="usb2" , + .num_lanes =ARRAY_SIZE (tegra186_usb2_lanes), + .lanes = tegra186_usb2_lanes, + .ops = &tegra186_usb2_pad_ops, +}; + +static const struct tegra_xusb_lane_soc tegra186_usb3_lanes[] = { +TEGRA186_LANE ("usb3-0" ,0 ,0 ,0 , usb3), +TEGRA186_LANE ("usb3-1" ,0 ,0 ,0 , usb3), +TEGRA186_LANE ("usb3-2" ,0 ,0 ,0 , usb3), +}; + +static const struct tegra_xusb_pad_soc tegra186_usb3_pad = { + .name ="usb3" , + .num_lanes =ARRAY_SIZE (tegra186_usb3_lanes), + .lanes = tegra186_usb3_lanes, + .ops = &tegra186_usb3_pad_ops, +}; + +static const struct tegra_xusb_pad_soc *const tegra186_pads[] = { + &tegra186_usb2_pad, + &tegra186_usb3_pad, +#if 0 /* TODO implement */ + &tegra186_hsic_pad, +#endif +}; +const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = { .num_pads =ARRAY_SIZE (tegra186_pads), .pads = tegra186_pads,
@@ -893,6 +894,7 @@ const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = { .num_supplies = ARRAY_SIZE(tegra186_xusb_padctl_supply_names), };EXPORT_SYMBOL_GPL (tegra186_xusb_padctl_soc); +#endif MODULE_AUTHOR ("JC Kuo <[email protected]>" );MODULE_DESCRIPTION ("NVIDIA Tegra186 XUSB Pad Controller driver" );
Signature · 1 line
2.17.1
JC Kuo
maintainerPATCH v2 4/7 phy: tegra: xusb: Add Tegra194 support
In reply to JC KuoAdd support for the XUSB pad controller found on Tegra194 SoCs. It is mostly similar to the same IP found on Tegra186, but the number of pads exposed differs, as do the programming sequences. Because most of the Tegra194 XUSB PADCTL registers definition and programming sequence are the same as Tegra186, Tegra194 XUSB PADCTL can share the same driver, xusb-tegra186.c, with Tegra186 XUSB PADCTL.
Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it is possible for some platforms have long signal trace that could not provide sufficient electrical environment for Gen 2 speed. This patch introduce a new device node property "nvidia,disable-gen2" that can be used to specifically disable Gen 2 speed for a particular USB 3.0 port so that the port can be limited to Gen 1 speed and avoid the instability.
---
Changes in v2:
- removed unnecessary #if/#endif pairs
- introduce new soc->supports_gen2 flag which indicate whether or not a soc supports USB 3.1 Gen 2 speed
drivers/phy/tegra/Makefile | 1 + drivers/phy/tegra/xusb-tegra186.c | 74 +++++++++++++++++++++++++++++++ drivers/phy/tegra/xusb.c | 7 +++ drivers/phy/tegra/xusb.h | 6 +++ 4 files changed, 88 insertions(+)
drivers/phy/tegra/Makefile +1 -0
@@ -6,4 +6,5 @@ phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_124_SOC) += xusb-tegra124.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_132_SOC) += xusb-tegra124.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_210_SOC) += xusb-tegra210.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_186_SOC) += xusb-tegra186.o +phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_194_SOC) += xusb-tegra186.o obj-$(CONFIG_PHY_TEGRA194_P2U) += phy-tegra194-p2u.o
drivers/phy/tegra/xusb-tegra186.c +74 -0
92 lines not on this page · raw message
drivers/phy/tegra/xusb.c +7 -0
@@ -65,6 +65,12 @@ static const struct of_device_id tegra_xusb_padctl_of_match[] = { .compatible = "nvidia,tegra186-xusb-padctl", .data = &tegra186_xusb_padctl_soc, }, +#endif +#if defined(CONFIG_ARCH_TEGRA_194_SOC ) + { + .compatible = "nvidia,tegra194-xusb-padctl", + .data = &tegra194_xusb_padctl_soc, + }, #endif { } };
@@ -738,6 +744,7 @@ static int tegra_xusb_usb3_port_parse_dt(struct tegra_xusb_usb3_port *usb3) usb3->port = value; usb3->internal =of_property_read_bool (np,"nvidia,internal" ); + usb3->disable_gen2 =of_property_read_bool (np,"nvidia,disable-gen2" ); usb3->supply =devm_regulator_get (&port->dev,"vbus" );return PTR_ERR_OR_ZERO (usb3->supply);
drivers/phy/tegra/xusb.h +6 -0
@@ -332,6 +332,7 @@ struct tegra_xusb_usb3_port {bool context_saved;unsigned int port;bool internal; +bool disable_gen2;u32 tap1;u32 amp;
@@ -389,6 +390,8 @@ struct tegra_xusb_padctl_soc {const char *const *supply_names;unsigned int num_supplies; + +bool supports_gen2; };struct tegra_xusb_padctl {
@@ -444,5 +447,8 @@ extern const struct tegra_xusb_padctl_soc tegra210_xusb_padctl_soc;#if defined(CONFIG_ARCH_TEGRA_186_SOC )extern const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc;#endif +#if defined(CONFIG_ARCH_TEGRA_194_SOC ) +extern const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc; +#endif #endif /* __PHY_TEGRA_XUSB_H */
Signature · 1 line
2.17.1
JC Kuo
maintainerPATCH v2 5/7 dt-bindings: phy: tegra: Add Tegra194 support
In reply to JC KuoExtend the bindings to cover the set of features found in Tegra194. Note that, technically, there are four more supplies connected to the XUSB pad controller (DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL) , but the power sequencing requirements of Tegra194 require these to be under the control of the PMIC.
Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it is possible for some platforms have long signal trace that could not provide sufficient electrical environment for Gen 2 speed. To deal with this, a new device node property "nvidia,disable-gen2" was added to Tegra194 that be used to specifically disable Gen 2 speed for a particular USB 3.0 port so that the port can be limited to Gen 1 speed and avoid the instability.
---
Changes in v2:
- fix a typo
.../bindings/phy/nvidia,tegra124-xusb-padctl.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt +16 -0
@@ -37,6 +37,7 @@ Required properties: - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl" - Tegra210: "nvidia,tegra210-xusb-padctl" - Tegra186: "nvidia,tegra186-xusb-padctl" + - Tegra194: "nvidia,tegra194-xusb-padctl" - reg: Physical base address and length of the controller's registers. - resets: Must contain an entry for each entry in reset-names. - reset-names: Must include the following entries:
@@ -62,6 +63,10 @@ For Tegra186: - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V. - vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V. +For Tegra194: +- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply + 3.3 V. +- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V. Pad nodes: ==========
@@ -154,6 +159,11 @@ For Tegra210, the list of valid PHY nodes is given below: - sata: sata-0 - functions: "usb3-ss", "sata" +For Tegra194, the list of valid PHY nodes is given below: +- usb2: usb2-0, usb2-1, usb2-2, usb2-3 + - functions: "xusb" +- usb3: usb3-0, usb3-1, usb3-2, usb3-3 + - functions: "xusb" Port nodes: ===========
@@ -221,6 +231,9 @@ Optional properties: is internal. In the absence of this property the port is considered to be external. +- nvidia,disable-gen2: A boolean property whose presence determines that a port + should be limited to USB 3.1 Gen 1. This property is only for Tegra194. + For Tegra124 and Tegra132, the XUSB pad controller exposes the following ports: - 3x USB2: usb2-0, usb2-1, usb2-2
@@ -233,6 +246,9 @@ For Tegra210, the XUSB pad controller exposes the following ports: - 2x HSIC: hsic-0, hsic-1 - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3 +For Tegra194, the XUSB pad controller exposes the following ports: +- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3 +- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3 Examples: =========
Signature · 1 line
2.17.1
JC Kuo
maintainerPATCH v2 6/7 arm64: tegra: Add XUSB and pad controller on Tegra194
In reply to JC KuoAdds the XUSB pad and XUSB controllers on Tegra194.
---
Changes in v2:
- renamed xhci@3610000 with usb@3610000
- moved padctl@3520000 and usb@3610000 inside /cbb
- cleaned up "clocks" property of usb@3610000 node
- added blanks lines to visually separate blocks
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 139 +++++++++++++++++++++++ 1 file changed, 139 insertions(+)
arch/arm64/boot/dts/nvidia/tegra194.dtsi +139 -0
@@ -487,6 +487,145 @@ status = "disabled"; }; + xusb_padctl: padctl@3520000 { + compatible = "nvidia,tegra194-xusb-padctl"; + reg = <0x03520000 0x1000>, + <0x03540000 0x1000>; + reg-names = "padctl", "ao"; + + resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; + reset-names = "padctl"; + + status = "disabled"; + + pads { + usb2 { + clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; + clock-names = "trk"; + + lanes { + usb2-0 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-1 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-2 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-3 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + + usb3 { + lanes { + usb3-0 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-1 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-2 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-3 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + }; + + ports { + usb2-0 { + status = "disabled"; + }; + + usb2-1 { + status = "disabled"; + }; + + usb2-2 { + status = "disabled"; + }; + + usb2-3 { + status = "disabled"; + }; + + usb3-0 { + status = "disabled"; + }; + + usb3-1 { + status = "disabled"; + }; + + usb3-2 { + status = "disabled"; + }; + + usb3-3 { + status = "disabled"; + }; + }; + }; + + usb@3610000 { + compatible = "nvidia,tegra194-xusb"; + reg = <0x03610000 0x40000>, + < 0x03600000 0x10000>; + reg-names = "hcd", "fpci"; + + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, + <&bpmp TEGRA194_CLK_XUSB_FALCON>, + <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA194_CLK_XUSB_SS>, + <&bpmp TEGRA194_CLK_CLK_M>, + <&bpmp TEGRA194_CLK_XUSB_FS>, + <&bpmp TEGRA194_CLK_UTMIPLL>, + <&bpmp TEGRA194_CLK_CLK_M>, + <&bpmp TEGRA194_CLK_PLLE>; + clock-names = "xusb_host", "xusb_falcon_src", + "xusb_ss", "xusb_ss_src", "xusb_hs_src", + "xusb_fs_src", "pll_u_480m", "clk_m", + "pll_e"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, + <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; + power-domain-names = "xusb_host", "xusb_ss"; + + nvidia,xusb-padctl = <&xusb_padctl>; + status = "disabled"; + }; + gic: interrupt-controller@3881000 { compatible = "arm,gic-400"; #interrupt-cells = <3>;
Signature · 1 line
2.17.1
JC Kuo
maintainerPATCH v2 7/7 arm64: tegra: Enable XUSB host in P2972-0000 board
In reply to JC KuoThis commit enables XUSB host and pad controller in Tegra194 P2972-0000 board.
---
Changes in v2:
- use capitalization of regulator names
- fix gpio property of VDD_5V_SATA regulator
.../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 36 ++++++++++- .../boot/dts/nvidia/tegra194-p2972-0000.dts | 62 +++++++++++++++++++ 2 files changed, 97 insertions(+), 1 deletion(-)
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +35 -1
@@ -66,6 +66,29 @@ vmmc-supply = <&vdd_emmc_3v3>; }; + padctl@3520000 { + avdd-usb-supply = <&vdd_usb_3v3>; + vclamp-usb-supply = <&vdd_1v8ao>; + + ports { + usb2-1 { + vbus-supply = <&vdd_5v0_sys>; + }; + + usb2-3 { + vbus-supply = <&vdd_5v_sata>; + }; + + usb3-0 { + vbus-supply = <&vdd_5v0_sys>; + }; + + usb3-3 { + vbus-supply = <&vdd_5v0_sys>; + }; + }; + }; + rtc@c2a0000 { status = "okay"; };
@@ -229,7 +252,7 @@ regulator-max-microvolt = <3300000>; }; - ldo5 { + vdd_usb_3v3: ldo5 { regulator-name = "VDD_USB_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
@@ -313,5 +336,16 @@ regulator-boot-on; enable-active-low; }; + + vdd_5v_sata: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + + regulator-name = "VDD_5V_SATA"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; };
arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +62 -0
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Signature · 1 line
2.17.1
Greg KH
maintainerQuoted 7 lines · JC Kuo
Hi,
This series introduces support for Tegra194 XUSB host and pad controller. Tegra194 XUSB host and pad controller are highly similar to the controllers found on Tegra186. Therefore, it's possible to resue
xhci-tegra.candxusb-tegra186.cfor Tegra194.
Quoted 8 lines
JC Kuo (7):
xhci: tegra: Parameterize mailbox register addresses
usb: host: xhci-tegra: Add Tegra194 XHCI support
phy: tegra: xusb: Protect Tegra186 soc with config
phy: tegra: xusb: Add Tegra194 support
dt-bindings: phy: tegra: Add Tegra194 support
arm64: tegra: Add XUSB and pad controller on Tegra194
arm64: tegra: Enable XUSB host in P2972-0000 board
What changed from v1? You need to put that somewhere, usually in the patches themselves, below the --- line.
Or at the very least, in the cover letter.
Given that I can't find it anywhere here, I'll expect a v3 with that information to be sent soon :(
thanks,
greg k-h
JC Kuo
maintainerQuoted 17 lines · Greg KH
Quoted 7 lines · JC Kuo
Hi,
This series introduces support for Tegra194 XUSB host and pad controller. Tegra194 XUSB host and pad controller are highly similar to the controllers found on Tegra186. Therefore, it's possible to resue
xhci-tegra.candxusb-tegra186.cfor Tegra194.Quoted 8 lines
JC Kuo (7):
xhci: tegra: Parameterize mailbox register addresses
usb: host: xhci-tegra: Add Tegra194 XHCI support
phy: tegra: xusb: Protect Tegra186 soc with config
phy: tegra: xusb: Add Tegra194 support
dt-bindings: phy: tegra: Add Tegra194 support
arm64: tegra: Add XUSB and pad controller on Tegra194
arm64: tegra: Enable XUSB host in P2972-0000 board
Quoted 8 lines
What changed from v1? You need to put that somewhere, usually in the patches themselves, below the --- line.
Or at the very least, in the cover letter.
Given that I can't find it anywhere here, I'll expect a v3 with that information to be sent soon :(
For the first two patches, v2 is identical to v1, sorry that I didn't describe in patches. For the patches 3 to 7, the individual patch has "Changes in v2:" session to describe.
I will submit v3 with patch 1 and 2 updated.
Thanks for the guidance,
JC