add Tegra194 XUSB host and pad controller support
Subsystems (5)
JC Kuo
maintainerv6 cover add Tegra194 XUSB host and pad controller support
v6:
phy: tegra: xusb: Protect Tegra186 soc with config
- no change
phy: tegra: xusb: Add Tegra194 support
- no change
dt-bindings: phy: tegra: Add Tegra194 support
- no change
arm64: tegra: Add XUSB and pad controller on Tegra194
- rebased
arm64: tegra: Enable XUSB host in P2972-0000 board
- re-use "maximum-speed" instead of adding "nvidia,disable-gen2"
v5:
phy: tegra: xusb: Protect Tegra186 soc with config
- no change
phy: tegra: xusb: Add Tegra194 support
- re-use "maximum-speed" instead of adding "nvidia,disable-gen2"
dt-bindings: phy: tegra: Add Tegra194 support
- re-use "maximum-speed" instead of adding "nvidia,disable-gen2"
arm64: tegra: Add XUSB and pad controller on Tegra194
- no change
arm64: tegra: Enable XUSB host in P2972-0000 board
- no change
v3:
add change log to cover latter
v2:
xhci: tegra: Parameterize mailbox register addresses
- no change
usb: host: xhci-tegra: Add Tegra194 XHCI support
- no change
phy: tegra: xusb: Protect Tegra186 soc with config
- new patch to protect Tegra186 soc data with config
phy: tegra: xusb: Add Tegra194 support
- removed unnecessary #if/#endif pairs
- introduce new soc->supports_gen2 flag which indicate whether or not a soc supports USB 3.1 Gen 2 speed
dt-bindings: phy: tegra: Add Tegra194 support
- fix a typo
arm64: tegra: Add XUSB and pad controller on Tegra194
- renamed xhci@3610000 with usb@3610000
- moved padctl@3520000 and usb@3610000 inside /cbb
- cleaned up "clocks" property of usb@3610000 node
- added blanks lines to visually separate blocks
arm64: tegra: Enable XUSB host in P2972-0000 board
- use capitalization of regulator names
- fix gpio property of VDD_5V_SATA regulator
JC Kuo (5):
phy: tegra: xusb: Protect Tegra186 soc with config
phy: tegra: xusb: Add Tegra194 support
dt-bindings: phy: tegra: Add Tegra194 support
arm64: tegra: Add XUSB and pad controller on Tegra194
arm64: tegra: Enable XUSB host in P2972-0000 board
.../phy/nvidia,tegra124-xusb-padctl.txt | 18 +++ .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 36 ++++- .../boot/dts/nvidia/tegra194-p2972-0000.dts | 63 ++++++++ arch/arm64/boot/dts/nvidia/tegra194.dtsi | 139 +++++++++++++++++ drivers/phy/tegra/Makefile | 1 + drivers/phy/tegra/xusb-tegra186.c | 143 +++++++++++++----- drivers/phy/tegra/xusb.c | 17 +++ drivers/phy/tegra/xusb.h | 5 + 8 files changed, 387 insertions(+), 35 deletions(-)
Signature · 1 line
2.17.1
JC Kuo
maintainerPATCH v6 1/5 phy: tegra: xusb: Protect Tegra186 soc with config
As xusb-tegra186.c will be reused for Tegra194, it would be good to protect Tegra186 soc data with CONFIG_ARCH_TEGRA_186_SOC. This commit also reshuffles Tegra186 soc data single CONFIG_ARCH_TEGRA_186_SOC will be sufficient.
---
Changes in v6: none
Changes in v5: none
Changes in v4: none
Changes in v3: none
Changes in v2:
- new patch to protect Tegra186 soc data with config
drivers/phy/tegra/xusb-tegra186.c | 70 ++++++++++++++++--------------- 1 file changed, 36 insertions(+), 34 deletions(-)
drivers/phy/tegra/xusb-tegra186.c +36 -34
@@ -503,19 +503,6 @@ static const char * const tegra186_usb2_functions[] = { "xusb", }; -static const struct tegra_xusb_lane_soc tegra186_usb2_lanes[] = { -TEGRA186_LANE ("usb2-0" ,0 ,0 ,0 , usb2), -TEGRA186_LANE ("usb2-1" ,0 ,0 ,0 , usb2), -TEGRA186_LANE ("usb2-2" ,0 ,0 ,0 , usb2), -}; - -static const struct tegra_xusb_pad_soc tegra186_usb2_pad = { - .name ="usb2" , - .num_lanes =ARRAY_SIZE (tegra186_usb2_lanes), - .lanes = tegra186_usb2_lanes, - .ops = &tegra186_usb2_pad_ops, -}; -static int tegra186_usb2_port_enable (struct tegra_xusb_port *port) {return 0 ;
@@ -765,27 +752,6 @@ static const char * const tegra186_usb3_functions[] = { "xusb", }; -static const struct tegra_xusb_lane_soc tegra186_usb3_lanes[] = { -TEGRA186_LANE ("usb3-0" ,0 ,0 ,0 , usb3), -TEGRA186_LANE ("usb3-1" ,0 ,0 ,0 , usb3), -TEGRA186_LANE ("usb3-2" ,0 ,0 ,0 , usb3), -}; - -static const struct tegra_xusb_pad_soc tegra186_usb3_pad = { - .name ="usb3" , - .num_lanes =ARRAY_SIZE (tegra186_usb3_lanes), - .lanes = tegra186_usb3_lanes, - .ops = &tegra186_usb3_pad_ops, -}; - -static const struct tegra_xusb_pad_soc *const tegra186_pads[] = { - &tegra186_usb2_pad, - &tegra186_usb3_pad, -#if 0 /* TODO implement */ - &tegra186_hsic_pad, -#endif -}; -static int tegra186_xusb_read_fuse_calibration (struct tegra186_xusb_padctl *padctl) {
@@ -885,6 +851,7 @@ static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = { .vbus_override = tegra186_xusb_padctl_vbus_override, }; +#if IS_ENABLED (CONFIG_ARCH_TEGRA_186_SOC )static const char *const tegra186_xusb_padctl_supply_names[] = {"avdd-pll-erefeut" , "avdd-usb",
@@ -892,6 +859,40 @@ static const char * const tegra186_xusb_padctl_supply_names[] = { "vddio-hsic", }; +static const struct tegra_xusb_lane_soc tegra186_usb2_lanes[] = { +TEGRA186_LANE ("usb2-0" ,0 ,0 ,0 , usb2), +TEGRA186_LANE ("usb2-1" ,0 ,0 ,0 , usb2), +TEGRA186_LANE ("usb2-2" ,0 ,0 ,0 , usb2), +}; + +static const struct tegra_xusb_pad_soc tegra186_usb2_pad = { + .name ="usb2" , + .num_lanes =ARRAY_SIZE (tegra186_usb2_lanes), + .lanes = tegra186_usb2_lanes, + .ops = &tegra186_usb2_pad_ops, +}; + +static const struct tegra_xusb_lane_soc tegra186_usb3_lanes[] = { +TEGRA186_LANE ("usb3-0" ,0 ,0 ,0 , usb3), +TEGRA186_LANE ("usb3-1" ,0 ,0 ,0 , usb3), +TEGRA186_LANE ("usb3-2" ,0 ,0 ,0 , usb3), +}; + +static const struct tegra_xusb_pad_soc tegra186_usb3_pad = { + .name ="usb3" , + .num_lanes =ARRAY_SIZE (tegra186_usb3_lanes), + .lanes = tegra186_usb3_lanes, + .ops = &tegra186_usb3_pad_ops, +}; + +static const struct tegra_xusb_pad_soc *const tegra186_pads[] = { + &tegra186_usb2_pad, + &tegra186_usb3_pad, +#if 0 /* TODO implement */ + &tegra186_hsic_pad, +#endif +}; +const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = { .num_pads =ARRAY_SIZE (tegra186_pads), .pads = tegra186_pads,
@@ -916,6 +917,7 @@ const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = { .num_supplies = ARRAY_SIZE(tegra186_xusb_padctl_supply_names), };EXPORT_SYMBOL_GPL (tegra186_xusb_padctl_soc); +#endif MODULE_AUTHOR ("JC Kuo <[email protected]>" );MODULE_DESCRIPTION ("NVIDIA Tegra186 XUSB Pad Controller driver" );
Signature · 1 line
2.17.1
JC Kuo
maintainerPATCH v6 2/5 phy: tegra: xusb: Add Tegra194 support
In reply to JC KuoAdd support for the XUSB pad controller found on Tegra194 SoCs. It is mostly similar to the same IP found on Tegra186, but the number of pads exposed differs, as do the programming sequences. Because most of the Tegra194 XUSB PADCTL registers definition and programming sequence are the same as Tegra186, Tegra194 XUSB PADCTL can share the same driver, xusb-tegra186.c, with Tegra186 XUSB PADCTL.
Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it is possible for some platforms have long signal trace that could not provide sufficient electrical environment for Gen 2 speed. This patch adds a "maximum-speed" property to usb3 ports which can be used to specify the maximum supported speed for any particular USB 3.1 port. For a port that is not capable of SuperSpeedPlus, "maximum-speed" property should carry "super-speed".
---
Changes in v6: none
Changes in v5:
- re-use "maximum-speed" instead of adding "nvidia,disable-gen2" Changes in v4: none
Changes in v3: none
Changes in v2:
- removed unnecessary #if/#endif pairs
- introduce new soc->supports_gen2 flag which indicate whether or not a soc supports USB 3.1 Gen 2 speed
drivers/phy/tegra/Makefile | 1 + drivers/phy/tegra/xusb-tegra186.c | 73 +++++++++++++++++++++++++++++++ drivers/phy/tegra/xusb.c | 17 +++++++ drivers/phy/tegra/xusb.h | 5 +++ 4 files changed, 96 insertions(+)
drivers/phy/tegra/Makefile +1 -0
@@ -6,4 +6,5 @@ phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_124_SOC) += xusb-tegra124.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_132_SOC) += xusb-tegra124.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_210_SOC) += xusb-tegra210.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_186_SOC) += xusb-tegra186.o +phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_194_SOC) += xusb-tegra186.o obj-$(CONFIG_PHY_TEGRA194_P2U) += phy-tegra194-p2u.o
drivers/phy/tegra/xusb-tegra186.c +73 -0
91 lines not on this page · raw message
drivers/phy/tegra/xusb.c +17 -0
@@ -65,6 +65,12 @@ static const struct of_device_id tegra_xusb_padctl_of_match[] = { .compatible = "nvidia,tegra186-xusb-padctl", .data = &tegra186_xusb_padctl_soc, }, +#endif +#if defined(CONFIG_ARCH_TEGRA_194_SOC ) + { + .compatible = "nvidia,tegra194-xusb-padctl", + .data = &tegra194_xusb_padctl_soc, + }, #endif { } };
@@ -726,6 +732,7 @@ static int tegra_xusb_usb3_port_parse_dt(struct tegra_xusb_usb3_port *usb3) {struct tegra_xusb_port *port = &usb3->base;struct device_node *np = port->dev.of_node; +enum usb_device_speed maximum_speed;u32 value;int err;
@@ -739,6 +746,16 @@ static int tegra_xusb_usb3_port_parse_dt(struct tegra_xusb_usb3_port *usb3) usb3->internal =of_property_read_bool (np,"nvidia,internal" ); +if (device_property_present (&port->dev,"maximum-speed" )) { + maximum_speed =usb_get_maximum_speed (&port->dev); +if (maximum_speed ==USB_SPEED_SUPER ) + usb3->disable_gen2 = true; +else if (maximum_speed ==USB_SPEED_SUPER_PLUS ) + usb3->disable_gen2 = false; +else +return -EINVAL ; + } + usb3->supply =devm_regulator_get (&port->dev,"vbus" );return PTR_ERR_OR_ZERO (usb3->supply); }
drivers/phy/tegra/xusb.h +5 -0
@@ -333,6 +333,7 @@ struct tegra_xusb_usb3_port {bool context_saved;unsigned int port;bool internal; +bool disable_gen2;u32 tap1;u32 amp;
@@ -392,6 +393,7 @@ struct tegra_xusb_padctl_soc {const char *const *supply_names;unsigned int num_supplies; +bool supports_gen2;bool need_fake_usb3_port; };
@@ -448,5 +450,8 @@ extern const struct tegra_xusb_padctl_soc tegra210_xusb_padctl_soc;#if defined(CONFIG_ARCH_TEGRA_186_SOC )extern const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc;#endif +#if defined(CONFIG_ARCH_TEGRA_194_SOC ) +extern const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc; +#endif #endif /* __PHY_TEGRA_XUSB_H */
Signature · 1 line
2.17.1
Re: [PATCH v6 2/5] phy: tegra: xusb: Add Tegra194 support
Quoted 27 lines · JC Kuo
Add support for the XUSB pad controller found on Tegra194 SoCs. It is mostly similar to the same IP found on Tegra186, but the number of pads exposed differs, as do the programming sequences. Because most of the Tegra194 XUSB PADCTL registers definition and programming sequence are the same as Tegra186, Tegra194 XUSB PADCTL can share the same driver,
xusb-tegra186.c, with Tegra186 XUSB PADCTL.Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it is possible for some platforms have long signal trace that could not provide sufficient electrical environment for Gen 2 speed. This patch adds a "maximum-speed" property to usb3 ports which can be used to specify the maximum supported speed for any particular USB 3.1 port. For a port that is not capable of SuperSpeedPlus, "maximum-speed" property should carry "super-speed".
Signed-off-by JC Kuo <[email protected]>---
Changes in v6: none
Changes in v5:
- re-use "maximum-speed" instead of adding "nvidia,disable-gen2" Changes in v4: none
Changes in v3: none
Changes in v2:
- removed unnecessary #if/#endif pairs
- introduce newsoc->supports_gen2flag which indicate whether or not a soc supports USB 3.1 Gen 2 speed
Quoted 5 lines
drivers/phy/tegra/Makefile | 1 + drivers/phy/tegra/xusb-tegra186.c | 73 +++++++++++++++++++++++++++++++ drivers/phy/tegra/xusb.c | 17 +++++++ drivers/phy/tegra/xusb.h | 5 +++ 4 files changed, 96 insertions(+)
JC Kuo
maintainerPATCH v6 3/5 dt-bindings: phy: tegra: Add Tegra194 support
In reply to JC KuoExtend the bindings to cover the set of features found in Tegra194. Note that, technically, there are four more supplies connected to the XUSB pad controller (DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL) , but the power sequencing requirements of Tegra194 require these to be under the control of the PMIC.
Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it is possible for some platforms have long signal trace that could not provide sufficient electrical environment for Gen 2 speed. This patch adds a "maximum-speed" property to usb3 ports which can be used to specify the maximum supported speed for any particular USB 3.1 port. For a port that is not capable of SuperSpeedPlus, "maximum-speed" property should carry "super-speed".
---
Changes in v6: none
Changes in v5:
- re-use "maximum-speed" instead of adding "nvidia,disable-gen2" Changes in v4: none
Changes in v3: none
Changes in v2:
- fix a typo
.../phy/nvidia,tegra124-xusb-padctl.txt | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt +18 -0
@@ -37,6 +37,7 @@ Required properties: - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl" - Tegra210: "nvidia,tegra210-xusb-padctl" - Tegra186: "nvidia,tegra186-xusb-padctl" + - Tegra194: "nvidia,tegra194-xusb-padctl" - reg: Physical base address and length of the controller's registers. - resets: Must contain an entry for each entry in reset-names. - reset-names: Must include the following entries:
@@ -62,6 +63,10 @@ For Tegra186: - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V. - vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V. +For Tegra194: +- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply + 3.3 V. +- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V. Pad nodes: ==========
@@ -154,6 +159,11 @@ For Tegra210, the list of valid PHY nodes is given below: - sata: sata-0 - functions: "usb3-ss", "sata" +For Tegra194, the list of valid PHY nodes is given below: +- usb2: usb2-0, usb2-1, usb2-2, usb2-3 + - functions: "xusb" +- usb3: usb3-0, usb3-1, usb3-2, usb3-3 + - functions: "xusb" Port nodes: ===========
@@ -221,6 +231,11 @@ Optional properties: is internal. In the absence of this property the port is considered to be external. +- maximum-speed: Only for Tegra194. A string property that specifies maximum + supported speed of a usb3 port. Valid values are: + - "super-speed-plus": default, the usb3 port supports USB 3.1 Gen 2 speed. + - "super-speed": the usb3 port supports USB 3.1 Gen 1 speed only. + For Tegra124 and Tegra132, the XUSB pad controller exposes the following ports: - 3x USB2: usb2-0, usb2-1, usb2-2
@@ -233,6 +248,9 @@ For Tegra210, the XUSB pad controller exposes the following ports: - 2x HSIC: hsic-0, hsic-1 - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3 +For Tegra194, the XUSB pad controller exposes the following ports: +- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3 +- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3 Examples: =========
Signature · 1 line
2.17.1
Re: [PATCH v6 3/5] dt-bindings: phy: tegra: Add Tegra194 support
Quoted 24 lines · JC Kuo
Extend the bindings to cover the set of features found in Tegra194. Note that, technically, there are four more supplies connected to the XUSB pad controller (
DVDD_PEX,DVDD_PEX_PLL,HVDD_PEXandHVDD_PEX_PLL) , but the power sequencing requirements of Tegra194 require these to be under the control of the PMIC.Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it is possible for some platforms have long signal trace that could not provide sufficient electrical environment for Gen 2 speed. This patch adds a "maximum-speed" property to usb3 ports which can be used to specify the maximum supported speed for any particular USB 3.1 port. For a port that is not capable of SuperSpeedPlus, "maximum-speed" property should carry "super-speed".
Signed-off-by JC Kuo <[email protected]>---
Changes in v6: none
Changes in v5:
- re-use "maximum-speed" instead of adding "nvidia,disable-gen2" Changes in v4: none
Changes in v3: none
Changes in v2:
- fix a typo
Quoted 2 lines
.../phy/nvidia,tegra124-xusb-padctl.txt | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
Re: [PATCH v6 3/5] dt-bindings: phy: tegra: Add Tegra194 support
In reply to JC KuoQuoted 24 lines · JC Kuo
Extend the bindings to cover the set of features found in Tegra194. Note that, technically, there are four more supplies connected to the XUSB pad controller (
DVDD_PEX,DVDD_PEX_PLL,HVDD_PEXandHVDD_PEX_PLL) , but the power sequencing requirements of Tegra194 require these to be under the control of the PMIC.Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it is possible for some platforms have long signal trace that could not provide sufficient electrical environment for Gen 2 speed. This patch adds a "maximum-speed" property to usb3 ports which can be used to specify the maximum supported speed for any particular USB 3.1 port. For a port that is not capable of SuperSpeedPlus, "maximum-speed" property should carry "super-speed".
Signed-off-by JC Kuo <[email protected]>---
Changes in v6: none
Changes in v5:
- re-use "maximum-speed" instead of adding "nvidia,disable-gen2" Changes in v4: none
Changes in v3: none
Changes in v2:
- fix a typo
Quoted 3 lines
.../phy/nvidia,tegra124-xusb-padctl.txt | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
JC Kuo
maintainerPATCH v6 4/5 arm64: tegra: Add XUSB and pad controller on Tegra194
In reply to JC KuoAdds the XUSB pad and XUSB controllers on Tegra194.
---
Changes in v6: rebase
Changes in v5: none
Changes in v4: none
Changes in v3: none
Changes in v2:
- renamed xhci@3610000 with usb@3610000
- moved padctl@3520000 and usb@3610000 inside /cbb
- cleaned up "clocks" property of usb@3610000 node
- added blanks lines to visually separate blocks
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 139 +++++++++++++++++++++++ 1 file changed, 139 insertions(+)
arch/arm64/boot/dts/nvidia/tegra194.dtsi +139 -0
@@ -537,6 +537,145 @@ status = "disabled"; }; + xusb_padctl: padctl@3520000 { + compatible = "nvidia,tegra194-xusb-padctl"; + reg = <0x03520000 0x1000>, + <0x03540000 0x1000>; + reg-names = "padctl", "ao"; + + resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; + reset-names = "padctl"; + + status = "disabled"; + + pads { + usb2 { + clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; + clock-names = "trk"; + + lanes { + usb2-0 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-1 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-2 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-3 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + + usb3 { + lanes { + usb3-0 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-1 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-2 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-3 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + }; + + ports { + usb2-0 { + status = "disabled"; + }; + + usb2-1 { + status = "disabled"; + }; + + usb2-2 { + status = "disabled"; + }; + + usb2-3 { + status = "disabled"; + }; + + usb3-0 { + status = "disabled"; + }; + + usb3-1 { + status = "disabled"; + }; + + usb3-2 { + status = "disabled"; + }; + + usb3-3 { + status = "disabled"; + }; + }; + }; + + usb@3610000 { + compatible = "nvidia,tegra194-xusb"; + reg = <0x03610000 0x40000>, + < 0x03600000 0x10000>; + reg-names = "hcd", "fpci"; + + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, + <&bpmp TEGRA194_CLK_XUSB_FALCON>, + <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA194_CLK_XUSB_SS>, + <&bpmp TEGRA194_CLK_CLK_M>, + <&bpmp TEGRA194_CLK_XUSB_FS>, + <&bpmp TEGRA194_CLK_UTMIPLL>, + <&bpmp TEGRA194_CLK_CLK_M>, + <&bpmp TEGRA194_CLK_PLLE>; + clock-names = "xusb_host", "xusb_falcon_src", + "xusb_ss", "xusb_ss_src", "xusb_hs_src", + "xusb_fs_src", "pll_u_480m", "clk_m", + "pll_e"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, + <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; + power-domain-names = "xusb_host", "xusb_ss"; + + nvidia,xusb-padctl = <&xusb_padctl>; + status = "disabled"; + }; + fuse@3820000 { compatible = "nvidia,tegra194-efuse"; reg = <0x03820000 0x10000>;
Signature · 1 line
2.17.1
Thierry Reding
AppliedRe: [PATCH v6 4/5] arm64: tegra: Add XUSB and pad controller on Tegra194
Quoted 14 lines · JC Kuo
Adds the XUSB pad and XUSB controllers on Tegra194.
Signed-off-by JC Kuo <[email protected]>---
Changes in v6: rebase
Changes in v5: none
Changes in v4: none
Changes in v3: none
Changes in v2:
- renamed xhci@3610000 with usb@3610000
- moved padctl@3520000 and usb@3610000 inside /cbb
- cleaned up "clocks" property of usb@3610000 node
- added blanks lines to visually separate blocks
Quoted 2 lines
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 139 +++++++++++++++++++++++ 1 file changed, 139 insertions(+)
Applied to for-5.7/arm64/dt, thanks.
Thierry
JC Kuo
maintainerPATCH v6 5/5 arm64: tegra: Enable XUSB host in P2972-0000 board
In reply to JC KuoThis commit enables XUSB host and pad controller in Tegra194 P2972-0000 board.
---
Changes in v6:
- re-use "maximum-speed" instead of adding "nvidia,disable-gen2" Changes in v5: none
Changes in v4: none
Changes in v3: none
Changes in v2:
- use capitalization of regulator names
- fix gpio property of VDD_5V_SATA regulator
.../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 36 ++++++++++- .../boot/dts/nvidia/tegra194-p2972-0000.dts | 63 +++++++++++++++++++ 2 files changed, 98 insertions(+), 1 deletion(-)
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +35 -1
@@ -71,6 +71,29 @@ vmmc-supply = <&vdd_emmc_3v3>; }; + padctl@3520000 { + avdd-usb-supply = <&vdd_usb_3v3>; + vclamp-usb-supply = <&vdd_1v8ao>; + + ports { + usb2-1 { + vbus-supply = <&vdd_5v0_sys>; + }; + + usb2-3 { + vbus-supply = <&vdd_5v_sata>; + }; + + usb3-0 { + vbus-supply = <&vdd_5v0_sys>; + }; + + usb3-3 { + vbus-supply = <&vdd_5v0_sys>; + }; + }; + }; + rtc@c2a0000 { status = "okay"; };
@@ -234,7 +257,7 @@ regulator-max-microvolt = <3300000>; }; - ldo5 { + vdd_usb_3v3: ldo5 { regulator-name = "VDD_USB_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
@@ -317,5 +340,16 @@ gpio = <&gpio TEGRA194_MAIN_GPIO(A, 1) GPIO_ACTIVE_HIGH>; regulator-boot-on; }; + + vdd_5v_sata: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + + regulator-name = "VDD_5V_SATA"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; };
arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +63 -0
69 lines not on this page · raw message
Signature · 1 line
2.17.1
Thierry Reding
AppliedRe: [PATCH v6 5/5] arm64: tegra: Enable XUSB host in P2972-0000 board
Quoted 14 lines · JC Kuo
This commit enables XUSB host and pad controller in Tegra194 P2972-0000 board.
Signed-off-by JC Kuo <[email protected]>---
Changes in v6:
- re-use "maximum-speed" instead of adding "nvidia,disable-gen2" Changes in v5: none
Changes in v4: none
Changes in v3: none
Changes in v2:
- use capitalization of regulator names
- fix gpio property ofVDD_5V_SATAregulator
Quoted 3 lines
.../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 36 ++++++++++- .../boot/dts/nvidia/tegra194-p2972-0000.dts | 63 +++++++++++++++++++ 2 files changed, 98 insertions(+), 1 deletion(-)
Applied to for-5.7/arm64/dt, thanks.
Thierry