hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge

Signed-off-by Philippe Mathieu-Daudé <[email protected]>

---
 MAINTAINERS | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

MAINTAINERS +6 -1

index 42e702f346..1f04502fac 100644
@@ -1230,7 +1230,6 @@ F: hw/pci-host/q35.c
 F: hw/pci-host/pam.c
 F: include/hw/pci-host/q35.h
 F: include/hw/pci-host/pam.h
-F: hw/isa/piix4.c
 F: hw/isa/lpc_ich9.c
 F: hw/i2c/smbus_ich9.c
 F: hw/acpi/piix4.c

@@ -1730,6 +1729,12 @@ F: hw/display/edid*
 F: include/hw/display/edid.h
 F: qemu-edid.c
 
+PIIX4 South Bridge (i82371AB)
+M: Hervé Poussineau <[email protected]>
+M: Philippe Mathieu-Daudé <[email protected]>
+S: Maintained
+F: hw/isa/piix4.c
+
 Firmware configuration (fw_cfg)
 M: Philippe Mathieu-Daudé <[email protected]>
 R: Laszlo Ersek <[email protected]>

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Philippe Mathieu-Daudé

author

2019-10-26 18:02 UTC #2 lore raw

PATCH v3 2/20 piix4: Add the Reset Control Register

From: Hervé Poussineau <[email protected]>

The RCR I/O port (0xcf9) is used to generate a hard reset or a soft reset.

Message-Id: <[email protected]>

Reviewed-by Aleksandar Markovic <[email protected]>

[PMD: rebased, updated includes]

Signed-off-by Philippe Mathieu-Daudé <[email protected]>

---
v3: Use RCR_IOPORT (Li Qiang)

---
 hw/isa/piix4.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 46 insertions(+), 3 deletions(-)

hw/isa/piix4.c +46 -3

index 890d999abf..7a1361a9dd 100644
@@ -2,6 +2,7 @@
  * QEMU PIIX4 PCI Bridge Emulation
  *
  * Copyright (c) 2006 Fabrice Bellard
+ * Copyright (c) 2018 Hervé Poussineau
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal

@@ -28,11 +29,17 @@
 #include "hw/isa/isa.h"
 #include "hw/sysbus.h"
 #include "migration/vmstate.h"
+#include "sysemu/reset.h"
+#include "sysemu/runstate.h"
 
 PCIDevice *piix4_dev;
 
 typedef struct PIIX4State {
     PCIDevice dev;
+
+    /* Reset Control Register */
+    MemoryRegion rcr_mem;
+    uint8_t rcr;
 } PIIX4State;
 
 #define TYPE_PIIX4_PCI_DEVICE "PIIX4"

@@ -87,15 +94,51 @@ static const VMStateDescription vmstate_piix4 = {
     }
 };
 
+static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
+                            unsigned int len)
+{
+    PIIX4State *s = opaque;
+
+    if (val & 4) {
+        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+        return;
+    }
+
+    s->rcr = val & 2; /* keep System Reset type only */
+}
+
+static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len)
+{
+    PIIX4State *s = opaque;
+
+    return s->rcr;
+}
+
+static const MemoryRegionOps piix4_rcr_ops = {
+    .read = piix4_rcr_read,
+    .write = piix4_rcr_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .impl = {
+        .min_access_size = 1,
+        .max_access_size = 1,
+    },
+};
+
 static void piix4_realize(PCIDevice *dev, Error **errp)
 {
-    PIIX4State *d = PIIX4_PCI_DEVICE(dev);
+    PIIX4State *s = PIIX4_PCI_DEVICE(dev);
 
-    if (!isa_bus_new(DEVICE(d), pci_address_space(dev),
+    if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
                      pci_address_space_io(dev), errp)) {
         return;
     }
-    piix4_dev = &d->dev;
+
+    memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
+                          "reset-control", 1);
+    memory_region_add_subregion_overlap(pci_address_space_io(dev),
+                                        RCR_IOPORT, &s->rcr_mem, 1);
+
+    piix4_dev = dev;
 }
 
 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)

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Philippe Mathieu-Daudé

author

2019-10-26 18:02 UTC #3 lore raw

PATCH v3 3/20 piix4: Add an i8259 Interrupt Controller as specified in datasheet

From: Hervé Poussineau <[email protected]>

Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4 gpio out. Remove i8259 instanciated in malta board, to not have it twice.

We can also remove the now unused piix4_init() function.

Message-Id: <[email protected]>

Reviewed-by Aleksandar Markovic <[email protected]>

[PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop]

Signed-off-by Philippe Mathieu-Daudé <[email protected]>

---
v3:
- "Add a i8259 -> Add an i8259" in title (Aleksandar)
- Changed 16 -> ISA_NUM_IRQS

---
 hw/isa/piix4.c       | 43 ++++++++++++++++++++++++++++++++-----------
 hw/mips/mips_malta.c | 32 +++++++++++++-------------------
 include/hw/i386/pc.h |  1 -
 3 files changed, 45 insertions(+), 31 deletions(-)

hw/isa/piix4.c +32 ~~-11~~

index 7a1361a9dd..7cf72e3118 100644
@@ -24,6 +24,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "hw/irq.h"
 #include "hw/i386/pc.h"
 #include "hw/pci/pci.h"
 #include "hw/isa/isa.h"

@@ -36,6 +37,8 @@ PCIDevice *piix4_dev;
 
 typedef struct PIIX4State {
     PCIDevice dev;
+    qemu_irq cpu_intr;
+    qemu_irq *isa;
 
     /* Reset Control Register */
     MemoryRegion rcr_mem;

@@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4 = {
     }
 };
 
+static void piix4_request_i8259_irq(void *opaque, int irq, int level)
+{
+    PIIX4State *s = opaque;
+    qemu_set_irq(s->cpu_intr, level);
+}
+
+static void piix4_set_i8259_irq(void *opaque, int irq, int level)
+{
+    PIIX4State *s = opaque;
+    qemu_set_irq(s->isa[irq], level);
+}
+
 static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
                             unsigned int len)
 {

@@ -127,29 +142,35 @@ static const MemoryRegionOps piix4_rcr_ops = {
 static void piix4_realize(PCIDevice *dev, Error **errp)
 {
     PIIX4State *s = PIIX4_PCI_DEVICE(dev);
+    ISABus *isa_bus;
+    qemu_irq *i8259_out_irq;
 
-    if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
-                     pci_address_space_io(dev), errp)) {
+    isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
+                          pci_address_space_io(dev), errp);
+    if (!isa_bus) {
         return;
     }
 
+    qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
+                            "isa", ISA_NUM_IRQS);
+    qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
+                             "intr", 1);
+
     memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
                           "reset-control", 1);
     memory_region_add_subregion_overlap(pci_address_space_io(dev),
                                         RCR_IOPORT, &s->rcr_mem, 1);
 
+    /* initialize i8259 pic */
+    i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
+    s->isa = i8259_init(isa_bus, *i8259_out_irq);
+
+    /* initialize ISA irqs */
+    isa_bus_irqs(isa_bus, s->isa);
+
     piix4_dev = dev;
 }
 
-int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
-{
-    PCIDevice *d;
-
-    d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
-    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
-    return d->devfn;
-}
-
 static void piix4_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);

hw/mips/mips_malta.c +13 ~~-19~~

index c1c8810e71..6d9b230322 100644
@@ -97,7 +97,7 @@ typedef struct {
     SysBusDevice parent_obj;
 
     MIPSCPSState cps;
-    qemu_irq *i8259;
+    qemu_irq i8259[ISA_NUM_IRQS];
 } MaltaState;
 
 static ISADevice *pit;

@@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine)
     int64_t kernel_entry, bootloader_run_addr;
     PCIBus *pci_bus;
     ISABus *isa_bus;
-    qemu_irq *isa_irq;
     qemu_irq cbus_irq, i8259_irq;
+    PCIDevice *pci;
     int piix4_devfn;
     I2CBus *smbus;
     DriveInfo *dinfo;

@@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState *machine)
     /* Board ID = 0x420 (Malta Board with CoreLV) */
     stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
 
-    /*
-     * We have a circular dependency problem: pci_bus depends on isa_irq,
-     * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
-     * on piix4, and piix4 depends on pci_bus.  To stop the cycle we have
-     * qemu_irq_proxy() adds an extra bit of indirection, allowing us
-     * to resolve the isa_irq -> i8259 dependency after i8259 is initialized.
-     */
-    isa_irq = qemu_irq_proxy(&s->i8259, 16);
-
     /* Northbridge */
-    pci_bus = gt64120_register(isa_irq);
+    pci_bus = gt64120_register(s->i8259);
 
     /* Southbridge */
     ide_drive_get(hd, ARRAY_SIZE(hd));
 
-    piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
+    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
+                                          true, "PIIX4");
+    dev = DEVICE(pci);
+    isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
+    piix4_devfn = pci->devfn;
 
-    /*
-     * Interrupt controller
-     * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
-     */
-    s->i8259 = i8259_init(isa_bus, i8259_irq);
+    /* Interrupt controller */
+    qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
+    for (int i = 0; i < ISA_NUM_IRQS; i++) {
+        s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
+    }
 
-    isa_bus_irqs(isa_bus, s->i8259);
     pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
     pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
     smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,

include/hw/i386/pc.h +0 -1

index f040a72095..f553b29652 100644
@@ -266,7 +266,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
 PCIBus *find_i440fx(void);
 /* piix4.c */
 extern PCIDevice *piix4_dev;
-int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
 
 /* pc_sysfw.c */
 void pc_system_flash_create(PCMachineState *pcms);

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Philippe Mathieu-Daudé

author

2019-10-26 18:03 UTC #4 lore raw

PATCH v3 4/20 Revert "irq: introduce qemu_irq_proxy()"

From: Philippe Mathieu-Daudé <[email protected]>

This function isn't used anymore.

This reverts commit 22ec3283efba9ba0792790da786d6776d83f2a92.

Reviewed-by Thomas Huth <[email protected]>

Signed-off-by Philippe Mathieu-Daudé <[email protected]>

---
 hw/core/irq.c    | 14 --------------
 include/hw/irq.h |  5 -----
 2 files changed, 19 deletions(-)

hw/core/irq.c +0 ~~-14~~

index 7cc0295d0e..fb3045b912 100644
@@ -120,20 +120,6 @@ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2)
     return qemu_allocate_irq(qemu_splitirq, s, 0);
 }
 
-static void proxy_irq_handler(void *opaque, int n, int level)
-{
-    qemu_irq **target = opaque;
-
-    if (*target) {
-        qemu_set_irq((*target)[n], level);
-    }
-}
-
-qemu_irq *qemu_irq_proxy(qemu_irq **target, int n)
-{
-    return qemu_allocate_irqs(proxy_irq_handler, target, n);
-}
-
 void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n)
 {
     int i;

include/hw/irq.h +0 -5

index fe527f6f51..24ba0ece11 100644
@@ -51,11 +51,6 @@ qemu_irq qemu_irq_invert(qemu_irq irq);
  */
 qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
 
-/* Returns a new IRQ set which connects 1:1 to another IRQ set, which
- * may be set later.
- */
-qemu_irq *qemu_irq_proxy(qemu_irq **target, int n);
-
 /* For internal use in qtest.  Similar to qemu_irq_split, but operating
    on an existing vector of qemu_irq.  */
 void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n);

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Philippe Mathieu-Daudé

author

2019-10-26 18:03 UTC #5 lore raw

PATCH v3 5/20 piix4: Rename PIIX4 object to piix4-isa

From: Hervé Poussineau <[email protected]>

Other piix4 parts are already named piix4-ide and piix4-usb-uhci.

Reviewed-by Philippe Mathieu-Daudé <[email protected]>

Message-Id: <[email protected]>

Reviewed-by Aleksandar Markovic <[email protected]>

[PMD: rebased]

Signed-off-by Philippe Mathieu-Daudé <[email protected]>

---
 hw/isa/piix4.c       | 1 -
 hw/mips/mips_malta.c | 2 +-
 include/hw/isa/isa.h | 2 ++
 3 files changed, 3 insertions(+), 2 deletions(-)

hw/isa/piix4.c +0 -1

index 7cf72e3118..fa387919b5 100644
@@ -45,7 +45,6 @@ typedef struct PIIX4State {
     uint8_t rcr;
 } PIIX4State;
 
-#define TYPE_PIIX4_PCI_DEVICE "PIIX4"
 #define PIIX4_PCI_DEVICE(obj) \
     OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)

hw/mips/mips_malta.c +1 -1

index 6d9b230322..5086024821 100644
@@ -1414,7 +1414,7 @@ void mips_malta_init(MachineState *machine)
     ide_drive_get(hd, ARRAY_SIZE(hd));
 
     pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
-                                          true, "PIIX4");
+                                          true, TYPE_PIIX4_PCI_DEVICE);
     dev = DEVICE(pci);
     isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
     piix4_devfn = pci->devfn;

include/hw/isa/isa.h +2 -0

index 018ada4f6f..79f703fd6c 100644
@@ -147,4 +147,6 @@ static inline ISABus *isa_bus_from_device(ISADevice *d)
     return ISA_BUS(qdev_get_parent_bus(DEVICE(d)));
 }
 
+#define TYPE_PIIX4_PCI_DEVICE "piix4-isa"
+
 #endif

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Philippe Mathieu-Daudé

author

2019-10-26 18:03 UTC #6 lore raw

PATCH v3 6/20 piix4: Add an i8257 DMA Controller as specified in datasheet

From: Hervé Poussineau <[email protected]>

The i8257 is not a chipset on the Malta board, but is part of the PIIX4 chipset.
Create the i8257 in the PIIX4 code, remove the one instantiated in malta board, to not have it twice.

Message-Id: <[email protected]>

Reviewed-by Aleksandar Markovic <[email protected]>

[PMD: rebased, reworded description]

Signed-off-by Philippe Mathieu-Daudé <[email protected]>

---
v3: Reworded commit description (Li Qiang)

---
 hw/isa/piix4.c       | 4 ++++
 hw/mips/mips_malta.c | 2 --
 2 files changed, 4 insertions(+), 2 deletions(-)

hw/isa/piix4.c +4 -0

index fa387919b5..9ebe98bdc3 100644
@@ -29,6 +29,7 @@
 #include "hw/pci/pci.h"
 #include "hw/isa/isa.h"
 #include "hw/sysbus.h"
+#include "hw/dma/i8257.h"
 #include "migration/vmstate.h"
 #include "sysemu/reset.h"
 #include "sysemu/runstate.h"

@@ -167,6 +168,9 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
     /* initialize ISA irqs */
     isa_bus_irqs(isa_bus, s->isa);
 
+    /* DMA */
+    i8257_dma_init(isa_bus, 0);
+
     piix4_dev = dev;
 }

hw/mips/mips_malta.c +0 -2

index 5086024821..44e5f8b26b 100644
@@ -28,7 +28,6 @@
 #include "cpu.h"
 #include "hw/i386/pc.h"
 #include "hw/isa/superio.h"
-#include "hw/dma/i8257.h"
 #include "hw/char/serial.h"
 #include "net/net.h"
 #include "hw/boards.h"

@@ -1430,7 +1429,6 @@ void mips_malta_init(MachineState *machine)
     smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
                           isa_get_irq(NULL, 9), NULL, 0, NULL);
     pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
-    i8257_dma_init(isa_bus, 0);
     mc146818_rtc_init(isa_bus, 2000, NULL);
 
     /* generate SPD EEPROM data */

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Philippe Mathieu-Daudé

author

2019-10-26 18:03 UTC #7 lore raw

PATCH v3 7/20 piix4: Add an i8254 PIT Controller as specified in datasheet

From: Hervé Poussineau <[email protected]>

Remove i8254 instanciated in malta board, to not have it twice.

Message-Id: <[email protected]>

Reviewed-by Aleksandar Markovic <[email protected]>

Signed-off-by Philippe Mathieu-Daudé <[email protected]>

---
v2: Fixed typo (thuth)

---
 hw/isa/piix4.c       | 4 ++++
 hw/mips/mips_malta.c | 4 ----
 2 files changed, 4 insertions(+), 4 deletions(-)

hw/isa/piix4.c +4 -0

index 9ebe98bdc3..c07a1e14a8 100644
@@ -30,6 +30,7 @@
 #include "hw/isa/isa.h"
 #include "hw/sysbus.h"
 #include "hw/dma/i8257.h"
+#include "hw/timer/i8254.h"
 #include "migration/vmstate.h"
 #include "sysemu/reset.h"
 #include "sysemu/runstate.h"

@@ -168,6 +169,9 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
     /* initialize ISA irqs */
     isa_bus_irqs(isa_bus, s->isa);
 
+    /* initialize pit */
+    i8254_pit_init(isa_bus, 0x40, 0, NULL);
+
     /* DMA */
     i8257_dma_init(isa_bus, 0);

hw/mips/mips_malta.c +0 -4

index 44e5f8b26b..9af486c77c 100644
@@ -45,7 +45,6 @@
 #include "hw/loader.h"
 #include "elf.h"
 #include "hw/rtc/mc146818rtc.h"
-#include "hw/timer/i8254.h"
 #include "exec/address-spaces.h"
 #include "hw/sysbus.h"             /* SysBusDevice */
 #include "qemu/host-utils.h"

@@ -99,8 +98,6 @@ typedef struct {
     qemu_irq i8259[ISA_NUM_IRQS];
 } MaltaState;
 
-static ISADevice *pit;
-
 static struct _loaderparams {
     int ram_size, ram_low_size;
     const char *kernel_filename;

@@ -1428,7 +1425,6 @@ void mips_malta_init(MachineState *machine)
     pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
     smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
                           isa_get_irq(NULL, 9), NULL, 0, NULL);
-    pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
     mc146818_rtc_init(isa_bus, 2000, NULL);
 
     /* generate SPD EEPROM data */

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Philippe Mathieu-Daudé

author

2019-10-26 18:03 UTC #8 lore raw

PATCH v3 8/20 piix4: Add a MC146818 RTC Controller as specified in datasheet

From: Philippe Mathieu-Daudé <[email protected]>

Remove mc146818rtc instanciated in malta board, to not have it twice.

Message-Id: <[email protected]>

[PMD: rebased, set RTC base_year to 2000]

Reviewed-by Aleksandar Markovic <[email protected]>

Signed-off-by Philippe Mathieu-Daudé <[email protected]>

---
 MAINTAINERS                   |  3 ++-
 hw/acpi/piix4.c               |  2 +-
 hw/i386/acpi-build.c          |  3 +--
 hw/i386/pc_piix.c             |  1 +
 hw/isa/piix4.c                | 22 ++++++++++++++++++++++
 hw/mips/mips_malta.c          |  4 +---
 include/hw/acpi/piix4.h       |  6 ------
 include/hw/i386/pc.h          |  6 ------
 include/hw/southbridge/piix.h | 20 ++++++++++++++++++++
 9 files changed, 48 insertions(+), 19 deletions(-)
 delete mode 100644 include/hw/acpi/piix4.h
 create mode 100644 include/hw/southbridge/piix.h

MAINTAINERS +2 -1

index 1f04502fac..90c5ece04b 100644
@@ -1235,7 +1235,7 @@ F: hw/i2c/smbus_ich9.c
 F: hw/acpi/piix4.c
 F: hw/acpi/ich9.c
 F: include/hw/acpi/ich9.h
-F: include/hw/acpi/piix4.h
+F: include/hw/southbridge/piix.h
 F: hw/misc/sga.c
 F: hw/isa/apm.c
 F: include/hw/isa/apm.h

@@ -1734,6 +1734,7 @@ M: Hervé Poussineau <[email protected]>
 M: Philippe Mathieu-Daudé <[email protected]>
 S: Maintained
 F: hw/isa/piix4.c
+F: include/hw/southbridge/piix.h
 
 Firmware configuration (fw_cfg)
 M: Philippe Mathieu-Daudé <[email protected]>

hw/acpi/piix4.c +1 -1

index 4e079b39bd..2efd1605b8 100644
@@ -21,6 +21,7 @@
 
 #include "qemu/osdep.h"
 #include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
 #include "hw/irq.h"
 #include "hw/isa/apm.h"
 #include "hw/i2c/pm_smbus.h"

@@ -32,7 +33,6 @@
 #include "qapi/error.h"
 #include "qemu/range.h"
 #include "exec/address-spaces.h"
-#include "hw/acpi/piix4.h"
 #include "hw/acpi/pcihp.h"
 #include "hw/acpi/cpu_hotplug.h"
 #include "hw/acpi/cpu.h"

hw/i386/acpi-build.c +1 -2

index 9dd3dbb16c..b1b050d8e2 100644
@@ -34,7 +34,6 @@
 #include "hw/acpi/acpi-defs.h"
 #include "hw/acpi/acpi.h"
 #include "hw/acpi/cpu.h"
-#include "hw/acpi/piix4.h"
 #include "hw/nvram/fw_cfg.h"
 #include "hw/acpi/bios-linker-loader.h"
 #include "hw/isa/isa.h"

@@ -52,7 +51,7 @@
 #include "sysemu/reset.h"
 
 /* Supported chipsets: */
-#include "hw/acpi/piix4.h"
+#include "hw/southbridge/piix.h"
 #include "hw/acpi/pcihp.h"
 #include "hw/i386/ich9.h"
 #include "hw/pci/pci_bus.h"

hw/i386/pc_piix.c +1 -0

index c15929a1f5..a96ede19b2 100644
@@ -30,6 +30,7 @@
 #include "hw/i386/x86.h"
 #include "hw/i386/pc.h"
 #include "hw/i386/apic.h"
+#include "hw/southbridge/piix.h"
 #include "hw/display/ramfb.h"
 #include "hw/firmware/smbios.h"
 #include "hw/pci/pci.h"

hw/isa/piix4.c +22 -0

index c07a1e14a8..6bf6f0c5d9 100644
@@ -24,6 +24,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "qapi/error.h"
 #include "hw/irq.h"
 #include "hw/i386/pc.h"
 #include "hw/pci/pci.h"

@@ -31,6 +32,7 @@
 #include "hw/sysbus.h"
 #include "hw/dma/i8257.h"
 #include "hw/timer/i8254.h"
+#include "hw/rtc/mc146818rtc.h"
 #include "migration/vmstate.h"
 #include "sysemu/reset.h"
 #include "sysemu/runstate.h"

@@ -42,6 +44,7 @@ typedef struct PIIX4State {
     qemu_irq cpu_intr;
     qemu_irq *isa;
 
+    RTCState rtc;
     /* Reset Control Register */
     MemoryRegion rcr_mem;
     uint8_t rcr;

@@ -145,6 +148,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
     PIIX4State *s = PIIX4_PCI_DEVICE(dev);
     ISABus *isa_bus;
     qemu_irq *i8259_out_irq;
+    Error *err = NULL;
 
     isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
                           pci_address_space_io(dev), errp);

@@ -175,9 +179,26 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
     /* DMA */
     i8257_dma_init(isa_bus, 0);
 
+    /* RTC */
+    qdev_set_parent_bus(DEVICE(&s->rtc), BUS(isa_bus));
+    qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
+    object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+    isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, RTC_ISA_IRQ);
+
     piix4_dev = dev;
 }
 
+static void piix4_init(Object *obj)
+{
+    PIIX4State *s = PIIX4_PCI_DEVICE(obj);
+
+    object_initialize(&s->rtc, sizeof(s->rtc), TYPE_MC146818_RTC);
+}
+
 static void piix4_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);

@@ -202,6 +223,7 @@ static const TypeInfo piix4_info = {
     .name          = TYPE_PIIX4_PCI_DEVICE,
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(PIIX4State),
+    .instance_init = piix4_init,
     .class_init    = piix4_class_init,
     .interfaces = (InterfaceInfo[]) {
         { INTERFACE_CONVENTIONAL_PCI_DEVICE },

hw/mips/mips_malta.c +1 -3

index 9af486c77c..645c223edb 100644
@@ -26,7 +26,7 @@
 #include "qemu/units.h"
 #include "qemu-common.h"
 #include "cpu.h"
-#include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
 #include "hw/isa/superio.h"
 #include "hw/char/serial.h"
 #include "net/net.h"

@@ -44,7 +44,6 @@
 #include "hw/irq.h"
 #include "hw/loader.h"
 #include "elf.h"
-#include "hw/rtc/mc146818rtc.h"
 #include "exec/address-spaces.h"
 #include "hw/sysbus.h"             /* SysBusDevice */
 #include "qemu/host-utils.h"

@@ -1425,7 +1424,6 @@ void mips_malta_init(MachineState *machine)
     pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
     smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
                           isa_get_irq(NULL, 9), NULL, 0, NULL);
-    mc146818_rtc_init(isa_bus, 2000, NULL);
 
     /* generate SPD EEPROM data */
     generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);

include/hw/acpi/piix4.h deleted +0 -6

deleted file mode 100644
index 028bb53e3d..0000000000
@@ -1,6 +0,0 @@
-#ifndef HW_ACPI_PIIX4_H
-#define HW_ACPI_PIIX4_H
-
-#define TYPE_PIIX4_PM "PIIX4_PM"
-
-#endif

include/hw/i386/pc.h +0 -6

index f553b29652..c933c0d3a1 100644
@@ -228,12 +228,6 @@ int cmos_get_fd_drive_type(FloppyDriveType fd0);
 
 #define PORT92_A20_LINE "a20"
 
-/* acpi_piix.c */
-
-I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
-                      qemu_irq sci_irq, qemu_irq smi_irq,
-                      int smm_enabled, DeviceState **piix4_pm);
-
 /* hpet.c */
 extern int no_hpet;

include/hw/southbridge/piix.h new file +20 -0

new file mode 100644
index 0000000000..b8ce26fec4
@@ -0,0 +1,20 @@
+/*
+ * QEMU PIIX South Bridge Emulation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef HW_SOUTHBRIDGE_PIIX_H
+#define HW_SOUTHBRIDGE_PIIX_H
+
+#define TYPE_PIIX4_PM "PIIX4_PM"
+
+I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
+                      qemu_irq sci_irq, qemu_irq smi_irq,
+                      int smm_enabled, DeviceState **piix4_pm);
+
+#endif

Signature · 7 lines

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_______________________________________________
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Philippe Mathieu-Daudé

author

2019-10-26 18:04 UTC #9 lore raw

PATCH v3 9/20 hw/mips/mips_malta: Create IDE hard drive array dynamically

In the next commit we'll refactor the PIIX4 code out of mips_malta_init(). As a preliminary step, add the 'ide_drives' variable and create the drive array dynamically.

Reviewed-by Aleksandar Markovic <[email protected]>

Signed-off-by Philippe Mathieu-Daudé <[email protected]>

---
 hw/mips/mips_malta.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

hw/mips/mips_malta.c +5 -2

index 645c223edb..239ea98ef8 100644
@@ -1235,7 +1235,8 @@ void mips_malta_init(MachineState *machine)
     int piix4_devfn;
     I2CBus *smbus;
     DriveInfo *dinfo;
-    DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
+    const size_t ide_drives = MAX_IDE_BUS * MAX_IDE_DEVS;
+    DriveInfo **hd;
     int fl_idx = 0;
     int be;

@@ -1406,7 +1407,8 @@ void mips_malta_init(MachineState *machine)
     pci_bus = gt64120_register(s->i8259);
 
     /* Southbridge */
-    ide_drive_get(hd, ARRAY_SIZE(hd));
+    hd = g_new(DriveInfo *, ide_drives);
+    ide_drive_get(hd, ide_drives);
 
     pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
                                           true, TYPE_PIIX4_PCI_DEVICE);

@@ -1421,6 +1423,7 @@ void mips_malta_init(MachineState *machine)
     }
 
     pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
+    g_free(hd);
     pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
     smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
                           isa_get_irq(NULL, 9), NULL, 0, NULL);

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Philippe Mathieu-Daudé

author

2019-10-26 18:04 UTC #10 lore raw

PATCH v3 10/20 hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()

The Malta board instantiate a PIIX4 chipset doing various calls. Refactor all those related calls into a single
function: piix4_create().

Reviewed-by Aleksandar Markovic <[email protected]>

Signed-off-by Philippe Mathieu-Daudé <[email protected]>

---
 hw/mips/mips_malta.c | 47 +++++++++++++++++++++++++++-----------------
 1 file changed, 29 insertions(+), 18 deletions(-)

hw/mips/mips_malta.c +29 ~~-18~~

index 239ea98ef8..9014d77b7a 100644
@@ -1210,6 +1210,34 @@ static void mips_create_cpu(MachineState *ms, MaltaState *s,
     }
 }
 
+static DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
+                                 I2CBus **smbus, size_t ide_buses)
+{
+    const size_t ide_drives = ide_buses * MAX_IDE_DEVS;
+    DriveInfo **hd;
+    PCIDevice *pci;
+    DeviceState *dev;
+
+    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
+                                          true, TYPE_PIIX4_PCI_DEVICE);
+    dev = DEVICE(pci);
+    if (isa_bus) {
+        *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
+    }
+
+    hd = g_new(DriveInfo *, ide_drives);
+    ide_drive_get(hd, ide_drives);
+    pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1);
+    g_free(hd);
+    pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci");
+    if (smbus) {
+        *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100,
+                               isa_get_irq(NULL, 9), NULL, 0, NULL);
+   }
+
+    return dev;
+}
+
 static
 void mips_malta_init(MachineState *machine)
 {

@@ -1231,12 +1259,8 @@ void mips_malta_init(MachineState *machine)
     PCIBus *pci_bus;
     ISABus *isa_bus;
     qemu_irq cbus_irq, i8259_irq;
-    PCIDevice *pci;
-    int piix4_devfn;
     I2CBus *smbus;
     DriveInfo *dinfo;
-    const size_t ide_drives = MAX_IDE_BUS * MAX_IDE_DEVS;
-    DriveInfo **hd;
     int fl_idx = 0;
     int be;

@@ -1407,14 +1431,7 @@ void mips_malta_init(MachineState *machine)
     pci_bus = gt64120_register(s->i8259);
 
     /* Southbridge */
-    hd = g_new(DriveInfo *, ide_drives);
-    ide_drive_get(hd, ide_drives);
-
-    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
-                                          true, TYPE_PIIX4_PCI_DEVICE);
-    dev = DEVICE(pci);
-    isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
-    piix4_devfn = pci->devfn;
+    dev = piix4_create(pci_bus, &isa_bus, &smbus, MAX_IDE_BUS);
 
     /* Interrupt controller */
     qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);

@@ -1422,12 +1439,6 @@ void mips_malta_init(MachineState *machine)
         s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
     }
 
-    pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
-    g_free(hd);
-    pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
-    smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
-                          isa_get_irq(NULL, 9), NULL, 0, NULL);
-
     /* generate SPD EEPROM data */
     generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
     generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]);

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Philippe Mathieu-Daudé

author

2019-10-26 18:04 UTC #11 lore raw

PATCH v3 11/20 hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c

From: Philippe Mathieu-Daudé <[email protected]>

Now that we properly refactored the piix4_create() function, let's move it to hw/isa/piix4.c where it belongs, so it can be reused on other places.

Reviewed-by Aleksandar Markovic <[email protected]>

Signed-off-by Philippe Mathieu-Daudé <[email protected]>

---
 hw/isa/piix4.c                | 30 ++++++++++++++++++++++++++++++
 hw/mips/gt64xxx_pci.c         |  1 +
 hw/mips/mips_malta.c          | 28 ----------------------------
 include/hw/i386/pc.h          |  2 --
 include/hw/southbridge/piix.h |  6 ++++++
 5 files changed, 37 insertions(+), 30 deletions(-)

hw/isa/piix4.c +30 -0

index 6bf6f0c5d9..f3e21ea76d 100644
@@ -27,12 +27,14 @@
 #include "qapi/error.h"
 #include "hw/irq.h"
 #include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
 #include "hw/pci/pci.h"
 #include "hw/isa/isa.h"
 #include "hw/sysbus.h"
 #include "hw/dma/i8257.h"
 #include "hw/timer/i8254.h"
 #include "hw/rtc/mc146818rtc.h"
+#include "hw/ide.h"
 #include "migration/vmstate.h"
 #include "sysemu/reset.h"
 #include "sysemu/runstate.h"

@@ -237,3 +239,31 @@ static void piix4_register_types(void)
 }
 
 type_init(piix4_register_types)
+
+DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
+                          I2CBus **smbus, size_t ide_buses)
+{
+    size_t ide_drives = ide_buses * MAX_IDE_DEVS;
+    DriveInfo **hd;
+    PCIDevice *pci;
+    DeviceState *dev;
+
+    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
+                                          true, TYPE_PIIX4_PCI_DEVICE);
+    dev = DEVICE(pci);
+    if (isa_bus) {
+        *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
+    }
+
+    hd = g_new(DriveInfo *, ide_drives);
+    ide_drive_get(hd, ide_drives);
+    pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1);
+    g_free(hd);
+    pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci");
+    if (smbus) {
+        *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100,
+                               isa_get_irq(NULL, 9), NULL, 0, NULL);
+   }
+
+    return dev;
+}

hw/mips/gt64xxx_pci.c +1 -0

index f325bd6c1c..c277398c0d 100644
@@ -28,6 +28,7 @@
 #include "hw/mips/mips.h"
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_host.h"
+#include "hw/southbridge/piix.h"
 #include "migration/vmstate.h"
 #include "hw/i386/pc.h"
 #include "hw/irq.h"

hw/mips/mips_malta.c +0 ~~-28~~

index 9014d77b7a..92e9ca5bfa 100644
@@ -1210,34 +1210,6 @@ static void mips_create_cpu(MachineState *ms, MaltaState *s,
     }
 }
 
-static DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
-                                 I2CBus **smbus, size_t ide_buses)
-{
-    const size_t ide_drives = ide_buses * MAX_IDE_DEVS;
-    DriveInfo **hd;
-    PCIDevice *pci;
-    DeviceState *dev;
-
-    pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
-                                          true, TYPE_PIIX4_PCI_DEVICE);
-    dev = DEVICE(pci);
-    if (isa_bus) {
-        *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
-    }
-
-    hd = g_new(DriveInfo *, ide_drives);
-    ide_drive_get(hd, ide_drives);
-    pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1);
-    g_free(hd);
-    pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci");
-    if (smbus) {
-        *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100,
-                               isa_get_irq(NULL, 9), NULL, 0, NULL);
-   }
-
-    return dev;
-}
-
 static
 void mips_malta_init(MachineState *machine)
 {

include/hw/i386/pc.h +0 -2

index c933c0d3a1..2fd40ceebe 100644
@@ -258,8 +258,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                     MemoryRegion *ram_memory);
 
 PCIBus *find_i440fx(void);
-/* piix4.c */
-extern PCIDevice *piix4_dev;
 
 /* pc_sysfw.c */
 void pc_system_flash_create(PCMachineState *pcms);

include/hw/southbridge/piix.h +6 -0

index b8ce26fec4..add352456b 100644
@@ -2,6 +2,7 @@
  * QEMU PIIX South Bridge Emulation
  *
  * Copyright (c) 2006 Fabrice Bellard
+ * Copyright (c) 2018 Hervé Poussineau
  *
  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  * See the COPYING file in the top-level directory.

@@ -17,4 +18,9 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                       qemu_irq sci_irq, qemu_irq smi_irq,
                       int smm_enabled, DeviceState **piix4_pm);
 
+extern PCIDevice *piix4_dev;
+
+DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
+                          I2CBus **smbus, size_t ide_buses);
+
 #endif

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Philippe Mathieu-Daudé

author

2019-10-26 18:04 UTC #12 lore raw

PATCH v3 12/20 hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers

These devices implemented their load_state_old() handler 10 years ago, previous to QEMU v0.12.
Since commit cc425b5ddf removed the pc-0.10 and pc-0.11 machines, we can drop this code.

Note: the mips_r4k machine started to use the i8254 device just after QEMU v0.5.0, but the MIPS machine types are not versioned, so there is no migration compatibility issue removing this handler.

Reviewed-by Aleksandar Markovic <[email protected]>

Signed-off-by Philippe Mathieu-Daudé <[email protected]>

---
 hw/acpi/piix4.c         | 40 ---------------------------------
 hw/intc/apic_common.c   | 49 -----------------------------------------
 hw/pci-host/piix.c      | 25 ---------------------
 hw/timer/i8254_common.c | 40 ---------------------------------
 4 files changed, 154 deletions(-)

hw/acpi/piix4.c +0 ~~-40~~

index 2efd1605b8..93aec2dd2c 100644
@@ -41,7 +41,6 @@
 #include "hw/acpi/memory_hotplug.h"
 #include "hw/acpi/acpi_dev_interface.h"
 #include "hw/xen/xen.h"
-#include "migration/qemu-file-types.h"
 #include "migration/vmstate.h"
 #include "hw/core/cpu.h"
 #include "trace.h"

@@ -204,43 +203,6 @@ static const VMStateDescription vmstate_pci_status = {
     }
 };
 
-static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
-{
-    PIIX4PMState *s = opaque;
-    int ret, i;
-    uint16_t temp;
-
-    ret = pci_device_load(PCI_DEVICE(s), f);
-    if (ret < 0) {
-        return ret;
-    }
-    qemu_get_be16s(f, &s->ar.pm1.evt.sts);
-    qemu_get_be16s(f, &s->ar.pm1.evt.en);
-    qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
-
-    ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
-    if (ret) {
-        return ret;
-    }
-
-    timer_get(f, s->ar.tmr.timer);
-    qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
-
-    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
-    for (i = 0; i < 3; i++) {
-        qemu_get_be16s(f, &temp);
-    }
-
-    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
-    for (i = 0; i < 3; i++) {
-        qemu_get_be16s(f, &temp);
-    }
-
-    ret = vmstate_load_state(f, &vmstate_pci_status,
-        &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1);
-    return ret;
-}
-
 static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
 {
     PIIX4PMState *s = opaque;

@@ -312,8 +274,6 @@ static const VMStateDescription vmstate_acpi = {
     .name = "piix4_pm",
     .version_id = 3,
     .minimum_version_id = 3,
-    .minimum_version_id_old = 1,
-    .load_state_old = acpi_load_old,
     .post_load = vmstate_acpi_post_load,
     .fields = (VMStateField[]) {
         VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),

hw/intc/apic_common.c +0 ~~-49~~

67 lines not on this page · raw message

hw/pci-host/piix.c +0 ~~-25~~

index 135c645535..2f4cbcbfe9 100644
@@ -33,7 +33,6 @@
 #include "qapi/error.h"
 #include "qemu/range.h"
 #include "hw/xen/xen.h"
-#include "migration/qemu-file-types.h"
 #include "migration/vmstate.h"
 #include "hw/pci-host/pam.h"
 #include "sysemu/reset.h"

@@ -174,28 +173,6 @@ static void i440fx_write_config(PCIDevice *dev,
     }
 }
 
-static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
-{
-    PCII440FXState *d = opaque;
-    PCIDevice *pd = PCI_DEVICE(d);
-    int ret, i;
-    uint8_t smm_enabled;
-
-    ret = pci_device_load(pd, f);
-    if (ret < 0)
-        return ret;
-    i440fx_update_memory_mappings(d);
-    qemu_get_8s(f, &smm_enabled);
-
-    if (version_id == 2) {
-        for (i = 0; i < PIIX_NUM_PIRQS; i++) {
-            qemu_get_be32(f); /* dummy load for compatibility */
-        }
-    }
-
-    return 0;
-}
-
 static int i440fx_post_load(void *opaque, int version_id)
 {
     PCII440FXState *d = opaque;

@@ -208,8 +185,6 @@ static const VMStateDescription vmstate_i440fx = {
     .name = "I440FX",
     .version_id = 3,
     .minimum_version_id = 3,
-    .minimum_version_id_old = 1,
-    .load_state_old = i440fx_load_old,
     .post_load = i440fx_post_load,
     .fields = (VMStateField[]) {
         VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),

hw/timer/i8254_common.c +0 ~~-40~~

index 57bf10cc94..050875b497 100644
@@ -29,7 +29,6 @@
 #include "qemu/timer.h"
 #include "hw/timer/i8254.h"
 #include "hw/timer/i8254_internal.h"
-#include "migration/qemu-file-types.h"
 #include "migration/vmstate.h"
 
 /* val must be 0 or 1 */

@@ -202,43 +201,6 @@ static const VMStateDescription vmstate_pit_channel = {
     }
 };
 
-static int pit_load_old(QEMUFile *f, void *opaque, int version_id)
-{
-    PITCommonState *pit = opaque;
-    PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
-    PITChannelState *s;
-    int i;
-
-    if (version_id != 1) {
-        return -EINVAL;
-    }
-
-    for (i = 0; i < 3; i++) {
-        s = &pit->channels[i];
-        s->count = qemu_get_be32(f);
-        qemu_get_be16s(f, &s->latched_count);
-        qemu_get_8s(f, &s->count_latched);
-        qemu_get_8s(f, &s->status_latched);
-        qemu_get_8s(f, &s->status);
-        qemu_get_8s(f, &s->read_state);
-        qemu_get_8s(f, &s->write_state);
-        qemu_get_8s(f, &s->write_latch);
-        qemu_get_8s(f, &s->rw_mode);
-        qemu_get_8s(f, &s->mode);
-        qemu_get_8s(f, &s->bcd);
-        qemu_get_8s(f, &s->gate);
-        s->count_load_time = qemu_get_be64(f);
-        s->irq_disabled = 0;
-        if (i == 0) {
-            s->next_transition_time = qemu_get_be64(f);
-        }
-    }
-    if (c->post_load) {
-        c->post_load(pit);
-    }
-    return 0;
-}
-
 static int pit_dispatch_pre_save(void *opaque)
 {
     PITCommonState *s = opaque;

@@ -266,8 +228,6 @@ static const VMStateDescription vmstate_pit_common = {
     .name = "i8254",
     .version_id = 3,
     .minimum_version_id = 2,
-    .minimum_version_id_old = 1,
-    .load_state_old = pit_load_old,
     .pre_save = pit_dispatch_pre_save,
     .post_load = pit_dispatch_post_load,
     .fields = (VMStateField[]) {

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Philippe Mathieu-Daudé

author

2019-10-26 18:04 UTC #13 lore raw

PATCH v3 13/20 hw/pci-host/piix: Extract piix3_create()

Extract the PIIX3 creation code from the i440fx_init() function.

Reviewed-by Aleksandar Markovic <[email protected]>

Signed-off-by Philippe Mathieu-Daudé <[email protected]>

---
 hw/pci-host/piix.c | 51 ++++++++++++++++++++++++++++------------------
 1 file changed, 31 insertions(+), 20 deletions(-)

hw/pci-host/piix.c +31 ~~-20~~

index 2f4cbcbfe9..3292703de7 100644
@@ -331,6 +331,36 @@ static void i440fx_realize(PCIDevice *dev, Error **errp)
     }
 }
 
+static PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
+{
+    PIIX3State *piix3;
+    PCIDevice *pci_dev;
+
+    /*
+     * Xen supports additional interrupt routes from the PCI devices to
+     * the IOAPIC: the four pins of each PCI device on the bus are also
+     * connected to the IOAPIC directly.
+     * These additional routes can be discovered through ACPI.
+     */
+    if (xen_enabled()) {
+        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
+                                                  TYPE_PIIX3_XEN_DEVICE);
+        piix3 = PIIX3_PCI_DEVICE(pci_dev);
+        pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
+                     piix3, XEN_PIIX_NUM_PIRQS);
+    } else {
+        pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
+                                                  TYPE_PIIX3_DEVICE);
+        piix3 = PIIX3_PCI_DEVICE(pci_dev);
+        pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
+                     piix3, PIIX_NUM_PIRQS);
+        pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
+    }
+    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
+
+    return piix3;
+}
+
 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                     PCII440FXState **pi440fx_state,
                     int *piix3_devfn,

@@ -400,27 +430,8 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                  PAM_EXPAN_SIZE);
     }
 
-    /* Xen supports additional interrupt routes from the PCI devices to
-     * the IOAPIC: the four pins of each PCI device on the bus are also
-     * connected to the IOAPIC directly.
-     * These additional routes can be discovered through ACPI. */
-    if (xen_enabled()) {
-        PCIDevice *pci_dev = pci_create_simple_multifunction(b,
-                             -1, true, TYPE_PIIX3_XEN_DEVICE);
-        piix3 = PIIX3_PCI_DEVICE(pci_dev);
-        pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
-                piix3, XEN_PIIX_NUM_PIRQS);
-    } else {
-        PCIDevice *pci_dev = pci_create_simple_multifunction(b,
-                             -1, true, TYPE_PIIX3_DEVICE);
-        piix3 = PIIX3_PCI_DEVICE(pci_dev);
-        pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
-                PIIX_NUM_PIRQS);
-        pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
-    }
+    piix3 = piix3_create(b, isa_bus);
     piix3->pic = pic;
-    *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
-
     *piix3_devfn = piix3->dev.devfn;
 
     ram_size = ram_size / 8 / 1024 / 1024;

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Philippe Mathieu-Daudé

author

2019-10-26 18:05 UTC #14 lore raw

PATCH v3 14/20 hw/pci-host/piix: Move RCR_IOPORT register definition

From: Philippe Mathieu-Daudé <[email protected]>

The RCR_IOPORT register belongs to the PIIX chipset. Move the definition to "piix.h", and prepend the PIIX prefix.

Reviewed-by Aleksandar Markovic <[email protected]>

Signed-off-by Philippe Mathieu-Daudé <[email protected]>

---
v2: prepend PIIX prefix (Aleksandar)

---
 hw/i386/acpi-build.c          | 2 +-
 hw/isa/piix4.c                | 2 +-
 hw/pci-host/piix.c            | 7 ++++---
 include/hw/i386/pc.h          | 6 ------
 include/hw/southbridge/piix.h | 6 ++++++
 5 files changed, 12 insertions(+), 11 deletions(-)

hw/i386/acpi-build.c +1 -1

index b1b050d8e2..266d9b534b 100644
@@ -209,7 +209,7 @@ static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
 
     /* The above need not be conditional on machine type because the reset port
      * happens to be the same on PIIX (pc) and ICH9 (q35). */
-    QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT);
+    QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT);
 
     /* Fill in optional s3/s4 related properties */
     o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);

hw/isa/piix4.c +1 -1

index f3e21ea76d..86678e6829 100644
@@ -166,7 +166,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
     memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
                           "reset-control", 1);
     memory_region_add_subregion_overlap(pci_address_space_io(dev),
-                                        RCR_IOPORT, &s->rcr_mem, 1);
+                                        PIIX_RCR_IOPORT, &s->rcr_mem, 1);
 
     /* initialize i8259 pic */
     i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);

hw/pci-host/piix.c +4 -3

index 3292703de7..6548d9a4b5 100644
@@ -27,6 +27,7 @@
 #include "hw/irq.h"
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_host.h"
+#include "hw/southbridge/piix.h"
 #include "hw/qdev-properties.h"
 #include "hw/isa/isa.h"
 #include "hw/sysbus.h"

@@ -87,7 +88,7 @@ typedef struct PIIX3State {
     /* Reset Control Register contents */
     uint8_t rcr;
 
-    /* IO memory region for Reset Control Register (RCR_IOPORT) */
+    /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
     MemoryRegion rcr_mem;
 } PIIX3State;

@@ -695,8 +696,8 @@ static void piix3_realize(PCIDevice *dev, Error **errp)
 
     memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
                           "piix3-reset-control", 1);
-    memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
-                                        &d->rcr_mem, 1);
+    memory_region_add_subregion_overlap(pci_address_space_io(dev),
+                                        PIIX_RCR_IOPORT, &d->rcr_mem, 1);
 
     qemu_register_reset(piix3_reset, d);
 }

include/hw/i386/pc.h +0 -6

index 2fd40ceebe..d6ff95e047 100644
@@ -240,12 +240,6 @@ typedef struct PCII440FXState PCII440FXState;
 
 #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
 
-/*
- * Reset Control Register: PCI-accessible ISA-Compatible Register at address
- * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
- */
-#define RCR_IOPORT 0xcf9
-
 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                     PCII440FXState **pi440fx_state, int *piix_devfn,
                     ISABus **isa_bus, qemu_irq *pic,

include/hw/southbridge/piix.h +6 -0

index add352456b..e49d4a6bbe 100644
@@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                       qemu_irq sci_irq, qemu_irq smi_irq,
                       int smm_enabled, DeviceState **piix4_pm);
 
+/*
+ * Reset Control Register: PCI-accessible ISA-Compatible Register at address
+ * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
+ */
+#define PIIX_RCR_IOPORT 0xcf9
+
 extern PCIDevice *piix4_dev;
 
 DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,

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Philippe Mathieu-Daudé

author

2019-10-26 18:04 UTC #15 lore raw

PATCH v3 15/20 hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers

The IRQ Route Control registers definitions belong to the PIIX chipset. We were only defining the 'A' register. Define the other B, C and D registers, and use them.

Acked-by Paul Durrant <[email protected]>

Reviewed-by Aleksandar Markovic <[email protected]>

Signed-off-by Philippe Mathieu-Daudé <[email protected]>

---
 hw/i386/xen/xen-hvm.c         | 5 +++--
 hw/mips/gt64xxx_pci.c         | 4 ++--
 hw/pci-host/piix.c            | 9 ++++-----
 include/hw/southbridge/piix.h | 6 ++++++
 4 files changed, 15 insertions(+), 9 deletions(-)

hw/i386/xen/xen-hvm.c +3 -2

index 95f23a263c..82ece6b9e7 100644
@@ -14,6 +14,7 @@
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_host.h"
 #include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
 #include "hw/irq.h"
 #include "hw/hw.h"
 #include "hw/i386/apic-msidef.h"

@@ -156,8 +157,8 @@ void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len)
             v = 0;
         }
         v &= 0xf;
-        if (((address + i) >= 0x60) && ((address + i) <= 0x63)) {
-            xen_set_pci_link_route(xen_domid, address + i - 0x60, v);
+        if (((address + i) >= PIIX_PIRQCA) && ((address + i) <= PIIX_PIRQCD)) {
+            xen_set_pci_link_route(xen_domid, address + i - PIIX_PIRQCA, v);
         }
     }
 }

hw/mips/gt64xxx_pci.c +2 -2

index c277398c0d..5cab9c1ee1 100644
@@ -1013,12 +1013,12 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
 
     /* now we change the pic irq level according to the piix irq mappings */
     /* XXX: optimize */
-    pic_irq = piix4_dev->config[0x60 + irq_num];
+    pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num];
     if (pic_irq < 16) {
         /* The pic level is the logical OR of all the PCI irqs mapped to it. */
         pic_level = 0;
         for (i = 0; i < 4; i++) {
-            if (pic_irq == piix4_dev->config[0x60 + i]) {
+            if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) {
                 pic_level |= pci_irq_levels[i];
             }
         }

hw/pci-host/piix.c +4 -5

index 6548d9a4b5..390fb9ceba 100644
@@ -61,7 +61,6 @@ typedef struct I440FXState {
 #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
 #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
 #define XEN_PIIX_NUM_PIRQS      128ULL
-#define PIIX_PIRQC              0x60
 
 typedef struct PIIX3State {
     PCIDevice dev;

@@ -468,7 +467,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
     int pic_irq;
     uint64_t mask;
 
-    pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
+    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
         return;
     }

@@ -482,7 +481,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
 {
     int pic_irq;
 
-    pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
+    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
         return;
     }

@@ -501,7 +500,7 @@ static void piix3_set_irq(void *opaque, int pirq, int level)
 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
 {
     PIIX3State *piix3 = opaque;
-    int irq = piix3->dev.config[PIIX_PIRQC + pin];
+    int irq = piix3->dev.config[PIIX_PIRQCA + pin];
     PCIINTxRoute route;
 
     if (irq < PIIX_NUM_PIC_IRQS) {

@@ -530,7 +529,7 @@ static void piix3_write_config(PCIDevice *dev,
                                uint32_t address, uint32_t val, int len)
 {
     pci_default_write_config(dev, address, val, len);
-    if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
+    if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
         PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
         int pic_irq;

include/hw/southbridge/piix.h +6 -0

index e49d4a6bbe..094508b928 100644
@@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                       qemu_irq sci_irq, qemu_irq smi_irq,
                       int smm_enabled, DeviceState **piix4_pm);
 
+/* PIRQRC[A:D]: PIRQx Route Control Registers */
+#define PIIX_PIRQCA 0x60
+#define PIIX_PIRQCB 0x61
+#define PIIX_PIRQCC 0x62
+#define PIIX_PIRQCD 0x63
+
 /*
  * Reset Control Register: PCI-accessible ISA-Compatible Register at address
  * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).

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Philippe Mathieu-Daudé

author

2019-10-26 18:05 UTC #16 lore raw

PATCH v3 16/20 hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h

From: Philippe Mathieu-Daudé <[email protected]>

The hw/pci-host/piix.c contains a mix of PIIX3 and i440FX chipsets functions. To be able to split it, we need to export some declarations first.

Reviewed-by Aleksandar Markovic <[email protected]>

Signed-off-by Philippe Mathieu-Daudé <[email protected]>

---
 MAINTAINERS                  |  1 +
 hw/acpi/pcihp.c              |  2 +-
 hw/i386/pc_piix.c            |  1 +
 hw/pci-host/piix.c           |  1 +
 include/hw/i386/pc.h         | 22 ---------------------
 include/hw/pci-host/i440fx.h | 37 ++++++++++++++++++++++++++++++++++++
 stubs/pci-host-piix.c        |  3 ++-
 7 files changed, 43 insertions(+), 24 deletions(-)
 create mode 100644 include/hw/pci-host/i440fx.h

MAINTAINERS +1 -0

index 90c5ece04b..a48daf0615 100644
@@ -1228,6 +1228,7 @@ F: hw/i386/
 F: hw/pci-host/piix.c
 F: hw/pci-host/q35.c
 F: hw/pci-host/pam.c
+F: include/hw/pci-host/i440fx.h
 F: include/hw/pci-host/q35.h
 F: include/hw/pci-host/pam.h
 F: hw/isa/lpc_ich9.c

hw/acpi/pcihp.c +1 -1

index 82d295b6e8..8413348a33 100644
@@ -27,7 +27,7 @@
 #include "qemu/osdep.h"
 #include "hw/acpi/pcihp.h"
 
-#include "hw/i386/pc.h"
+#include "hw/pci-host/i440fx.h"
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_bridge.h"
 #include "hw/acpi/acpi.h"

hw/i386/pc_piix.c +1 -0

index a96ede19b2..ba35d5685e 100644
@@ -30,6 +30,7 @@
 #include "hw/i386/x86.h"
 #include "hw/i386/pc.h"
 #include "hw/i386/apic.h"
+#include "hw/pci-host/i440fx.h"
 #include "hw/southbridge/piix.h"
 #include "hw/display/ramfb.h"
 #include "hw/firmware/smbios.h"

hw/pci-host/piix.c +1 -0

index 390fb9ceba..95b04122fa 100644
@@ -27,6 +27,7 @@
 #include "hw/irq.h"
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_host.h"
+#include "hw/pci-host/i440fx.h"
 #include "hw/southbridge/piix.h"
 #include "hw/qdev-properties.h"
 #include "hw/isa/isa.h"

include/hw/i386/pc.h +0 ~~-22~~

index d6ff95e047..e6fa8418ca 100644
@@ -231,28 +231,6 @@ int cmos_get_fd_drive_type(FloppyDriveType fd0);
 /* hpet.c */
 extern int no_hpet;
 
-/* piix_pci.c */
-struct PCII440FXState;
-typedef struct PCII440FXState PCII440FXState;
-
-#define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
-#define TYPE_I440FX_PCI_DEVICE "i440FX"
-
-#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
-
-PCIBus *i440fx_init(const char *host_type, const char *pci_type,
-                    PCII440FXState **pi440fx_state, int *piix_devfn,
-                    ISABus **isa_bus, qemu_irq *pic,
-                    MemoryRegion *address_space_mem,
-                    MemoryRegion *address_space_io,
-                    ram_addr_t ram_size,
-                    ram_addr_t below_4g_mem_size,
-                    ram_addr_t above_4g_mem_size,
-                    MemoryRegion *pci_memory,
-                    MemoryRegion *ram_memory);
-
-PCIBus *find_i440fx(void);
-
 /* pc_sysfw.c */
 void pc_system_flash_create(PCMachineState *pcms);
 void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory);

include/hw/pci-host/i440fx.h new file +37 -0

new file mode 100644
index 0000000000..e327f9bf87
@@ -0,0 +1,37 @@
+/*
+ * QEMU i440FX North Bridge Emulation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef HW_PCI_I440FX_H
+#define HW_PCI_I440FX_H
+
+#include "hw/hw.h"
+#include "hw/pci/pci_bus.h"
+
+typedef struct PCII440FXState PCII440FXState;
+
+#define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
+#define TYPE_I440FX_PCI_DEVICE "i440FX"
+
+#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
+
+PCIBus *i440fx_init(const char *host_type, const char *pci_type,
+                    PCII440FXState **pi440fx_state, int *piix_devfn,
+                    ISABus **isa_bus, qemu_irq *pic,
+                    MemoryRegion *address_space_mem,
+                    MemoryRegion *address_space_io,
+                    ram_addr_t ram_size,
+                    ram_addr_t below_4g_mem_size,
+                    ram_addr_t above_4g_mem_size,
+                    MemoryRegion *pci_memory,
+                    MemoryRegion *ram_memory);
+
+PCIBus *find_i440fx(void);
+
+#endif

stubs/pci-host-piix.c +2 -1

index 6ed81b1f21..93975adbfe 100644
@@ -1,5 +1,6 @@
 #include "qemu/osdep.h"
-#include "hw/i386/pc.h"
+#include "hw/pci-host/i440fx.h"
+
 PCIBus *find_i440fx(void)
 {
     return NULL;

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Philippe Mathieu-Daudé

author

2019-10-26 18:05 UTC #17 lore raw

PATCH v3 17/20 hw/pci-host/piix: Fix code style issues

We will move this code, fix its style first.

Reviewed-by Aleksandar Markovic <[email protected]>

Signed-off-by Philippe Mathieu-Daudé <[email protected]>

---
 hw/pci-host/piix.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

hw/pci-host/piix.c +4 -3

index 95b04122fa..1544c4726b 100644
@@ -133,9 +133,10 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
 static void piix3_write_config_xen(PCIDevice *dev,
                                uint32_t address, uint32_t val, int len);
 
-/* return the global irq number corresponding to a given device irq
-   pin. We could also use the bus number to have a more precise
-   mapping. */
+/*
+ * Return the global irq number corresponding to a given device irq
+ * pin. We could also use the bus number to have a more precise mapping.
+ */
 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
 {
     int slot_addend;

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Philippe Mathieu-Daudé

author

2019-10-26 18:05 UTC #18 lore raw

PATCH v3 18/20 hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c

From: Philippe Mathieu-Daudé <[email protected]>

Move all the PIIX3 functions to a new file: hw/isa/piix3.c.

Reviewed-by Aleksandar Markovic <[email protected]>

Signed-off-by Philippe Mathieu-Daudé <[email protected]>

---
Checkpatch warning:

ERROR: spaces required around that '*' (ctx:VxV)
#312: FILE: hw/isa/piix3.c:248:

 +    .subsections = (const VMStateDescription*[]) {
                                              ^
---
 MAINTAINERS                   |   1 +
 hw/i386/Kconfig               |   1 +
 hw/isa/Kconfig                |   4 +
 hw/isa/Makefile.objs          |   1 +
 hw/isa/piix3.c                | 399 +++++++++++++++++++++++++++++++++
 hw/pci-host/Kconfig           |   1 -
 hw/pci-host/piix.c            | 402 ----------------------------------
 include/hw/southbridge/piix.h |  36 +++
 8 files changed, 442 insertions(+), 403 deletions(-)
 create mode 100644 hw/isa/piix3.c

MAINTAINERS +1 -0

index a48daf0615..e7e7bfc890 100644
@@ -1231,6 +1231,7 @@ F: hw/pci-host/pam.c
 F: include/hw/pci-host/i440fx.h
 F: include/hw/pci-host/q35.h
 F: include/hw/pci-host/pam.h
+F: hw/isa/piix3.c
 F: hw/isa/lpc_ich9.c
 F: hw/i2c/smbus_ich9.c
 F: hw/acpi/piix4.c

hw/i386/Kconfig +1 -0

index b25bb6d78a..d420b35548 100644
@@ -61,6 +61,7 @@ config I440FX
     select PC_ACPI
     select ACPI_SMBUS
     select PCI_PIIX
+    select PIIX3
     select IDE_PIIX
     select DIMM
     select SMBIOS

hw/isa/Kconfig +4 -0

index 98a289957e..8a38813cc1 100644
@@ -29,6 +29,10 @@ config PC87312
     select FDC
     select IDE_ISA
 
+config PIIX3
+    bool
+    select ISA_BUS
+
 config PIIX4
     bool
     # For historical reasons, SuperIO devices are created in the board

hw/isa/Makefile.objs +1 -0

index ff97485504..8e73960a75 100644
@@ -3,6 +3,7 @@ common-obj-$(CONFIG_ISA_SUPERIO) += isa-superio.o
 common-obj-$(CONFIG_APM) += apm.o
 common-obj-$(CONFIG_I82378) += i82378.o
 common-obj-$(CONFIG_PC87312) += pc87312.o
+common-obj-$(CONFIG_PIIX3) += piix3.o
 common-obj-$(CONFIG_PIIX4) += piix4.o
 common-obj-$(CONFIG_VT82C686) += vt82c686.o
 common-obj-$(CONFIG_SMC37C669) += smc37c669-superio.o

hw/isa/piix3.c new file +399 -0

399 lines not on this page · raw message

hw/pci-host/Kconfig +0 -1

index 1edc1a31d4..397043b289 100644
@@ -32,7 +32,6 @@ config PCI_PIIX
     bool
     select PCI
     select PAM
-    select ISA_BUS
 
 config PCI_EXPRESS_Q35
     bool

hw/pci-host/piix.c +0 ~~-402~~

450 lines not on this page · raw message

include/hw/southbridge/piix.h +36 -0

index 094508b928..152628c6d9 100644
@@ -12,6 +12,8 @@
 #ifndef HW_SOUTHBRIDGE_PIIX_H
 #define HW_SOUTHBRIDGE_PIIX_H
 
+#include "hw/pci/pci.h"
+
 #define TYPE_PIIX4_PM "PIIX4_PM"
 
 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,

@@ -30,8 +32,42 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
  */
 #define PIIX_RCR_IOPORT 0xcf9
 
+#define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
+#define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
+
+typedef struct PIIXState {
+    PCIDevice dev;
+
+    /*
+     * bitmap to track pic levels.
+     * The pic level is the logical OR of all the PCI irqs mapped to it
+     * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
+     *
+     * PIRQ is mapped to PIC pins, we track it by
+     * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
+     * pic_irq * PIIX_NUM_PIRQS + pirq
+     */
+#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
+#error "unable to encode pic state in 64bit in pic_levels."
+#endif
+    uint64_t pic_levels;
+
+    qemu_irq *pic;
+
+    /* This member isn't used. Just for save/load compatibility */
+    int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
+
+    /* Reset Control Register contents */
+    uint8_t rcr;
+
+    /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
+    MemoryRegion rcr_mem;
+} PIIX3State;
+
 extern PCIDevice *piix4_dev;
 
+PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus);
+
 DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
                           I2CBus **smbus, size_t ide_buses);

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Philippe Mathieu-Daudé

author

2019-10-26 18:05 UTC #19 lore raw

PATCH v3 19/20 hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'

From: Philippe Mathieu-Daudé <[email protected]>

We moved all the PIIX3 southbridge code out of hw/pci-host/piix.c, it now only contains i440FX northbridge code.
Rename it to match the chipset modelled.

Reviewed-by Aleksandar Markovic <[email protected]>

Signed-off-by Philippe Mathieu-Daudé <[email protected]>

---
 MAINTAINERS                      | 2 +-
 hw/i386/Kconfig                  | 2 +-
 hw/pci-host/Kconfig              | 2 +-
 hw/pci-host/Makefile.objs        | 2 +-
 hw/pci-host/{piix.c => i440fx.c} | 0
 5 files changed, 4 insertions(+), 4 deletions(-)
 rename hw/pci-host/{piix.c => i440fx.c} (100%)

MAINTAINERS +1 -1

index e7e7bfc890..87e7fb1a65 100644
@@ -1225,7 +1225,7 @@ M: Marcel Apfelbaum <[email protected]>
 S: Supported
 F: include/hw/i386/
 F: hw/i386/
-F: hw/pci-host/piix.c
+F: hw/pci-host/i440fx.c
 F: hw/pci-host/q35.c
 F: hw/pci-host/pam.c
 F: include/hw/pci-host/i440fx.h

hw/i386/Kconfig +1 -1

index d420b35548..5a494342ea 100644
@@ -60,7 +60,7 @@ config I440FX
     select PC_PCI
     select PC_ACPI
     select ACPI_SMBUS
-    select PCI_PIIX
+    select PCI_I440FX
     select PIIX3
     select IDE_PIIX
     select DIMM

hw/pci-host/Kconfig +1 -1

index 397043b289..b0aa8351c4 100644
@@ -28,7 +28,7 @@ config PCI_SABRE
     select PCI
     bool
 
-config PCI_PIIX
+config PCI_I440FX
     bool
     select PCI
     select PAM

hw/pci-host/Makefile.objs +1 -1

index a9cd3e022d..efd752b766 100644
@@ -13,7 +13,7 @@ common-obj-$(CONFIG_VERSATILE_PCI) += versatile.o
 
 common-obj-$(CONFIG_PCI_SABRE) += sabre.o
 common-obj-$(CONFIG_FULONG) += bonito.o
-common-obj-$(CONFIG_PCI_PIIX) += piix.o
+common-obj-$(CONFIG_PCI_I440FX) += i440fx.o
 common-obj-$(CONFIG_PCI_EXPRESS_Q35) += q35.o
 common-obj-$(CONFIG_PCI_EXPRESS_GENERIC_BRIDGE) += gpex.o
 common-obj-$(CONFIG_PCI_EXPRESS_XILINX) += xilinx-pcie.o

hw/pci-host/i440fx.c renamed from hw/pci-host/piix.c +0 -0

similarity index 100%
rename from hw/pci-host/piix.c
rename to hw/pci-host/i440fx.c

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Philippe Mathieu-Daudé

author

2019-10-26 18:05 UTC #20 lore raw

PATCH v3 20/20 hw/pci-host/i440fx: Remove the last PIIX3 traces

The PIIX3 is not tied to the i440FX and can even be used without it. Move its creation to the machine code (pc_piix.c).
We have now removed the last trace of southbridge code in the i440FX northbridge.

Reviewed-by Aleksandar Markovic <[email protected]>

Signed-off-by Philippe Mathieu-Daudé <[email protected]>

---
 hw/i386/pc_piix.c            | 8 +++++++-
 hw/pci-host/i440fx.c         | 8 --------
 include/hw/pci-host/i440fx.h | 3 +--
 3 files changed, 8 insertions(+), 11 deletions(-)

hw/i386/pc_piix.c +7 -1

index ba35d5685e..2aefa3b8df 100644
@@ -192,14 +192,20 @@ static void pc_init1(MachineState *machine,
     gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled);
 
     if (pcmc->pci_enabled) {
+        PIIX3State *piix3;
+
         pci_bus = i440fx_init(host_type,
                               pci_type,
-                              &i440fx_state, &piix3_devfn, &isa_bus, x86ms->gsi,
+                              &i440fx_state,
                               system_memory, system_io, machine->ram_size,
                               x86ms->below_4g_mem_size,
                               x86ms->above_4g_mem_size,
                               pci_memory, ram_memory);
         pcms->bus = pci_bus;
+
+        piix3 = piix3_create(pci_bus, &isa_bus);
+        piix3->pic = x86ms->gsi;
+        piix3_devfn = piix3->dev.devfn;
     } else {
         pci_bus = NULL;
         i440fx_state = NULL;

hw/pci-host/i440fx.c +0 -8

index 79ecd58a2b..f27131102d 100644
@@ -27,7 +27,6 @@
 #include "hw/pci/pci.h"
 #include "hw/pci/pci_host.h"
 #include "hw/pci-host/i440fx.h"
-#include "hw/southbridge/piix.h"
 #include "hw/qdev-properties.h"
 #include "hw/sysbus.h"
 #include "qapi/error.h"

@@ -272,8 +271,6 @@ static void i440fx_realize(PCIDevice *dev, Error **errp)
 
 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                     PCII440FXState **pi440fx_state,
-                    int *piix3_devfn,
-                    ISABus **isa_bus, qemu_irq *pic,
                     MemoryRegion *address_space_mem,
                     MemoryRegion *address_space_io,
                     ram_addr_t ram_size,

@@ -286,7 +283,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
     PCIBus *b;
     PCIDevice *d;
     PCIHostState *s;
-    PIIX3State *piix3;
     PCII440FXState *f;
     unsigned i;
     I440FXState *i440fx;

@@ -339,10 +335,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
                  PAM_EXPAN_SIZE);
     }
 
-    piix3 = piix3_create(b, isa_bus);
-    piix3->pic = pic;
-    *piix3_devfn = piix3->dev.devfn;
-
     ram_size = ram_size / 8 / 1024 / 1024;
     if (ram_size > 255) {
         ram_size = 255;

include/hw/pci-host/i440fx.h +1 -2

index e327f9bf87..f54e6466e4 100644
@@ -22,8 +22,7 @@ typedef struct PCII440FXState PCII440FXState;
 #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
 
 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
-                    PCII440FXState **pi440fx_state, int *piix_devfn,
-                    ISABus **isa_bus, qemu_irq *pic,
+                    PCII440FXState **pi440fx_state,
                     MemoryRegion *address_space_mem,
                     MemoryRegion *address_space_io,
                     ram_addr_t ram_size,

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Aleksandar Markovic

2019-10-27 07:44 UTC #21 lore raw

Quoted 73 lines · Philippe Mathieu-Daudé

Changes since v2 [0]:
- Use a #define
- Reword one description
- Added review tags (thanks all for reviewing!)
Changes since v1 [1]:
- Removed patch reintroducing DO_UPCAST() use (thuth)
- Took various patches out to reduce series (thuth)
- Added review tags (thanks all for reviewing!)
$ git backport-diff -u pc_split_i440fx_piix-v2
Key:
[----] : patches are identical
[####] : number of functional differences between upstream/downstream patch
[down] : patch is downstream-only
The flags [FC] indicate (F)unctional and (C)ontextual differences,
respectively
001/20:[----] [--] 'MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets'
002/20:[0004] [FC] 'piix4: Add the Reset Control Register' 003/20:[0002] [FC] 'piix4: Add an i8259 Interrupt Controller as specified in datasheet'
004/20:[----] [--] 'Revert "irq: introduce qemu_irq_proxy()"' 005/20:[----] [--] 'piix4: Rename PIIX4 object to piix4-isa' 006/20:[----] [--] 'piix4: Add an i8257 DMA Controller as specified in datasheet'
007/20:[----] [-C] 'piix4: Add an i8254 PIT Controller as specified in datasheet'
008/20:[0004] [FC] 'piix4: Add a MC146818 RTC Controller as specified in datasheet'
009/20:[----] [--] 'hw/mips/mips_malta: Create IDE hard drive array dynamically'
010/20:[----] [--] 'hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()'
011/20:[----] [-C] 'hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c' 012/20:[----] [--] 'hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers'
013/20:[----] [--] 'hw/pci-host/piix: Extract piix3_create()' 014/20:[0002] [FC] 'hw/pci-host/piix: Move RCR_IOPORT register definition' 015/20:[----] [--] 'hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers'
016/20:[----] [-C] 'hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h'
017/20:[----] [--] 'hw/pci-host/piix: Fix code style issues' 018/20:[----] [--] 'hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c'
019/20:[----] [--] 'hw/pci-host: Rename incorrectly named 'piix' as 'i440fx''
020/20:[0004] [FC] 'hw/pci-host/i440fx: Remove the last PIIX3 traces'
Previous cover:
This series is a rework of "piix4: cleanup and improvements" [2] from Hervé, and my "remove i386/pc dependency: PIIX cleanup" [3].
Still trying to remove the strong X86/PC dependency 2 years later, one step at a time.
Here we split the PIIX3 southbridge from i440FX northbridge. The i440FX northbridge is only used by the PC machine, while the PIIX southbridge is also used by the Malta MIPS machine.
This is also a step forward using KConfig with the Malta board. Without this split, it was impossible to compile the Malta without pulling various X86 pieces of code.
The overall design cleanup is not yet perfect, but enough to post as a series.
Now that the PIIX3 code is extracted, the code duplication with the PIIX4 chipset is obvious. Not worth improving for now because it isn't broken.

Quoted 10 lines

Based-on: <[email protected]> to include:
mc146818rtc: Allow call object_initialize(MC146818_RTC) instead of rtc_init()
https://mid.mail-archive.com/[email protected]
Since Aleksandar offered me to send the pull request [4] I plan to do it once Paolo's pull [5] is merged.

Philippe,

I attempted the other day the integration of v2 of this series into MIPS pull request, but couldn't do it - since another series of yours was already merged, acting on the same code, making rebasing difficult. Now this, v3, series can't be applied since certain patches in some, on surface, unrelated series aren't megred, and v3 assumes they are merged.

If you send a series, it should preferably be based on the latest (current) code base, not on some imagined future state.

Why did you create this such mess with interdependencies of your own multiple series, and just right before softfreeze? :( You should have distributed submitting those series over longer time interval, and absolutely avoid, if possible, this hectic around-softfreeze period. You did the opposite: waited for softfreeze to become close, and sent several interdependant series in matter of days - creating stress without any real technical reason.

In case you, for any reason, can't complete this by softfreeze, I advice you not to rush, and postpone the integration to 5.0.

Thanks,
Aleksandar

Quoted 72 lines

Thanks,
Phil.
CI results:
https://travis-ci.org/philmd/qemu/builds/603253987
https://app.shippable.com/github/philmd/qemu/runs/550/summary/console
[0] https://lists.gnu.org/archive/html/qemu-devel/2019-10/msg04662.html
[1] https://lists.gnu.org/archive/html/qemu-devel/2019-10/msg03685.html
[2] https://www.mail-archive.com/[email protected]/msg500737.html
[3] https://www.mail-archive.com/[email protected]/msg504081.html
[4] https://lists.gnu.org/archive/html/qemu-devel/2019-10/msg04959.html
[5] https://lists.gnu.org/archive/html/qemu-devel/2019-10/msg07339.html
Hervé Poussineau (5):
piix4: Add the Reset Control Register
piix4: Add an i8259 Interrupt Controller as specified in datasheet
piix4: Rename PIIX4 object to piix4-isa
piix4: Add an i8257 DMA Controller as specified in datasheet
piix4: Add an i8254 PIT Controller as specified in datasheet
Philippe Mathieu-Daudé (15):
MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets Revert "irq: introduce qemu_irq_proxy()"
piix4: Add a MC146818 RTC Controller as specified in datasheet hw/mips/mips_malta: Create IDE hard drive array dynamically hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create() hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers hw/pci-host/piix: Extract piix3_create()
hw/pci-host/piix: Move RCR_IOPORT register definition hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h hw/pci-host/piix: Fix code style issues
hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c hw/pci-host: Rename incorrectly named 'piix' as 'i440fx' hw/pci-host/i440fx: Remove the last PIIX3 traces
 MAINTAINERS                      |  14 +-
 hw/acpi/pcihp.c                  |   2 +-
 hw/acpi/piix4.c                  |  42 +--
 hw/core/irq.c                    |  14 -
 hw/i386/Kconfig                  |   3 +-
 hw/i386/acpi-build.c             |   5 +-
 hw/i386/pc_piix.c                |  10 +-
 hw/i386/xen/xen-hvm.c            |   5 +-
 hw/intc/apic_common.c            |  49 ----
 hw/isa/Kconfig                   |   4 +
 hw/isa/Makefile.objs             |   1 +
 hw/isa/piix3.c                   | 399 +++++++++++++++++++++++++++++
 hw/isa/piix4.c                   | 151 ++++++++++-
 hw/mips/gt64xxx_pci.c            |   5 +-
 hw/mips/mips_malta.c             |  46 +---
 hw/pci-host/Kconfig              |   3 +-
 hw/pci-host/Makefile.objs        |   2 +-
 hw/pci-host/{piix.c => i440fx.c} | 424 +------------------------------
 hw/timer/i8254_common.c          |  40 ---
 include/hw/acpi/piix4.h          |   6 -
 include/hw/i386/pc.h             |  37 ---
 include/hw/irq.h                 |   5 -
 include/hw/isa/isa.h             |   2 +
 include/hw/pci-host/i440fx.h     |  36 +++
 include/hw/southbridge/piix.h    |  74 ++++++
 stubs/pci-host-piix.c            |   3 +-
 26 files changed, 699 insertions(+), 683 deletions(-)
 create mode 100644 hw/isa/piix3.c
 rename hw/pci-host/{piix.c => i440fx.c} (58%)
 delete mode 100644 include/hw/acpi/piix4.h
 create mode 100644 include/hw/pci-host/i440fx.h
 create mode 100644 include/hw/southbridge/piix.h

Quoted 5 lines

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Philippe Mathieu-Daudé

author

2019-10-30 09:53 UTC #22 lore raw

Hi Aleksandar,

Quoted 88 lines · Aleksandar Markovic

On Saturday, October 26, 2019, Philippe Mathieu-Daudé <[email protected] <mailto:[email protected]>> wrote:
Changes since v2 [0]:
- Use a #define
- Reword one description
- Added review tags (thanks all for reviewing!)
Changes since v1 [1]:
- Removed patch reintroducing DO_UPCAST() use (thuth)
- Took various patches out to reduce series (thuth)
- Added review tags (thanks all for reviewing!)
$ git backport-diff -u pc_split_i440fx_piix-v2
Key:
[----] : patches are identical
[####] : number of functional differences between upstream/downstream patch
[down] : patch is downstream-only
The flags [FC] indicate (F)unctional and (C)ontextual differences, respectively
001/20:[----] [--] 'MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets'
002/20:[0004] [FC] 'piix4: Add the Reset Control Register' 003/20:[0002] [FC] 'piix4: Add an i8259 Interrupt Controller as specified in datasheet'
004/20:[----] [--] 'Revert "irq: introduce qemu_irq_proxy()"' 005/20:[----] [--] 'piix4: Rename PIIX4 object to piix4-isa' 006/20:[----] [--] 'piix4: Add an i8257 DMA Controller as specified in datasheet'
007/20:[----] [-C] 'piix4: Add an i8254 PIT Controller as specified in datasheet'
008/20:[0004] [FC] 'piix4: Add a MC146818 RTC Controller as specified in datasheet'
009/20:[----] [--] 'hw/mips/mips_malta: Create IDE hard drive array dynamically'
010/20:[----] [--] 'hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()'
011/20:[----] [-C] 'hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c' 012/20:[----] [--] 'hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers'
013/20:[----] [--] 'hw/pci-host/piix: Extract piix3_create()' 014/20:[0002] [FC] 'hw/pci-host/piix: Move RCR_IOPORT register definition'
015/20:[----] [--] 'hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers'
016/20:[----] [-C] 'hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h'
017/20:[----] [--] 'hw/pci-host/piix: Fix code style issues' 018/20:[----] [--] 'hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c'
019/20:[----] [--] 'hw/pci-host: Rename incorrectly named 'piix' as 'i440fx''
020/20:[0004] [FC] 'hw/pci-host/i440fx: Remove the last PIIX3 traces'
Previous cover:
This series is a rework of "piix4: cleanup and improvements" [2] from Hervé, and my "remove i386/pc dependency: PIIX cleanup" [3].
Still trying to remove the strong X86/PC dependency 2 years later, one step at a time.
Here we split the PIIX3 southbridge from i440FX northbridge. The i440FX northbridge is only used by the PC machine, while the PIIX southbridge is also used by the Malta MIPS machine.
This is also a step forward using KConfig with the Malta board. Without this split, it was impossible to compile the Malta without pulling various X86 pieces of code.
The overall design cleanup is not yet perfect, but enough to post as a series.
Now that the PIIX3 code is extracted, the code duplication with the PIIX4 chipset is obvious. Not worth improving for now because it isn't broken.
Based-on: <[email protected] <mailto:[email protected]>>
to include:
mc146818rtc: Allow call object_initialize(MC146818_RTC) instead of
rtc_init()
https://mid.mail-archive.com/[email protected] <https://mid.mail-archive.com/[email protected]>
Since Aleksandar offered me to send the pull request [4] I plan to do it once Paolo's pull [5] is merged.

Quoted 5 lines

Philippe,
I attempted the other day the integration of v2 of this series into MIPS pull request, but couldn't do it - since another series of yours was already merged, acting on the same code, making rebasing difficult. Now this, v3, series can't be applied since certain patches in some, on surface, unrelated series aren't megred, and v3 assumes they are merged.
If you send a series, it should preferably be based on the latest (current) code base, not on some imagined future state.

I used the 'based-on' tag to refer other series, and patchew succeeded at applying this series on top of it and build/test it.

Based-on: <[email protected]

Quoted 1 line

Why did you create this such mess with interdependencies of your own multiple series, and just right before softfreeze? :( You should have distributed submitting those series over longer time interval, and absolutely avoid, if possible, this hectic around-softfreeze period. You did the opposite: waited for softfreeze to become close, and sent several interdependant series in matter of days - creating stress without any real technical reason.

This series touches multiple subsystems, so different maintainers had to take the various parts, so I had to split.

Also Peter gave the recommendation on the list to not put more than 20 patches in a series, to make it digestible for review.

Quoted 1 line

In case you, for any reason, can't complete this by softfreeze, I advice you not to rush, and postpone the integration to 5.0.

This series doesn't provide any useful feature, it is a simple cleanup, posted and reviewed before soft freeze, so we still have 1 week (until hard freeze) to have it merged, or postpone. No need to stress out for a cleanup ;)

Regards,

Phil.

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Aleksandar Markovic

2019-10-30 13:48 UTC #23 lore raw

Quoted 11 lines

In case you, for any reason, can't complete this by softfreeze, I advice
Quoted 2 lines
you not to rush, and postpone the integration to 5.0.
This series doesn't provide any useful feature, it is a simple cleanup, posted and reviewed before soft freeze, so we still have 1 week (until hard freeze) to have it merged, or postpone. No need to stress out for a cleanup ;)

I sounded too tight, and I apologize.

You submitted the pull request before softfreeze, so, in my understanding, it should be merged, after some integration hickups are resolved. And I am positive you will resolve them.

By 'completing' I meant 'sending the pull request', so you are on time in my book.

Take it easy, and I welcome this fine work of yours to be integrated.

Aleksandar

Quoted 4 lines

Regards,
Phil.

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2019-10-30 12:42 UTC #24 lore raw