NVIDIA Tegra20 CPUFreq driver major update

PATCH Superseded Dmitry Osipenko 3 participants 18 messages Dec 18, 2019 – Feb 2, 2020

Subsystems (7)

Device tree bindings Arm (32-bit) Arm sub-architectures Common clk +3 more subsystems

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Dmitry Osipenko

author

2019-12-18 20:21 UTC #0 lore raw

v6 cover NVIDIA Tegra20 CPUFreq driver major update

Hello,

This series moves intermediate-clk handling from tegra20-cpufreq into tegra-clk driver. This allows us to switch to generic cpufreq-dt driver which brings voltage scaling, per-hardware OPPs and Tegra30 support out of the box. All boards need to adopt CPU OPPs in their device-trees in order to get cpufreq support.

Changelog:

v6: - Dropped "cpufreq: dt-platdev: Blacklist NVIDIA Tegra20 and Tegra30 SoCs"
patch from the series since Viresh picked up that patch separately.

- Added two new patches to this series:

ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30/114/124
ARM: tegra: Don't enable PLLX while resuming from LP1 on Tegra30

Previously these patches were sent out separately from this series, but it should be more consistent to include them into the series since they directly relate to enabling of the cpufreq driver on Tegra30.

v5: - The "Use generic cpufreq-dt driver (Tegra30 supported now)" patch
is separated now into two patches by factoring out the blacklisting of cpufreq-dt-platdev into a standalone patch. This is done in a response to request from Jon Hunter to fix the warning splats during boot that are coming from OPP core because OPPs are unavailable. The OPPs will become available once tegra20-cpufreq driver will be updated to support the cpufreq-dt.

v4: - Updated CCLK diagram in the "Add custom CCLK implementation" patch.

- <linux/cpu.h> is now included in the "Use generic cpufreq-dt driver" patch, for consistency.

- Returned value of get_cpu_device() is now checked in the "Use generic cpufreq-dt driver" patch, for consistency as well.

v3: - The "Add custom CCLK implementation" patch was updated in accordance
to the comments from Peter De Schrijver. We will not use the clock skipper.

- Re added OPPs for T30 Beaver board because Thierry has that board ;)

- Added r-b for the "DT binding" patch from Rob Herring.

v2: - Kept modularity of the tegra20-cpufreq as was requested by Viresh Kumar
in a review comment to v1.

- Added acks from Viresh Kumar.

- Added tested-by from Nicolas Chauvet to the "trimslice" patch. Nicolas told me on IRC that it works fine.

- Fixed compilation of the "Add custom CCLK implementation" patch. The error happened because v1 was based on top of yet unreviewed/unapplied patch "clk: tegra: divider: Support enable-bit for Super clocks". Thanks to Peter Geis for reporting the problem.

- Replaced Tegra30 "beaver" board with "cardhu-a04" because turned out that's what NVIDIA uses in the testing farm.

Dmitry Osipenko (12):
clk: tegra: Add custom CCLK implementation
clk: tegra: pll: Add pre/post rate-change hooks
clk: tegra: cclk: Add helpers for handling PLLX rate changes
clk: tegra20: Use custom CCLK implementation
clk: tegra30: Use custom CCLK implementation
ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30/114/124
ARM: tegra: Don't enable PLLX while resuming from LP1 on Tegra30
dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30
cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported
now)
ARM: tegra: Create tegra20-cpufreq platform device on Tegra30
ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS
ARM: dts: tegra30: beaver: Add CPU Operating Performance Points

 .../cpufreq/nvidia,tegra20-cpufreq.txt        |  56 +++++
 arch/arm/boot/dts/tegra30-beaver.dts          |  40 +++-
 arch/arm/mach-tegra/sleep-tegra30.S           |  18 +-
 arch/arm/mach-tegra/tegra.c                   |   4 +
 drivers/clk/tegra/Makefile                    |   1 +
 drivers/clk/tegra/clk-pll.c                   |  12 +-
 drivers/clk/tegra/clk-tegra-super-cclk.c      | 212 +++++++++++++++++
 drivers/clk/tegra/clk-tegra20.c               |   7 +-
 drivers/clk/tegra/clk-tegra30.c               |   6 +-
 drivers/clk/tegra/clk.h                       |  19 +-
 drivers/cpufreq/Kconfig.arm                   |   6 +-
 drivers/cpufreq/tegra20-cpufreq.c             | 217 +++++-------------
 12 files changed, 418 insertions(+), 180 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt
 create mode 100644 drivers/clk/tegra/clk-tegra-super-cclk.c

Signature · 1 line

2.24.0

Dmitry Osipenko

author

2019-12-18 20:21 UTC #1 lore raw

PATCH v6 1/12 clk: tegra: Add custom CCLK implementation

CCLK stands for "CPU Clock", CPU core is running off CCLK. CCLK supports multiple parents, it has internal clock divider and a clock skipper. PLLX is the main CCLK parent that provides clock rates above 1GHz and it has special property such that the CCLK's internal divider is set into bypass mode when PLLX is selected as a parent for CCLK.

This patch forks generic Super Clock into CCLK implementation which takes into account all CCLK specifics. The proper CCLK implementation is needed by the upcoming Tegra20 CPUFreq driver update that will allow to utilize the generic cpufreq-dt driver by moving intermediate clock selection into the clock driver.

Note that technically this patch could be squashed into clk-super.c, but it is cleaner to have a separate source file. Also note that currently all CCLKLP bits are left in the clk-super.c and only CCLKG is supported by clk-tegra-super-cclk. It shouldn't be difficult to move the CCLKLP bits, but CCLKLP is not used by anything in kernel and thus better not to touch it for now.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 drivers/clk/tegra/Makefile               |   1 +
 drivers/clk/tegra/clk-tegra-super-cclk.c | 178 +++++++++++++++++++++++
 drivers/clk/tegra/clk.h                  |  11 +-
 3 files changed, 188 insertions(+), 2 deletions(-)
 create mode 100644 drivers/clk/tegra/clk-tegra-super-cclk.c

drivers/clk/tegra/Makefile +1 -0

index df966ca06788..f04b490f5416 100644
@@ -14,6 +14,7 @@ obj-y					+= clk-tegra-audio.o
 obj-y					+= clk-tegra-periph.o
 obj-y					+= clk-tegra-pmc.o
 obj-y					+= clk-tegra-fixed.o
+obj-y					+= clk-tegra-super-cclk.o
 obj-y					+= clk-tegra-super-gen4.o
 obj-$(CONFIG_TEGRA_CLK_EMC)		+= clk-emc.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clk-tegra20.o

drivers/clk/tegra/clk-tegra-super-cclk.c new file +178 -0

178 lines not on this page · raw message

drivers/clk/tegra/clk.h +9 -2

index 416a6b09f6a3..ee35a847df08 100644
@@ -729,8 +729,10 @@ struct clk *tegra_clk_register_periph_data(void __iomem *clk_base,
  * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates
  *     that this is LP cluster clock.
  * TEGRA210_CPU_CLK - This flag is used to identify CPU cluster for gen5
- * super mux parent using PLLP branches. To use PLLP branches to CPU, need
- * to configure additional bit PLLP_OUT_CPU in the clock registers.
+ *     super mux parent using PLLP branches. To use PLLP branches to CPU, need
+ *     to configure additional bit PLLP_OUT_CPU in the clock registers.
+ * TEGRA20_SUPER_CLK - Tegra20 doesn't have a dedicated divider for Super
+ *     clocks, it only has a clock-skipper.
  */
 struct tegra_clk_super_mux {
 	struct clk_hw	hw;

@@ -748,6 +750,7 @@ struct tegra_clk_super_mux {
 
 #define TEGRA_DIVIDER_2 BIT(0)
 #define TEGRA210_CPU_CLK BIT(1)
+#define TEGRA20_SUPER_CLK BIT(2)
 
 extern const struct clk_ops tegra_clk_super_ops;
 struct clk *tegra_clk_register_super_mux(const char *name,

@@ -758,6 +761,10 @@ struct clk *tegra_clk_register_super_clk(const char *name,
 		const char * const *parent_names, u8 num_parents,
 		unsigned long flags, void __iomem *reg, u8 clk_super_flags,
 		spinlock_t *lock);
+struct clk *tegra_clk_register_super_cclk(const char *name,
+		const char * const *parent_names, u8 num_parents,
+		unsigned long flags, void __iomem *reg, u8 clk_super_flags,
+		spinlock_t *lock);
 
 /**
  * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC

Signature · 1 line

2.24.0

Dmitry Osipenko

author

2019-12-18 20:21 UTC #2 lore raw

PATCH v6 2/12 clk: tegra: pll: Add pre/post rate-change hooks

In reply to Dmitry Osipenko

There is a need to temporarily re-parent CCLK away from PLLX if PLLX's rate is about to change. The newly introduced PLL pre/post rate-change hooks allow to handle such case.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 drivers/clk/tegra/clk-pll.c | 12 +++++++++++-
 drivers/clk/tegra/clk.h     |  6 ++++++
 2 files changed, 17 insertions(+), 1 deletion(-)

drivers/clk/tegra/clk-pll.c +11 -1

index 531c2b3d814e..0b212cf2e794 100644
@@ -744,13 +744,19 @@ static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 
 	state = clk_pll_is_enabled(hw);
 
+	if (state && pll->params->pre_rate_change) {
+		ret = pll->params->pre_rate_change();
+		if (WARN_ON(ret))
+			return ret;
+	}
+
 	_get_pll_mnp(pll, &old_cfg);
 
 	if (state && pll->params->defaults_set && pll->params->dyn_ramp &&
 			(cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) {
 		ret = pll->params->dyn_ramp(pll, cfg);
 		if (!ret)
-			return 0;
+			goto done;
 	}
 
 	if (state) {

@@ -772,6 +778,10 @@ static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 		pll_clk_start_ss(pll);
 	}
 
+done:
+	if (state && pll->params->post_rate_change)
+		pll->params->post_rate_change();
+
 	return ret;
 }

drivers/clk/tegra/clk.h +6 -0

index ee35a847df08..fa18bef914af 100644
@@ -266,6 +266,10 @@ struct tegra_clk_pll;
  *				disabled.
  * @dyn_ramp:			Callback which can be used to define a custom
  *				dynamic ramp function for a given PLL.
+ * @pre_rate_change:		Callback which is invoked just before changing
+ *				PLL's rate.
+ * @post_rate_change:		Callback which is invoked right after changing
+ *				PLL's rate.
  *
  * Flags:
  * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for

@@ -342,6 +346,8 @@ struct tegra_clk_pll_params {
 	void	(*set_defaults)(struct tegra_clk_pll *pll);
 	int	(*dyn_ramp)(struct tegra_clk_pll *pll,
 			struct tegra_clk_pll_freq_table *cfg);
+	int	(*pre_rate_change)(void);
+	void	(*post_rate_change)(void);
 };
 
 #define TEGRA_PLL_USE_LOCK BIT(0)

Signature · 1 line

2.24.0

Dmitry Osipenko

author

2019-12-18 20:21 UTC #3 lore raw

PATCH v6 3/12 clk: tegra: cclk: Add helpers for handling PLLX rate changes

In reply to Dmitry Osipenko

CCLK should be re-parented away from PLLX if PLLX's rate is changing. The PLLP parent is a common safe CPU parent for all Tegra SoCs, thus CCLK will be re-parented to PLLP before PLLX rate-change begins and then switched back to PLLX after the rate-change completion. This patch adds helper functions which perform CCLK re-parenting, these helpers will be utilized by further patches.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 drivers/clk/tegra/clk-tegra-super-cclk.c | 34 ++++++++++++++++++++++++
 drivers/clk/tegra/clk.h                  |  2 ++
 2 files changed, 36 insertions(+)

drivers/clk/tegra/clk-tegra-super-cclk.c +34 -0

index 7bcb9e8d0860..a03119c30456 100644
@@ -25,6 +25,9 @@
 
 #define SUPER_CDIV_ENB		BIT(31)
 
+static struct tegra_clk_super_mux *cclk_super;
+static bool cclk_on_pllx;
+
 static u8 cclk_super_get_parent(struct clk_hw *hw)
 {
 	return tegra_clk_super_ops.get_parent(hw);

@@ -115,6 +118,9 @@ struct clk *tegra_clk_register_super_cclk(const char *name,
 	struct clk_init_data init;
 	u32 val;
 
+	if (WARN_ON(cclk_super))
+		return ERR_PTR(-EBUSY);
+
 	super = kzalloc(sizeof(*super), GFP_KERNEL);
 	if (!super)
 		return ERR_PTR(-ENOMEM);

@@ -173,6 +179,34 @@ struct clk *tegra_clk_register_super_cclk(const char *name,
 	clk = clk_register(NULL, &super->hw);
 	if (IS_ERR(clk))
 		kfree(super);
+	else
+		cclk_super = super;
 
 	return clk;
 }
+
+int tegra_cclk_pre_pllx_rate_change(void)
+{
+	if (IS_ERR_OR_NULL(cclk_super))
+		return -EINVAL;
+
+	if (cclk_super_get_parent(&cclk_super->hw) == PLLX_INDEX)
+		cclk_on_pllx = true;
+	else
+		cclk_on_pllx = false;
+
+	/*
+	 * CPU needs to be temporarily re-parented away from PLLX if PLLX
+	 * changes its rate. PLLP is a safe parent for CPU on all Tegra SoCs.
+	 */
+	if (cclk_on_pllx)
+		cclk_super_set_parent(&cclk_super->hw, PLLP_INDEX);
+
+	return 0;
+}
+
+void tegra_cclk_post_pllx_rate_change(void)
+{
+	if (cclk_on_pllx)
+		cclk_super_set_parent(&cclk_super->hw, PLLX_INDEX);
+}

drivers/clk/tegra/clk.h +2 -0

index fa18bef914af..0afe28f4372b 100644
@@ -771,6 +771,8 @@ struct clk *tegra_clk_register_super_cclk(const char *name,
 		const char * const *parent_names, u8 num_parents,
 		unsigned long flags, void __iomem *reg, u8 clk_super_flags,
 		spinlock_t *lock);
+int tegra_cclk_pre_pllx_rate_change(void);
+void tegra_cclk_post_pllx_rate_change(void);
 
 /**
  * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC

Signature · 1 line

2.24.0

Dmitry Osipenko

author

2019-12-18 20:21 UTC #4 lore raw

PATCH v6 4/12 clk: tegra20: Use custom CCLK implementation

In reply to Dmitry Osipenko

We're going to use the generic cpufreq-dt driver on Tegra20 and thus CCLK intermediate re-parenting will be performed by the clock driver. There is now special CCLK implementation that supports all CCLK quirks, this patch makes Tegra20 SoCs to use that implementation.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 drivers/clk/tegra/clk-tegra20.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

drivers/clk/tegra/clk-tegra20.c +5 -2

index 4d8222f5c638..eb821666ca61 100644
@@ -391,6 +391,8 @@ static struct tegra_clk_pll_params pll_x_params = {
 	.lock_delay = 300,
 	.freq_table = pll_x_freq_table,
 	.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
+	.pre_rate_change = tegra_cclk_pre_pllx_rate_change,
+	.post_rate_change = tegra_cclk_post_pllx_rate_change,
 };
 
 static struct tegra_clk_pll_params pll_e_params = {

@@ -704,9 +706,10 @@ static void tegra20_super_clk_init(void)
 	struct clk *clk;
 
 	/* CCLK */
-	clk = tegra_clk_register_super_mux("cclk", cclk_parents,
+	clk = tegra_clk_register_super_cclk("cclk", cclk_parents,
 			      ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT,
-			      clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
+			      clk_base + CCLK_BURST_POLICY, TEGRA20_SUPER_CLK,
+			      NULL);
 	clks[TEGRA20_CLK_CCLK] = clk;
 
 	/* SCLK */

Signature · 1 line

2.24.0

Dmitry Osipenko

author

2019-12-18 20:21 UTC #5 lore raw

PATCH v6 5/12 clk: tegra30: Use custom CCLK implementation

In reply to Dmitry Osipenko

We're going to use the generic cpufreq-dt driver on Tegra30 and thus CCLK intermediate re-parenting will be performed by the clock driver. There is now special CCLK implementation that supports all CCLK quirks, this patch makes Tegra30 SoCs to use that implementation.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 drivers/clk/tegra/clk-tegra30.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

drivers/clk/tegra/clk-tegra30.c +4 -2

index c8bc18e4d7e5..0fe03d69fe1a 100644
@@ -499,6 +499,8 @@ static struct tegra_clk_pll_params pll_x_params __ro_after_init = {
 	.freq_table = pll_x_freq_table,
 	.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON |
 		 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
+	.pre_rate_change = tegra_cclk_pre_pllx_rate_change,
+	.post_rate_change = tegra_cclk_post_pllx_rate_change,
 };
 
 static struct tegra_clk_pll_params pll_e_params __ro_after_init = {

@@ -932,11 +934,11 @@ static void __init tegra30_super_clk_init(void)
 	clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL);
 
 	/* CCLKG */
-	clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
+	clk = tegra_clk_register_super_cclk("cclk_g", cclk_g_parents,
 				  ARRAY_SIZE(cclk_g_parents),
 				  CLK_SET_RATE_PARENT,
 				  clk_base + CCLKG_BURST_POLICY,
-				  0, 4, 0, 0, NULL);
+				  0, NULL);
 	clks[TEGRA30_CLK_CCLK_G] = clk;
 
 	/*

Signature · 1 line

2.24.0

Dmitry Osipenko

author

2019-12-18 20:21 UTC #6 lore raw

PATCH v6 6/12 ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30/114/124

In reply to Dmitry Osipenko

The early-resume code shall not switch CPU to PLLX because PLLX configuration could be unstable or PLLX should be simply disabled if CPU enters into suspend running off some other PLL (the case if CPUFREQ driver is active). The actual burst policy is restored by the clock drivers.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 arch/arm/mach-tegra/sleep-tegra30.S | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

arch/arm/mach-tegra/sleep-tegra30.S +2 -5

index 3341a12bbb9c..9a20c93abe48 100644
@@ -383,11 +383,8 @@ _pll_m_c_x_done:
 	ldr	r4, [r5, #0x1C]		@ restore SCLK_BURST
 	str	r4, [r0, #CLK_RESET_SCLK_BURST]
 
-	cmp	r10, #TEGRA30
-	movweq	r4, #:lower16:((1 << 28) | (0x8))	@ burst policy is PLLX
-	movteq	r4, #:upper16:((1 << 28) | (0x8))
-	movwne	r4, #:lower16:((1 << 28) | (0xe))
-	movtne	r4, #:upper16:((1 << 28) | (0xe))
+	movw	r4, #:lower16:((1 << 28) | (0x4))	@ burst policy is PLLP
+	movt	r4, #:upper16:((1 << 28) | (0x4))
 	str	r4, [r0, #CLK_RESET_CCLK_BURST]
 
 	/* Restore pad power state to normal */

Signature · 1 line

2.24.0

Dmitry Osipenko

author

2019-12-18 20:21 UTC #7 lore raw

PATCH v6 7/12 ARM: tegra: Don't enable PLLX while resuming from LP1 on Tegra30

In reply to Dmitry Osipenko

PLLX may be kept disabled if cpufreq driver selects some other clock for CPU. In that case PLLX will be disabled later in the resume path by the CLK driver, which also can enable PLLX if necessary by itself. Thus there is no need to enable PLLX early during resume. Tegra114/124 CLK drivers do not manage PLLX on resume and thus they are left untouched by this patch.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 arch/arm/mach-tegra/sleep-tegra30.S | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

arch/arm/mach-tegra/sleep-tegra30.S +10 -1

index 9a20c93abe48..4f073869b8ac 100644
@@ -358,7 +358,6 @@ _no_pll_iddq_exit:
 
 	pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
 	pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
-	pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
 
 _pll_m_c_x_done:
 	pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC

@@ -368,8 +367,18 @@ _pll_m_c_x_done:
 	pll_locked r1, r0, CLK_RESET_PLLP_BASE
 	pll_locked r1, r0, CLK_RESET_PLLA_BASE
 	pll_locked r1, r0, CLK_RESET_PLLC_BASE
+
+	/*
+	 * CPUFreq driver could select other PLL for CPU. PLLX will be
+	 * enabled by the Tegra30 CLK driver on an as-needed basis, see
+	 * tegra30_cpu_clock_resume().
+	 */
+	cmp	r10, #TEGRA30
+	beq	_pll_m_c_x_locked
+
 	pll_locked r1, r0, CLK_RESET_PLLX_BASE
 
+_pll_m_c_x_locked:
 	mov32	r7, TEGRA_TMRUS_BASE
 	ldr	r1, [r7]
 	add	r1, r1, #LOCK_DELAY

Signature · 1 line

2.24.0

Marcel Ziswiler

Tested-by on v6 7/12

2020-02-01 22:57 UTC #8 lore raw

Re: [PATCH v6 07/12] ARM: tegra: Don't enable PLLX while resuming from LP1 on Tegra30

Hi Dmitry

Finally, I came around giving this a try again on the Colibri T20 and Apalis/Colibri T30.

Overall, works like a charm and you may add the following to the entire series:

Quoted 11 lines · Dmitry Osipenko

PLLX may be kept disabled if cpufreq driver selects some other clock for
CPU. In that case PLLX will be disabled later in the resume path by the
CLK driver, which also can enable PLLX if necessary by itself. Thus there
is no need to enable PLLX early during resume. Tegra114/124 CLK drivers do
not manage PLLX on resume and thus they are left untouched by this patch.

Quoted 1 line

Signed-off-by Dmitry Osipenko <[email protected]>

Tested-by Marcel Ziswiler <[email protected]>

Tested-on: Colibri T20, Apalis/Colibri T30 on resp. EvalBoards

Quoted 26 lines

---
 arch/arm/mach-tegra/sleep-tegra30.S | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

arch/arm/mach- renamed from arch/arm/mach-tegra/sleep-tegra30.S +0 -0

tegra/sleep-tegra30.S
index 9a20c93abe48..4f073869b8ac 100644

arch/arm/mach-tegra/sleep-tegra30.S +5 -1

@@ -358,7 +358,6 @@ _no_pll_iddq_exit:
 
 	pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
 	pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
-	pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
 
 _pll_m_c_x_done:
 	pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC

@@ -368,8 +367,18 @@ _pll_m_c_x_done:
 	pll_locked r1, r0, CLK_RESET_PLLP_BASE
 	pll_locked r1, r0, CLK_RESET_PLLA_BASE
 	pll_locked r1, r0, CLK_RESET_PLLC_BASE
+
+	/*
+	 * CPUFreq driver could select other PLL for CPU. PLLX will be
+	 * enabled by the Tegra30 CLK driver on an as-needed basis, see
+	 * tegra30_cpu_clock_resume().

arch/arm/mach-tegra/sleep-tegra30.S _pll_m_c_x_done: · line 384

Quoted 10 lines

arch/arm/mach-tegra/sleep-tegra30.S +5 -0

+	 */
+	cmp	r10, #TEGRA30
+	beq	_pll_m_c_x_locked
+
 	pll_locked r1, r0, CLK_RESET_PLLX_BASE
 
+_pll_m_c_x_locked:
 	mov32	r7, TEGRA_TMRUS_BASE
 	ldr	r1, [r7]
 	add	r1, r1, #LOCK_DELAY

Unfortunately, that one does no longer apply after the following patch recently got applied on Wed Jan 8:

commit 1a3388d506bf ("ARM: tegra: Enable PLLP bypass during Tegra124 LP1")

Thanks!

Cheers

Marcel

Dmitry Osipenko

author

2020-02-02 01:08 UTC #9 lore raw

Re: [PATCH v6 07/12] ARM: tegra: Don't enable PLLX while resuming from LP1 on Tegra30

02.02.2020 01:57, Marcel Ziswiler пишет:

Quoted 20 lines

Hi Dmitry
Finally, I came around giving this a try again on the Colibri T20 and Apalis/Colibri T30.
Overall, works like a charm and you may add the following to the entire series:
Quoted 11 lines · Dmitry Osipenko
PLLX may be kept disabled if cpufreq driver selects some other clock for
CPU. In that case PLLX will be disabled later in the resume path by the
CLK driver, which also can enable PLLX if necessary by itself. Thus there
is no need to enable PLLX early during resume. Tegra114/124 CLK drivers do
not manage PLLX on resume and thus they are left untouched by this patch.

Quoted 4 lines

Quoted 1 line
Signed-off-by Dmitry Osipenko <[email protected]>
Tested-by Marcel Ziswiler <[email protected]>
Tested-on: Colibri T20, Apalis/Colibri T30 on resp. EvalBoards

Hello Marcel,

Thank you very much for the testing! Very appreciate that!

Could you please clarify whether you tried to enable the CPU DVFS by including OPPs/etc into device-tree files of the tested boards?

Quoted 40 lines

Quoted 26 lines

---
 arch/arm/mach-tegra/sleep-tegra30.S | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

arch/arm/mach- renamed from arch/arm/mach-tegra/sleep-tegra30.S +0 -0

tegra/sleep-tegra30.S
index 9a20c93abe48..4f073869b8ac 100644

arch/arm/mach-tegra/sleep-tegra30.S +5 -1

@@ -358,7 +358,6 @@ _no_pll_iddq_exit:
 
 	pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
 	pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
-	pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
 
 _pll_m_c_x_done:
 	pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC

@@ -368,8 +367,18 @@ _pll_m_c_x_done:
 	pll_locked r1, r0, CLK_RESET_PLLP_BASE
 	pll_locked r1, r0, CLK_RESET_PLLA_BASE
 	pll_locked r1, r0, CLK_RESET_PLLC_BASE
+
+	/*
+	 * CPUFreq driver could select other PLL for CPU. PLLX will be
+	 * enabled by the Tegra30 CLK driver on an as-needed basis, see
+	 * tegra30_cpu_clock_resume().

arch/arm/mach-tegra/sleep-tegra30.S _pll_m_c_x_done: · line 384

Quoted 10 lines

arch/arm/mach-tegra/sleep-tegra30.S +5 -0

+	 */
+	cmp	r10, #TEGRA30
+	beq	_pll_m_c_x_locked
+
 	pll_locked r1, r0, CLK_RESET_PLLX_BASE
 
+_pll_m_c_x_locked:
 	mov32	r7, TEGRA_TMRUS_BASE
 	ldr	r1, [r7]
 	add	r1, r1, #LOCK_DELAY

Unfortunately, that one does no longer apply after the following patch recently got applied on Wed Jan 8:

Quoted 4 lines

commit 1a3388d506bf ("ARM: tegra: Enable PLLP bypass during Tegra124 LP1")
Thanks!

Yes, I'm aware about it and going to send out the updated version of the patches soon. Meanwhile you could find recent rebase of the patches here [1].

[1] https://github.com/grate-driver/linux/commits/master

Dmitry Osipenko

author

2019-12-18 20:21 UTC #10 lore raw

PATCH v6 8/12 dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30

In reply to Dmitry Osipenko

Add device-tree binding that describes CPU frequency-scaling hardware found on NVIDIA Tegra20/30 SoCs.

Acked-by Viresh Kumar <[email protected]>

Reviewed-by Rob Herring <[email protected]>

Signed-off-by Dmitry Osipenko <[email protected]>

---
 .../cpufreq/nvidia,tegra20-cpufreq.txt        | 56 +++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt

Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt new file +56 -0

new file mode 100644
index 000000000000..daeca6ae6b76
@@ -0,0 +1,56 @@
+Binding for NVIDIA Tegra20 CPUFreq
+==================================
+
+Required properties:
+- clocks: Must contain an entry for the CPU clock.
+  See ../clocks/clock-bindings.txt for details.
+- operating-points-v2: See ../bindings/opp/opp.txt for details.
+- #cooling-cells: Should be 2. See ../thermal/thermal.txt for details.
+
+For each opp entry in 'operating-points-v2' table:
+- opp-supported-hw: Two bitfields indicating:
+	On Tegra20:
+	1. CPU process ID mask
+	2. SoC speedo ID mask
+
+	On Tegra30:
+	1. CPU process ID mask
+	2. CPU speedo ID mask
+
+	A bitwise AND is performed against these values and if any bit
+	matches, the OPP gets enabled.
+
+- opp-microvolt: CPU voltage triplet.
+
+Optional properties:
+- cpu-supply: Phandle to the CPU power supply.
+
+Example:
+	regulators {
+		cpu_reg: regulator0 {
+			regulator-name = "vdd_cpu";
+		};
+	};
+
+	cpu0_opp_table: opp_table0 {
+		compatible = "operating-points-v2";
+
+		opp@456000000 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <825000 825000 1125000>;
+			opp-supported-hw = <0x03 0x0001>;
+			opp-hz = /bits/ 64 <456000000>;
+		};
+
+		...
+	};
+
+	cpus {
+		cpu@0 {
+			compatible = "arm,cortex-a9";
+			clocks = <&tegra_car TEGRA20_CLK_CCLK>;
+			operating-points-v2 = <&cpu0_opp_table>;
+			cpu-supply = <&cpu_reg>;
+			#cooling-cells = <2>;
+		};
+	};

Signature · 1 line

2.24.0

Dmitry Osipenko

author

2019-12-18 20:21 UTC #11 lore raw

PATCH v6 9/12 cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now)

In reply to Dmitry Osipenko

Re-parenting to intermediate clock is supported now by the clock driver and thus there is no need in a customized CPUFreq driver, all that code is common for both Tegra20 and Tegra30. The available CPU freqs are now specified in device-tree in a form of OPPs, all users should update their device-trees.

Acked-by Viresh Kumar <[email protected]>

Signed-off-by Dmitry Osipenko <[email protected]>

---
 drivers/cpufreq/Kconfig.arm       |   6 +-
 drivers/cpufreq/tegra20-cpufreq.c | 217 ++++++++----------------------
 2 files changed, 59 insertions(+), 164 deletions(-)

drivers/cpufreq/Kconfig.arm +3 -3

index 3858d86cf409..92a6a5089979 100644
@@ -295,11 +295,11 @@ config ARM_TANGO_CPUFREQ
 	default y
 
 config ARM_TEGRA20_CPUFREQ
-	tristate "Tegra20 CPUFreq support"
-	depends on ARCH_TEGRA
+	tristate "Tegra20/30 CPUFreq support"
+	depends on ARCH_TEGRA && CPUFREQ_DT
 	default y
 	help
-	  This adds the CPUFreq driver support for Tegra20 SOCs.
+	  This adds the CPUFreq driver support for Tegra20/30 SOCs.
 
 config ARM_TEGRA124_CPUFREQ
 	bool "Tegra124 CPUFreq support"

drivers/cpufreq/tegra20-cpufreq.c +56 ~~-161~~

257 lines not on this page · raw message

Signature · 1 line

2.24.0

Dmitry Osipenko

author

2019-12-18 20:21 UTC #12 lore raw

PATCH v6 10/12 ARM: tegra: Create tegra20-cpufreq platform device on Tegra30

In reply to Dmitry Osipenko

The tegra20-cpufreq now instantiates cpufreq-dt and Tegra30 is fully supported by that driver.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 arch/arm/mach-tegra/tegra.c | 4 ++++
 1 file changed, 4 insertions(+)

arch/arm/mach-tegra/tegra.c +4 -0

index e512e606eabd..1e3b85923ca3 100644
@@ -95,6 +95,10 @@ static void __init tegra_dt_init_late(void)
 	if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
 	    of_machine_is_compatible("nvidia,tegra20"))
 		platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0);
+
+	if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) &&
+	    of_machine_is_compatible("nvidia,tegra30"))
+		platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0);
 }
 
 static const char * const tegra_dt_board_compat[] = {

Signature · 1 line

2.24.0

Dmitry Osipenko

author

2019-12-18 20:21 UTC #13 lore raw

PATCH v6 11/12 ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS

In reply to Dmitry Osipenko

Set min/max voltage and couple CPU/CORE regulators.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 arch/arm/boot/dts/tegra30-beaver.dts | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

arch/arm/boot/dts/tegra30-beaver.dts +13 -3

index a3b0f3555cd2..6ebb3105af9e 100644
@@ -1806,9 +1806,14 @@ vdd2_reg: vdd2 {
 
 				vddctrl_reg: vddctrl {
 					regulator-name = "vdd_cpu,vdd_sys";
-					regulator-min-microvolt = <1000000>;
-					regulator-max-microvolt = <1000000>;
+					regulator-min-microvolt = <800000>;
+					regulator-max-microvolt = <1250000>;
+					regulator-coupled-with = <&core_vdd_reg>;
+					regulator-coupled-max-spread = <300000>;
+					regulator-max-step-microvolt = <100000>;
 					regulator-always-on;
+
+					nvidia,tegra-cpu-regulator;
 				};
 
 				vio_reg: vio {

@@ -1868,17 +1873,22 @@ ldo8_reg: ldo8 {
 			};
 		};
 
-		tps62361@60 {
+		core_vdd_reg: tps62361@60 {
 			compatible = "ti,tps62361";
 			reg = <0x60>;
 
 			regulator-name = "tps62361-vout";
 			regulator-min-microvolt = <500000>;
 			regulator-max-microvolt = <1500000>;
+			regulator-coupled-with = <&vddctrl_reg>;
+			regulator-coupled-max-spread = <300000>;
+			regulator-max-step-microvolt = <100000>;
 			regulator-boot-on;
 			regulator-always-on;
 			ti,vsel0-state-high;
 			ti,vsel1-state-high;
+
+			nvidia,tegra-core-regulator;
 		};
 	};

Signature · 1 line

2.24.0

Dmitry Osipenko

author

2019-12-18 20:21 UTC #14 lore raw

PATCH v6 12/12 ARM: dts: tegra30: beaver: Add CPU Operating Performance Points

In reply to Dmitry Osipenko

Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on beaver.

Signed-off-by Dmitry Osipenko <[email protected]>

---
 arch/arm/boot/dts/tegra30-beaver.dts | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

arch/arm/boot/dts/tegra30-beaver.dts +24 -0

index 6ebb3105af9e..86556622be25 100644
@@ -2,6 +2,8 @@
 /dts-v1/;
 
 #include "tegra30.dtsi"
+#include "tegra30-cpu-opp.dtsi"
+#include "tegra30-cpu-opp-microvolt.dtsi"
 
 / {
 	model = "NVIDIA Tegra30 Beaver evaluation board";

@@ -2124,4 +2126,26 @@ sound {
 			 <&tegra_car TEGRA30_CLK_EXTERN1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
+
+	cpus {
+		cpu0: cpu@0 {
+			cpu-supply = <&vddctrl_reg>;
+			operating-points-v2 = <&cpu0_opp_table>;
+		};
+
+		cpu@1 {
+			cpu-supply = <&vddctrl_reg>;
+			operating-points-v2 = <&cpu0_opp_table>;
+		};
+
+		cpu@2 {
+			cpu-supply = <&vddctrl_reg>;
+			operating-points-v2 = <&cpu0_opp_table>;
+		};
+
+		cpu@3 {
+			cpu-supply = <&vddctrl_reg>;
+			operating-points-v2 = <&cpu0_opp_table>;
+		};
+	};
 };

Signature · 1 line

2.24.0

Dmitry Osipenko

author

2020-01-07 23:17 UTC #15 lore raw

In reply to Dmitry Osipenko

18.12.2019 23:21, Dmitry Osipenko пишет:

Quoted 77 lines

Hello,
This series moves intermediate-clk handling from tegra20-cpufreq into tegra-clk driver. This allows us to switch to generic cpufreq-dt driver which brings voltage scaling, per-hardware OPPs and Tegra30 support out of the box. All boards need to adopt CPU OPPs in their device-trees in order to get cpufreq support.
Changelog:
v6: - Dropped "cpufreq: dt-platdev: Blacklist NVIDIA Tegra20 and Tegra30 SoCs"
patch from the series since Viresh picked up that patch separately.
- Added two new patches to this series:
ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30/114/124
ARM: tegra: Don't enable PLLX while resuming from LP1 on Tegra30
Previously these patches were sent out separately from this series, but it should be more consistent to include them into the series since they directly relate to enabling of the cpufreq driver on Tegra30.
v5: - The "Use generic cpufreq-dt driver (Tegra30 supported now)" patch
is separated now into two patches by factoring out the blacklisting of cpufreq-dt-platdev into a standalone patch. This is done in a response to request from Jon Hunter to fix the warning splats during boot that are coming from OPP core because OPPs are unavailable. The OPPs will become available once tegra20-cpufreq driver will be updated to support the cpufreq-dt.
v4: - Updated CCLK diagram in the "Add custom CCLK implementation" patch.
- <linux/cpu.h> is now included in the "Use generic cpufreq-dt driver" patch, for consistency.
- Returned value of get_cpu_device() is now checked in the "Use generic cpufreq-dt driver" patch, for consistency as well.
v3: - The "Add custom CCLK implementation" patch was updated in accordance
to the comments from Peter De Schrijver. We will not use the clock skipper.
- Re added OPPs for T30 Beaver board because Thierry has that board ;)
- Added r-b for the "DT binding" patch from Rob Herring.
v2: - Kept modularity of the tegra20-cpufreq as was requested by Viresh Kumar
in a review comment to v1.
- Added acks from Viresh Kumar.
- Added tested-by from Nicolas Chauvet to the "trimslice" patch. Nicolas told me on IRC that it works fine.
- Fixed compilation of the "Add custom CCLK implementation" patch. The error happened because v1 was based on top of yet unreviewed/unapplied patch "clk: tegra: divider: Support enable-bit for Super clocks". Thanks to Peter Geis for reporting the problem.
- Replaced Tegra30 "beaver" board with "cardhu-a04" because turned out that's what NVIDIA uses in the testing farm.
Dmitry Osipenko (12):
clk: tegra: Add custom CCLK implementation
clk: tegra: pll: Add pre/post rate-change hooks
clk: tegra: cclk: Add helpers for handling PLLX rate changes
clk: tegra20: Use custom CCLK implementation
clk: tegra30: Use custom CCLK implementation
ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30/114/124
ARM: tegra: Don't enable PLLX while resuming from LP1 on Tegra30
dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30
cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported
now)
ARM: tegra: Create tegra20-cpufreq platform device on Tegra30
ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS
ARM: dts: tegra30: beaver: Add CPU Operating Performance Points

Quoted 16 lines

 .../cpufreq/nvidia,tegra20-cpufreq.txt        |  56 +++++
 arch/arm/boot/dts/tegra30-beaver.dts          |  40 +++-
 arch/arm/mach-tegra/sleep-tegra30.S           |  18 +-
 arch/arm/mach-tegra/tegra.c                   |   4 +
 drivers/clk/tegra/Makefile                    |   1 +
 drivers/clk/tegra/clk-pll.c                   |  12 +-
 drivers/clk/tegra/clk-tegra-super-cclk.c      | 212 +++++++++++++++++
 drivers/clk/tegra/clk-tegra20.c               |   7 +-
 drivers/clk/tegra/clk-tegra30.c               |   6 +-
 drivers/clk/tegra/clk.h                       |  19 +-
 drivers/cpufreq/Kconfig.arm                   |   6 +-
 drivers/cpufreq/tegra20-cpufreq.c             | 217 +++++-------------
 12 files changed, 418 insertions(+), 180 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt
 create mode 100644 drivers/clk/tegra/clk-tegra-super-cclk.c

Hello Peter,

Could you please take a look at the patches and ACK them if they are okay to you?

Peter De Schrijver

Acked-by on the v6 series

2020-01-14 15:53 UTC #16 lore raw

In reply to Dmitry Osipenko

Acked-by Peter De Schrijver <[email protected]>

Quoted 99 lines · Dmitry Osipenko

External email: Use caution opening links or attachments
Hello,
This series moves intermediate-clk handling from tegra20-cpufreq into tegra-clk driver. This allows us to switch to generic cpufreq-dt driver which brings voltage scaling, per-hardware OPPs and Tegra30 support out of the box. All boards need to adopt CPU OPPs in their device-trees in order to get cpufreq support.
Changelog:
v6: - Dropped "cpufreq: dt-platdev: Blacklist NVIDIA Tegra20 and Tegra30 SoCs"
patch from the series since Viresh picked up that patch separately.
- Added two new patches to this series:
ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30/114/124
ARM: tegra: Don't enable PLLX while resuming from LP1 on Tegra30
Previously these patches were sent out separately from this series, but it should be more consistent to include them into the series since they directly relate to enabling of the cpufreq driver on Tegra30.
v5: - The "Use generic cpufreq-dt driver (Tegra30 supported now)" patch
is separated now into two patches by factoring out the blacklisting of cpufreq-dt-platdev into a standalone patch. This is done in a response to request from Jon Hunter to fix the warning splats during boot that are coming from OPP core because OPPs are unavailable. The OPPs will become available once tegra20-cpufreq driver will be updated to support the cpufreq-dt.
v4: - Updated CCLK diagram in the "Add custom CCLK implementation" patch.
- <linux/cpu.h> is now included in the "Use generic cpufreq-dt driver" patch, for consistency.
- Returned value of get_cpu_device() is now checked in the "Use generic cpufreq-dt driver" patch, for consistency as well.
v3: - The "Add custom CCLK implementation" patch was updated in accordance
to the comments from Peter De Schrijver. We will not use the clock skipper.
- Re added OPPs for T30 Beaver board because Thierry has that board ;)
- Added r-b for the "DT binding" patch from Rob Herring.
v2: - Kept modularity of the tegra20-cpufreq as was requested by Viresh Kumar
in a review comment to v1.
- Added acks from Viresh Kumar.
- Added tested-by from Nicolas Chauvet to the "trimslice" patch. Nicolas told me on IRC that it works fine.
- Fixed compilation of the "Add custom CCLK implementation" patch. The error happened because v1 was based on top of yet unreviewed/unapplied patch "clk: tegra: divider: Support enable-bit for Super clocks". Thanks to Peter Geis for reporting the problem.
- Replaced Tegra30 "beaver" board with "cardhu-a04" because turned out that's what NVIDIA uses in the testing farm.
Dmitry Osipenko (12):
clk: tegra: Add custom CCLK implementation
clk: tegra: pll: Add pre/post rate-change hooks
clk: tegra: cclk: Add helpers for handling PLLX rate changes
clk: tegra20: Use custom CCLK implementation
clk: tegra30: Use custom CCLK implementation
ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30/114/124
ARM: tegra: Don't enable PLLX while resuming from LP1 on Tegra30
dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30
cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported
now)
ARM: tegra: Create tegra20-cpufreq platform device on Tegra30
ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS
ARM: dts: tegra30: beaver: Add CPU Operating Performance Points
 .../cpufreq/nvidia,tegra20-cpufreq.txt        |  56 +++++
 arch/arm/boot/dts/tegra30-beaver.dts          |  40 +++-
 arch/arm/mach-tegra/sleep-tegra30.S           |  18 +-
 arch/arm/mach-tegra/tegra.c                   |   4 +
 drivers/clk/tegra/Makefile                    |   1 +
 drivers/clk/tegra/clk-pll.c                   |  12 +-
 drivers/clk/tegra/clk-tegra-super-cclk.c      | 212 +++++++++++++++++
 drivers/clk/tegra/clk-tegra20.c               |   7 +-
 drivers/clk/tegra/clk-tegra30.c               |   6 +-
 drivers/clk/tegra/clk.h                       |  19 +-
 drivers/cpufreq/Kconfig.arm                   |   6 +-
 drivers/cpufreq/tegra20-cpufreq.c             | 217 +++++-------------
 12 files changed, 418 insertions(+), 180 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt
 create mode 100644 drivers/clk/tegra/clk-tegra-super-cclk.c
--
2.24.0

Dmitry Osipenko

author

2020-01-14 20:36 UTC #17 lore raw

14.01.2020 18:53, Peter De Schrijver пишет:

Quoted 1 line

Acked-by Peter De Schrijver <[email protected]>

Thanks! Should help to get these patches into 5.7 :)