Split SDM845 interconnect nodes and consolidate RPMh support
v2 cover Split SDM845 interconnect nodes and consolidate RPMh support
While there are no current consumers of the SDM845 interconnect device in devicetree, take this opportunity to redefine the interconnect device nodes as the previous definitions of using a single child node under the apps_rsc device did not accurately capture the description of the hardware. The Network-On-Chip (NoC) interconnect devices should be represented in a manner akin to QCS404 platforms[1] where there is a separation of NoC devices and its RPM/RPMh counterparts.
The bcm-voter devices are representing the RPMh devices that the interconnect providers need to communicate with and there can be more than one instance of the Bus Clock Manager (BCM) which can live under different instances of Resource State Coordinators (RSC). There are display use cases where consumers may need to target a different bcm-voter (Some display specific RSC) than the default, and there needs to be a way to represent this connection in devicetree.
This patches series extends the discussions[2][3] involving the SDM845 interconnect bindings by adding accompanying driver implementations using the split NoC devices. Some of the code used to support the SDM845 provider driver are refactored into common modules that can used by other RPMh based interconnect providers such as SC7180[4]. This patch series also updates existing sdm845 binding documentation to DT schema format using json-schema.
v2:
- Reorganized dt-binding patches
- Fixed a bug that adds duplicate BCM node to voter (Georgi)
- Addressed misc. comments (Georgi)
v1: https://lkml.org/lkml/2019/12/16/15
[1]: https://lkml.org/lkml/2019/6/13/143
[2]: https://lkml.org/lkml/2019/7/19/1063
[3]: https://lkml.org/lkml/2019/10/16/1793
[4]: https://lkml.org/lkml/2019/11/26/389
David Dai (6):
dt-bindings: interconnect: Convert qcom,sdm845 to DT schema
dt-bindings: interconnect: Add YAML schemas for QCOM bcm-voter
dt-bindings: interconnect: Update Qualcomm SDM845 DT bindings
interconnect: qcom: Consolidate interconnect RPMh support
interconnect: qcom: sdm845: Split qnodes into their respective NoCs
arm64: dts: sdm845: Redefine interconnect provider DT nodes
.../bindings/interconnect/qcom,bcm-voter.yaml | 45 + .../bindings/interconnect/qcom,sdm845.txt | 24 - .../bindings/interconnect/qcom,sdm845.yaml | 74 ++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 61 +- drivers/interconnect/qcom/Kconfig | 8 + drivers/interconnect/qcom/Makefile | 4 + drivers/interconnect/qcom/bcm-voter.c | 363 +++++++ drivers/interconnect/qcom/bcm-voter.h | 28 + drivers/interconnect/qcom/icc-rpmh.c | 158 +++ drivers/interconnect/qcom/icc-rpmh.h | 151 +++ drivers/interconnect/qcom/sdm845.c | 1132 ++++++++------------ include/dt-bindings/interconnect/qcom,sdm845.h | 263 ++--- 12 files changed, 1498 insertions(+), 813 deletions(-) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml delete mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sdm845.txt create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml create mode 100644 drivers/interconnect/qcom/bcm-voter.c create mode 100644 drivers/interconnect/qcom/bcm-voter.h create mode 100644 drivers/interconnect/qcom/icc-rpmh.c create mode 100644 drivers/interconnect/qcom/icc-rpmh.h
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v2 1/6 dt-bindings: interconnect: Convert qcom,sdm845 to DT schema
Convert the qcom,sdm845 interconnect provider binding to DT schema.
Signed-off-by David Dai <[email protected]>
--- .../bindings/interconnect/qcom,sdm845.txt | 24 ------------ .../bindings/interconnect/qcom,sdm845.yaml | 43 ++++++++++++++++++++++ 2 files changed, 43 insertions(+), 24 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sdm845.txt create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml
Documentation/devicetree/bindings/interconnect/qcom,sdm845.txt deleted +0 -24
@@ -1,24 +0,0 @@ -Qualcomm SDM845 Network-On-Chip interconnect driver binding ------------------------------------------------------------ - -SDM845 interconnect providers support system bandwidth requirements through -RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is -able to communicate with the BCM through the Resource State Coordinator (RSC) -associated with each execution environment. Provider nodes must reside within -an RPMh device node pertaining to their RSC and each provider maps to a single -RPMh resource. - -Required properties : -- compatible : shall contain only one of the following: - "qcom,sdm845-rsc-hlos" -- #interconnect-cells : should contain 1 - -Examples: - -apps_rsc: rsc { - rsc_hlos: interconnect { - compatible = "qcom,sdm845-rsc-hlos"; - #interconnect-cells = <1>; - }; -}; -
Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml new file +43 -0
43 lines not on this page · raw message
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH v2 1/6] dt-bindings: interconnect: Convert qcom,sdm845 to DT schema
Quoted 10 lines · David Dai
Convert the qcom,sdm845 interconnect provider binding to DT schema.
Signed-off-by David Dai <[email protected]>--- .../bindings/interconnect/qcom,sdm845.txt | 24 ------------ .../bindings/interconnect/qcom,sdm845.yaml | 43 ++++++++++++++++++++++ 2 files changed, 43 insertions(+), 24 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sdm845.txt create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml
Reviewed-by Rob Herring <[email protected]>
PATCH v2 2/6 dt-bindings: interconnect: Add YAML schemas for QCOM bcm-voter
In reply to David DaiAdd YAML schemas for interconnect bcm-voters found on QCOM RPMh-based SoCs.
Signed-off-by David Dai <[email protected]>
--- .../bindings/interconnect/qcom,bcm-voter.yaml | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml
Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml new file +45 -0
@@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,bcm-voter.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm BCM-Voter Interconnect + +maintainers: + - David Dai <[email protected]> + +description: | + The Bus Clock Manager (BCM) is a dedicated hardware accelerator + that manages shared system resources by aggregating requests + from multiple Resource State Coordinators (RSC). Interconnect + providers are able to vote for aggregated thresholds values from + consumers by communicating through their respective RSCs. + +properties: + compatible: + enum: + - qcom,sdm845-bcm-voter + +required: + - compatible + +additionalProperties: false + +examples: + - | + apps_rsc: interconnect@179c0000 { + compatible = "qcom,rpmh-rsc"; + + apps_bcm_voter: bcm_voter { + compatible = "qcom,sdm845-bcm-voter"; + }; + }; + + disp_rsc: interconnect@179d0000 { + compatible = "qcom,rpmh-rsc"; + + disp_bcm_voter: bcm_voter { + compatible = "qcom,sdm845-bcm-voter"; + }; + };
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Rob Herring
maintainerRe: [PATCH v2 2/6] dt-bindings: interconnect: Add YAML schemas for QCOM bcm-voter
Quoted 17 lines · David Dai
Add YAML schemas for interconnect bcm-voters found on QCOM RPMh-based SoCs.
Signed-off-by David Dai <[email protected]>--- .../bindings/interconnect/qcom,bcm-voter.yaml | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yamlDocumentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml new file +2
-0@@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2
Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml line 12
Quoted 10 lines
Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml new file +10
-0+--- +$id: http://devicetree.org/schemas/interconnect/qcom,bcm-voter.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm BCM-Voter Interconnect + +maintainers: + - David Dai <[email protected]> + +description: |
Don't need '|' unless you need formatting preserved.
Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml line 17
Quoted 5 lines
Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml new file +5
-0+ The Bus Clock Manager (BCM) is a dedicated hardware accelerator + that manages shared system resources by aggregating requests + from multiple Resource State Coordinators (RSC). Interconnect + providers are able to vote for aggregated thresholds values from + consumers by communicating through their respective RSCs.
Indent should be 2 spaces.
Quoted 4 lines
Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml new file +4
-0+ +properties: + compatible: + enum:
Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml line 31
Quoted 10 lines
Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml new file +10
-0+ - qcom,sdm845-bcm-voter + +required: + - compatible + +additionalProperties: false + +examples: + - | + apps_rsc: interconnect@179c0000 {
Unit-address should also have 'reg' property.
Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml line 32
Quoted 1 line
Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml new file +1
-0+ compatible = "qcom,rpmh-rsc";
Note that once this has a schema, it will be checked, so make sure it's complete.
Quoted 17 lines
Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml new file +13
-0+ + apps_bcm_voter: bcm_voter { + compatible = "qcom,sdm845-bcm-voter"; + }; + }; + + disp_rsc: interconnect@179d0000 { + compatible = "qcom,rpmh-rsc"; + + disp_bcm_voter: bcm_voter { + compatible = "qcom,sdm845-bcm-voter"; + }; + };Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v2 3/6 dt-bindings: interconnect: Update Qualcomm SDM845 DT bindings
In reply to David DaiRedefine the Network-on-Chip devices to more accurately describe the interconnect topology on Qualcomm's SDM845 platform. Each interconnect device can communicate with different instances of the RPMh hardware which are described as RSCs(Resource State Coordinators).
Signed-off-by David Dai <[email protected]>
--- .../bindings/interconnect/qcom,sdm845.yaml | 49 ++++++++++++++++++---- 1 file changed, 40 insertions(+), 9 deletions(-)
Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml +40 -9
@@ -13,21 +13,44 @@ description: | SDM845 interconnect providers support system bandwidth requirements through RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is able to communicate with the BCM through the Resource State Coordinator (RSC) - associated with each execution environment. Provider nodes must reside within - an RPMh device node pertaining to their RSC and each provider maps to a - single RPMh resource. + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. properties: + reg: + maxItems: 1 + compatible: enum: - - qcom,sdm845-rsc-hlos + - qcom,sdm845-aggre1-noc + - qcom,sdm845-aggre2-noc + - qcom,sdm845-config-noc + - qcom,sdm845-dc-noc + - qcom,sdm845-gladiator-noc + - qcom,sdm845-mem-noc + - qcom,sdm845-mmss-noc + - qcom,sdm845-system-noc '#interconnect-cells': const: 1 + qcom,bcm-voter-names: + items: + - const: apps + - const: disp + + qcom,bcm-voters: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + List of phandles to qcom,bcm-voter nodes that are required by + this interconnect to send RPMh commands. + required: - compatible + - reg - '#interconnect-cells' + - qcom,bcm-voters additionalProperties: false
@@ -35,9 +58,17 @@ examples: - | #include <dt-bindings/interconnect/qcom,sdm845.h> - apps_rsc: rsc { - rsc_hlos: interconnect { - compatible = "qcom,sdm845-rsc-hlos"; - #interconnect-cells = <1>; - }; + mem_noc: interconnect@1380000 { + compatible = "qcom,sdm845-mem-noc"; + reg = <0 0x01380000 0 0x27200>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,sdm845-mmss-noc"; + reg = <0 0x01740000 0 0x1c1000>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "apps", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; };
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Rob Herring
maintainerRe: [PATCH v2 3/6] dt-bindings: interconnect: Update Qualcomm SDM845 DT bindings
Quoted 38 lines · David Dai
Redefine the Network-on-Chip devices to more accurately describe the interconnect topology on Qualcomm's SDM845 platform. Each interconnect device can communicate with different instances of the RPMh hardware which are described as RSCs(Resource State Coordinators).
Signed-off-by David Dai <[email protected]>--- .../bindings/interconnect/qcom,sdm845.yaml | 49 ++++++++++++++++++---- 1 file changed, 40 insertions(+), 9 deletions(-)Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml +12
-4@@ -13,21 +13,44 @@ description: | SDM845 interconnect providers support system bandwidth requirements through RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is able to communicate with the BCM through the Resource State Coordinator (RSC) - associated with each execution environment. Provider nodes must reside within - an RPMh device node pertaining to their RSC and each provider maps to a - single RPMh resource. + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. properties: + reg: + maxItems: 1 + compatible: enum: - - qcom,sdm845-rsc-hlos + - qcom,sdm845-aggre1-noc + - qcom,sdm845-aggre2-noc + - qcom,sdm845-config-noc + - qcom,sdm845-dc-noc + - qcom,sdm845-gladiator-noc + - qcom,sdm845-mem-noc
Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml description: | · line 41
Quoted 10 lines
Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml +6
-0+ - qcom,sdm845-mmss-noc + - qcom,sdm845-system-noc '#interconnect-cells': const: 1 + qcom,bcm-voter-names: + items: + - const: apps + - const: disp
If these are always the names, why do you need them?
Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml description: | · line 47
Quoted 6 lines
Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml +6
-0+ + qcom,bcm-voters: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + List of phandles to qcom,bcm-voter nodes that are required by + this interconnect to send RPMh commands.
Is the max length 2?
Quoted 36 lines
Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml +16
-5+ required: - compatible + - reg - '#interconnect-cells' + - qcom,bcm-voters additionalProperties: false@@ -35,9 +58,17 @@ examples: - | #include <dt-bindings/interconnect/qcom,sdm845.h> - apps_rsc: rsc { - rsc_hlos: interconnect { - compatible = "qcom,sdm845-rsc-hlos"; - #interconnect-cells = <1>; - }; + mem_noc: interconnect@1380000 { + compatible = "qcom,sdm845-mem-noc"; + reg = <0 0x01380000 0 0x27200>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,sdm845-mmss-noc"; + reg = <0 0x01740000 0 0x1c1000>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "apps", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; };Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH v2 3/6] dt-bindings: interconnect: Update Qualcomm SDM845 DT bindings
Quoted 42 lines · Rob Herring
Quoted 41 lines · David Dai
Redefine the Network-on-Chip devices to more accurately describe the interconnect topology on Qualcomm's SDM845 platform. Each interconnect device can communicate with different instances of the RPMh hardware which are described as RSCs(Resource State Coordinators).
Signed-off-by David Dai <[email protected]>--- .../bindings/interconnect/qcom,sdm845.yaml | 49 ++++++++++++++++++---- 1 file changed, 40 insertions(+), 9 deletions(-)Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml +14
-4@@ -13,21 +13,44 @@ description: | SDM845 interconnect providers support system bandwidth requirements through RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is able to communicate with the BCM through the Resource State Coordinator (RSC) - associated with each execution environment. Provider nodes must reside within - an RPMh device node pertaining to their RSC and each provider maps to a - single RPMh resource. + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. properties: + reg: + maxItems: 1 + compatible: enum: - - qcom,sdm845-rsc-hlos + - qcom,sdm845-aggre1-noc + - qcom,sdm845-aggre2-noc + - qcom,sdm845-config-noc + - qcom,sdm845-dc-noc + - qcom,sdm845-gladiator-noc + - qcom,sdm845-mem-noc + - qcom,sdm845-mmss-noc + - qcom,sdm845-system-noc
Quoted 8 lines
Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml description: | · line 41
Quoted 7 lines
Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml +4
-0'#interconnect-cells': const: 1 + qcom,bcm-voter-names: + items: + - const: apps + - const: dispIf these are always the names, why do you need them?
Disp and apps bcm voters are the only ones supported for sdm845, but the number of voters and voter names may be different for other non-sdm845 based boards.
Quoted 7 lines
Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml description: | · line 47
Quoted 6 lines
Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml +6
-0+ + qcom,bcm-voters: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + List of phandles to qcom,bcm-voter nodes that are required by + this interconnect to send RPMh commands.Is the max length 2?
For sdm845, yes.
Quoted 36 lines
Quoted 36 lines
Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml +16
-5+ required: - compatible + - reg - '#interconnect-cells' + - qcom,bcm-voters additionalProperties: false@@ -35,9 +58,17 @@ examples: - | #include <dt-bindings/interconnect/qcom,sdm845.h> - apps_rsc: rsc { - rsc_hlos: interconnect { - compatible = "qcom,sdm845-rsc-hlos"; - #interconnect-cells = <1>; - }; + mem_noc: interconnect@1380000 { + compatible = "qcom,sdm845-mem-noc"; + reg = <0 0x01380000 0 0x27200>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,sdm845-mmss-noc"; + reg = <0 0x01740000 0 0x1c1000>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "apps", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; };Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH v2 3/6] dt-bindings: interconnect: Update Qualcomm SDM845 DT bindings
In reply to David DaiQuoted 11 lines · David Dai
Redefine the Network-on-Chip devices to more accurately describe the interconnect topology on Qualcomm's SDM845 platform. Each interconnect device can communicate with different instances of the RPMh hardware which are described as RSCs(Resource State Coordinators).
Signed-off-by David Dai <[email protected]>--- .../bindings/interconnect/qcom,sdm845.yaml | 49 ++++++++++++++++++---- 1 file changed, 40 insertions(+), 9 deletions(-)
This patch doesn't seem to apply cleanly on top of patch 1 because of whitespace context differences.
I'll use this as an opportunity to plug the "patman" tool, which lives (weirdly) in the u-boot repository, but is an excellent way to manage and spin upstream submissions.
-Evan
PATCH v2 4/6 interconnect: qcom: Consolidate interconnect RPMh support
In reply to David DaiAdd bcm voter driver and add support for RPMh specific interconnect providers which implements the set and aggregate functionalities that translates bandwidth requests into RPMh messages. These modules provide a common set of functionalities for all Qualcomm RPMh based interconnect providers and should help reduce code duplication when adding new providers.
Signed-off-by David Dai <[email protected]>
--- drivers/interconnect/qcom/Kconfig | 8 + drivers/interconnect/qcom/Makefile | 4 + drivers/interconnect/qcom/bcm-voter.c | 363 ++++++++++++++++++++++++++++++++++ drivers/interconnect/qcom/bcm-voter.h | 28 +++ drivers/interconnect/qcom/icc-rpmh.c | 158 +++++++++++++++ drivers/interconnect/qcom/icc-rpmh.h | 151 ++++++++++++++ 6 files changed, 712 insertions(+) create mode 100644 drivers/interconnect/qcom/bcm-voter.c create mode 100644 drivers/interconnect/qcom/bcm-voter.h create mode 100644 drivers/interconnect/qcom/icc-rpmh.c create mode 100644 drivers/interconnect/qcom/icc-rpmh.h
drivers/interconnect/qcom/Kconfig +8 -0
@@ -5,6 +5,9 @@ config INTERCONNECT_QCOM help Support for Qualcomm's Network-on-Chip interconnect hardware. +config INTERCONNECT_QCOM_BCM_VOTER + tristate + config INTERCONNECT_QCOM_MSM8974 tristate "Qualcomm MSM8974 interconnect driver" depends on INTERCONNECT_QCOM
@@ -23,10 +26,15 @@ config INTERCONNECT_QCOM_QCS404 This is a driver for the Qualcomm Network-on-Chip on qcs404-based platforms. +config INTERCONNECT_QCOM_RPMH + tristate + config INTERCONNECT_QCOM_SDM845 tristate "Qualcomm SDM845 interconnect driver" depends on INTERCONNECT_QCOM depends on (QCOM_RPMH && QCOM_COMMAND_DB && OF) || COMPILE_TEST + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER help This is a driver for the Qualcomm Network-on-Chip on sdm845-based platforms.
drivers/interconnect/qcom/Makefile +4 -0
@@ -4,8 +4,12 @@ qnoc-msm8974-objs := msm8974.o qnoc-qcs404-objs := qcs404.o qnoc-sdm845-objs := sdm845.o icc-smd-rpm-objs := smd-rpm.o +icc-bcm-voter-objs := bcm-voter.o +icc-rpmh-obj := icc-rpmh.o +obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8974) += qnoc-msm8974.o obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o +obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o
drivers/interconnect/qcom/bcm-voter.c new file +363 -0
363 lines not on this page · raw message
drivers/interconnect/qcom/bcm-voter.h new file +28 -0
@@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright (c) 2019, The Linux Foundation. All rights reserved. +* +*/ + +#ifndef __DRIVERS_INTERCONNECT_QCOM_BCM_VOTER_H__ +#define __DRIVERS_INTERCONNECT_QCOM_BCM_VOTER_H__ + +#include <soc/qcom/cmd-db.h> +#include <soc/qcom/rpmh.h> +#include <soc/qcom/tcs.h> + +#include "icc-rpmh.h" + +#define DEFINE_QBCM (_name, _bcmname, _keepalive, _numnodes, ...) \ + static struct qcom_icc_bcm _name = { \ + .name = _bcmname, \ + .keepalive = _keepalive, \ + .num_nodes = _numnodes, \ + .nodes = { __VA_ARGS__ }, \ + } + +struct bcm_voter *of_bcm_voter_get (struct device *dev,const char *name); +void qcom_icc_bcm_voter_add (struct bcm_voter *voter,struct qcom_icc_bcm *bcm); +int qcom_icc_bcm_voter_commit (struct bcm_voter *voter); + +#endif
drivers/interconnect/qcom/icc-rpmh.c new file +158 -0
158 lines not on this page · raw message
drivers/interconnect/qcom/icc-rpmh.h new file +151 -0
151 lines not on this page · raw message
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH v2 4/6] interconnect: qcom: Consolidate interconnect RPMh support
Quoted 8 lines · David Dai
Add bcm voter driver and add support for RPMh specific interconnect providers which implements the set and aggregate functionalities that translates bandwidth requests into RPMh messages. These modules provide a common set of functionalities for all Qualcomm RPMh based interconnect providers and should help reduce code duplication when adding new providers.
Signed-off-by David Dai <[email protected]>
This was a little tough to wrap my head around, but then I understood that most of it was a copy of functions from sdm845.c, which are later deleted in patch 5 when sdm845.c uses the bcm-voter driver.
Quoted 75 lines
--- drivers/interconnect/qcom/Kconfig | 8 + drivers/interconnect/qcom/Makefile | 4 + drivers/interconnect/qcom/bcm-voter.c | 363 ++++++++++++++++++++++++++++++++++ drivers/interconnect/qcom/bcm-voter.h | 28 +++ drivers/interconnect/qcom/icc-rpmh.c | 158 +++++++++++++++ drivers/interconnect/qcom/icc-rpmh.h | 151 ++++++++++++++ 6 files changed, 712 insertions(+) create mode 100644 drivers/interconnect/qcom/bcm-voter.c create mode 100644 drivers/interconnect/qcom/bcm-voter.h create mode 100644 drivers/interconnect/qcom/icc-rpmh.c create mode 100644 drivers/interconnect/qcom/icc-rpmh.hdrivers/interconnect/qcom/Kconfig +8
-0@@ -5,6 +5,9 @@ config INTERCONNECT_QCOM help Support for Qualcomm's Network-on-Chip interconnect hardware. +config INTERCONNECT_QCOM_BCM_VOTER + tristate + config INTERCONNECT_QCOM_MSM8974 tristate "Qualcomm MSM8974 interconnect driver" depends on INTERCONNECT_QCOM@@ -23,10 +26,15 @@ config INTERCONNECT_QCOM_QCS404 This is a driver for the Qualcomm Network-on-Chip on qcs404-based platforms. +config INTERCONNECT_QCOM_RPMH + tristate + config INTERCONNECT_QCOM_SDM845 tristate "Qualcomm SDM845 interconnect driver" depends on INTERCONNECT_QCOM depends on (QCOM_RPMH && QCOM_COMMAND_DB && OF) || COMPILE_TEST + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER help This is a driver for the Qualcomm Network-on-Chip on sdm845-based platforms.drivers/interconnect/qcom/Makefile +4
-0@@ -4,8 +4,12 @@ qnoc-msm8974-objs := msm8974.o qnoc-qcs404-objs := qcs404.o qnoc-sdm845-objs := sdm845.o icc-smd-rpm-objs := smd-rpm.o +icc-bcm-voter-objs := bcm-voter.o +icc-rpmh-obj := icc-rpmh.o +obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8974) += qnoc-msm8974.o obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o +obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.odrivers/interconnect/qcom/bcm-voter.c new file +9
-0@@ -0,0 +1,363 @@ +// SPDX-License-Identifier: GPL-2.0 +/* +* Copyright (c) 2019, The Linux Foundation. All rights reserved. +* +*/ +#include <linux/interconnect-provider.h> +#include <linux/list_sort.h> +#include <linux/module.h> +#include <linux/of.h>
drivers/interconnect/qcom/bcm-voter.c line 19
Quoted 10 lines
drivers/interconnect/qcom/bcm-voter.c new file +10
-0+#include <linux/of_platform.h> +#include <linux/platform_device.h> + +#include <soc/qcom/rpmh.h> +#include <soc/qcom/tcs.h> + +#include "bcm-voter.h" +#include "icc-rpmh.h" + +static LIST_HEAD (bcm_voters);
Doesn't this need a lock?
Quoted 91 lines
drivers/interconnect/qcom/bcm-voter.c new file +91
-0+ +/** +* struct bcm_voter - Bus Clock Manager voter +* @dev: reference to the device that communicates with the BCM +* @np: reference to the device node to match bcm voters +* @lock: mutex to protect commit and wake/sleep lists in the voter +* @commit_list: list containing bcms to be committed to hardware +* @ws_list: list containing bcms that have different wake/sleep votes +* @voter_node: list of bcm voters +*/ +struct bcm_voter { +struct device *dev; +struct device_node *np; +struct mutex lock; +struct list_head commit_list; +struct list_head ws_list; +struct list_head voter_node; +}; + +static int cmp_vcd (void *priv,struct list_head *a,struct list_head *b) +{ +const struct qcom_icc_bcm *bcm_a = + list_entry(a, struct qcom_icc_bcm, list); +const struct qcom_icc_bcm *bcm_b = + list_entry(b, struct qcom_icc_bcm, list); + +if (bcm_a->aux_data.vcd < bcm_b->aux_data.vcd) +return -1 ; +else if (bcm_a->aux_data.vcd == bcm_b->aux_data.vcd) +return 0 ; +else +return 1 ; +} + +static void bcm_aggregate (struct qcom_icc_bcm *bcm) +{ +size_t i, bucket; +u64 agg_avg[QCOM_ICC_NUM_BUCKETS ] = {0 }; +u64 agg_peak[QCOM_ICC_NUM_BUCKETS ] = {0 }; +u64 temp; + +for (bucket =0 ; bucket <QCOM_ICC_NUM_BUCKETS ; bucket++) { +for (i =0 ; i < bcm->num_nodes; i++) { + temp = bcm->nodes[i]->sum_avg[bucket] * bcm->aux_data.width; +do_div (temp, bcm->nodes[i]->buswidth * bcm->nodes[i]->channels); + agg_avg[bucket] =max (agg_avg[bucket], temp); + + temp = bcm->nodes[i]->max_peak[bucket] * bcm->aux_data.width; +do_div (temp, bcm->nodes[i]->buswidth); + agg_peak[bucket] =max (agg_peak[bucket], temp); + } + + temp = agg_avg[bucket] *1000ULL ; +do_div (temp, bcm->aux_data.unit); + bcm->vote_x[bucket] = temp; + + temp = agg_peak[bucket] *1000ULL ; +do_div (temp, bcm->aux_data.unit); + bcm->vote_y[bucket] = temp; + } + +if (bcm->keepalive && bcm->vote_x[QCOM_ICC_BUCKET_AMC ] ==0 && + bcm->vote_y[QCOM_ICC_BUCKET_AMC ] ==0 ) { + bcm->vote_x[QCOM_ICC_BUCKET_AMC ] =1 ; + bcm->vote_x[QCOM_ICC_BUCKET_WAKE ] =1 ; + bcm->vote_y[QCOM_ICC_BUCKET_AMC ] =1 ; + bcm->vote_y[QCOM_ICC_BUCKET_WAKE ] =1 ; + } +} + +static inline void tcs_cmd_gen (struct tcs_cmd *cmd,u64 vote_x,u64 vote_y, +u32 addr,bool commit) +{ +bool valid = true; + +if (!cmd) +return ; + +if (vote_x ==0 && vote_y ==0 ) + valid = false; + +if (vote_x >BCM_TCS_CMD_VOTE_MASK ) + vote_x =BCM_TCS_CMD_VOTE_MASK ; + +if (vote_y >BCM_TCS_CMD_VOTE_MASK ) + vote_y =BCM_TCS_CMD_VOTE_MASK ; + + cmd->addr = addr; + cmd->data =BCM_TCS_CMD (commit, valid, vote_x, vote_y); + +/*
drivers/interconnect/qcom/bcm-voter.c line 120
Quoted 10 lines
drivers/interconnect/qcom/bcm-voter.c new file +10
-0+* Set the wait for completion flag on command that need to be completed +* before the next command. +*/ +if (commit) + cmd->wait = true; +} + +static void tcs_list_gen (struct list_head *bcm_list,int bucket, +struct tcs_cmd tcs_list[MAX_VCD ], +int n[MAX_VCD ])
"n" should really be MAX_VCD + 1 to guarantee that it's zero-terminated, otherwise rpmh_write_batch() could go nuts.
Quoted 18 lines
drivers/interconnect/qcom/bcm-voter.c new file +18
-0+{ +struct qcom_icc_bcm *bcm; +bool commit; +size_t idx =0 , batch =0 , cur_vcd_size =0 ; + +memset (n,0 ,sizeof (int ) *MAX_VCD ); + +list_for_each_entry (bcm, bcm_list, list) { + commit = false; + cur_vcd_size++; +if ((list_is_last (&bcm->list, bcm_list)) || + bcm->aux_data.vcd !=list_next_entry (bcm, list)->aux_data.vcd) { + commit = true; + cur_vcd_size =0 ; + } +tcs_cmd_gen (&tcs_list[idx], bcm->vote_x[bucket], + bcm->vote_y[bucket], bcm->addr, commit); + idx++;
drivers/interconnect/qcom/bcm-voter.c line 148
Quoted 10 lines
drivers/interconnect/qcom/bcm-voter.c new file +10
-0+ n[batch]++; +/* +* Batch the BCMs in such a way that we do not split them in +* multiple payloads when they are under the same VCD. This is +* to ensure that every BCM is committed since we only set the +* commit bit on the last BCM request of every VCD. +*/ +if (n[batch] >=MAX_RPMH_PAYLOAD ) { +if (!commit) { + n[batch] = cur_vcd_size;
You lost what used to be a -= here to just an = during the copy from sdm845.c. How did that happen?
Quoted 123 lines
drivers/interconnect/qcom/bcm-voter.c new file +123
-0+ n[batch +1 ] = cur_vcd_size; + } + batch++; + } + } +} + +/** +* of_bcm_voter_get - gets a bcm voter handle from DT node +* @dev: device pointer for the consumer device +* @name: name for the bcm voter device +* +* This function will match a device_node pointer for the phandle +* specified in the device DT and return a bcm_voter handle on success. +* +* Returns bcm_voter pointer or ERR_PTR() on error. EPROBE_DEFER is returned +* when matching bcm voter is yet to be found. +*/ +struct bcm_voter *of_bcm_voter_get (struct device *dev,const char *name) +{ +struct bcm_voter *voter =ERR_PTR (-EPROBE_DEFER ); +struct bcm_voter *temp; +struct device_node *np, *node; +int idx =0 ; + +if (!dev || !dev->of_node) +return ERR_PTR (-ENODEV ); + + np = dev->of_node; + +if (name) { + idx =of_property_match_string (np,"qcom,bcm-voter-names" , name); +if (idx <0 ) +return ERR_PTR (idx); + } + + node =of_parse_phandle (np,"qcom,bcm-voters" , idx); + +list_for_each_entry (temp, &bcm_voters, voter_node) { +if (temp->np == node) { + voter = temp; +break ; + } + } + +return voter; +} +EXPORT_SYMBOL_GPL (of_bcm_voter_get); + +/** +* qcom_icc_bcm_voter_add - queues up the bcm nodes that require updates +* @voter: voter that the bcms are being added to +* @bcm: bcm to add to the commit and wake sleep list +*/ +void qcom_icc_bcm_voter_add (struct bcm_voter *voter,struct qcom_icc_bcm *bcm) +{ +if (!voter) +return ; + +mutex_lock (&voter->lock); +if (list_empty (&bcm->list)) +list_add_tail (&bcm->list, &voter->commit_list); + +if (list_empty (&bcm->ws_list)) +list_add_tail (&bcm->ws_list, &voter->ws_list); + +mutex_unlock (&voter->lock); +} +EXPORT_SYMBOL_GPL (qcom_icc_bcm_voter_add); + +/** +* qcom_icc_bcm_voter_commit - generates and commits tcs cmds based on bcms +* @voter: voter that needs flushing +* +* This function generates a set of AMC commands and flushes to the BCM device +* associated with the voter. It conditionally generate WAKE and SLEEP commands +* based on deltas between WAKE/SLEEP requirements. The ws_list persists +* through multiple commit requests and bcm nodes are removed only when the +* requirements for WAKE matches SLEEP. +* +* Returns 0 on success, or an appropriate error code otherwise. +*/ +int qcom_icc_bcm_voter_commit (struct bcm_voter *voter) +{ +struct qcom_icc_bcm *bcm; +struct qcom_icc_bcm *bcm_tmp; +int commit_idx[MAX_VCD ]; +struct tcs_cmd cmds[MAX_BCMS ]; +int ret =0 ; + +if (!voter) +return 0 ; + +mutex_lock (&voter->lock); +list_for_each_entry (bcm, &voter->commit_list, list) +bcm_aggregate (bcm); + +/* +* Pre sort the BCMs based on VCD for ease of generating a command list +* that groups the BCMs with the same VCD together. VCDs are numbered +* with lowest being the most expensive time wise, ensuring that +* those commands are being sent the earliest in the queue. This needs +* to be sorted every commit since we can't guarantee the order in which +* the BCMs are added to the list. +*/ +list_sort (NULL , &voter->commit_list, cmp_vcd); + +/* +* Construct the command list based on a pre ordered list of BCMs +* based on VCD. +*/ +tcs_list_gen (&voter->commit_list,QCOM_ICC_BUCKET_AMC , cmds, commit_idx); + +if (!commit_idx[0 ]) + goto out; + + ret =rpmh_invalidate (voter->dev); +if (ret) { +pr_err ("Error invalidating RPMH client (%d)\n" , ret); + goto out; + } + + ret = rpmh_write_batch(voter->dev, RPMH_ACTIVE_ONLY_STATE,
drivers/interconnect/qcom/bcm-voter.c line 281
Quoted 10 lines
drivers/interconnect/qcom/bcm-voter.c new file +10
-0+ cmds, commit_idx); +if (ret) { +pr_err ("Error sending AMC RPMH requests (%d)\n" , ret); + goto out; + } + +list_for_each_entry_safe (bcm, bcm_tmp, &voter->commit_list, list) +list_del_init (&bcm->list); + +INIT_LIST_HEAD (&voter->commit_list);
This isn't necessary, you just carefully cherry-picked everything off the list in the previous line.
Quoted 32 lines
drivers/interconnect/qcom/bcm-voter.c new file +32
-0+ +list_for_each_entry_safe (bcm, bcm_tmp, &voter->ws_list, ws_list) { +/* +* Only generate WAKE and SLEEP commands if a resource's +* requirements change as the execution environment transitions +* between different power states. +*/ +if (bcm->vote_x[QCOM_ICC_BUCKET_WAKE ] != + bcm->vote_x[QCOM_ICC_BUCKET_SLEEP ] || + bcm->vote_y[QCOM_ICC_BUCKET_WAKE ] != + bcm->vote_y[QCOM_ICC_BUCKET_SLEEP ]) +list_add_tail (&bcm->list, &voter->commit_list); +else +list_del_init (&bcm->ws_list); + } + +if (list_empty (&voter->commit_list)) + goto out; + +list_sort (NULL , &voter->commit_list, cmp_vcd); + +tcs_list_gen (&voter->commit_list,QCOM_ICC_BUCKET_WAKE , cmds, commit_idx); + + ret =rpmh_write_batch (voter->dev,RPMH_WAKE_ONLY_STATE , cmds, commit_idx); +if (ret) { +pr_err ("Error sending WAKE RPMH requests (%d)\n" , ret); + goto out; + } + +tcs_list_gen (&voter->commit_list,QCOM_ICC_BUCKET_SLEEP , cmds, commit_idx); + + ret =rpmh_write_batch (voter->dev,RPMH_SLEEP_STATE , cmds, commit_idx);
drivers/interconnect/qcom/bcm-voter.c line 323
Quoted 10 lines
drivers/interconnect/qcom/bcm-voter.c new file +10
-0+if (ret) { +pr_err ("Error sending SLEEP RPMH requests (%d)\n" , ret); + goto out; + } + +out: +list_for_each_entry_safe (bcm, bcm_tmp, &voter->commit_list, list) +list_del_init (&bcm->list); + +INIT_LIST_HEAD (&voter->commit_list);
You can also remove this.
Quoted 398 lines
drivers/interconnect/qcom/bcm-voter.c new file +40
-0+mutex_unlock (&voter->lock); +return ret; +} +EXPORT_SYMBOL_GPL (qcom_icc_bcm_voter_commit); + +static int qcom_icc_bcm_voter_probe (struct platform_device *pdev) +{ +struct bcm_voter *voter; + + voter =devm_kzalloc (&pdev->dev,sizeof (*voter),GFP_KERNEL ); +if (!voter) +return -ENOMEM ; + + voter->dev = &pdev->dev; + voter->np = pdev->dev.of_node; +mutex_init (&voter->lock); +INIT_LIST_HEAD (&voter->commit_list); +INIT_LIST_HEAD (&voter->ws_list); +list_add_tail (&voter->voter_node, &bcm_voters); + +return 0 ; +} + +static const struct of_device_id bcm_voter_of_match[] = { + { .compatible ="qcom,sdm845-bcm-voter" }, + { }, +}; + +static struct platform_driver qcom_icc_bcm_voter_driver = { + .probe = qcom_icc_bcm_voter_probe, + .driver = { + .name ="sdm845_bcm_voter" , + .of_match_table = bcm_voter_of_match, + }, +}; +module_platform_driver (qcom_icc_bcm_voter_driver); +MODULE_AUTHOR ("David Dai <[email protected]>" ); +MODULE_DESCRIPTION ("Qualcomm BCM Voter interconnect driver" ); +MODULE_LICENSE ("GPL v2" ); +drivers/interconnect/qcom/bcm-voter.h new file +28
-0@@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright (c) 2019, The Linux Foundation. All rights reserved. +* +*/ + +#ifndef __DRIVERS_INTERCONNECT_QCOM_BCM_VOTER_H__ +#define __DRIVERS_INTERCONNECT_QCOM_BCM_VOTER_H__ + +#include <soc/qcom/cmd-db.h> +#include <soc/qcom/rpmh.h> +#include <soc/qcom/tcs.h> + +#include "icc-rpmh.h" + +#define DEFINE_QBCM (_name, _bcmname, _keepalive, _numnodes, ...) \ + static struct qcom_icc_bcm _name = { \ + .name = _bcmname, \ + .keepalive = _keepalive, \ + .num_nodes = _numnodes, \ + .nodes = { __VA_ARGS__ }, \ + } + +struct bcm_voter *of_bcm_voter_get (struct device *dev,const char *name); +void qcom_icc_bcm_voter_add (struct bcm_voter *voter,struct qcom_icc_bcm *bcm); +int qcom_icc_bcm_voter_commit (struct bcm_voter *voter); + +#endif drivers/interconnect/qcom/icc-rpmh.c new file +158
-0@@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0 +/* +* Copyright (c) 2019, The Linux Foundation. All rights reserved. +* +*/ + +#include <asm/div64.h> +#include <dt-bindings/interconnect/qcom,sdm845.h> +#include <linux/interconnect.h> +#include <linux/interconnect-provider.h> +#include <linux/module.h> + +#include "bcm-voter.h" +#include "icc-rpmh.h" + +/** +* qcom_icc_pre_aggregate - cleans up stale values from prior icc_set +* @node: icc node to operate on +*/ +void qcom_icc_pre_aggregate (struct icc_node *node) +{ +size_t i; +struct qcom_icc_node *qn; + + qn = node->data; + +for (i =0 ; i <QCOM_ICC_NUM_BUCKETS ; i++) { + qn->sum_avg[i] =0 ; + qn->max_peak[i] =0 ; + } +} +EXPORT_SYMBOL_GPL (qcom_icc_pre_aggregate); + +/** +* qcom_icc_aggregate - aggregate bw for buckets indicated by tag +* @node: node to aggregate +* @tag: tag to indicate which buckets to aggregate +* @avg_bw: new bw to sum aggregate +* @peak_bw: new bw to max aggregate +* @agg_avg: existing aggregate avg bw val +* @agg_peak: existing aggregate peak bw val +*/ +int qcom_icc_aggregate (struct icc_node *node,u32 tag,u32 avg_bw, +u32 peak_bw,u32 *agg_avg,u32 *agg_peak) +{ +size_t i; +struct qcom_icc_node *qn; +struct qcom_icc_provider *qp; + + qn = node->data; + qp =to_qcom_provider (node->provider); + +if (!tag) + tag =QCOM_ICC_TAG_ALWAYS ; + +for (i =0 ; i <QCOM_ICC_NUM_BUCKETS ; i++) { +if (tag &BIT (i)) { + qn->sum_avg[i] += avg_bw; + qn->max_peak[i] =max_t (u32, qn->max_peak[i], peak_bw); + } + } + + *agg_avg += avg_bw; + *agg_peak =max_t (u32, *agg_peak, peak_bw); + +for (i =0 ; i < qn->num_bcms; i++) +qcom_icc_bcm_voter_add (qp->voter, qn->bcms[i]); + +return 0 ; +} +EXPORT_SYMBOL_GPL (qcom_icc_aggregate); + +/** +* qcom_icc_set - set the constraints based on path +* @src: source node for the path to set constraints on +* @dst: destination node for the path to set constraints on +* +* Return: 0 on success, or an error code otherwise +*/ +int qcom_icc_set (struct icc_node *src,struct icc_node *dst) +{ +struct qcom_icc_provider *qp; +struct icc_node *node; +int ret =0 ; + +if (!src) + node = dst; +else + node = src; + + qp =to_qcom_provider (node->provider); + +qcom_icc_bcm_voter_commit (qp->voter); + +return ret; +} +EXPORT_SYMBOL_GPL (qcom_icc_set); + +/** +* qcom_icc_bcm_init - populates bcm aux data and connect qnodes +* @bcm: bcm to be initialized +* @dev: associated provider device +* +* Return: 0 on success, or an error code otherwise +*/ +int qcom_icc_bcm_init (struct qcom_icc_bcm *bcm,struct device *dev) +{ +struct qcom_icc_node *qn; +const struct bcm_db *data; +size_t data_count; +int i; + + bcm->addr =cmd_db_read_addr (bcm->name); +if (!bcm->addr) { +dev_err (dev,"%s could not find RPMh address\n" , + bcm->name); +return -EINVAL ; + } + + data =cmd_db_read_aux_data (bcm->name, &data_count); +if (IS_ERR (data)) { +dev_err (dev,"%s command db read error (%ld)\n" , + bcm->name,PTR_ERR (data)); +return PTR_ERR (data); + } +if (!data_count) { +dev_err (dev,"%s command db missing or partial aux data\n" , + bcm->name); +return -EINVAL ; + } + + bcm->aux_data.unit =le32_to_cpu (data->unit); + bcm->aux_data.width =le16_to_cpu (data->width); + bcm->aux_data.vcd = data->vcd; + bcm->aux_data.reserved = data->reserved; +INIT_LIST_HEAD (&bcm->list); +INIT_LIST_HEAD (&bcm->ws_list); + +/* +* Link Qnodes to their respective BCMs +*/ +for (i =0 ; i < bcm->num_nodes; i++) { + qn = bcm->nodes[i]; + qn->bcms[qn->num_bcms] = bcm; + qn->num_bcms++; + } + +return 0 ; +} +EXPORT_SYMBOL_GPL (qcom_icc_bcm_init); + +static struct platform_driver qcom_icc_rpmh_driver = { + .driver = { + .name ="icc_rpmh" , + }, +}; +module_platform_driver (qcom_icc_rpmh_driver); +MODULE_LICENSE ("GPL v2" );drivers/interconnect/qcom/icc-rpmh.h new file +151
-1@@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright (c) 2019, The Linux Foundation. All rights reserved. +* +*/ + +#ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_RPMH_H__ +#define __DRIVERS_INTERCONNECT_QCOM_ICC_RPMH_H__ + +#define to_qcom_provider (_provider) \ + container_of(_provider, struct qcom_icc_provider, provider) + +/** +* struct qcom_icc_provider - Qualcomm specific interconnect provider +* @provider: generic interconnect provider +* @dev: reference to the NoC device +* @bcms: list of bcms that maps to the provider +* @num_bcms: number of @bcms +* @voter: bcm voter targeted by this provider +*/ +struct qcom_icc_provider { +struct icc_provider provider; +struct device *dev; +struct qcom_icc_bcm **bcms; +size_t num_bcms; +struct bcm_voter *voter; +}; + +/** +* struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager (BCM) +* @unit: divisor used to convert bytes/sec bw value to an RPMh msg +* @width: multiplier used to convert bytes/sec bw value to an RPMh msg +* @vcd: virtual clock domain that this bcm belongs to +* @reserved: reserved field +*/ +struct bcm_db { +__le32 unit; +__le16 width; +u8 vcd; +u8 reserved; +}; + +#define MAX_LINKS 128 +#define MAX_BCMS 64 +#define MAX_BCM_PER_NODE 3 +#define MAX_VCD 10 + +/* +* The AMC bucket denotes constraints that are applied to hardware when +* icc_set_bw() completes, whereas the WAKE and SLEEP constraints are applied +* when the execution environment transitions between active and low power mode. +*/ +#define QCOM_ICC_BUCKET_AMC 0 +#define QCOM_ICC_BUCKET_WAKE 1 +#define QCOM_ICC_BUCKET_SLEEP 2 +#define QCOM_ICC_NUM_BUCKETS 3 +#define QCOM_ICC_TAG_AMC BIT(QCOM_ICC_BUCKET_AMC) +#define QCOM_ICC_TAG_WAKE BIT(QCOM_ICC_BUCKET_WAKE) +#define QCOM_ICC_TAG_SLEEP BIT(QCOM_ICC_BUCKET_SLEEP) +#define QCOM_ICC_TAG_ACTIVE_ONLY (QCOM_ICC_TAG_AMC | QCOM_ICC_TAG_WAKE) +#define QCOM_ICC_TAG_ALWAYS (QCOM_ICC_TAG_AMC | QCOM_ICC_TAG_WAKE |\ + QCOM_ICC_TAG_SLEEP) + +/** +* struct qcom_icc_node - Qualcomm specific interconnect nodes +* @name: the node name used in debugfs +* @links: an array of nodes where we can go next while traversing +* @id: a unique node identifier +* @num_links: the total number of @links +* @channels: num of channels at this node +* @buswidth: width of the interconnect between a node and the bus +* @sum_avg: current sum aggregate value of all avg bw requests +* @max_peak: current max aggregate value of all peak bw requests +* @bcms: list of bcms associated with this logical node +* @num_bcms: num of @bcms +*/ +struct qcom_icc_node { +const char *name; +u16 links[MAX_LINKS ]; +u16 id; +u16 num_links; +u16 channels; +u16 buswidth; +u64 sum_avg[QCOM_ICC_NUM_BUCKETS ]; +u64 max_peak[QCOM_ICC_NUM_BUCKETS ]; +struct qcom_icc_bcm *bcms[MAX_BCM_PER_NODE ]; +size_t num_bcms; +}; + +/** +* struct qcom_icc_bcm - Qualcomm specific hardware accelerator nodes +* known as Bus Clock Manager (BCM) +* @name: the bcm node name used to fetch BCM data from command db +* @type: latency or bandwidth bcm +* @addr: address offsets used when voting to RPMH +* @vote_x: aggregated threshold values, represents sum_bw when @type is bw bcm +* @vote_y: aggregated threshold values, represents peak_bw when @type is bw bcm +* @dirty: flag used to indicate whether the bcm needs to be committed +* @keepalive: flag used to indicate whether a keepalive is required +* @aux_data: auxiliary data used when calculating threshold values and +* communicating with RPMh +* @list: used to link to other bcms when compiling lists for commit +* @ws_list: used to keep track of bcms that may transition between wake/sleep +* @num_nodes: total number of @num_nodes +* @nodes: list of qcom_icc_nodes that this BCM encapsulates +*/ +struct qcom_icc_bcm { +const char *name; +u32 type; +u32 addr; +u64 vote_x[QCOM_ICC_NUM_BUCKETS ]; +u64 vote_y[QCOM_ICC_NUM_BUCKETS ]; +bool dirty; +bool keepalive; +struct bcm_db aux_data; +struct list_head list; +struct list_head ws_list; +size_t num_nodes; +struct qcom_icc_node *nodes[]; +}; + +struct qcom_icc_fabric { +struct qcom_icc_node **nodes; +size_t num_nodes; +}; + +struct qcom_icc_desc { +struct qcom_icc_node **nodes; +size_t num_nodes; +struct qcom_icc_bcm **bcms; +size_t num_bcms; +}; + +#define DEFINE_QNODE (_name, _id, _channels, _buswidth, \ + _numlinks, ...) \ + static struct qcom_icc_node _name = { \ + .id = _id, \ + .name = #_name, \ + .channels = _channels, \ + .buswidth = _buswidth, \ + .num_links = _numlinks, \ + .links = { __VA_ARGS__ }, \ + } + +int qcom_icc_aggregate (struct icc_node *node,u32 tag,u32 avg_bw, +u32 peak_bw,u32 *agg_avg,u32 *agg_peak); +int qcom_icc_set (struct icc_node *src,struct icc_node *dst); +int qcom_icc_bcm_init (struct qcom_icc_bcm *bcm,struct device *dev); +void qcom_icc_pre_aggregate (struct icc_node *node); + +#endif --The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH v2 4/6] interconnect: qcom: Consolidate interconnect RPMh support
Hey Evan,
I am taking a stab at re-spinning the series. Apart the issues you've identified I added a few more to the list.
Quoted 37 lines · Evan Green
Quoted 8 lines · David Dai
Add bcm voter driver and add support for RPMh specific interconnect providers which implements the set and aggregate functionalities that translates bandwidth requests into RPMh messages. These modules provide a common set of functionalities for all Qualcomm RPMh based interconnect providers and should help reduce code duplication when adding new providers.
Signed-off-by David Dai <[email protected]>This was a little tough to wrap my head around, but then I understood that most of it was a copy of functions from
sdm845.c, which are later deleted in patch 5 whensdm845.cuses the bcm-voter driver.Quoted 23 lines
--- drivers/interconnect/qcom/Kconfig | 8 + drivers/interconnect/qcom/Makefile | 4 + drivers/interconnect/qcom/bcm-voter.c | 363 ++++++++++++++++++++++++++++++++++ drivers/interconnect/qcom/bcm-voter.h | 28 +++ drivers/interconnect/qcom/icc-rpmh.c | 158 +++++++++++++++ drivers/interconnect/qcom/icc-rpmh.h | 151 ++++++++++++++ 6 files changed, 712 insertions(+) create mode 100644 drivers/interconnect/qcom/bcm-voter.c create mode 100644 drivers/interconnect/qcom/bcm-voter.h create mode 100644 drivers/interconnect/qcom/icc-rpmh.c create mode 100644 drivers/interconnect/qcom/icc-rpmh.hdrivers/interconnect/qcom/Kconfig +0
-0@@ -5,6 +5,9 @@ config INTERCONNECT_QCOM help Support for Qualcomm's Network-on-Chip interconnecthardware.
Quoted 2 lines
drivers/interconnect/qcom/Kconfig config INTERCONNECT_QCOM · line 9
Quoted 2 lines
drivers/interconnect/qcom/Kconfig +2
-0+config INTERCONNECT_QCOM_BCM_VOTER + tristate
Looks like the dependencies are
not captured.
Quoted 11 lines
drivers/interconnect/qcom/Kconfig config INTERCONNECT_QCOM_QCS404 · line 30
Quoted 11 lines
drivers/interconnect/qcom/Kconfig +1
-0+ config INTERCONNECT_QCOM_MSM8974 tristate "Qualcomm MSM8974 interconnect driver" depends on INTERCONNECT_QCOM@@ -23,10 +26,15 @@ config INTERCONNECT_QCOM_QCS404 This is a driver for the Qualcomm Network-on-Chip onqcs404-based
platforms.drivers/interconnect/qcom/Kconfig +2
-0+config INTERCONNECT_QCOM_RPMH + tristate
Looks like the dependencies are
not captured.
Quoted 14 lines
Quoted 14 lines
+
configINTERCONNECT_QCOM_SDM845
tristate "Qualcomm SDM845 interconnect driver" depends onINTERCONNECT_QCOM
depends on (QCOM_RPMH&&QCOM_COMMAND_DB&& OF) ||COMPILE_TESTdrivers/interconnect/qcom/Kconfig +2
-0+ select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER help This is a driver for the Qualcomm Network-on-Chip onsdm845-based
platforms.drivers/interconnect/qcom/Makefile +0
-0
Quoted 8 lines
drivers/interconnect/qcom/Makefile qnoc-msm8974-objs := msm8974.o · line 8
Quoted 8 lines
drivers/interconnect/qcom/Makefile +2
-0@@ -4,8 +4,12 @@ qnoc-msm8974-objs := msm8974.o qnoc-qcs404-objs := qcs404.o qnoc-sdm845-objs := sdm845.o icc-smd-rpm-objs := smd-rpm.o +icc-bcm-voter-objs := bcm-voter.o +icc-rpmh-obj := icc-rpmh.o
nit: could be re-ordered
Quoted 26 lines
Quoted 26 lines
drivers/interconnect/qcom/Makefile +2
-0+obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8974) += qnoc-msm8974.o obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o +obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.odrivers/interconnect/qcom/bcm-voter.c new file +13
-0@@ -0,0 +1,363 @@ +// SPDX-License-Identifier: GPL-2.0 +/* +* Copyright (c) 2019, The Linux Foundation. All rights reserved. +* +*/ +#include <linux/interconnect-provider.h> +#include <linux/list_sort.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> + +#include <soc/qcom/rpmh.h>
Quoted 8 lines
drivers/interconnect/qcom/bcm-voter.c line 19
Quoted 6 lines
drivers/interconnect/qcom/bcm-voter.c new file +6
-0+#include <soc/qcom/tcs.h> + +#include "bcm-voter.h" +#include "icc-rpmh.h" + +static LIST_HEAD (bcm_voters);Doesn't this need a lock?
yes this does need a lock.
Quoted 101 lines
Quoted 101 lines
drivers/interconnect/qcom/bcm-voter.c new file +8
-0+ +/** +* struct bcm_voter - Bus Clock Manager voter +* @dev: reference to the device that communicates with the BCM +* @np: reference to the device node to match bcm voters +* @lock: mutex to protect commit and wake/sleep lists in the voter +* @commit_list: list containing bcms to be committed to hardware +* @ws_list: list containing bcms that have different wake/sleep votes
+ * @voter_node: list of bcm voters
+ */drivers/interconnect/qcom/bcm-voter.c new file +10
-0+struct bcm_voter { +struct device *dev; +struct device_node *np; +struct mutex lock; +struct list_head commit_list; +struct list_head ws_list; +struct list_head voter_node; +}; + +static int cmp_vcd(void *priv, struct list_head *a, struct list_head*b)
drivers/interconnect/qcom/bcm-voter.c new file +24
-0+{ +const struct qcom_icc_bcm *bcm_a = + list_entry(a, struct qcom_icc_bcm, list); +const struct qcom_icc_bcm *bcm_b = + list_entry(b, struct qcom_icc_bcm, list); + +if (bcm_a->aux_data.vcd < bcm_b->aux_data.vcd) +return -1 ; +else if (bcm_a->aux_data.vcd == bcm_b->aux_data.vcd) +return 0 ; +else +return 1 ; +} + +static void bcm_aggregate (struct qcom_icc_bcm *bcm) +{ +size_t i, bucket; +u64 agg_avg[QCOM_ICC_NUM_BUCKETS ] = {0 }; +u64 agg_peak[QCOM_ICC_NUM_BUCKETS ] = {0 }; +u64 temp; + +for (bucket =0 ; bucket <QCOM_ICC_NUM_BUCKETS ; bucket++) { +for (i =0 ; i < bcm->num_nodes; i++) { + temp = bcm->nodes[i]->sum_avg[bucket] *
bcm->aux_data.width;
+ do_div(temp, bcm->nodes[i]->buswidth *
bcm->nodes[i]->channels);drivers/interconnect/qcom/bcm-voter.c new file +3
-0+ agg_avg[bucket] =max (agg_avg[bucket], temp); + + temp = bcm->nodes[i]->max_peak[bucket] *
bcm->aux_data.width;drivers/interconnect/qcom/bcm-voter.c new file +2
-0+do_div (temp, bcm->nodes[i]->buswidth); + agg_peak[bucket] = max(agg_peak[bucket],temp);
drivers/interconnect/qcom/bcm-voter.c new file +21
-0+ } + + temp = agg_avg[bucket] *1000ULL ; +do_div (temp, bcm->aux_data.unit); + bcm->vote_x[bucket] = temp; + + temp = agg_peak[bucket] *1000ULL ; +do_div (temp, bcm->aux_data.unit); + bcm->vote_y[bucket] = temp; + } + +if (bcm->keepalive && bcm->vote_x[QCOM_ICC_BUCKET_AMC ] ==0 && + bcm->vote_y[QCOM_ICC_BUCKET_AMC ] ==0 ) { + bcm->vote_x[QCOM_ICC_BUCKET_AMC ] =1 ; + bcm->vote_x[QCOM_ICC_BUCKET_WAKE ] =1 ; + bcm->vote_y[QCOM_ICC_BUCKET_AMC ] =1 ; + bcm->vote_y[QCOM_ICC_BUCKET_WAKE ] =1 ; + } +} + +static inline void tcs_cmd_gen(struct tcs_cmd *cmd, u64 vote_x, u64
vote_y,drivers/interconnect/qcom/bcm-voter.c new file +21
-0+ u32 addr, bool commit) +{ + bool valid = true; + +if (!cmd) +return ; + +if (vote_x ==0 && vote_y ==0 ) + valid = false; + +if (vote_x >BCM_TCS_CMD_VOTE_MASK ) + vote_x =BCM_TCS_CMD_VOTE_MASK ; + +if (vote_y >BCM_TCS_CMD_VOTE_MASK ) + vote_y =BCM_TCS_CMD_VOTE_MASK ; + + cmd->addr = addr; + cmd->data =BCM_TCS_CMD (commit, valid, vote_x, vote_y); + +/* +* Set the wait for completion flag on command that need to be completed
Quoted 8 lines
drivers/interconnect/qcom/bcm-voter.c line 119
Quoted 8 lines
drivers/interconnect/qcom/bcm-voter.c new file +8
-0+* before the next command. +*/ +if (commit) + cmd->wait = true; +} + +static void tcs_list_gen(struct list_head *bcm_list, int bucket, + struct tcs_cmd tcs_list[MAX_VCD],
tcs_list should be an array of
size MAX_BCMS.
Quoted 4 lines
Quoted 1 line
+ int n[MAX_VCD])
"n" should really be
MAX_VCD+ 1 to guarantee that it's zero-terminated, otherwiserpmh_write_batch()could go nuts.
though the combination MAX_VCD, MAX_BCMs and vcd info read back from cmd_db for the bcms ensure that situation does not occur, it does make sense to have it MAX_VCD + 1.
Quoted 184 lines
Quoted 28 lines
drivers/interconnect/qcom/bcm-voter.c new file +12
-0+{ + struct qcom_icc_bcm *bcm; + bool commit; + size_t idx = 0, batch = 0, cur_vcd_size = 0; + + memset(n, 0, sizeof(int) * MAX_VCD); + + list_for_each_entry(bcm, bcm_list, list) { + commit = false; + cur_vcd_size++; + if ((list_is_last(&bcm->list, bcm_list)) || + bcm->aux_data.vcd != list_next_entry(bcm,list)->aux_data.vcd) {
drivers/interconnect/qcom/bcm-voter.c new file +9
-0+ commit = true; + cur_vcd_size =0 ; + } +tcs_cmd_gen (&tcs_list[idx], bcm->vote_x[bucket], + bcm->vote_y[bucket], bcm->addr, commit); + idx++; + n[batch]++; +/* +* Batch the BCMs in such a way that we do not split them in
+ * multiple payloads when they are under the same VCD.
This is
+ * to ensure that every BCM is committed since we only
set thedrivers/interconnect/qcom/bcm-voter.c line 148
Quoted 5 lines
drivers/interconnect/qcom/bcm-voter.c new file +5
-0+* commit bit on the last BCM request of every VCD. +*/ +if (n[batch] >=MAX_RPMH_PAYLOAD ) { +if (!commit) { + n[batch] = cur_vcd_size;You lost what used to be a -= here to just an = during the copy from
sdm845.c. How did that happen?Quoted 147 lines
drivers/interconnect/qcom/bcm-voter.c new file +14
-0+ n[batch +1 ] = cur_vcd_size; + } + batch++; + } + } +} + +/** +* of_bcm_voter_get - gets a bcm voter handle from DT node +* @dev: device pointer for the consumer device +* @name: name for the bcm voter device +* +* This function will match a device_node pointer for the phandle +* specified in the device DT and return a bcm_voter handle on success.
+ *
+ * Returnsbcm_voterpointer orERR_PTR()on error.EPROBE_DEFERis returned
+ * when matching bcm voter is yet to be found.
+ */
+structbcm_voter*of_bcm_voter_get(struct device *dev, const char *name)drivers/interconnect/qcom/bcm-voter.c new file +13
-0+{ +struct bcm_voter *voter =ERR_PTR (-EPROBE_DEFER ); +struct bcm_voter *temp; +struct device_node *np, *node; +int idx =0 ; + +if (!dev || !dev->of_node) +return ERR_PTR (-ENODEV ); + + np = dev->of_node; + +if (name) { + idx = of_property_match_string(np,"qcom,bcm-voter-names", name);
drivers/interconnect/qcom/bcm-voter.c new file +19
-0+if (idx <0 ) +return ERR_PTR (idx); + } + + node =of_parse_phandle (np,"qcom,bcm-voters" , idx); + +list_for_each_entry (temp, &bcm_voters, voter_node) { +if (temp->np == node) { + voter = temp; +break ; + } + } + +return voter; +} +EXPORT_SYMBOL_GPL (of_bcm_voter_get); + +/** +* qcom_icc_bcm_voter_add - queues up the bcm nodes that require updates
+ * @voter: voter that the bcms are being added to
+ * @bcm: bcm to add to the commit and wake sleep list
+ */
+voidqcom_icc_bcm_voter_add(struct bcm_voter *voter, struct qcom_icc_bcm *bcm)drivers/interconnect/qcom/bcm-voter.c new file +17
-0+{ +if (!voter) +return ; + +mutex_lock (&voter->lock); +if (list_empty (&bcm->list)) +list_add_tail (&bcm->list, &voter->commit_list); + +if (list_empty (&bcm->ws_list)) +list_add_tail (&bcm->ws_list, &voter->ws_list); + +mutex_unlock (&voter->lock); +} +EXPORT_SYMBOL_GPL (qcom_icc_bcm_voter_add); + +/** +* qcom_icc_bcm_voter_commit - generates and commits tcs cmds based on bcms
+ * @voter: voter that needs flushing
+ *
+ * This function generates a set of AMC commands and flushes to the BCM device
+ * associated with the voter. It conditionally generate WAKE and SLEEP commands
+ * based on deltas between WAKE/SLEEP requirements. Thews_listpersists
+ * through multiple commit requests and bcm nodes are removed only when the
+ * requirements for WAKE matches SLEEP.
+ *
+ * Returns 0 on success, or an appropriate error code otherwise.
+ */drivers/interconnect/qcom/bcm-voter.c new file +17
-0+int qcom_icc_bcm_voter_commit (struct bcm_voter *voter) +{ +struct qcom_icc_bcm *bcm; +struct qcom_icc_bcm *bcm_tmp; +int commit_idx[MAX_VCD ]; +struct tcs_cmd cmds[MAX_BCMS ]; +int ret =0 ; + +if (!voter) +return 0 ; + +mutex_lock (&voter->lock); +list_for_each_entry (bcm, &voter->commit_list, list) +bcm_aggregate (bcm); + +/* +* Pre sort the BCMs based on VCD for ease of generating a command list
+ * that groups the BCMs with the same VCD together. VCDs are
numbered
+ * with lowest being the most expensive time wise, ensuring
that
+ * those commands are being sent the earliest in the queue.
This needs
+ * to be sorted every commit since we can't guarantee the
order in whichdrivers/interconnect/qcom/bcm-voter.c new file +6
-0+* the BCMs are added to the list. +*/ +list_sort (NULL , &voter->commit_list, cmp_vcd); + +/* +* Construct the command list based on a pre ordered list of BCMs
drivers/interconnect/qcom/bcm-voter.c new file +3
-0+* based on VCD. +*/ + tcs_list_gen(&voter->commit_list, QCOM_ICC_BUCKET_AMC, cmds,
commit_idx);drivers/interconnect/qcom/bcm-voter.c new file +17
-0+ +if (!commit_idx[0 ]) + goto out; + + ret =rpmh_invalidate (voter->dev); +if (ret) { +pr_err ("Error invalidating RPMH client (%d)\n" , ret); + goto out; + } + + ret =rpmh_write_batch (voter->dev,RPMH_ACTIVE_ONLY_STATE , + cmds, commit_idx); +if (ret) { +pr_err ("Error sending AMC RPMH requests (%d)\n" , ret); + goto out; + } +
Quoted 8 lines
drivers/interconnect/qcom/bcm-voter.c line 281
Quoted 5 lines
+ list_for_each_entry_safe(bcm,
bcm_tmp,&voter->commit_list,
list)drivers/interconnect/qcom/bcm-voter.c new file +3
-0+list_del_init (&bcm->list); + +INIT_LIST_HEAD (&voter->commit_list);This isn't necessary, you just carefully cherry-picked everything off the list in the previous line.
will drop it
Quoted 48 lines
Quoted 48 lines
drivers/interconnect/qcom/bcm-voter.c new file +2
-0+ + list_for_each_entry_safe(bcm, bcm_tmp, &voter->ws_list,
ws_list) {drivers/interconnect/qcom/bcm-voter.c new file +2
-0+/* +* Only generate WAKE and SLEEP commands if a resource's
+ * requirements change as the execution environment
transitionsdrivers/interconnect/qcom/bcm-voter.c new file +7
-0+* between different power states. +*/ +if (bcm->vote_x[QCOM_ICC_BUCKET_WAKE ] != + bcm->vote_x[QCOM_ICC_BUCKET_SLEEP ] || + bcm->vote_y[QCOM_ICC_BUCKET_WAKE ] != + bcm->vote_y[QCOM_ICC_BUCKET_SLEEP ]) + list_add_tail(&bcm->list,
&voter->commit_list);drivers/interconnect/qcom/bcm-voter.c new file +10
-0+else +list_del_init (&bcm->ws_list); + } + +if (list_empty (&voter->commit_list)) + goto out; + +list_sort (NULL , &voter->commit_list, cmp_vcd); + + tcs_list_gen(&voter->commit_list, QCOM_ICC_BUCKET_WAKE, cmds,
commit_idx);drivers/interconnect/qcom/bcm-voter.c new file +2
-0+ + ret = rpmh_write_batch(voter->dev, RPMH_WAKE_ONLY_STATE, cmds,
commit_idx);drivers/interconnect/qcom/bcm-voter.c new file +2
-0+if (ret) { + pr_err("Error sending WAKE RPMH requests (%d)\n",ret);
drivers/interconnect/qcom/bcm-voter.c new file +4
-0+ goto out; + } + + tcs_list_gen(&voter->commit_list, QCOM_ICC_BUCKET_SLEEP, cmds,
commit_idx);drivers/interconnect/qcom/bcm-voter.c new file +2
-0+ + ret = rpmh_write_batch(voter->dev, RPMH_SLEEP_STATE, cmds,
commit_idx);drivers/interconnect/qcom/bcm-voter.c new file +2
-0+if (ret) { + pr_err("Error sending SLEEP RPMH requests (%d)\n",ret);
drivers/interconnect/qcom/bcm-voter.c new file +3
-0+ goto out; + } +
Quoted 8 lines
drivers/interconnect/qcom/bcm-voter.c line 281
Quoted 6 lines
drivers/interconnect/qcom/bcm-voter.c new file +2
-0+out: + list_for_each_entry_safe(bcm, bcm_tmp, &voter->commit_list,list)
drivers/interconnect/qcom/bcm-voter.c new file +3
-0+list_del_init (&bcm->list); + +INIT_LIST_HEAD (&voter->commit_list);You can also remove this.
will drop it
Quoted 65 lines
Quoted 65 lines
drivers/interconnect/qcom/bcm-voter.c new file +40
-0+mutex_unlock (&voter->lock); +return ret; +} +EXPORT_SYMBOL_GPL (qcom_icc_bcm_voter_commit); + +static int qcom_icc_bcm_voter_probe (struct platform_device *pdev) +{ +struct bcm_voter *voter; + + voter =devm_kzalloc (&pdev->dev,sizeof (*voter),GFP_KERNEL ); +if (!voter) +return -ENOMEM ; + + voter->dev = &pdev->dev; + voter->np = pdev->dev.of_node; +mutex_init (&voter->lock); +INIT_LIST_HEAD (&voter->commit_list); +INIT_LIST_HEAD (&voter->ws_list); +list_add_tail (&voter->voter_node, &bcm_voters); + +return 0 ; +} + +static const struct of_device_id bcm_voter_of_match[] = { + { .compatible ="qcom,sdm845-bcm-voter" }, + { }, +}; + +static struct platform_driver qcom_icc_bcm_voter_driver = { + .probe = qcom_icc_bcm_voter_probe, + .driver = { + .name ="sdm845_bcm_voter" , + .of_match_table = bcm_voter_of_match, + }, +}; +module_platform_driver (qcom_icc_bcm_voter_driver); +MODULE_AUTHOR ("David Dai <[email protected]>" ); +MODULE_DESCRIPTION ("Qualcomm BCM Voter interconnect driver" ); +MODULE_LICENSE ("GPL v2" ); +drivers/interconnect/qcom/bcm-voter.h new file +16
-0@@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright (c) 2019, The Linux Foundation. All rights reserved. +* +*/ + +#ifndef __DRIVERS_INTERCONNECT_QCOM_BCM_VOTER_H__ +#define __DRIVERS_INTERCONNECT_QCOM_BCM_VOTER_H__ + +#include <soc/qcom/cmd-db.h> +#include <soc/qcom/rpmh.h> +#include <soc/qcom/tcs.h> + +#include "icc-rpmh.h" + +#define DEFINE_QBCM (_name, _bcmname, _keepalive, _numnodes, ...) \
Quoted 8 lines
drivers/interconnect/qcom/bcm-voter.h
Quoted 8 lines
drivers/interconnect/qcom/bcm-voter.h new file +4
-0+static struct qcom_icc_bcm _name = { \ + .name = _bcmname, \ + .keepalive = _keepalive, \ + .num_nodes = _numnodes, \
should be able to calculate the num_nodes from VA_ARGS..
Quoted 16 lines
Quoted 16 lines
drivers/interconnect/qcom/bcm-voter.h new file +4
-0+ .nodes = { __VA_ARGS__ }, \ + } + +struct bcm_voter *of_bcm_voter_get(struct device *dev, const char*name);
+voidqcom_icc_bcm_voter_add(struct bcm_voter *voter, struct qcom_icc_bcm *bcm);drivers/interconnect/qcom/bcm-voter.h new file +3
-0+int qcom_icc_bcm_voter_commit (struct bcm_voter *voter); + +#endif drivers/interconnect/qcom/icc-rpmh.c new file +0
-0
Quoted 8 lines
drivers/interconnect/qcom/icc-rpmh.c line 7
Quoted 8 lines
drivers/interconnect/qcom/icc-rpmh.c new file +7
-0@@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0 +/* +* Copyright (c) 2019, The Linux Foundation. All rights reserved. +* +*/ + +#include <asm/div64.h>
looks like ^^ should be included
in bcm_voter instead...
Quoted 1 line
drivers/interconnect/qcom/icc-rpmh.c line 8
Quoted 1 line
drivers/interconnect/qcom/icc-rpmh.c new file +1
-0+#include <dt-bindings/interconnect/qcom,sdm845.h>
^^ not needed
Quoted 3 lines
drivers/interconnect/qcom/icc-rpmh.c line 11
Quoted 3 lines
drivers/interconnect/qcom/icc-rpmh.c new file +3
-0+#include <linux/interconnect.h> +#include <linux/interconnect-provider.h> +#include <linux/module.h>
dropping this as well for the
reasons mentioned below.
Quoted 93 lines
Quoted 93 lines
drivers/interconnect/qcom/icc-rpmh.c new file +48
-0+ +#include "bcm-voter.h" +#include "icc-rpmh.h" + +/** +* qcom_icc_pre_aggregate - cleans up stale values from prior icc_set +* @node: icc node to operate on +*/ +void qcom_icc_pre_aggregate (struct icc_node *node) +{ +size_t i; +struct qcom_icc_node *qn; + + qn = node->data; + +for (i =0 ; i <QCOM_ICC_NUM_BUCKETS ; i++) { + qn->sum_avg[i] =0 ; + qn->max_peak[i] =0 ; + } +} +EXPORT_SYMBOL_GPL (qcom_icc_pre_aggregate); + +/** +* qcom_icc_aggregate - aggregate bw for buckets indicated by tag +* @node: node to aggregate +* @tag: tag to indicate which buckets to aggregate +* @avg_bw: new bw to sum aggregate +* @peak_bw: new bw to max aggregate +* @agg_avg: existing aggregate avg bw val +* @agg_peak: existing aggregate peak bw val +*/ +int qcom_icc_aggregate (struct icc_node *node,u32 tag,u32 avg_bw, +u32 peak_bw,u32 *agg_avg,u32 *agg_peak) +{ +size_t i; +struct qcom_icc_node *qn; +struct qcom_icc_provider *qp; + + qn = node->data; + qp =to_qcom_provider (node->provider); + +if (!tag) + tag =QCOM_ICC_TAG_ALWAYS ; + +for (i =0 ; i <QCOM_ICC_NUM_BUCKETS ; i++) { +if (tag &BIT (i)) { + qn->sum_avg[i] += avg_bw; + qn->max_peak[i] = max_t(u32, qn->max_peak[i],
peak_bw);drivers/interconnect/qcom/icc-rpmh.c new file +44
-0+ } + } + + *agg_avg += avg_bw; + *agg_peak =max_t (u32, *agg_peak, peak_bw); + +for (i =0 ; i < qn->num_bcms; i++) +qcom_icc_bcm_voter_add (qp->voter, qn->bcms[i]); + +return 0 ; +} +EXPORT_SYMBOL_GPL (qcom_icc_aggregate); + +/** +* qcom_icc_set - set the constraints based on path +* @src: source node for the path to set constraints on +* @dst: destination node for the path to set constraints on +* +* Return: 0 on success, or an error code otherwise +*/ +int qcom_icc_set (struct icc_node *src,struct icc_node *dst) +{ +struct qcom_icc_provider *qp; +struct icc_node *node; +int ret =0 ; + +if (!src) + node = dst; +else + node = src; + + qp =to_qcom_provider (node->provider); + +qcom_icc_bcm_voter_commit (qp->voter); + +return ret; +} +EXPORT_SYMBOL_GPL (qcom_icc_set); + +/** +* qcom_icc_bcm_init - populates bcm aux data and connect qnodes +* @bcm: bcm to be initialized +* @dev: associated provider device +*
Quoted 8 lines
drivers/interconnect/qcom/icc-rpmh.c line 111
Quoted 8 lines
+ * Return: 0 on success, or an error code otherwise
+ */drivers/interconnect/qcom/icc-rpmh.c new file +6
-0+int qcom_icc_bcm_init (struct qcom_icc_bcm *bcm,struct device *dev) +{ +struct qcom_icc_node *qn; +const struct bcm_db *data; +size_t data_count; +int i;
I'll add a check to see if
bcm is already initialsed.
Quoted 39 lines
Quoted 39 lines
drivers/interconnect/qcom/icc-rpmh.c new file +16
-0+ + bcm->addr =cmd_db_read_addr (bcm->name); +if (!bcm->addr) { +dev_err (dev,"%s could not find RPMh address\n" , + bcm->name); +return -EINVAL ; + } + + data =cmd_db_read_aux_data (bcm->name, &data_count); +if (IS_ERR (data)) { +dev_err (dev,"%s command db read error (%ld)\n" , + bcm->name,PTR_ERR (data)); +return PTR_ERR (data); + } +if (!data_count) { + dev_err(dev, "%s command db missing or partial auxdata\n",
drivers/interconnect/qcom/icc-rpmh.c new file +22
-0+ bcm->name); +return -EINVAL ; + } + + bcm->aux_data.unit =le32_to_cpu (data->unit); + bcm->aux_data.width =le16_to_cpu (data->width); + bcm->aux_data.vcd = data->vcd; + bcm->aux_data.reserved = data->reserved; +INIT_LIST_HEAD (&bcm->list); +INIT_LIST_HEAD (&bcm->ws_list); + +/* +* Link Qnodes to their respective BCMs +*/ +for (i =0 ; i < bcm->num_nodes; i++) { + qn = bcm->nodes[i]; + qn->bcms[qn->num_bcms] = bcm; + qn->num_bcms++; + } + +return 0 ; +}
Quoted 8 lines
drivers/interconnect/qcom/icc-rpmh.c line 157
Quoted 8 lines
drivers/interconnect/qcom/icc-rpmh.c new file +8
-0+EXPORT_SYMBOL_GPL (qcom_icc_bcm_init); + +static struct platform_driver qcom_icc_rpmh_driver = { + .driver = { + .name ="icc_rpmh" , + }, +}; +module_platform_driver (qcom_icc_rpmh_driver);
I don't see any reason for ^^ to
be a module platform driver, will remove it and list them as a set
of helper functions.
Quoted 160 lines
Quoted 160 lines
drivers/interconnect/qcom/icc-rpmh.c new file +1
-0+MODULE_LICENSE ("GPL v2" );drivers/interconnect/qcom/icc-rpmh.h new file +30
-0@@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright (c) 2019, The Linux Foundation. All rights reserved. +* +*/ + +#ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_RPMH_H__ +#define __DRIVERS_INTERCONNECT_QCOM_ICC_RPMH_H__ + +#define to_qcom_provider (_provider) \ + container_of(_provider, struct qcom_icc_provider, provider) + +/** +* struct qcom_icc_provider - Qualcomm specific interconnect provider +* @provider: generic interconnect provider +* @dev: reference to the NoC device +* @bcms: list of bcms that maps to the provider +* @num_bcms: number of @bcms +* @voter: bcm voter targeted by this provider +*/ +struct qcom_icc_provider { +struct icc_provider provider; +struct device *dev; +struct qcom_icc_bcm **bcms; +size_t num_bcms; +struct bcm_voter *voter; +}; + +/** +* struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager (BCM)
+ * @unit: divisor used to convert bytes/sec bw value to an RPMh msg
+ * @width: multiplier used to convert bytes/sec bw value to an RPMh msg
+ * @vcd: virtual clock domain that this bcm belongs to
+ * @reserved: reserved field
+ */drivers/interconnect/qcom/icc-rpmh.h new file +14
-0+struct bcm_db { +__le32 unit; +__le16 width; +u8 vcd; +u8 reserved; +}; + +#define MAX_LINKS 128 +#define MAX_BCMS 64 +#define MAX_BCM_PER_NODE 3 +#define MAX_VCD 10 + +/* +* The AMC bucket denotes constraints that are applied to hardware when
+ *icc_set_bw()completes, whereas the WAKE and SLEEP constraints are applied
+ * when the execution environment transitions between active and low power mode.
+ */drivers/interconnect/qcom/icc-rpmh.h new file +8
-0+#define QCOM_ICC_BUCKET_AMC 0 +#define QCOM_ICC_BUCKET_WAKE 1 +#define QCOM_ICC_BUCKET_SLEEP 2 +#define QCOM_ICC_NUM_BUCKETS 3 +#define QCOM_ICC_TAG_AMC BIT(QCOM_ICC_BUCKET_AMC) +#define QCOM_ICC_TAG_WAKE BIT(QCOM_ICC_BUCKET_WAKE) +#define QCOM_ICC_TAG_SLEEP BIT(QCOM_ICC_BUCKET_SLEEP) +#define QCOM_ICC_TAG_ACTIVE_ONLY (QCOM_ICC_TAG_AMC |
QCOM_ICC_TAG_WAKE)
+#defineQCOM_ICC_TAG_ALWAYS(QCOM_ICC_TAG_AMC|QCOM_ICC_TAG_WAKE|\drivers/interconnect/qcom/icc-rpmh.h new file +35
-0+ QCOM_ICC_TAG_SLEEP) + +/** +* struct qcom_icc_node - Qualcomm specific interconnect nodes +* @name: the node name used in debugfs +* @links: an array of nodes where we can go next while traversing +* @id: a unique node identifier +* @num_links: the total number of @links +* @channels: num of channels at this node +* @buswidth: width of the interconnect between a node and the bus +* @sum_avg: current sum aggregate value of all avg bw requests +* @max_peak: current max aggregate value of all peak bw requests +* @bcms: list of bcms associated with this logical node +* @num_bcms: num of @bcms +*/ +struct qcom_icc_node { +const char *name; +u16 links[MAX_LINKS ]; +u16 id; +u16 num_links; +u16 channels; +u16 buswidth; +u64 sum_avg[QCOM_ICC_NUM_BUCKETS ]; +u64 max_peak[QCOM_ICC_NUM_BUCKETS ]; +struct qcom_icc_bcm *bcms[MAX_BCM_PER_NODE ]; +size_t num_bcms; +}; + +/** +* struct qcom_icc_bcm - Qualcomm specific hardware accelerator nodes +* known as Bus Clock Manager (BCM) +* @name: the bcm node name used to fetch BCM data from command db +* @type: latency or bandwidth bcm +* @addr: address offsets used when voting to RPMH +* @vote_x: aggregated threshold values, represents sum_bw when @type is bw bcm
+ * @vote_y: aggregated threshold values, representspeak_bwwhen @type is bw bcm
+ * @dirty: flag used to indicate whether the bcm needs to be committed
+ * @keepalive: flag used to indicate whether a keepalive is required
+ * @aux_data: auxiliary data used when calculating threshold values and
+ * communicating with RPMh
+ * @list: used to link to other bcms when compiling lists for commit
+ * @ws_list: used to keep track of bcms that may transition between wake/sleep
+ * @num_nodes: total number of @num_nodes
+ * @nodes: list ofqcom_icc_nodesthat this BCM encapsulates
+ */drivers/interconnect/qcom/icc-rpmh.h new file +31
-0+struct qcom_icc_bcm { +const char *name; +u32 type; +u32 addr; +u64 vote_x[QCOM_ICC_NUM_BUCKETS ]; +u64 vote_y[QCOM_ICC_NUM_BUCKETS ]; +bool dirty; +bool keepalive; +struct bcm_db aux_data; +struct list_head list; +struct list_head ws_list; +size_t num_nodes; +struct qcom_icc_node *nodes[]; +}; + +struct qcom_icc_fabric { +struct qcom_icc_node **nodes; +size_t num_nodes; +}; + +struct qcom_icc_desc { +struct qcom_icc_node **nodes; +size_t num_nodes; +struct qcom_icc_bcm **bcms; +size_t num_bcms; +}; + +#define DEFINE_QNODE (_name, _id, _channels, _buswidth, \ + _numlinks, ...) \ + static struct qcom_icc_node _name = { \ + .id = _id, \
Quoted 8 lines
drivers/interconnect/qcom/icc-rpmh.h
Quoted 8 lines
drivers/interconnect/qcom/icc-rpmh.h new file +4
-0+ .name = #_name, \ + .channels = _channels, \ + .buswidth = _buswidth, \ + .num_links = _numlinks, \
should be able to calculate the
num of links from VA_ARGS...
Quoted 14 lines
Quoted 14 lines
drivers/interconnect/qcom/icc-rpmh.h new file +10
-1+ .links = { __VA_ARGS__ }, \ + } + +int qcom_icc_aggregate (struct icc_node *node,u32 tag,u32 avg_bw, +u32 peak_bw,u32 *agg_avg,u32 *agg_peak); +int qcom_icc_set (struct icc_node *src,struct icc_node *dst); +int qcom_icc_bcm_init (struct qcom_icc_bcm *bcm,struct device *dev); +void qcom_icc_pre_aggregate (struct icc_node *node); + +#endif --The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
PATCH v2 5/6 interconnect: qcom: sdm845: Split qnodes into their respective NoCs
In reply to David DaiIn order to better represent the hardware and its different Network-On-Chip devices, split the sdm845 provider driver into NoC specific providers. Remove duplicate functionality already provided by the icc rpmh and bcm voter drivers to calculate and commit bandwidth requests to hardware.
Signed-off-by David Dai <[email protected]>
--- drivers/interconnect/qcom/sdm845.c | 1132 ++++++++++-------------- include/dt-bindings/interconnect/qcom,sdm845.h | 263 +++--- 2 files changed, 609 insertions(+), 786 deletions(-)
drivers/interconnect/qcom/sdm845.c +475 -657
@@ -5,283 +5,285 @@*/ #include <asm/div64.h> -#include <dt-bindings/interconnect/qcom,sdm845.h> #include <linux/device.h> #include <linux/interconnect.h> #include <linux/interconnect-provider.h> #include <linux/io.h> #include <linux/module.h> #include <linux/of_device.h> -#include <linux/of_platform.h> -#include <linux/platform_device.h> #include <linux/sort.h> -#include <soc/qcom/cmd-db.h> -#include <soc/qcom/rpmh.h> -#include <soc/qcom/tcs.h> - -#define to_qcom_provider (_provider) \ - container_of(_provider, struct qcom_icc_provider, provider) - -struct qcom_icc_provider { -struct icc_provider provider; -struct device *dev; -struct qcom_icc_bcm **bcms; -size_t num_bcms; -}; - -/** -* struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager (BCM) -* @unit: divisor used to convert bytes/sec bw value to an RPMh msg -* @width: multiplier used to convert bytes/sec bw value to an RPMh msg -* @vcd: virtual clock domain that this bcm belongs to -* @reserved: reserved field -*/ -struct bcm_db { -__le32 unit; -__le16 width; -u8 vcd; -u8 reserved; -}; - -#define SDM845_MAX_LINKS 43 -#define SDM845_MAX_BCMS 30 -#define SDM845_MAX_BCM_PER_NODE 2 -#define SDM845_MAX_VCD 10 - -/* -* The AMC bucket denotes constraints that are applied to hardware when -* icc_set_bw() completes, whereas the WAKE and SLEEP constraints are applied -* when the execution environment transitions between active and low power mode. -*/ -#define QCOM_ICC_BUCKET_AMC 0 -#define QCOM_ICC_BUCKET_WAKE 1 -#define QCOM_ICC_BUCKET_SLEEP 2 -#define QCOM_ICC_NUM_BUCKETS 3 -#define QCOM_ICC_TAG_AMC BIT(QCOM_ICC_BUCKET_AMC) -#define QCOM_ICC_TAG_WAKE BIT(QCOM_ICC_BUCKET_WAKE) -#define QCOM_ICC_TAG_SLEEP BIT(QCOM_ICC_BUCKET_SLEEP) -#define QCOM_ICC_TAG_ACTIVE_ONLY (QCOM_ICC_TAG_AMC | QCOM_ICC_TAG_WAKE) -#define QCOM_ICC_TAG_ALWAYS (QCOM_ICC_TAG_AMC | QCOM_ICC_TAG_WAKE |\ - QCOM_ICC_TAG_SLEEP) - -/** -* struct qcom_icc_node - Qualcomm specific interconnect nodes -* @name: the node name used in debugfs -* @links: an array of nodes where we can go next while traversing -* @id: a unique node identifier -* @num_links: the total number of @links -* @channels: num of channels at this node -* @buswidth: width of the interconnect between a node and the bus -* @sum_avg: current sum aggregate value of all avg bw requests -* @max_peak: current max aggregate value of all peak bw requests -* @bcms: list of bcms associated with this logical node -* @num_bcms: num of @bcms -*/ -struct qcom_icc_node { -const char *name; -u16 links[SDM845_MAX_LINKS ]; -u16 id; -u16 num_links; -u16 channels; -u16 buswidth; -u64 sum_avg[QCOM_ICC_NUM_BUCKETS ]; -u64 max_peak[QCOM_ICC_NUM_BUCKETS ]; -struct qcom_icc_bcm *bcms[SDM845_MAX_BCM_PER_NODE ]; -size_t num_bcms; -}; - -/** -* struct qcom_icc_bcm - Qualcomm specific hardware accelerator nodes -* known as Bus Clock Manager (BCM) -* @name: the bcm node name used to fetch BCM data from command db -* @type: latency or bandwidth bcm -* @addr: address offsets used when voting to RPMH -* @vote_x: aggregated threshold values, represents sum_bw when @type is bw bcm -* @vote_y: aggregated threshold values, represents peak_bw when @type is bw bcm -* @dirty: flag used to indicate whether the bcm needs to be committed -* @keepalive: flag used to indicate whether a keepalive is required -* @aux_data: auxiliary data used when calculating threshold values and -* communicating with RPMh -* @list: used to link to other bcms when compiling lists for commit -* @num_nodes: total number of @num_nodes -* @nodes: list of qcom_icc_nodes that this BCM encapsulates -*/ -struct qcom_icc_bcm { -const char *name; -u32 type; -u32 addr; -u64 vote_x[QCOM_ICC_NUM_BUCKETS ]; -u64 vote_y[QCOM_ICC_NUM_BUCKETS ]; -bool dirty; -bool keepalive; -struct bcm_db aux_data; -struct list_head list; -size_t num_nodes; -struct qcom_icc_node *nodes[]; -}; - -struct qcom_icc_fabric { -struct qcom_icc_node **nodes; -size_t num_nodes; -}; +#include <dt-bindings/interconnect/qcom,sdm845.h> -struct qcom_icc_desc { -struct qcom_icc_node **nodes; -size_t num_nodes; -struct qcom_icc_bcm **bcms; -size_t num_bcms; +#include "bcm-voter.h" +#include "icc-rpmh.h" + +enum { +SDM845_MASTER_A1NOC_CFG =1 , +SDM845_MASTER_BLSP_1 , +SDM845_MASTER_TSIF , +SDM845_MASTER_SDCC_2 , +SDM845_MASTER_SDCC_4 , +SDM845_MASTER_UFS_CARD , +SDM845_MASTER_UFS_MEM , +SDM845_MASTER_PCIE_0 , +SDM845_MASTER_A2NOC_CFG , +SDM845_MASTER_QDSS_BAM , +SDM845_MASTER_BLSP_2 , +SDM845_MASTER_CNOC_A2NOC , +SDM845_MASTER_CRYPTO , +SDM845_MASTER_IPA , +SDM845_MASTER_PCIE_1 , +SDM845_MASTER_QDSS_ETR , +SDM845_MASTER_USB3_0 , +SDM845_MASTER_USB3_1 , +SDM845_MASTER_CAMNOC_HF0_UNCOMP , +SDM845_MASTER_CAMNOC_HF1_UNCOMP , +SDM845_MASTER_CAMNOC_SF_UNCOMP , +SDM845_MASTER_SPDM , +SDM845_MASTER_TIC , +SDM845_MASTER_SNOC_CNOC , +SDM845_MASTER_QDSS_DAP , +SDM845_MASTER_CNOC_DC_NOC , +SDM845_MASTER_APPSS_PROC , +SDM845_MASTER_GNOC_CFG , +SDM845_MASTER_LLCC , +SDM845_MASTER_TCU_0 , +SDM845_MASTER_MEM_NOC_CFG , +SDM845_MASTER_GNOC_MEM_NOC , +SDM845_MASTER_MNOC_HF_MEM_NOC , +SDM845_MASTER_MNOC_SF_MEM_NOC , +SDM845_MASTER_SNOC_GC_MEM_NOC , +SDM845_MASTER_SNOC_SF_MEM_NOC , +SDM845_MASTER_GFX3D , +SDM845_MASTER_CNOC_MNOC_CFG , +SDM845_MASTER_CAMNOC_HF0 , +SDM845_MASTER_CAMNOC_HF1 , +SDM845_MASTER_CAMNOC_SF , +SDM845_MASTER_MDP0 , +SDM845_MASTER_MDP1 , +SDM845_MASTER_ROTATOR , +SDM845_MASTER_VIDEO_P0 , +SDM845_MASTER_VIDEO_P1 , +SDM845_MASTER_VIDEO_PROC , +SDM845_MASTER_SNOC_CFG , +SDM845_MASTER_A1NOC_SNOC , +SDM845_MASTER_A2NOC_SNOC , +SDM845_MASTER_GNOC_SNOC , +SDM845_MASTER_MEM_NOC_SNOC , +SDM845_MASTER_ANOC_PCIE_SNOC , +SDM845_MASTER_PIMEM , +SDM845_MASTER_GIC , +SDM845_SLAVE_A1NOC_SNOC , +SDM845_SLAVE_SERVICE_A1NOC , +SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC , +SDM845_SLAVE_A2NOC_SNOC , +SDM845_SLAVE_ANOC_PCIE_SNOC , +SDM845_SLAVE_SERVICE_A2NOC , +SDM845_SLAVE_CAMNOC_UNCOMP , +SDM845_SLAVE_A1NOC_CFG , +SDM845_SLAVE_A2NOC_CFG , +SDM845_SLAVE_AOP , +SDM845_SLAVE_AOSS , +SDM845_SLAVE_CAMERA_CFG , +SDM845_SLAVE_CLK_CTL , +SDM845_SLAVE_CDSP_CFG , +SDM845_SLAVE_RBCPR_CX_CFG , +SDM845_SLAVE_CRYPTO_0_CFG , +SDM845_SLAVE_DCC_CFG , +SDM845_SLAVE_CNOC_DDRSS , +SDM845_SLAVE_DISPLAY_CFG , +SDM845_SLAVE_GLM , +SDM845_SLAVE_GFX3D_CFG , +SDM845_SLAVE_IMEM_CFG , +SDM845_SLAVE_IPA_CFG , +SDM845_SLAVE_CNOC_MNOC_CFG , +SDM845_SLAVE_PCIE_0_CFG , +SDM845_SLAVE_PCIE_1_CFG , +SDM845_SLAVE_PDM , +SDM845_SLAVE_SOUTH_PHY_CFG , +SDM845_SLAVE_PIMEM_CFG , +SDM845_SLAVE_PRNG , +SDM845_SLAVE_QDSS_CFG , +SDM845_SLAVE_BLSP_2 , +SDM845_SLAVE_BLSP_1 , +SDM845_SLAVE_SDCC_2 , +SDM845_SLAVE_SDCC_4 , +SDM845_SLAVE_SNOC_CFG , +SDM845_SLAVE_SPDM_WRAPPER , +SDM845_SLAVE_SPSS_CFG , +SDM845_SLAVE_TCSR , +SDM845_SLAVE_TLMM_NORTH , +SDM845_SLAVE_TLMM_SOUTH , +SDM845_SLAVE_TSIF , +SDM845_SLAVE_UFS_CARD_CFG , +SDM845_SLAVE_UFS_MEM_CFG , +SDM845_SLAVE_USB3_0 , +SDM845_SLAVE_USB3_1 , +SDM845_SLAVE_VENUS_CFG , +SDM845_SLAVE_VSENSE_CTRL_CFG , +SDM845_SLAVE_CNOC_A2NOC , +SDM845_SLAVE_SERVICE_CNOC , +SDM845_SLAVE_LLCC_CFG , +SDM845_SLAVE_MEM_NOC_CFG , +SDM845_SLAVE_GNOC_SNOC , +SDM845_SLAVE_GNOC_MEM_NOC , +SDM845_SLAVE_SERVICE_GNOC , +SDM845_SLAVE_EBI1 , +SDM845_SLAVE_MSS_PROC_MS_MPU_CFG , +SDM845_SLAVE_MEM_NOC_GNOC , +SDM845_SLAVE_LLCC , +SDM845_SLAVE_MEM_NOC_SNOC , +SDM845_SLAVE_SERVICE_MEM_NOC , +SDM845_SLAVE_MNOC_SF_MEM_NOC , +SDM845_SLAVE_MNOC_HF_MEM_NOC , +SDM845_SLAVE_SERVICE_MNOC , +SDM845_SLAVE_APPSS , +SDM845_SLAVE_SNOC_CNOC , +SDM845_SLAVE_SNOC_MEM_NOC_GC , +SDM845_SLAVE_SNOC_MEM_NOC_SF , +SDM845_SLAVE_IMEM , +SDM845_SLAVE_PCIE_0 , +SDM845_SLAVE_PCIE_1 , +SDM845_SLAVE_PIMEM , +SDM845_SLAVE_SERVICE_SNOC , +SDM845_SLAVE_QDSS_STM , +SDM845_SLAVE_TCU }; -#define DEFINE_QNODE (_name, _id, _channels, _buswidth, \ - _numlinks, ...) \ - static struct qcom_icc_node _name = { \ - .id = _id, \ - .name = #_name, \ - .channels = _channels, \ - .buswidth = _buswidth, \ - .num_links = _numlinks, \ - .links = { __VA_ARGS__ }, \ - } - -DEFINE_QNODE (qhm_a1noc_cfg,MASTER_A1NOC_CFG ,1 ,4 ,1 ,SLAVE_SERVICE_A1NOC ); -DEFINE_QNODE (qhm_qup1,MASTER_BLSP_1 ,1 ,4 ,1 ,SLAVE_A1NOC_SNOC ); -DEFINE_QNODE (qhm_tsif,MASTER_TSIF ,1 ,4 ,1 ,SLAVE_A1NOC_SNOC ); -DEFINE_QNODE (xm_sdc2,MASTER_SDCC_2 ,1 ,8 ,1 ,SLAVE_A1NOC_SNOC ); -DEFINE_QNODE (xm_sdc4,MASTER_SDCC_4 ,1 ,8 ,1 ,SLAVE_A1NOC_SNOC ); -DEFINE_QNODE (xm_ufs_card,MASTER_UFS_CARD ,1 ,8 ,1 ,SLAVE_A1NOC_SNOC ); -DEFINE_QNODE (xm_ufs_mem,MASTER_UFS_MEM ,1 ,8 ,1 ,SLAVE_A1NOC_SNOC ); -DEFINE_QNODE (xm_pcie_0,MASTER_PCIE_0 ,1 ,8 ,1 ,SLAVE_ANOC_PCIE_A1NOC_SNOC ); -DEFINE_QNODE (qhm_a2noc_cfg,MASTER_A2NOC_CFG ,1 ,4 ,1 ,SLAVE_SERVICE_A2NOC ); -DEFINE_QNODE (qhm_qdss_bam,MASTER_QDSS_BAM ,1 ,4 ,1 ,SLAVE_A2NOC_SNOC ); -DEFINE_QNODE (qhm_qup2,MASTER_BLSP_2 ,1 ,4 ,1 ,SLAVE_A2NOC_SNOC ); -DEFINE_QNODE (qnm_cnoc,MASTER_CNOC_A2NOC ,1 ,8 ,1 ,SLAVE_A2NOC_SNOC ); -DEFINE_QNODE (qxm_crypto,MASTER_CRYPTO ,1 ,8 ,1 ,SLAVE_A2NOC_SNOC ); -DEFINE_QNODE (qxm_ipa,MASTER_IPA ,1 ,8 ,1 ,SLAVE_A2NOC_SNOC ); -DEFINE_QNODE (xm_pcie3_1,MASTER_PCIE_1 ,1 ,8 ,1 ,SLAVE_ANOC_PCIE_SNOC ); -DEFINE_QNODE (xm_qdss_etr,MASTER_QDSS_ETR ,1 ,8 ,1 ,SLAVE_A2NOC_SNOC ); -DEFINE_QNODE (xm_usb3_0,MASTER_USB3_0 ,1 ,8 ,1 ,SLAVE_A2NOC_SNOC ); -DEFINE_QNODE (xm_usb3_1,MASTER_USB3_1 ,1 ,8 ,1 ,SLAVE_A2NOC_SNOC ); -DEFINE_QNODE (qxm_camnoc_hf0_uncomp,MASTER_CAMNOC_HF0_UNCOMP ,1 ,32 ,1 ,SLAVE_CAMNOC_UNCOMP ); -DEFINE_QNODE (qxm_camnoc_hf1_uncomp,MASTER_CAMNOC_HF1_UNCOMP ,1 ,32 ,1 ,SLAVE_CAMNOC_UNCOMP ); -DEFINE_QNODE (qxm_camnoc_sf_uncomp,MASTER_CAMNOC_SF_UNCOMP ,1 ,32 ,1 ,SLAVE_CAMNOC_UNCOMP ); -DEFINE_QNODE (qhm_spdm,MASTER_SPDM ,1 ,4 ,1 ,SLAVE_CNOC_A2NOC ); -DEFINE_QNODE (qhm_tic,MASTER_TIC ,1 ,4 ,43 ,SLAVE_A1NOC_CFG ,SLAVE_A2NOC_CFG ,SLAVE_AOP ,SLAVE_AOSS ,SLAVE_CAMERA_CFG ,SLAVE_CLK_CTL ,SLAVE_CDSP_CFG ,SLAVE_RBCPR_CX_CFG ,SLAVE_CRYPTO_0_CFG ,SLAVE_DCC_CFG ,SLAVE_CNOC_DDRSS ,SLAVE_DISPLAY_CFG ,SLAVE_GLM ,SLAVE_GFX3D_CFG ,SLAVE_IMEM_CFG ,SLAVE_IPA_CFG ,SLAVE_CNOC_MNOC_CFG ,SLAVE_PCIE_0_CFG ,SLAVE_PCIE_1_CFG ,SLAVE_PDM ,SLAVE_SOUTH_PHY_CFG ,SLAVE_PIMEM_CFG ,SLAVE_PRNG ,SLAVE_QDSS_CFG ,SLAVE_BLSP_2 ,SLAVE_BLSP_1 ,SLAVE_SDCC_2 ,SLAVE_SDCC_4 ,SLAVE_SNOC_CFG ,SLAVE_SPDM_WRAPPER ,SLAVE_SPSS_CFG ,SLAVE_TCSR ,SLAVE_TLMM_NORTH ,SLAVE_TLMM_SOUTH ,SLAVE_TSIF ,SLAVE_UFS_CARD_CFG ,SLAVE_UFS_MEM_CFG ,SLAVE_USB3_0 ,SLAVE_USB3_1 ,SLAVE_VENUS_CFG ,SLAVE_VSENSE_CTRL_CFG ,SLAVE_CNOC_A2NOC ,SLAVE_SERVICE_CNOC ); -DEFINE_QNODE (qnm_snoc,MASTER_SNOC_CNOC ,1 ,8 ,42 ,SLAVE_A1NOC_CFG ,SLAVE_A2NOC_CFG ,SLAVE_AOP ,SLAVE_AOSS ,SLAVE_CAMERA_CFG ,SLAVE_CLK_CTL ,SLAVE_CDSP_CFG ,SLAVE_RBCPR_CX_CFG ,SLAVE_CRYPTO_0_CFG ,SLAVE_DCC_CFG ,SLAVE_CNOC_DDRSS ,SLAVE_DISPLAY_CFG ,SLAVE_GLM ,SLAVE_GFX3D_CFG ,SLAVE_IMEM_CFG ,SLAVE_IPA_CFG ,SLAVE_CNOC_MNOC_CFG ,SLAVE_PCIE_0_CFG ,SLAVE_PCIE_1_CFG ,SLAVE_PDM ,SLAVE_SOUTH_PHY_CFG ,SLAVE_PIMEM_CFG ,SLAVE_PRNG ,SLAVE_QDSS_CFG ,SLAVE_BLSP_2 ,SLAVE_BLSP_1 ,SLAVE_SDCC_2 ,SLAVE_SDCC_4 ,SLAVE_SNOC_CFG ,SLAVE_SPDM_WRAPPER ,SLAVE_SPSS_CFG ,SLAVE_TCSR ,SLAVE_TLMM_NORTH ,SLAVE_TLMM_SOUTH ,SLAVE_TSIF ,SLAVE_UFS_CARD_CFG ,SLAVE_UFS_MEM_CFG ,SLAVE_USB3_0 ,SLAVE_USB3_1 ,SLAVE_VENUS_CFG ,SLAVE_VSENSE_CTRL_CFG ,SLAVE_SERVICE_CNOC ); -DEFINE_QNODE (xm_qdss_dap,MASTER_QDSS_DAP ,1 ,8 ,43 ,SLAVE_A1NOC_CFG ,SLAVE_A2NOC_CFG ,SLAVE_AOP ,SLAVE_AOSS ,SLAVE_CAMERA_CFG ,SLAVE_CLK_CTL ,SLAVE_CDSP_CFG ,SLAVE_RBCPR_CX_CFG ,SLAVE_CRYPTO_0_CFG ,SLAVE_DCC_CFG ,SLAVE_CNOC_DDRSS ,SLAVE_DISPLAY_CFG ,SLAVE_GLM ,SLAVE_GFX3D_CFG ,SLAVE_IMEM_CFG ,SLAVE_IPA_CFG ,SLAVE_CNOC_MNOC_CFG ,SLAVE_PCIE_0_CFG ,SLAVE_PCIE_1_CFG ,SLAVE_PDM ,SLAVE_SOUTH_PHY_CFG ,SLAVE_PIMEM_CFG ,SLAVE_PRNG ,SLAVE_QDSS_CFG ,SLAVE_BLSP_2 ,SLAVE_BLSP_1 ,SLAVE_SDCC_2 ,SLAVE_SDCC_4 ,SLAVE_SNOC_CFG ,SLAVE_SPDM_WRAPPER ,SLAVE_SPSS_CFG ,SLAVE_TCSR ,SLAVE_TLMM_NORTH ,SLAVE_TLMM_SOUTH ,SLAVE_TSIF ,SLAVE_UFS_CARD_CFG ,SLAVE_UFS_MEM_CFG ,SLAVE_USB3_0 ,SLAVE_USB3_1 ,SLAVE_VENUS_CFG ,SLAVE_VSENSE_CTRL_CFG ,SLAVE_CNOC_A2NOC ,SLAVE_SERVICE_CNOC ); -DEFINE_QNODE (qhm_cnoc,MASTER_CNOC_DC_NOC ,1 ,4 ,2 ,SLAVE_LLCC_CFG ,SLAVE_MEM_NOC_CFG ); -DEFINE_QNODE (acm_l3,MASTER_APPSS_PROC ,1 ,16 ,3 ,SLAVE_GNOC_SNOC ,SLAVE_GNOC_MEM_NOC ,SLAVE_SERVICE_GNOC ); -DEFINE_QNODE (pm_gnoc_cfg,MASTER_GNOC_CFG ,1 ,4 ,1 ,SLAVE_SERVICE_GNOC ); -DEFINE_QNODE (llcc_mc,MASTER_LLCC ,4 ,4 ,1 ,SLAVE_EBI1 ); -DEFINE_QNODE (acm_tcu,MASTER_TCU_0 ,1 ,8 ,3 ,SLAVE_MEM_NOC_GNOC ,SLAVE_LLCC ,SLAVE_MEM_NOC_SNOC ); -DEFINE_QNODE (qhm_memnoc_cfg,MASTER_MEM_NOC_CFG ,1 ,4 ,2 ,SLAVE_MSS_PROC_MS_MPU_CFG ,SLAVE_SERVICE_MEM_NOC ); -DEFINE_QNODE (qnm_apps,MASTER_GNOC_MEM_NOC ,2 ,32 ,1 ,SLAVE_LLCC ); -DEFINE_QNODE (qnm_mnoc_hf,MASTER_MNOC_HF_MEM_NOC ,2 ,32 ,2 ,SLAVE_MEM_NOC_GNOC ,SLAVE_LLCC ); -DEFINE_QNODE (qnm_mnoc_sf,MASTER_MNOC_SF_MEM_NOC ,1 ,32 ,3 ,SLAVE_MEM_NOC_GNOC ,SLAVE_LLCC ,SLAVE_MEM_NOC_SNOC ); -DEFINE_QNODE (qnm_snoc_gc,MASTER_SNOC_GC_MEM_NOC ,1 ,8 ,1 ,SLAVE_LLCC ); -DEFINE_QNODE (qnm_snoc_sf,MASTER_SNOC_SF_MEM_NOC ,1 ,16 ,2 ,SLAVE_MEM_NOC_GNOC ,SLAVE_LLCC ); -DEFINE_QNODE (qxm_gpu,MASTER_GFX3D ,2 ,32 ,3 ,SLAVE_MEM_NOC_GNOC ,SLAVE_LLCC ,SLAVE_MEM_NOC_SNOC ); -DEFINE_QNODE (qhm_mnoc_cfg,MASTER_CNOC_MNOC_CFG ,1 ,4 ,1 ,SLAVE_SERVICE_MNOC ); -DEFINE_QNODE (qxm_camnoc_hf0,MASTER_CAMNOC_HF0 ,1 ,32 ,1 ,SLAVE_MNOC_HF_MEM_NOC ); -DEFINE_QNODE (qxm_camnoc_hf1,MASTER_CAMNOC_HF1 ,1 ,32 ,1 ,SLAVE_MNOC_HF_MEM_NOC ); -DEFINE_QNODE (qxm_camnoc_sf,MASTER_CAMNOC_SF ,1 ,32 ,1 ,SLAVE_MNOC_SF_MEM_NOC ); -DEFINE_QNODE (qxm_mdp0,MASTER_MDP0 ,1 ,32 ,1 ,SLAVE_MNOC_HF_MEM_NOC ); -DEFINE_QNODE (qxm_mdp1,MASTER_MDP1 ,1 ,32 ,1 ,SLAVE_MNOC_HF_MEM_NOC ); -DEFINE_QNODE (qxm_rot,MASTER_ROTATOR ,1 ,32 ,1 ,SLAVE_MNOC_SF_MEM_NOC ); -DEFINE_QNODE (qxm_venus0,MASTER_VIDEO_P0 ,1 ,32 ,1 ,SLAVE_MNOC_SF_MEM_NOC ); -DEFINE_QNODE (qxm_venus1,MASTER_VIDEO_P1 ,1 ,32 ,1 ,SLAVE_MNOC_SF_MEM_NOC ); -DEFINE_QNODE (qxm_venus_arm9,MASTER_VIDEO_PROC ,1 ,8 ,1 ,SLAVE_MNOC_SF_MEM_NOC ); -DEFINE_QNODE (qhm_snoc_cfg,MASTER_SNOC_CFG ,1 ,4 ,1 ,SLAVE_SERVICE_SNOC ); -DEFINE_QNODE (qnm_aggre1_noc,MASTER_A1NOC_SNOC ,1 ,16 ,6 ,SLAVE_APPSS ,SLAVE_SNOC_CNOC ,SLAVE_SNOC_MEM_NOC_SF ,SLAVE_IMEM ,SLAVE_PIMEM ,SLAVE_QDSS_STM ); -DEFINE_QNODE (qnm_aggre2_noc,MASTER_A2NOC_SNOC ,1 ,16 ,9 ,SLAVE_APPSS ,SLAVE_SNOC_CNOC ,SLAVE_SNOC_MEM_NOC_SF ,SLAVE_IMEM ,SLAVE_PCIE_0 ,SLAVE_PCIE_1 ,SLAVE_PIMEM ,SLAVE_QDSS_STM ,SLAVE_TCU ); -DEFINE_QNODE (qnm_gladiator_sodv,MASTER_GNOC_SNOC ,1 ,8 ,8 ,SLAVE_APPSS ,SLAVE_SNOC_CNOC ,SLAVE_IMEM ,SLAVE_PCIE_0 ,SLAVE_PCIE_1 ,SLAVE_PIMEM ,SLAVE_QDSS_STM ,SLAVE_TCU ); -DEFINE_QNODE (qnm_memnoc,MASTER_MEM_NOC_SNOC ,1 ,8 ,5 ,SLAVE_APPSS ,SLAVE_SNOC_CNOC ,SLAVE_IMEM ,SLAVE_PIMEM ,SLAVE_QDSS_STM ); -DEFINE_QNODE (qnm_pcie_anoc,MASTER_ANOC_PCIE_SNOC ,1 ,16 ,5 ,SLAVE_APPSS ,SLAVE_SNOC_CNOC ,SLAVE_SNOC_MEM_NOC_SF ,SLAVE_IMEM ,SLAVE_QDSS_STM ); -DEFINE_QNODE (qxm_pimem,MASTER_PIMEM ,1 ,8 ,2 ,SLAVE_SNOC_MEM_NOC_GC ,SLAVE_IMEM ); -DEFINE_QNODE (xm_gic,MASTER_GIC ,1 ,8 ,2 ,SLAVE_SNOC_MEM_NOC_GC ,SLAVE_IMEM ); -DEFINE_QNODE (qns_a1noc_snoc,SLAVE_A1NOC_SNOC ,1 ,16 ,1 ,MASTER_A1NOC_SNOC ); -DEFINE_QNODE (srvc_aggre1_noc,SLAVE_SERVICE_A1NOC ,1 ,4 ,0 ); -DEFINE_QNODE (qns_pcie_a1noc_snoc,SLAVE_ANOC_PCIE_A1NOC_SNOC ,1 ,16 ,1 ,MASTER_ANOC_PCIE_SNOC ); -DEFINE_QNODE (qns_a2noc_snoc,SLAVE_A2NOC_SNOC ,1 ,16 ,1 ,MASTER_A2NOC_SNOC ); -DEFINE_QNODE (qns_pcie_snoc,SLAVE_ANOC_PCIE_SNOC ,1 ,16 ,1 ,MASTER_ANOC_PCIE_SNOC ); -DEFINE_QNODE (srvc_aggre2_noc,SLAVE_SERVICE_A2NOC ,1 ,4 ,0 ); -DEFINE_QNODE (qns_camnoc_uncomp,SLAVE_CAMNOC_UNCOMP ,1 ,32 ,0 ); -DEFINE_QNODE (qhs_a1_noc_cfg,SLAVE_A1NOC_CFG ,1 ,4 ,1 ,MASTER_A1NOC_CFG ); -DEFINE_QNODE (qhs_a2_noc_cfg,SLAVE_A2NOC_CFG ,1 ,4 ,1 ,MASTER_A2NOC_CFG ); -DEFINE_QNODE (qhs_aop,SLAVE_AOP ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_aoss,SLAVE_AOSS ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_camera_cfg,SLAVE_CAMERA_CFG ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_clk_ctl,SLAVE_CLK_CTL ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_compute_dsp_cfg,SLAVE_CDSP_CFG ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_cpr_cx,SLAVE_RBCPR_CX_CFG ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_crypto0_cfg,SLAVE_CRYPTO_0_CFG ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_dcc_cfg,SLAVE_DCC_CFG ,1 ,4 ,1 ,MASTER_CNOC_DC_NOC ); -DEFINE_QNODE (qhs_ddrss_cfg,SLAVE_CNOC_DDRSS ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_display_cfg,SLAVE_DISPLAY_CFG ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_glm,SLAVE_GLM ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_gpuss_cfg,SLAVE_GFX3D_CFG ,1 ,8 ,0 ); -DEFINE_QNODE (qhs_imem_cfg,SLAVE_IMEM_CFG ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_ipa,SLAVE_IPA_CFG ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_mnoc_cfg,SLAVE_CNOC_MNOC_CFG ,1 ,4 ,1 ,MASTER_CNOC_MNOC_CFG ); -DEFINE_QNODE (qhs_pcie0_cfg,SLAVE_PCIE_0_CFG ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_pcie_gen3_cfg,SLAVE_PCIE_1_CFG ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_pdm,SLAVE_PDM ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_phy_refgen_south,SLAVE_SOUTH_PHY_CFG ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_pimem_cfg,SLAVE_PIMEM_CFG ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_prng,SLAVE_PRNG ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_qdss_cfg,SLAVE_QDSS_CFG ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_qupv3_north,SLAVE_BLSP_2 ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_qupv3_south,SLAVE_BLSP_1 ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_sdc2,SLAVE_SDCC_2 ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_sdc4,SLAVE_SDCC_4 ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_snoc_cfg,SLAVE_SNOC_CFG ,1 ,4 ,1 ,MASTER_SNOC_CFG ); -DEFINE_QNODE (qhs_spdm,SLAVE_SPDM_WRAPPER ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_spss_cfg,SLAVE_SPSS_CFG ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_tcsr,SLAVE_TCSR ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_tlmm_north,SLAVE_TLMM_NORTH ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_tlmm_south,SLAVE_TLMM_SOUTH ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_tsif,SLAVE_TSIF ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_ufs_card_cfg,SLAVE_UFS_CARD_CFG ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_ufs_mem_cfg,SLAVE_UFS_MEM_CFG ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_usb3_0,SLAVE_USB3_0 ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_usb3_1,SLAVE_USB3_1 ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_venus_cfg,SLAVE_VENUS_CFG ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_vsense_ctrl_cfg,SLAVE_VSENSE_CTRL_CFG ,1 ,4 ,0 ); -DEFINE_QNODE (qns_cnoc_a2noc,SLAVE_CNOC_A2NOC ,1 ,8 ,1 ,MASTER_CNOC_A2NOC ); -DEFINE_QNODE (srvc_cnoc,SLAVE_SERVICE_CNOC ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_llcc,SLAVE_LLCC_CFG ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_memnoc,SLAVE_MEM_NOC_CFG ,1 ,4 ,1 ,MASTER_MEM_NOC_CFG ); -DEFINE_QNODE (qns_gladiator_sodv,SLAVE_GNOC_SNOC ,1 ,8 ,1 ,MASTER_GNOC_SNOC ); -DEFINE_QNODE (qns_gnoc_memnoc,SLAVE_GNOC_MEM_NOC ,2 ,32 ,1 ,MASTER_GNOC_MEM_NOC ); -DEFINE_QNODE (srvc_gnoc,SLAVE_SERVICE_GNOC ,1 ,4 ,0 ); -DEFINE_QNODE (ebi,SLAVE_EBI1 ,4 ,4 ,0 ); -DEFINE_QNODE (qhs_mdsp_ms_mpu_cfg,SLAVE_MSS_PROC_MS_MPU_CFG ,1 ,4 ,0 ); -DEFINE_QNODE (qns_apps_io,SLAVE_MEM_NOC_GNOC ,1 ,32 ,0 ); -DEFINE_QNODE (qns_llcc,SLAVE_LLCC ,4 ,16 ,1 ,MASTER_LLCC ); -DEFINE_QNODE (qns_memnoc_snoc,SLAVE_MEM_NOC_SNOC ,1 ,8 ,1 ,MASTER_MEM_NOC_SNOC ); -DEFINE_QNODE (srvc_memnoc,SLAVE_SERVICE_MEM_NOC ,1 ,4 ,0 ); -DEFINE_QNODE (qns2_mem_noc,SLAVE_MNOC_SF_MEM_NOC ,1 ,32 ,1 ,MASTER_MNOC_SF_MEM_NOC ); -DEFINE_QNODE (qns_mem_noc_hf,SLAVE_MNOC_HF_MEM_NOC ,2 ,32 ,1 ,MASTER_MNOC_HF_MEM_NOC ); -DEFINE_QNODE (srvc_mnoc,SLAVE_SERVICE_MNOC ,1 ,4 ,0 ); -DEFINE_QNODE (qhs_apss,SLAVE_APPSS ,1 ,8 ,0 ); -DEFINE_QNODE (qns_cnoc,SLAVE_SNOC_CNOC ,1 ,8 ,1 ,MASTER_SNOC_CNOC ); -DEFINE_QNODE (qns_memnoc_gc,SLAVE_SNOC_MEM_NOC_GC ,1 ,8 ,1 ,MASTER_SNOC_GC_MEM_NOC ); -DEFINE_QNODE (qns_memnoc_sf,SLAVE_SNOC_MEM_NOC_SF ,1 ,16 ,1 ,MASTER_SNOC_SF_MEM_NOC ); -DEFINE_QNODE (qxs_imem,SLAVE_IMEM ,1 ,8 ,0 ); -DEFINE_QNODE (qxs_pcie,SLAVE_PCIE_0 ,1 ,8 ,0 ); -DEFINE_QNODE (qxs_pcie_gen3,SLAVE_PCIE_1 ,1 ,8 ,0 ); -DEFINE_QNODE (qxs_pimem,SLAVE_PIMEM ,1 ,8 ,0 ); -DEFINE_QNODE (srvc_snoc,SLAVE_SERVICE_SNOC ,1 ,4 ,0 ); -DEFINE_QNODE (xs_qdss_stm,SLAVE_QDSS_STM ,1 ,4 ,0 ); -DEFINE_QNODE (xs_sys_tcu_cfg,SLAVE_TCU ,1 ,8 ,0 ); - -#define DEFINE_QBCM (_name, _bcmname, _keepalive, _numnodes, ...) \ - static struct qcom_icc_bcm _name = { \ - .name = _bcmname, \ - .keepalive = _keepalive, \ - .num_nodes = _numnodes, \ - .nodes = { __VA_ARGS__ }, \ - } +DEFINE_QNODE (qhm_a1noc_cfg,SDM845_MASTER_A1NOC_CFG ,1 ,4 ,1 ,SDM845_SLAVE_SERVICE_A1NOC ); +DEFINE_QNODE (qhm_qup1,SDM845_MASTER_BLSP_1 ,1 ,4 ,1 ,SDM845_SLAVE_A1NOC_SNOC ); +DEFINE_QNODE (qhm_tsif,SDM845_MASTER_TSIF ,1 ,4 ,1 ,SDM845_SLAVE_A1NOC_SNOC ); +DEFINE_QNODE (xm_sdc2,SDM845_MASTER_SDCC_2 ,1 ,8 ,1 ,SDM845_SLAVE_A1NOC_SNOC ); +DEFINE_QNODE (xm_sdc4,SDM845_MASTER_SDCC_4 ,1 ,8 ,1 ,SDM845_SLAVE_A1NOC_SNOC ); +DEFINE_QNODE (xm_ufs_card,SDM845_MASTER_UFS_CARD ,1 ,8 ,1 ,SDM845_SLAVE_A1NOC_SNOC ); +DEFINE_QNODE (xm_ufs_mem,SDM845_MASTER_UFS_MEM ,1 ,8 ,1 ,SDM845_SLAVE_A1NOC_SNOC ); +DEFINE_QNODE (xm_pcie_0,SDM845_MASTER_PCIE_0 ,1 ,8 ,1 ,SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC ); +DEFINE_QNODE (qhm_a2noc_cfg,SDM845_MASTER_A2NOC_CFG ,1 ,4 ,1 ,SDM845_SLAVE_SERVICE_A2NOC ); +DEFINE_QNODE (qhm_qdss_bam,SDM845_MASTER_QDSS_BAM ,1 ,4 ,1 ,SDM845_SLAVE_A2NOC_SNOC ); +DEFINE_QNODE (qhm_qup2,SDM845_MASTER_BLSP_2 ,1 ,4 ,1 ,SDM845_SLAVE_A2NOC_SNOC ); +DEFINE_QNODE (qnm_cnoc,SDM845_MASTER_CNOC_A2NOC ,1 ,8 ,1 ,SDM845_SLAVE_A2NOC_SNOC ); +DEFINE_QNODE (qxm_crypto,SDM845_MASTER_CRYPTO ,1 ,8 ,1 ,SDM845_SLAVE_A2NOC_SNOC ); +DEFINE_QNODE (qxm_ipa,SDM845_MASTER_IPA ,1 ,8 ,1 ,SDM845_SLAVE_A2NOC_SNOC ); +DEFINE_QNODE (xm_pcie3_1,SDM845_MASTER_PCIE_1 ,1 ,8 ,1 ,SDM845_SLAVE_ANOC_PCIE_SNOC ); +DEFINE_QNODE (xm_qdss_etr,SDM845_MASTER_QDSS_ETR ,1 ,8 ,1 ,SDM845_SLAVE_A2NOC_SNOC ); +DEFINE_QNODE (xm_usb3_0,SDM845_MASTER_USB3_0 ,1 ,8 ,1 ,SDM845_SLAVE_A2NOC_SNOC ); +DEFINE_QNODE (xm_usb3_1,SDM845_MASTER_USB3_1 ,1 ,8 ,1 ,SDM845_SLAVE_A2NOC_SNOC ); +DEFINE_QNODE (qxm_camnoc_hf0_uncomp,SDM845_MASTER_CAMNOC_HF0_UNCOMP ,1 ,32 ,1 ,SDM845_SLAVE_CAMNOC_UNCOMP ); +DEFINE_QNODE (qxm_camnoc_hf1_uncomp,SDM845_MASTER_CAMNOC_HF1_UNCOMP ,1 ,32 ,1 ,SDM845_SLAVE_CAMNOC_UNCOMP ); +DEFINE_QNODE (qxm_camnoc_sf_uncomp,SDM845_MASTER_CAMNOC_SF_UNCOMP ,1 ,32 ,1 ,SDM845_SLAVE_CAMNOC_UNCOMP ); +DEFINE_QNODE (qhm_spdm,SDM845_MASTER_SPDM ,1 ,4 ,1 ,SDM845_SLAVE_CNOC_A2NOC ); +DEFINE_QNODE (qhm_tic,SDM845_MASTER_TIC ,1 ,4 ,43 ,SDM845_SLAVE_A1NOC_CFG ,SDM845_SLAVE_A2NOC_CFG ,SDM845_SLAVE_AOP ,SDM845_SLAVE_AOSS ,SDM845_SLAVE_CAMERA_CFG ,SDM845_SLAVE_CLK_CTL ,SDM845_SLAVE_CDSP_CFG ,SDM845_SLAVE_RBCPR_CX_CFG ,SDM845_SLAVE_CRYPTO_0_CFG ,SDM845_SLAVE_DCC_CFG ,SDM845_SLAVE_CNOC_DDRSS ,SDM845_SLAVE_DISPLAY_CFG ,SDM845_SLAVE_GLM ,SDM845_SLAVE_GFX3D_CFG ,SDM845_SLAVE_IMEM_CFG ,SDM845_SLAVE_IPA_CFG ,SDM845_SLAVE_CNOC_MNOC_CFG ,SDM845_SLAVE_PCIE_0_CFG ,SDM845_SLAVE_PCIE_1_CFG ,SDM845_SLAVE_PDM , +SDM845_SLAVE_SOUTH_PHY_CFG ,SDM845_SLAVE_PIMEM_CFG ,SDM845_SLAVE_PRNG ,SDM845_SLAVE_QDSS_CFG ,SDM845_SLAVE_BLSP_2 ,SDM845_SLAVE_BLSP_1 ,SDM845_SLAVE_SDCC_2 ,SDM845_SLAVE_SDCC_4 ,SDM845_SLAVE_SNOC_CFG ,SDM845_SLAVE_SPDM_WRAPPER ,SDM845_SLAVE_SPSS_CFG ,SDM845_SLAVE_TCSR ,SDM845_SLAVE_TLMM_NORTH ,SDM845_SLAVE_TLMM_SOUTH ,SDM845_SLAVE_TSIF ,SDM845_SLAVE_UFS_CARD_CFG ,SDM845_SLAVE_UFS_MEM_CFG ,SDM845_SLAVE_USB3_0 ,SDM845_SLAVE_USB3_1 ,SDM845_SLAVE_VENUS_CFG ,SDM845_SLAVE_VSENSE_CTRL_CFG ,SDM845_SLAVE_CNOC_A2NOC ,SDM845_SLAVE_SERVICE_CNOC ); +DEFINE_QNODE (qnm_snoc,SDM845_MASTER_SNOC_CNOC ,1 ,8 ,42 ,SDM845_SLAVE_A1NOC_CFG ,SDM845_SLAVE_A2NOC_CFG ,SDM845_SLAVE_AOP ,SDM845_SLAVE_AOSS ,SDM845_SLAVE_CAMERA_CFG ,SDM845_SLAVE_CLK_CTL ,SDM845_SLAVE_CDSP_CFG ,SDM845_SLAVE_RBCPR_CX_CFG ,SDM845_SLAVE_CRYPTO_0_CFG ,SDM845_SLAVE_DCC_CFG ,SDM845_SLAVE_CNOC_DDRSS ,SDM845_SLAVE_DISPLAY_CFG ,SDM845_SLAVE_GLM ,SDM845_SLAVE_GFX3D_CFG ,SDM845_SLAVE_IMEM_CFG ,SDM845_SLAVE_IPA_CFG ,SDM845_SLAVE_CNOC_MNOC_CFG ,SDM845_SLAVE_PCIE_0_CFG ,SDM845_SLAVE_PCIE_1_CFG ,SDM845_SLAVE_PDM , +SDM845_SLAVE_SOUTH_PHY_CFG ,SDM845_SLAVE_PIMEM_CFG ,SDM845_SLAVE_PRNG ,SDM845_SLAVE_QDSS_CFG ,SDM845_SLAVE_BLSP_2 ,SDM845_SLAVE_BLSP_1 ,SDM845_SLAVE_SDCC_2 ,SDM845_SLAVE_SDCC_4 ,SDM845_SLAVE_SNOC_CFG ,SDM845_SLAVE_SPDM_WRAPPER ,SDM845_SLAVE_SPSS_CFG ,SDM845_SLAVE_TCSR ,SDM845_SLAVE_TLMM_NORTH ,SDM845_SLAVE_TLMM_SOUTH ,SDM845_SLAVE_TSIF ,SDM845_SLAVE_UFS_CARD_CFG ,SDM845_SLAVE_UFS_MEM_CFG ,SDM845_SLAVE_USB3_0 ,SDM845_SLAVE_USB3_1 ,SDM845_SLAVE_VENUS_CFG ,SDM845_SLAVE_VSENSE_CTRL_CFG ,SDM845_SLAVE_SERVICE_CNOC ); +DEFINE_QNODE (xm_qdss_dap,SDM845_MASTER_QDSS_DAP ,1 ,8 ,43 ,SDM845_SLAVE_A1NOC_CFG ,SDM845_SLAVE_A2NOC_CFG ,SDM845_SLAVE_AOP ,SDM845_SLAVE_AOSS ,SDM845_SLAVE_CAMERA_CFG ,SDM845_SLAVE_CLK_CTL ,SDM845_SLAVE_CDSP_CFG ,SDM845_SLAVE_RBCPR_CX_CFG ,SDM845_SLAVE_CRYPTO_0_CFG ,SDM845_SLAVE_DCC_CFG ,SDM845_SLAVE_CNOC_DDRSS ,SDM845_SLAVE_DISPLAY_CFG ,SDM845_SLAVE_GLM ,SDM845_SLAVE_GFX3D_CFG ,SDM845_SLAVE_IMEM_CFG ,SDM845_SLAVE_IPA_CFG ,SDM845_SLAVE_CNOC_MNOC_CFG ,SDM845_SLAVE_PCIE_0_CFG ,SDM845_SLAVE_PCIE_1_CFG ,SDM845_SLAVE_PDM , +SDM845_SLAVE_SOUTH_PHY_CFG ,SDM845_SLAVE_PIMEM_CFG ,SDM845_SLAVE_PRNG ,SDM845_SLAVE_QDSS_CFG ,SDM845_SLAVE_BLSP_2 ,SDM845_SLAVE_BLSP_1 ,SDM845_SLAVE_SDCC_2 ,SDM845_SLAVE_SDCC_4 ,SDM845_SLAVE_SNOC_CFG ,SDM845_SLAVE_SPDM_WRAPPER ,SDM845_SLAVE_SPSS_CFG ,SDM845_SLAVE_TCSR ,SDM845_SLAVE_TLMM_NORTH ,SDM845_SLAVE_TLMM_SOUTH ,SDM845_SLAVE_TSIF ,SDM845_SLAVE_UFS_CARD_CFG ,SDM845_SLAVE_UFS_MEM_CFG ,SDM845_SLAVE_USB3_0 ,SDM845_SLAVE_USB3_1 ,SDM845_SLAVE_VENUS_CFG ,SDM845_SLAVE_VSENSE_CTRL_CFG ,SDM845_SLAVE_CNOC_A2NOC ,SDM845_SLAVE_SERVICE_CNOC ); +DEFINE_QNODE (qhm_cnoc,SDM845_MASTER_CNOC_DC_NOC ,1 ,4 ,2 ,SDM845_SLAVE_LLCC_CFG ,SDM845_SLAVE_MEM_NOC_CFG ); +DEFINE_QNODE (acm_l3,SDM845_MASTER_APPSS_PROC ,1 ,16 ,3 ,SDM845_SLAVE_GNOC_SNOC ,SDM845_SLAVE_GNOC_MEM_NOC ,SDM845_SLAVE_SERVICE_GNOC ); +DEFINE_QNODE (pm_gnoc_cfg,SDM845_MASTER_GNOC_CFG ,1 ,4 ,1 ,SDM845_SLAVE_SERVICE_GNOC ); +DEFINE_QNODE (llcc_mc,SDM845_MASTER_LLCC ,4 ,4 ,1 ,SDM845_SLAVE_EBI1 ); +DEFINE_QNODE (acm_tcu,SDM845_MASTER_TCU_0 ,1 ,8 ,3 ,SDM845_SLAVE_MEM_NOC_GNOC ,SDM845_SLAVE_LLCC ,SDM845_SLAVE_MEM_NOC_SNOC ); +DEFINE_QNODE (qhm_memnoc_cfg,SDM845_MASTER_MEM_NOC_CFG ,1 ,4 ,2 ,SDM845_SLAVE_MSS_PROC_MS_MPU_CFG ,SDM845_SLAVE_SERVICE_MEM_NOC ); +DEFINE_QNODE (qnm_apps,SDM845_MASTER_GNOC_MEM_NOC ,2 ,32 ,1 ,SDM845_SLAVE_LLCC ); +DEFINE_QNODE (qnm_mnoc_hf,SDM845_MASTER_MNOC_HF_MEM_NOC ,2 ,32 ,2 ,SDM845_SLAVE_MEM_NOC_GNOC ,SDM845_SLAVE_LLCC ); +DEFINE_QNODE (qnm_mnoc_sf,SDM845_MASTER_MNOC_SF_MEM_NOC ,1 ,32 ,3 ,SDM845_SLAVE_MEM_NOC_GNOC ,SDM845_SLAVE_LLCC ,SDM845_SLAVE_MEM_NOC_SNOC ); +DEFINE_QNODE (qnm_snoc_gc,SDM845_MASTER_SNOC_GC_MEM_NOC ,1 ,8 ,1 ,SDM845_SLAVE_LLCC ); +DEFINE_QNODE (qnm_snoc_sf,SDM845_MASTER_SNOC_SF_MEM_NOC ,1 ,16 ,2 ,SDM845_SLAVE_MEM_NOC_GNOC ,SDM845_SLAVE_LLCC ); +DEFINE_QNODE (qxm_gpu,SDM845_MASTER_GFX3D ,2 ,32 ,3 ,SDM845_SLAVE_MEM_NOC_GNOC ,SDM845_SLAVE_LLCC ,SDM845_SLAVE_MEM_NOC_SNOC ); +DEFINE_QNODE (qhm_mnoc_cfg,SDM845_MASTER_CNOC_MNOC_CFG ,1 ,4 ,1 ,SDM845_SLAVE_SERVICE_MNOC ); +DEFINE_QNODE (qxm_camnoc_hf0,SDM845_MASTER_CAMNOC_HF0 ,1 ,32 ,1 ,SDM845_SLAVE_MNOC_HF_MEM_NOC ); +DEFINE_QNODE (qxm_camnoc_hf1,SDM845_MASTER_CAMNOC_HF1 ,1 ,32 ,1 ,SDM845_SLAVE_MNOC_HF_MEM_NOC ); +DEFINE_QNODE (qxm_camnoc_sf,SDM845_MASTER_CAMNOC_SF ,1 ,32 ,1 ,SDM845_SLAVE_MNOC_SF_MEM_NOC ); +DEFINE_QNODE (qxm_mdp0,SDM845_MASTER_MDP0 ,1 ,32 ,1 ,SDM845_SLAVE_MNOC_HF_MEM_NOC ); +DEFINE_QNODE (qxm_mdp1,SDM845_MASTER_MDP1 ,1 ,32 ,1 ,SDM845_SLAVE_MNOC_HF_MEM_NOC ); +DEFINE_QNODE (qxm_rot,SDM845_MASTER_ROTATOR ,1 ,32 ,1 ,SDM845_SLAVE_MNOC_SF_MEM_NOC ); +DEFINE_QNODE (qxm_venus0,SDM845_MASTER_VIDEO_P0 ,1 ,32 ,1 ,SDM845_SLAVE_MNOC_SF_MEM_NOC ); +DEFINE_QNODE (qxm_venus1,SDM845_MASTER_VIDEO_P1 ,1 ,32 ,1 ,SDM845_SLAVE_MNOC_SF_MEM_NOC ); +DEFINE_QNODE (qxm_venus_arm9,SDM845_MASTER_VIDEO_PROC ,1 ,8 ,1 ,SDM845_SLAVE_MNOC_SF_MEM_NOC ); +DEFINE_QNODE (qhm_snoc_cfg,SDM845_MASTER_SNOC_CFG ,1 ,4 ,1 ,SDM845_SLAVE_SERVICE_SNOC ); +DEFINE_QNODE (qnm_aggre1_noc,SDM845_MASTER_A1NOC_SNOC ,1 ,16 ,6 ,SDM845_SLAVE_APPSS ,SDM845_SLAVE_SNOC_CNOC ,SDM845_SLAVE_SNOC_MEM_NOC_SF ,SDM845_SLAVE_IMEM ,SDM845_SLAVE_PIMEM ,SDM845_SLAVE_QDSS_STM ); +DEFINE_QNODE (qnm_aggre2_noc,SDM845_MASTER_A2NOC_SNOC ,1 ,16 ,9 ,SDM845_SLAVE_APPSS ,SDM845_SLAVE_SNOC_CNOC ,SDM845_SLAVE_SNOC_MEM_NOC_SF ,SDM845_SLAVE_IMEM ,SDM845_SLAVE_PCIE_0 ,SDM845_SLAVE_PCIE_1 ,SDM845_SLAVE_PIMEM ,SDM845_SLAVE_QDSS_STM ,SDM845_SLAVE_TCU ); +DEFINE_QNODE (qnm_gladiator_sodv,SDM845_MASTER_GNOC_SNOC ,1 ,8 ,8 ,SDM845_SLAVE_APPSS ,SDM845_SLAVE_SNOC_CNOC ,SDM845_SLAVE_IMEM ,SDM845_SLAVE_PCIE_0 ,SDM845_SLAVE_PCIE_1 ,SDM845_SLAVE_PIMEM ,SDM845_SLAVE_QDSS_STM ,SDM845_SLAVE_TCU ); +DEFINE_QNODE (qnm_memnoc,SDM845_MASTER_MEM_NOC_SNOC ,1 ,8 ,5 ,SDM845_SLAVE_APPSS ,SDM845_SLAVE_SNOC_CNOC ,SDM845_SLAVE_IMEM ,SDM845_SLAVE_PIMEM ,SDM845_SLAVE_QDSS_STM ); +DEFINE_QNODE (qnm_pcie_anoc,SDM845_MASTER_ANOC_PCIE_SNOC ,1 ,16 ,5 ,SDM845_SLAVE_APPSS ,SDM845_SLAVE_SNOC_CNOC ,SDM845_SLAVE_SNOC_MEM_NOC_SF ,SDM845_SLAVE_IMEM ,SDM845_SLAVE_QDSS_STM ); +DEFINE_QNODE (qxm_pimem,SDM845_MASTER_PIMEM ,1 ,8 ,2 ,SDM845_SLAVE_SNOC_MEM_NOC_GC ,SDM845_SLAVE_IMEM ); +DEFINE_QNODE (xm_gic,SDM845_MASTER_GIC ,1 ,8 ,2 ,SDM845_SLAVE_SNOC_MEM_NOC_GC ,SDM845_SLAVE_IMEM ); +DEFINE_QNODE (qns_a1noc_snoc,SDM845_SLAVE_A1NOC_SNOC ,1 ,16 ,1 ,SDM845_MASTER_A1NOC_SNOC ); +DEFINE_QNODE (srvc_aggre1_noc,SDM845_SLAVE_SERVICE_A1NOC ,1 ,4 ,0 ); +DEFINE_QNODE (qns_pcie_a1noc_snoc,SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC ,1 ,16 ,1 ,SDM845_MASTER_ANOC_PCIE_SNOC ); +DEFINE_QNODE (qns_a2noc_snoc,SDM845_SLAVE_A2NOC_SNOC ,1 ,16 ,1 ,SDM845_MASTER_A2NOC_SNOC ); +DEFINE_QNODE (qns_pcie_snoc,SDM845_SLAVE_ANOC_PCIE_SNOC ,1 ,16 ,1 ,SDM845_MASTER_ANOC_PCIE_SNOC ); +DEFINE_QNODE (srvc_aggre2_noc,SDM845_SLAVE_SERVICE_A2NOC ,1 ,4 ,0 ); +DEFINE_QNODE (qns_camnoc_uncomp,SDM845_SLAVE_CAMNOC_UNCOMP ,1 ,32 ,0 ); +DEFINE_QNODE (qhs_a1_noc_cfg,SDM845_SLAVE_A1NOC_CFG ,1 ,4 ,1 ,SDM845_MASTER_A1NOC_CFG ); +DEFINE_QNODE (qhs_a2_noc_cfg,SDM845_SLAVE_A2NOC_CFG ,1 ,4 ,1 ,SDM845_MASTER_A2NOC_CFG ); +DEFINE_QNODE (qhs_aop,SDM845_SLAVE_AOP ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_aoss,SDM845_SLAVE_AOSS ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_camera_cfg,SDM845_SLAVE_CAMERA_CFG ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_clk_ctl,SDM845_SLAVE_CLK_CTL ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_compute_dsp_cfg,SDM845_SLAVE_CDSP_CFG ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_cpr_cx,SDM845_SLAVE_RBCPR_CX_CFG ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_crypto0_cfg,SDM845_SLAVE_CRYPTO_0_CFG ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_dcc_cfg,SDM845_SLAVE_DCC_CFG ,1 ,4 ,1 ,SDM845_MASTER_CNOC_DC_NOC ); +DEFINE_QNODE (qhs_ddrss_cfg,SDM845_SLAVE_CNOC_DDRSS ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_display_cfg,SDM845_SLAVE_DISPLAY_CFG ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_glm,SDM845_SLAVE_GLM ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_gpuss_cfg,SDM845_SLAVE_GFX3D_CFG ,1 ,8 ,0 ); +DEFINE_QNODE (qhs_imem_cfg,SDM845_SLAVE_IMEM_CFG ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_ipa,SDM845_SLAVE_IPA_CFG ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_mnoc_cfg,SDM845_SLAVE_CNOC_MNOC_CFG ,1 ,4 ,1 ,SDM845_MASTER_CNOC_MNOC_CFG ); +DEFINE_QNODE (qhs_pcie0_cfg,SDM845_SLAVE_PCIE_0_CFG ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_pcie_gen3_cfg,SDM845_SLAVE_PCIE_1_CFG ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_pdm,SDM845_SLAVE_PDM ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_phy_refgen_south,SDM845_SLAVE_SOUTH_PHY_CFG ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_pimem_cfg,SDM845_SLAVE_PIMEM_CFG ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_prng,SDM845_SLAVE_PRNG ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_qdss_cfg,SDM845_SLAVE_QDSS_CFG ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_qupv3_north,SDM845_SLAVE_BLSP_2 ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_qupv3_south,SDM845_SLAVE_BLSP_1 ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_sdc2,SDM845_SLAVE_SDCC_2 ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_sdc4,SDM845_SLAVE_SDCC_4 ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_snoc_cfg,SDM845_SLAVE_SNOC_CFG ,1 ,4 ,1 ,SDM845_MASTER_SNOC_CFG ); +DEFINE_QNODE (qhs_spdm,SDM845_SLAVE_SPDM_WRAPPER ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_spss_cfg,SDM845_SLAVE_SPSS_CFG ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_tcsr,SDM845_SLAVE_TCSR ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_tlmm_north,SDM845_SLAVE_TLMM_NORTH ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_tlmm_south,SDM845_SLAVE_TLMM_SOUTH ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_tsif,SDM845_SLAVE_TSIF ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_ufs_card_cfg,SDM845_SLAVE_UFS_CARD_CFG ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_ufs_mem_cfg,SDM845_SLAVE_UFS_MEM_CFG ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_usb3_0,SDM845_SLAVE_USB3_0 ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_usb3_1,SDM845_SLAVE_USB3_1 ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_venus_cfg,SDM845_SLAVE_VENUS_CFG ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_vsense_ctrl_cfg,SDM845_SLAVE_VSENSE_CTRL_CFG ,1 ,4 ,0 ); +DEFINE_QNODE (qns_cnoc_a2noc,SDM845_SLAVE_CNOC_A2NOC ,1 ,8 ,1 ,SDM845_MASTER_CNOC_A2NOC ); +DEFINE_QNODE (srvc_cnoc,SDM845_SLAVE_SERVICE_CNOC ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_llcc,SDM845_SLAVE_LLCC_CFG ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_memnoc,SDM845_SLAVE_MEM_NOC_CFG ,1 ,4 ,1 ,SDM845_MASTER_MEM_NOC_CFG ); +DEFINE_QNODE (qns_gladiator_sodv,SDM845_SLAVE_GNOC_SNOC ,1 ,8 ,1 ,SDM845_MASTER_GNOC_SNOC ); +DEFINE_QNODE (qns_gnoc_memnoc,SDM845_SLAVE_GNOC_MEM_NOC ,2 ,32 ,1 ,SDM845_MASTER_GNOC_MEM_NOC ); +DEFINE_QNODE (srvc_gnoc,SDM845_SLAVE_SERVICE_GNOC ,1 ,4 ,0 ); +DEFINE_QNODE (ebi,SDM845_SLAVE_EBI1 ,4 ,4 ,0 ); +DEFINE_QNODE (qhs_mdsp_ms_mpu_cfg,SDM845_SLAVE_MSS_PROC_MS_MPU_CFG ,1 ,4 ,0 ); +DEFINE_QNODE (qns_apps_io,SDM845_SLAVE_MEM_NOC_GNOC ,1 ,32 ,0 ); +DEFINE_QNODE (qns_llcc,SDM845_SLAVE_LLCC ,4 ,16 ,1 ,SDM845_MASTER_LLCC ); +DEFINE_QNODE (qns_memnoc_snoc,SDM845_SLAVE_MEM_NOC_SNOC ,1 ,8 ,1 ,SDM845_MASTER_MEM_NOC_SNOC ); +DEFINE_QNODE (srvc_memnoc,SDM845_SLAVE_SERVICE_MEM_NOC ,1 ,4 ,0 ); +DEFINE_QNODE (qns2_mem_noc,SDM845_SLAVE_MNOC_SF_MEM_NOC ,1 ,32 ,1 ,SDM845_MASTER_MNOC_SF_MEM_NOC ); +DEFINE_QNODE (qns_mem_noc_hf,SDM845_SLAVE_MNOC_HF_MEM_NOC ,2 ,32 ,1 ,SDM845_MASTER_MNOC_HF_MEM_NOC ); +DEFINE_QNODE (srvc_mnoc,SDM845_SLAVE_SERVICE_MNOC ,1 ,4 ,0 ); +DEFINE_QNODE (qhs_apss,SDM845_SLAVE_APPSS ,1 ,8 ,0 ); +DEFINE_QNODE (qns_cnoc,SDM845_SLAVE_SNOC_CNOC ,1 ,8 ,1 ,SDM845_MASTER_SNOC_CNOC ); +DEFINE_QNODE (qns_memnoc_gc,SDM845_SLAVE_SNOC_MEM_NOC_GC ,1 ,8 ,1 ,SDM845_MASTER_SNOC_GC_MEM_NOC ); +DEFINE_QNODE (qns_memnoc_sf,SDM845_SLAVE_SNOC_MEM_NOC_SF ,1 ,16 ,1 ,SDM845_MASTER_SNOC_SF_MEM_NOC ); +DEFINE_QNODE (qxs_imem,SDM845_SLAVE_IMEM ,1 ,8 ,0 ); +DEFINE_QNODE (qxs_pcie,SDM845_SLAVE_PCIE_0 ,1 ,8 ,0 ); +DEFINE_QNODE (qxs_pcie_gen3,SDM845_SLAVE_PCIE_1 ,1 ,8 ,0 ); +DEFINE_QNODE (qxs_pimem,SDM845_SLAVE_PIMEM ,1 ,8 ,0 ); +DEFINE_QNODE (srvc_snoc,SDM845_SLAVE_SERVICE_SNOC ,1 ,4 ,0 ); +DEFINE_QNODE (xs_qdss_stm,SDM845_SLAVE_QDSS_STM ,1 ,4 ,0 ); +DEFINE_QNODE (xs_sys_tcu_cfg,SDM845_SLAVE_TCU ,1 ,8 ,0 );DEFINE_QBCM (bcm_acv,"ACV" , false,1 , &ebi);DEFINE_QBCM (bcm_mc0,"MC0" , true,1 , &ebi);
@@ -312,68 +314,71 @@ struct qcom_icc_desc {DEFINE_QBCM (bcm_sn14,"SN14" , false,1 , &qnm_pcie_anoc);DEFINE_QBCM (bcm_sn15,"SN15" , false,1 , &qnm_memnoc); -static struct qcom_icc_node *rsc_hlos_nodes[] = { - [MASTER_APPSS_PROC ] = &acm_l3, - [MASTER_TCU_0 ] = &acm_tcu, - [MASTER_LLCC ] = &llcc_mc, - [MASTER_GNOC_CFG ] = &pm_gnoc_cfg, +static struct qcom_icc_bcm *aggre1_noc_bcms[] = { + &bcm_sn9, +}; + +static struct qcom_icc_node *aggre1_noc_nodes[] = { [MASTER_A1NOC_CFG ] = &qhm_a1noc_cfg, + [MASTER_TSIF ] = &qhm_tsif, + [MASTER_SDCC_2 ] = &xm_sdc2, + [MASTER_SDCC_4 ] = &xm_sdc4, + [MASTER_UFS_CARD ] = &xm_ufs_card, + [MASTER_UFS_MEM ] = &xm_ufs_mem, + [MASTER_PCIE_0 ] = &xm_pcie_0, + [SLAVE_A1NOC_SNOC ] = &qns_a1noc_snoc, + [SLAVE_SERVICE_A1NOC ] = &srvc_aggre1_noc, + [SLAVE_ANOC_PCIE_A1NOC_SNOC ] = &qns_pcie_a1noc_snoc, +}; + +static struct qcom_icc_desc sdm845_aggre1_noc = { + .nodes = aggre1_noc_nodes, + .num_nodes =ARRAY_SIZE (aggre1_noc_nodes), + .bcms = aggre1_noc_bcms, + .num_bcms =ARRAY_SIZE (aggre1_noc_bcms), +}; + +static struct qcom_icc_bcm *aggre2_noc_bcms[] = { + &bcm_ce0, + &bcm_sn11, + &bcm_qup0, +}; + +static struct qcom_icc_node *aggre2_noc_nodes[] = { [MASTER_A2NOC_CFG ] = &qhm_a2noc_cfg, - [MASTER_CNOC_DC_NOC ] = &qhm_cnoc, - [MASTER_MEM_NOC_CFG ] = &qhm_memnoc_cfg, - [MASTER_CNOC_MNOC_CFG ] = &qhm_mnoc_cfg, [MASTER_QDSS_BAM ] = &qhm_qdss_bam, - [MASTER_BLSP_1 ] = &qhm_qup1, - [MASTER_BLSP_2 ] = &qhm_qup2, - [MASTER_SNOC_CFG ] = &qhm_snoc_cfg, - [MASTER_SPDM ] = &qhm_spdm, - [MASTER_TIC ] = &qhm_tic, - [MASTER_TSIF ] = &qhm_tsif, - [MASTER_A1NOC_SNOC ] = &qnm_aggre1_noc, - [MASTER_A2NOC_SNOC ] = &qnm_aggre2_noc, - [MASTER_GNOC_MEM_NOC ] = &qnm_apps, [MASTER_CNOC_A2NOC ] = &qnm_cnoc, - [MASTER_GNOC_SNOC ] = &qnm_gladiator_sodv, - [MASTER_MEM_NOC_SNOC ] = &qnm_memnoc, - [MASTER_MNOC_HF_MEM_NOC ] = &qnm_mnoc_hf, - [MASTER_MNOC_SF_MEM_NOC ] = &qnm_mnoc_sf, - [MASTER_ANOC_PCIE_SNOC ] = &qnm_pcie_anoc, - [MASTER_SNOC_CNOC ] = &qnm_snoc, - [MASTER_SNOC_GC_MEM_NOC ] = &qnm_snoc_gc, - [MASTER_SNOC_SF_MEM_NOC ] = &qnm_snoc_sf, - [MASTER_CAMNOC_HF0 ] = &qxm_camnoc_hf0, - [MASTER_CAMNOC_HF0_UNCOMP ] = &qxm_camnoc_hf0_uncomp, - [MASTER_CAMNOC_HF1 ] = &qxm_camnoc_hf1, - [MASTER_CAMNOC_HF1_UNCOMP ] = &qxm_camnoc_hf1_uncomp, - [MASTER_CAMNOC_SF ] = &qxm_camnoc_sf, - [MASTER_CAMNOC_SF_UNCOMP ] = &qxm_camnoc_sf_uncomp, [MASTER_CRYPTO ] = &qxm_crypto, - [MASTER_GFX3D ] = &qxm_gpu, [MASTER_IPA ] = &qxm_ipa, - [MASTER_MDP0 ] = &qxm_mdp0, - [MASTER_MDP1 ] = &qxm_mdp1, - [MASTER_PIMEM ] = &qxm_pimem, - [MASTER_ROTATOR ] = &qxm_rot, - [MASTER_VIDEO_P0 ] = &qxm_venus0, - [MASTER_VIDEO_P1 ] = &qxm_venus1, - [MASTER_VIDEO_PROC ] = &qxm_venus_arm9, - [MASTER_GIC ] = &xm_gic, [MASTER_PCIE_1 ] = &xm_pcie3_1, - [MASTER_PCIE_0 ] = &xm_pcie_0, - [MASTER_QDSS_DAP ] = &xm_qdss_dap, [MASTER_QDSS_ETR ] = &xm_qdss_etr, - [MASTER_SDCC_2 ] = &xm_sdc2, - [MASTER_SDCC_4 ] = &xm_sdc4, - [MASTER_UFS_CARD ] = &xm_ufs_card, - [MASTER_UFS_MEM ] = &xm_ufs_mem, [MASTER_USB3_0 ] = &xm_usb3_0, [MASTER_USB3_1 ] = &xm_usb3_1, - [SLAVE_EBI1 ] = &ebi, + [SLAVE_A2NOC_SNOC ] = &qns_a2noc_snoc, + [SLAVE_ANOC_PCIE_SNOC ] = &qns_pcie_snoc, + [SLAVE_SERVICE_A2NOC ] = &srvc_aggre2_noc, +}; + +static struct qcom_icc_desc sdm845_aggre2_noc = { + .nodes = aggre2_noc_nodes, + .num_nodes =ARRAY_SIZE (aggre2_noc_nodes), + .bcms = aggre2_noc_bcms, + .num_bcms =ARRAY_SIZE (aggre2_noc_bcms), +}; + +static struct qcom_icc_bcm *config_noc_bcms[] = { + &bcm_cn0, +}; + +static struct qcom_icc_node *config_noc_nodes[] = { + [MASTER_SPDM ] = &qhm_spdm, + [MASTER_TIC ] = &qhm_tic, + [MASTER_SNOC_CNOC ] = &qnm_snoc, + [MASTER_QDSS_DAP ] = &xm_qdss_dap, [SLAVE_A1NOC_CFG ] = &qhs_a1_noc_cfg, [SLAVE_A2NOC_CFG ] = &qhs_a2_noc_cfg, [SLAVE_AOP ] = &qhs_aop, [SLAVE_AOSS ] = &qhs_aoss, - [SLAVE_APPSS ] = &qhs_apss, [SLAVE_CAMERA_CFG ] = &qhs_camera_cfg, [SLAVE_CLK_CTL ] = &qhs_clk_ctl, [SLAVE_CDSP_CFG ] = &qhs_compute_dsp_cfg,
@@ -386,9 +391,6 @@ struct qcom_icc_desc { [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, [SLAVE_IMEM_CFG] = &qhs_imem_cfg, [SLAVE_IPA_CFG] = &qhs_ipa, - [SLAVE_LLCC_CFG] = &qhs_llcc, - [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, - [SLAVE_MEM_NOC_CFG] = &qhs_memnoc, [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg, [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, [SLAVE_PCIE_1_CFG] = &qhs_pcie_gen3_cfg,
@@ -414,53 +416,122 @@ struct qcom_icc_desc { [SLAVE_USB3_1] = &qhs_usb3_1, [SLAVE_VENUS_CFG] = &qhs_venus_cfg, [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, - [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc, - [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, - [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, - [SLAVE_MEM_NOC_GNOC] = &qns_apps_io, - [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, - [SLAVE_SNOC_CNOC] = &qns_cnoc, [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc, + [SLAVE_SERVICE_CNOC] = &srvc_cnoc, +}; + +static struct qcom_icc_desc sdm845_config_noc = { + .nodes = config_noc_nodes, + .num_nodes =ARRAY_SIZE (config_noc_nodes), + .bcms = config_noc_bcms, + .num_bcms =ARRAY_SIZE (config_noc_bcms), +}; + +static struct qcom_icc_bcm *dc_noc_bcms[] = { +}; + +static struct qcom_icc_node *dc_noc_nodes[] = { + [MASTER_CNOC_DC_NOC ] = &qhm_cnoc, + [SLAVE_LLCC_CFG ] = &qhs_llcc, + [SLAVE_MEM_NOC_CFG ] = &qhs_memnoc, +}; + +static struct qcom_icc_desc sdm845_dc_noc = { + .nodes = dc_noc_nodes, + .num_nodes =ARRAY_SIZE (dc_noc_nodes), + .bcms = dc_noc_bcms, + .num_bcms =ARRAY_SIZE (dc_noc_bcms), +}; + +static struct qcom_icc_bcm *gladiator_noc_bcms[] = { +}; + +static struct qcom_icc_node *gladiator_noc_nodes[] = { + [MASTER_APPSS_PROC ] = &acm_l3, + [MASTER_GNOC_CFG ] = &pm_gnoc_cfg, [SLAVE_GNOC_SNOC ] = &qns_gladiator_sodv, [SLAVE_GNOC_MEM_NOC ] = &qns_gnoc_memnoc, - [SLAVE_LLCC] = &qns_llcc, - [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, - [SLAVE_SNOC_MEM_NOC_GC] = &qns_memnoc_gc, - [SLAVE_SNOC_MEM_NOC_SF] = &qns_memnoc_sf, - [SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc, - [SLAVE_ANOC_PCIE_A1NOC_SNOC] = &qns_pcie_a1noc_snoc, - [SLAVE_ANOC_PCIE_SNOC] = &qns_pcie_snoc, - [SLAVE_IMEM] = &qxs_imem, - [SLAVE_PCIE_0] = &qxs_pcie, - [SLAVE_PCIE_1] = &qxs_pcie_gen3, - [SLAVE_PIMEM] = &qxs_pimem, - [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, - [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, - [SLAVE_SERVICE_CNOC] = &srvc_cnoc, [SLAVE_SERVICE_GNOC ] = &srvc_gnoc, - [SLAVE_SERVICE_MEM_NOC] = &srvc_memnoc, - [SLAVE_SERVICE_MNOC] = &srvc_mnoc, - [SLAVE_SERVICE_SNOC] = &srvc_snoc, - [SLAVE_QDSS_STM] = &xs_qdss_stm, - [SLAVE_TCU] = &xs_sys_tcu_cfg, }; -static struct qcom_icc_bcm *rsc_hlos_bcms[] = { - &bcm_acv, +static struct qcom_icc_desc sdm845_gladiator_noc = { + .nodes = gladiator_noc_nodes, + .num_nodes =ARRAY_SIZE (gladiator_noc_nodes), + .bcms = gladiator_noc_bcms, + .num_bcms =ARRAY_SIZE (gladiator_noc_bcms), +}; + +static struct qcom_icc_bcm *mem_noc_bcms[] = { &bcm_mc0, + &bcm_acv, &bcm_sh0, - &bcm_mm0, &bcm_sh1, - &bcm_mm1, &bcm_sh2, - &bcm_mm2, &bcm_sh3, - &bcm_mm3, &bcm_sh5, +}; + +static struct qcom_icc_node *mem_noc_nodes[] = { + [MASTER_TCU_0 ] = &acm_tcu, + [MASTER_MEM_NOC_CFG ] = &qhm_memnoc_cfg, + [MASTER_GNOC_MEM_NOC ] = &qnm_apps, + [MASTER_MNOC_HF_MEM_NOC ] = &qnm_mnoc_hf, + [MASTER_MNOC_SF_MEM_NOC ] = &qnm_mnoc_sf, + [MASTER_SNOC_GC_MEM_NOC ] = &qnm_snoc_gc, + [MASTER_SNOC_SF_MEM_NOC ] = &qnm_snoc_sf, + [MASTER_GFX3D ] = &qxm_gpu, + [SLAVE_MSS_PROC_MS_MPU_CFG ] = &qhs_mdsp_ms_mpu_cfg, + [SLAVE_MEM_NOC_GNOC ] = &qns_apps_io, + [SLAVE_LLCC ] = &qns_llcc, + [SLAVE_MEM_NOC_SNOC ] = &qns_memnoc_snoc, + [SLAVE_SERVICE_MEM_NOC ] = &srvc_memnoc, + [MASTER_LLCC ] = &llcc_mc, + [SLAVE_EBI1 ] = &ebi, +}; + +static struct qcom_icc_desc sdm845_mem_noc = { + .nodes = mem_noc_nodes, + .num_nodes =ARRAY_SIZE (mem_noc_nodes), + .bcms = mem_noc_bcms, + .num_bcms =ARRAY_SIZE (mem_noc_bcms), +}; + +static struct qcom_icc_bcm *mmss_noc_bcms[] = { + &bcm_mm0, + &bcm_mm1, + &bcm_mm2, + &bcm_mm3, +}; + +static struct qcom_icc_node *mmss_noc_nodes[] = { + [MASTER_CNOC_MNOC_CFG ] = &qhm_mnoc_cfg, + [MASTER_CAMNOC_HF0 ] = &qxm_camnoc_hf0, + [MASTER_CAMNOC_HF1 ] = &qxm_camnoc_hf1, + [MASTER_CAMNOC_SF ] = &qxm_camnoc_sf, + [MASTER_MDP0 ] = &qxm_mdp0, + [MASTER_MDP1 ] = &qxm_mdp1, + [MASTER_ROTATOR ] = &qxm_rot, + [MASTER_VIDEO_P0 ] = &qxm_venus0, + [MASTER_VIDEO_P1 ] = &qxm_venus1, + [MASTER_VIDEO_PROC ] = &qxm_venus_arm9, + [SLAVE_MNOC_SF_MEM_NOC ] = &qns2_mem_noc, + [SLAVE_MNOC_HF_MEM_NOC ] = &qns_mem_noc_hf, + [SLAVE_SERVICE_MNOC ] = &srvc_mnoc, + [MASTER_CAMNOC_HF0_UNCOMP ] = &qxm_camnoc_hf0_uncomp, + [MASTER_CAMNOC_HF1_UNCOMP ] = &qxm_camnoc_hf1_uncomp, + [MASTER_CAMNOC_SF_UNCOMP ] = &qxm_camnoc_sf_uncomp, + [SLAVE_CAMNOC_UNCOMP ] = &qns_camnoc_uncomp, +}; + +static struct qcom_icc_desc sdm845_mmss_noc = { + .nodes = mmss_noc_nodes, + .num_nodes =ARRAY_SIZE (mmss_noc_nodes), + .bcms = mmss_noc_bcms, + .num_bcms =ARRAY_SIZE (mmss_noc_bcms), +}; + +static struct qcom_icc_bcm *system_noc_bcms[] = { &bcm_sn0, - &bcm_ce0, - &bcm_cn0, - &bcm_qup0, &bcm_sn1, &bcm_sn2, &bcm_sn3,
@@ -476,297 +547,34 @@ struct qcom_icc_desc { &bcm_sn15, }; -static struct qcom_icc_desc sdm845_rsc_hlos = { - .nodes = rsc_hlos_nodes, - .num_nodes =ARRAY_SIZE (rsc_hlos_nodes), - .bcms = rsc_hlos_bcms, - .num_bcms =ARRAY_SIZE (rsc_hlos_bcms), +static struct qcom_icc_node *system_noc_nodes[] = { + [MASTER_SNOC_CFG ] = &qhm_snoc_cfg, + [MASTER_A1NOC_SNOC ] = &qnm_aggre1_noc, + [MASTER_A2NOC_SNOC ] = &qnm_aggre2_noc, + [MASTER_GNOC_SNOC ] = &qnm_gladiator_sodv, + [MASTER_MEM_NOC_SNOC ] = &qnm_memnoc, + [MASTER_ANOC_PCIE_SNOC ] = &qnm_pcie_anoc, + [MASTER_PIMEM ] = &qxm_pimem, + [MASTER_GIC ] = &xm_gic, + [SLAVE_APPSS ] = &qhs_apss, + [SLAVE_SNOC_CNOC ] = &qns_cnoc, + [SLAVE_SNOC_MEM_NOC_GC ] = &qns_memnoc_gc, + [SLAVE_SNOC_MEM_NOC_SF ] = &qns_memnoc_sf, + [SLAVE_IMEM ] = &qxs_imem, + [SLAVE_PCIE_0 ] = &qxs_pcie, + [SLAVE_PCIE_1 ] = &qxs_pcie_gen3, + [SLAVE_PIMEM ] = &qxs_pimem, + [SLAVE_SERVICE_SNOC ] = &srvc_snoc, + [SLAVE_QDSS_STM ] = &xs_qdss_stm, + [SLAVE_TCU ] = &xs_sys_tcu_cfg, }; -static int qcom_icc_bcm_init (struct qcom_icc_bcm *bcm,struct device *dev) -{ -struct qcom_icc_node *qn; -const struct bcm_db *data; -size_t data_count; -int i; - - bcm->addr =cmd_db_read_addr (bcm->name); -if (!bcm->addr) { -dev_err (dev,"%s could not find RPMh address\n" , - bcm->name); -return -EINVAL ; - } - - data =cmd_db_read_aux_data (bcm->name, &data_count); -if (IS_ERR (data)) { -dev_err (dev,"%s command db read error (%ld)\n" , - bcm->name,PTR_ERR (data)); -return PTR_ERR (data); - } -if (!data_count) { -dev_err (dev,"%s command db missing or partial aux data\n" , - bcm->name); -return -EINVAL ; - } - - bcm->aux_data.unit =le32_to_cpu (data->unit); - bcm->aux_data.width =le16_to_cpu (data->width); - bcm->aux_data.vcd = data->vcd; - bcm->aux_data.reserved = data->reserved; - -/* -* Link Qnodes to their respective BCMs -*/ -for (i =0 ; i < bcm->num_nodes; i++) { - qn = bcm->nodes[i]; - qn->bcms[qn->num_bcms] = bcm; - qn->num_bcms++; - } - -return 0 ; -} - -inline void tcs_cmd_gen (struct tcs_cmd *cmd,u64 vote_x,u64 vote_y, -u32 addr,bool commit) -{ -bool valid = true; - -if (!cmd) -return ; - -if (vote_x ==0 && vote_y ==0 ) - valid = false; - -if (vote_x >BCM_TCS_CMD_VOTE_MASK ) - vote_x =BCM_TCS_CMD_VOTE_MASK ; - -if (vote_y >BCM_TCS_CMD_VOTE_MASK ) - vote_y =BCM_TCS_CMD_VOTE_MASK ; - - cmd->addr = addr; - cmd->data =BCM_TCS_CMD (commit, valid, vote_x, vote_y); - -/* -* Set the wait for completion flag on command that need to be completed -* before the next command. -*/ -if (commit) - cmd->wait = true; -} - -static void tcs_list_gen (struct list_head *bcm_list,int bucket, -struct tcs_cmd tcs_list[SDM845_MAX_VCD ], -int n[SDM845_MAX_VCD ]) -{ -struct qcom_icc_bcm *bcm; -bool commit; -size_t idx =0 , batch =0 , cur_vcd_size =0 ; - -memset (n,0 ,sizeof (int ) *SDM845_MAX_VCD ); - -list_for_each_entry (bcm, bcm_list, list) { - commit = false; - cur_vcd_size++; -if ((list_is_last (&bcm->list, bcm_list)) || - bcm->aux_data.vcd !=list_next_entry (bcm, list)->aux_data.vcd) { - commit = true; - cur_vcd_size =0 ; - } -tcs_cmd_gen (&tcs_list[idx], bcm->vote_x[bucket], - bcm->vote_y[bucket], bcm->addr, commit); - idx++; - n[batch]++; -/* -* Batch the BCMs in such a way that we do not split them in -* multiple payloads when they are under the same VCD. This is -* to ensure that every BCM is committed since we only set the -* commit bit on the last BCM request of every VCD. -*/ -if (n[batch] >=MAX_RPMH_PAYLOAD ) { -if (!commit) { - n[batch] -= cur_vcd_size; - n[batch +1 ] = cur_vcd_size; - } - batch++; - } - } -} - -static void bcm_aggregate (struct qcom_icc_bcm *bcm) -{ -size_t i, bucket; -u64 agg_avg[QCOM_ICC_NUM_BUCKETS ] = {0 }; -u64 agg_peak[QCOM_ICC_NUM_BUCKETS ] = {0 }; -u64 temp; - -for (bucket =0 ; bucket <QCOM_ICC_NUM_BUCKETS ; bucket++) { -for (i =0 ; i < bcm->num_nodes; i++) { - temp = bcm->nodes[i]->sum_avg[bucket] * bcm->aux_data.width; -do_div (temp, bcm->nodes[i]->buswidth * bcm->nodes[i]->channels); - agg_avg[bucket] =max (agg_avg[bucket], temp); - - temp = bcm->nodes[i]->max_peak[bucket] * bcm->aux_data.width; -do_div (temp, bcm->nodes[i]->buswidth); - agg_peak[bucket] =max (agg_peak[bucket], temp); - } - - temp = agg_avg[bucket] *1000ULL ; -do_div (temp, bcm->aux_data.unit); - bcm->vote_x[bucket] = temp; - - temp = agg_peak[bucket] *1000ULL ; -do_div (temp, bcm->aux_data.unit); - bcm->vote_y[bucket] = temp; - } - -if (bcm->keepalive && bcm->vote_x[QCOM_ICC_BUCKET_AMC ] ==0 && - bcm->vote_y[QCOM_ICC_BUCKET_AMC ] ==0 ) { - bcm->vote_x[QCOM_ICC_BUCKET_AMC ] =1 ; - bcm->vote_x[QCOM_ICC_BUCKET_WAKE ] =1 ; - bcm->vote_y[QCOM_ICC_BUCKET_AMC ] =1 ; - bcm->vote_y[QCOM_ICC_BUCKET_WAKE ] =1 ; - } - - bcm->dirty = false; -} - -static void qcom_icc_pre_aggregate (struct icc_node *node) -{ -size_t i; -struct qcom_icc_node *qn; - - qn = node->data; - -for (i =0 ; i <QCOM_ICC_NUM_BUCKETS ; i++) { - qn->sum_avg[i] =0 ; - qn->max_peak[i] =0 ; - } -} - -static int qcom_icc_aggregate (struct icc_node *node,u32 tag,u32 avg_bw, -u32 peak_bw,u32 *agg_avg,u32 *agg_peak) -{ -size_t i; -struct qcom_icc_node *qn; - - qn = node->data; - -if (!tag) - tag =QCOM_ICC_TAG_ALWAYS ; - -for (i =0 ; i <QCOM_ICC_NUM_BUCKETS ; i++) { -if (tag &BIT (i)) { - qn->sum_avg[i] += avg_bw; - qn->max_peak[i] =max_t (u32, qn->max_peak[i], peak_bw); - } - } - - *agg_avg += avg_bw; - *agg_peak =max_t (u32, *agg_peak, peak_bw); - -for (i =0 ; i < qn->num_bcms; i++) - qn->bcms[i]->dirty = true; - -return 0 ; -} - -static int qcom_icc_set (struct icc_node *src,struct icc_node *dst) -{ -struct qcom_icc_provider *qp; -struct icc_node *node; -struct tcs_cmd cmds[SDM845_MAX_BCMS ]; -struct list_head commit_list; -int commit_idx[SDM845_MAX_VCD ]; -int ret =0 , i; - -if (!src) - node = dst; -else - node = src; - - qp =to_qcom_provider (node->provider); - -INIT_LIST_HEAD (&commit_list); - -for (i =0 ; i < qp->num_bcms; i++) { -if (qp->bcms[i]->dirty) { -bcm_aggregate (qp->bcms[i]); -list_add_tail (&qp->bcms[i]->list, &commit_list); - } - } - -/* -* Construct the command list based on a pre ordered list of BCMs -* based on VCD. -*/ -tcs_list_gen (&commit_list,QCOM_ICC_BUCKET_AMC , cmds, commit_idx); - -if (!commit_idx[0 ]) -return ret; - - ret =rpmh_invalidate (qp->dev); -if (ret) { -pr_err ("Error invalidating RPMH client (%d)\n" , ret); -return ret; - } - - ret =rpmh_write_batch (qp->dev,RPMH_ACTIVE_ONLY_STATE , - cmds, commit_idx); -if (ret) { -pr_err ("Error sending AMC RPMH requests (%d)\n" , ret); -return ret; - } - -INIT_LIST_HEAD (&commit_list); - -for (i =0 ; i < qp->num_bcms; i++) { -/* -* Only generate WAKE and SLEEP commands if a resource's -* requirements change as the execution environment transitions -* between different power states. -*/ -if (qp->bcms[i]->vote_x[QCOM_ICC_BUCKET_WAKE ] != - qp->bcms[i]->vote_x[QCOM_ICC_BUCKET_SLEEP ] || - qp->bcms[i]->vote_y[QCOM_ICC_BUCKET_WAKE ] != - qp->bcms[i]->vote_y[QCOM_ICC_BUCKET_SLEEP ]) { -list_add_tail (&qp->bcms[i]->list, &commit_list); - } - } - -if (list_empty (&commit_list)) -return ret; - -tcs_list_gen (&commit_list,QCOM_ICC_BUCKET_WAKE , cmds, commit_idx); - - ret =rpmh_write_batch (qp->dev,RPMH_WAKE_ONLY_STATE , cmds, commit_idx); -if (ret) { -pr_err ("Error sending WAKE RPMH requests (%d)\n" , ret); -return ret; - } - -tcs_list_gen (&commit_list,QCOM_ICC_BUCKET_SLEEP , cmds, commit_idx); - - ret =rpmh_write_batch (qp->dev,RPMH_SLEEP_STATE , cmds, commit_idx); -if (ret) { -pr_err ("Error sending SLEEP RPMH requests (%d)\n" , ret); -return ret; - } - -return ret; -} - -static int cmp_vcd (const void *_l,const void *_r) -{ -const struct qcom_icc_bcm **l = (const struct qcom_icc_bcm **)_l; -const struct qcom_icc_bcm **r = (const struct qcom_icc_bcm **)_r; - -if (l[0 ]->aux_data.vcd < r[0 ]->aux_data.vcd) -return -1 ; -else if (l[0 ]->aux_data.vcd == r[0 ]->aux_data.vcd) -return 0 ; -else -return 1 ; -} +static struct qcom_icc_desc sdm845_system_noc = { + .nodes = system_noc_nodes, + .num_nodes =ARRAY_SIZE (system_noc_nodes), + .bcms = system_noc_bcms, + .num_bcms =ARRAY_SIZE (system_noc_bcms), +};static int qnoc_probe (struct platform_device *pdev) {
@@ -808,6 +616,12 @@ static int qnoc_probe(struct platform_device *pdev) qp->bcms = desc->bcms; qp->num_bcms = desc->num_bcms; + qp->voter =of_bcm_voter_get (qp->dev,NULL ); +if (IS_ERR (qp->voter)) { +dev_err (&pdev->dev,"bcm_voter err:%ld\n" ,PTR_ERR (qp->voter)); +return PTR_ERR (qp->voter); + } + ret =icc_provider_add (provider);if (ret) {dev_err (&pdev->dev,"error adding interconnect provider\n" );
@@ -817,6 +631,9 @@ static int qnoc_probe(struct platform_device *pdev)for (i =0 ; i < num_nodes; i++) {size_t j; +if (!qnodes[i]) +continue ; + node =icc_node_create (qnodes[i]->id);if (IS_ERR (node)) { ret =PTR_ERR (node);
@@ -827,10 +644,6 @@ static int qnoc_probe(struct platform_device *pdev) node->data = qnodes[i];icc_node_add (node, provider); -dev_dbg (&pdev->dev,"registered node %p %s %d\n" , node, - qnodes[i]->name, node->id); - -/* populate links */ for (j =0 ; j < qnodes[i]->num_links; j++)icc_link_create (node, qnodes[i]->links[j]);
@@ -841,19 +654,9 @@ static int qnoc_probe(struct platform_device *pdev)for (i =0 ; i < qp->num_bcms; i++)qcom_icc_bcm_init (qp->bcms[i], &pdev->dev); -/* -* Pre sort the BCMs based on VCD for ease of generating a command list -* that groups the BCMs with the same VCD together. VCDs are numbered -* with lowest being the most expensive time wise, ensuring that -* those commands are being sent the earliest in the queue. -*/ -sort (qp->bcms, qp->num_bcms,sizeof (*qp->bcms), cmp_vcd,NULL ); -platform_set_drvdata (pdev, qp); -dev_dbg (&pdev->dev,"Registered SDM845 ICC\n" ); - -return ret; +return 0 ; err:icc_nodes_remove (provider);icc_provider_del (provider);
@@ -869,8 +672,23 @@ static int qnoc_remove(struct platform_device *pdev) }static const struct of_device_id qnoc_of_match[] = { - { .compatible ="qcom,sdm845-rsc-hlos" , .data = &sdm845_rsc_hlos }, - { }, + { .compatible ="qcom,sdm845-aggre1-noc" , + .data = &sdm845_aggre1_noc}, + { .compatible ="qcom,sdm845-aggre2-noc" , + .data = &sdm845_aggre2_noc}, + { .compatible ="qcom,sdm845-config-noc" , + .data = &sdm845_config_noc}, + { .compatible ="qcom,sdm845-dc-noc" , + .data = &sdm845_dc_noc}, + { .compatible ="qcom,sdm845-gladiator-noc" , + .data = &sdm845_gladiator_noc}, + { .compatible ="qcom,sdm845-mem-noc" , + .data = &sdm845_mem_noc}, + { .compatible ="qcom,sdm845-mmss-noc" , + .data = &sdm845_mmss_noc}, + { .compatible ="qcom,sdm845-system-noc" , + .data = &sdm845_system_noc}, + { } };MODULE_DEVICE_TABLE (of, qnoc_of_match);
include/dt-bindings/interconnect/qcom,sdm845.h +134 -129
268 lines not on this page · raw message
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH v2 5/6] interconnect: qcom: sdm845: Split qnodes into their respective NoCs
Quoted 17 lines · David Dai
In order to better represent the hardware and its different Network-On-Chip devices, split the sdm845 provider driver into NoC specific providers. Remove duplicate functionality already provided by the icc rpmh and bcm voter drivers to calculate and commit bandwidth requests to hardware.
Signed-off-by David Dai <[email protected]>--- drivers/interconnect/qcom/sdm845.c | 1132 ++++++++++-------------- include/dt-bindings/interconnect/qcom,sdm845.h | 263 +++--- 2 files changed, 609 insertions(+), 786 deletions(-)drivers/interconnect/qcom/sdm845.c +0
-0
drivers/interconnect/qcom/sdm845.c line 7
Quoted 3 lines
drivers/interconnect/qcom/sdm845.c +0
-0@@ -5,283 +5,285 @@*/ #include <asm/div64.h>
You don't need this header anymore, right?
drivers/interconnect/qcom/sdm845.c line 14
Quoted 10 lines
drivers/interconnect/qcom/sdm845.c +0
-3-#include <dt-bindings/interconnect/qcom,sdm845.h> #include <linux/device.h> #include <linux/interconnect.h> #include <linux/interconnect-provider.h> #include <linux/io.h> #include <linux/module.h> #include <linux/of_device.h> -#include <linux/of_platform.h> -#include <linux/platform_device.h> #include <linux/sort.h>
..or this one.
Re: [PATCH v2 5/6] interconnect: qcom: sdm845: Split qnodes into their respective NoCs
Quoted 21 lines · Evan Green
Quoted 20 lines · David Dai
In order to better represent the hardware and its different Network-On-Chip devices, split the sdm845 provider driver into NoC specific providers. Remove duplicate functionality already provided by the icc rpmh and bcm voter drivers to calculate and commit bandwidth requests to hardware.
Signed-off-by David Dai <[email protected]>--- drivers/interconnect/qcom/sdm845.c | 1132 ++++++++++-------------- include/dt-bindings/interconnect/qcom,sdm845.h | 263 +++--- 2 files changed, 609 insertions(+), 786 deletions(-)drivers/interconnect/qcom/sdm845.c +0
-0@@ -5,283 +5,285 @@*/
Quoted 9 lines
drivers/interconnect/qcom/sdm845.c line 7
Quoted 1 line
drivers/interconnect/qcom/sdm845.c +0
-0#include <asm/div64.h> You don't need this header anymore, right?
Quoted 5 lines
drivers/interconnect/qcom/sdm845.c +0
-1-#include <dt-bindings/interconnect/qcom,sdm845.h> #include <linux/device.h> #include <linux/interconnect.h> #include <linux/interconnect-provider.h> #include <linux/io.h>
^^ can also be dropped
Quoted 3 lines
drivers/interconnect/qcom/sdm845.c line 15
Quoted 3 lines
drivers/interconnect/qcom/sdm845.c +0
-1#include <linux/module.h> #include <linux/of_device.h> -#include <linux/of_platform.h>
^^ can also be dropped
Quoted 4 lines
drivers/interconnect/qcom/sdm845.c line 14
Quoted 2 lines
drivers/interconnect/qcom/sdm845.c +0
-1-#include <linux/platform_device.h> #include <linux/sort.h> ..or this one.
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
PATCH v2 6/6 arm64: dts: sdm845: Redefine interconnect provider DT nodes
In reply to David DaiAdd the DT nodes for each of the Network-On-Chip interconnect buses found on SDM845 based platform and redefine the rsc_hlos child node as a bcm-voter device to better represent the hardware.
Signed-off-by David Dai <[email protected]>
--- arch/arm64/boot/dts/qcom/sdm845.dtsi | 61 ++++++++++++++++++++++++++++++++++-- 1 file changed, 58 insertions(+), 3 deletions(-)
arch/arm64/boot/dts/qcom/sdm845.dtsi +58 -3
@@ -1364,6 +1364,55 @@ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; }; + mem_noc: interconnect@1380000 { + compatible = "qcom,sdm845-mem-noc"; + reg = <0 0x01380000 0 0x27200>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + dc_noc: interconnect@14e0000 { + compatible = "qcom,sdm845-dc-noc"; + reg = <0 0x014e0000 0 0x400>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + config_noc: interconnect@1500000 { + compatible = "qcom,sdm845-config-noc"; + reg = <0 0x01500000 0 0x5080>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + compatible = "qcom,sdm845-system-noc"; + reg = <0 0x01620000 0 0x18080>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,sdm845-aggre1-noc"; + reg = <0 0x016e0000 0 0xd080>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sdm845-aggre2-noc"; + reg = <0 0x01700000 0 0x3b100>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,sdm845-mmss-noc"; + reg = <0 0x01740000 0 0x1c1000>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
@@ -3100,6 +3149,13 @@ #mbox-cells = <1>; }; + gladiator_noc: interconnect@17900000 { + compatible = "qcom,sdm845-gladiator-noc"; + reg = <0 0x17900000 0 0xd080>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + apps_rsc: rsc@179c0000 { label = "apps_rsc"; compatible = "qcom,rpmh-rsc";
@@ -3174,9 +3230,8 @@ }; }; - rsc_hlos: interconnect { - compatible = "qcom,sdm845-rsc-hlos"; - #interconnect-cells = <1>; + apps_bcm_voter: bcm-voter { + compatible = "qcom,sdm845-bcm-voter"; }; };
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Re: [PATCH v2 6/6] arm64: dts: sdm845: Redefine interconnect provider DT nodes
Quoted 85 lines · David Dai
Add the DT nodes for each of the Network-On-Chip interconnect buses found on SDM845 based platform and redefine the
rsc_hloschild node as a bcm-voter device to better represent the hardware.Signed-off-by David Dai <[email protected]>--- arch/arm64/boot/dts/qcom/sdm845.dtsi | 61 ++++++++++++++++++++++++++++++++++-- 1 file changed, 58 insertions(+), 3 deletions(-)arch/arm64/boot/dts/qcom/sdm845.dtsi +56
-0@@ -1364,6 +1364,55 @@ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; }; + mem_noc: interconnect@1380000 { + compatible = "qcom,sdm845-mem-noc"; + reg = <0 0x01380000 0 0x27200>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + dc_noc: interconnect@14e0000 { + compatible = "qcom,sdm845-dc-noc"; + reg = <0 0x014e0000 0 0x400>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + config_noc: interconnect@1500000 { + compatible = "qcom,sdm845-config-noc"; + reg = <0 0x01500000 0 0x5080>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + compatible = "qcom,sdm845-system-noc"; + reg = <0 0x01620000 0 0x18080>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,sdm845-aggre1-noc"; + reg = <0 0x016e0000 0 0xd080>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sdm845-aggre2-noc"; + reg = <0 0x01700000 0 0x3b100>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,sdm845-mmss-noc"; + reg = <0 0x01740000 0 0x1c1000>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0";@@ -3100,6 +3149,13 @@ #mbox-cells = <1>; }; + gladiator_noc: interconnect@17900000 { + compatible = "qcom,sdm845-gladiator-noc"; + reg = <0 0x17900000 0 0xd080>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + apps_rsc: rsc@179c0000 { label = "apps_rsc"; compatible = "qcom,rpmh-rsc";
arch/arm64/boot/dts/qcom/sdm845.dtsi line 3179
Quoted 6 lines
arch/arm64/boot/dts/qcom/sdm845.dtsi +0
-3@@ -3174,9 +3230,8 @@ }; }; - rsc_hlos: interconnect { - compatible = "qcom,sdm845-rsc-hlos"; - #interconnect-cells = <1>;
With this reworking of the bindings the examples in these files are now broken:Documentation/devicetree/bindings/display/msm/gpu.txt Documentation/devicetree/bindings/display/msm/dpu.txt
It would be nice to fix them up in a subsequent change. -Evan
Re: [PATCH v2 6/6] arm64: dts: sdm845: Redefine interconnect provider DT nodes
Quoted 100 lines · Evan Green
Quoted 88 lines · David Dai
Add the DT nodes for each of the Network-On-Chip interconnect buses found on SDM845 based platform and redefine the
rsc_hloschild node as a bcm-voter device to better represent the hardware.Signed-off-by David Dai <[email protected]>--- arch/arm64/boot/dts/qcom/sdm845.dtsi | 61 ++++++++++++++++++++++++++++++++++-- 1 file changed, 58 insertions(+), 3 deletions(-)arch/arm64/boot/dts/qcom/sdm845.dtsi +49
-0@@ -1364,6 +1364,55 @@ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; }; + mem_noc: interconnect@1380000 { + compatible = "qcom,sdm845-mem-noc"; + reg = <0 0x01380000 0 0x27200>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + dc_noc: interconnect@14e0000 { + compatible = "qcom,sdm845-dc-noc"; + reg = <0 0x014e0000 0 0x400>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + config_noc: interconnect@1500000 { + compatible = "qcom,sdm845-config-noc"; + reg = <0 0x01500000 0 0x5080>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + compatible = "qcom,sdm845-system-noc"; + reg = <0 0x01620000 0 0x18080>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,sdm845-aggre1-noc"; + reg = <0 0x016e0000 0 0xd080>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sdm845-aggre2-noc"; + reg = <0 0x01700000 0 0x3b100>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,sdm845-mmss-noc"; + reg = <0 0x01740000 0 0x1c1000>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sdm845-ufshc","qcom,ufshc",
"jedec,ufs-2.0";arch/arm64/boot/dts/qcom/sdm845.dtsi +7
-0@@ -3100,6 +3149,13 @@ #mbox-cells = <1>; }; + gladiator_noc: interconnect@17900000 { + compatible = "qcom,sdm845-gladiator-noc"; + reg = <0 0x17900000 0 0xd080>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + apps_rsc: rsc@179c0000 { label = "apps_rsc"; compatible = "qcom,rpmh-rsc";arch/arm64/boot/dts/qcom/sdm845.dtsi line 3179
Quoted 6 lines
arch/arm64/boot/dts/qcom/sdm845.dtsi +0
-3@@ -3174,9 +3230,8 @@ }; }; - rsc_hlos: interconnect { - compatible = "qcom,sdm845-rsc-hlos"; - #interconnect-cells = <1>;With this reworking of the bindings the examples in these files are now broken:
Documentation/devicetree/bindings/display/msm/gpu.txtDocumentation/devicetree/bindings/display/msm/dpu.txt
Quoted 1 line
It would be nice to fix them up in a subsequent change.
looks like most of them qcom
display bindings are in the
process of getting converted
to yaml, we'll have to make
sure that it gets addressed
then.
Quoted 1 line
-Evan
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Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.