arm/arm64: Add ITS tests

PROPBASER, PENDBASE and GICR_CTRL will be used for LPI management.

Signed-off-by Eric Auger <[email protected]>

---
  lib/arm/asm/gic-v3.h | 6 ++++++
  1 file changed, 6 insertions(+)

lib/arm/asm/gic-v3.h +1 -0

index 6beeab6..ffb2e26 100644
@@ -18,6 +18,7 @@
   * We expect to be run in Non-secure mode, thus we define the
   * group1 enable bits with respect to that view.
   */
+#define GICD_CTLR			0x0000
  #define GICD_CTLR_RWP			(1U << 31)
  #define GICD_CTLR_ARE_NS		(1U << 4)
  #define GICD_CTLR_ENABLE_G1A		(1U << 1)

lib/arm/asm/gic-v3.h +3 -0

+#define GICR_CTLR			GICD_CTLR
+#define GICR_CTLR_ENABLE_LPIS		(1UL << 0)
+
  #define ICC_SGI1R_AFFINITY_1_SHIFT	16
  #define ICC_SGI1R_AFFINITY_2_SHIFT	32
  #define ICC_SGI1R_AFFINITY_3_SHIFT	48

Detect the presence of an ITS as part of the GICv3 init routine, initialize its base address and read few registers the IIDR, the TYPER to store its dimensioning parameters. Also parse the BASER registers.

This is our first ITS test, belonging to a new "its" group.

Signed-off-by Eric Auger <[email protected]>

---

v2 -> v3:
- updated dates and changed author
- squash "arm/arm64: ITS: Test BASER" into this patch but removes setup_baser which will be introduced later.
- only compile on aarch64
- restrict the new test to aarch64

v1 -> v2:
- clean GITS_TYPER macros and unused fields in typer struct
- remove memory attribute related macros
- remove everything related to memory attributes
- s/dev_baser/coll_baser/ in report_info
- add extra line
- removed index filed in its_baser

---
  arm/Makefile.arm64         |   1 +
  arm/gic.c                  |  49 ++++++++++++++++++
  arm/unittests.cfg          |   7 +++
  lib/arm/asm/gic-v3-its.h   | 103 +++++++++++++++++++++++++++++++++++++
  lib/arm/gic-v3-its.c       |  88 +++++++++++++++++++++++++++++++
  lib/arm/gic.c              |  30 +++++++++--
  lib/arm64/asm/gic-v3-its.h |   1 +
  7 files changed, 274 insertions(+), 5 deletions(-)

create mode 100644 lib/arm/asm/gic-v3-its.h
create mode 100644 lib/arm/gic-v3-its.c
create mode 100644 lib/arm64/asm/gic-v3-its.h

arm/Makefile.arm64 +1 -0

index 6d3dc2c..2571ffb 100644
@@ -19,6 +19,7 @@ endef
  cstart.o = $(TEST_DIR)/cstart64.o
  cflatobjs += lib/arm64/processor.o
  cflatobjs += lib/arm64/spinlock.o
+cflatobjs += lib/arm/gic-v3-its.o
 
  OBJDIRS += lib/arm64
 

arm/gic.c +25 -0

index abf08c7..4d7dd03 100644
@@ -16,6 +16,7 @@
  #include <asm/processor.h>
  #include <asm/delay.h>
  #include <asm/gic.h>
+#include <asm/gic-v3-its.h>
  #include <asm/smp.h>
  #include <asm/barrier.h>
  #include <asm/io.h>

@@ -518,6 +519,50 @@ static void gic_test_mmio(void)
  		test_targets(nr_irqs);
  }
 
+#if defined(__arm__)
+
+static void test_its_introspection(void) {}
+
+#else /* __arch64__ */
+
+static void test_its_introspection(void)
+{
+	struct its_baser *dev_baser, *coll_baser;
+	struct its_typer *typer = &its_data.typer;
+
+	if (!gicv3_its_base()) {
+		report_skip("No ITS, skip ...");
+		return;
+	}
+
+	/* IIDR */
+	report(test_readonly_32(gicv3_its_base() + GITS_IIDR, false),
+	       "GITS_IIDR is read-only"),
+
+	/* TYPER */
+	report(test_readonly_32(gicv3_its_base() + GITS_TYPER, false),
+	       "GITS_TYPER is read-only");
+

arm/gic.c +8 -0

+}
+
+#endif
+
  int main(int argc, char **argv)
  {
  	if (!gic_init()) {

@@ -549,6 +594,10 @@ int main(int argc, char **argv)
  		report_prefix_push(argv[1]);
  		gic_test_mmio();
  		report_prefix_pop();
+	} else if (strcmp(argv[1], "its-introspection") == 0) {
+		report_prefix_push(argv[1]);
+		test_its_introspection();
+		report_prefix_pop();
  	} else {
  		report_abort("Unknown subtest '%s'", argv[1]);
  	}

arm/unittests.cfg +7 -0

index daeb5a0..ba2b31b 100644
@@ -122,6 +122,13 @@ smp = $MAX_SMP
  extra_params = -machine gic-version=3 -append 'active'
  groups = gic
 
+[its-introspection]
+file = gic.flat
+smp = $MAX_SMP
+extra_params = -machine gic-version=3 -append 'its-introspection'
+groups = its
+arch = arm64
+
  # Test PSCI emulation
  [psci]
  file = psci.flat

lib/arm/asm/gic-v3-its.h new file +103 -0

new file mode 100644
index 0000000..815c515
@@ -0,0 +1,103 @@
+/*
+ * All ITS* defines are lifted from include/linux/irqchip/arm-gic-v3.h
+ *
+ * Copyright (C) 2020, Red Hat Inc, Eric Auger <[email protected]>
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.
+ */
+#ifndef _ASMARM_GIC_V3_ITS_H_
+#define _ASMARM_GIC_V3_ITS_H_
+
+#ifndef __ASSEMBLY__
+
+struct its_typer {
+	unsigned int ite_size;
+	unsigned int eventid_bits;
+	unsigned int deviceid_bits;
+	unsigned int collid_bits;
+	bool pta;
+	bool phys_lpi;
+	bool virt_lpi;
+};
+
+struct its_baser {
+	int type;
+	size_t psz;
+	int nr_pages;
+	bool indirect;
+	phys_addr_t table_addr;
+	bool valid;
+	int esz;
+};
+
+#define GITS_BASER_NR_REGS              8
+
+struct its_data {
+	void *base;
+	struct its_typer typer;
+	struct its_baser baser[GITS_BASER_NR_REGS];
+};
+
+extern struct its_data its_data;
+
+#define gicv3_its_base()		(its_data.base)
+
+#if defined(__aarch64__)
+
+#define GITS_CTLR			0x0000
+#define GITS_IIDR			0x0004
+#define GITS_TYPER			0x0008
+#define GITS_CBASER			0x0080
+#define GITS_CWRITER			0x0088
+#define GITS_CREADR			0x0090
+#define GITS_BASER			0x0100
+
+#define GITS_TYPER_PLPIS                BIT(0)
+#define GITS_TYPER_VLPIS		BIT(1)
+#define GITS_TYPER_ITT_ENTRY_SIZE	GENMASK_ULL(7, 4)
+#define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT	4
+#define GITS_TYPER_IDBITS		GENMASK_ULL(8, 12)
+#define GITS_TYPER_IDBITS_SHIFT         8
+#define GITS_TYPER_DEVBITS		GENMASK_ULL(13, 17)
+#define GITS_TYPER_DEVBITS_SHIFT        13
+#define GITS_TYPER_PTA                  BIT(19)
+#define GITS_TYPER_CIDBITS		GENMASK_ULL(32, 35)
+#define GITS_TYPER_CIDBITS_SHIFT	32
+#define GITS_TYPER_CIL			BIT(36)
+
+#define GITS_CTLR_ENABLE		(1U << 0)
+
+#define GITS_CBASER_VALID		(1UL << 63)
+
+#define GITS_BASER_VALID		BIT(63)
+#define GITS_BASER_INDIRECT		BIT(62)
+#define GITS_BASER_TYPE_SHIFT		(56)
+#define GITS_BASER_TYPE(r)		(((r) >> GITS_BASER_TYPE_SHIFT) & 7)
+#define GITS_BASER_ENTRY_SIZE_SHIFT	(48)
+#define GITS_BASER_ENTRY_SIZE(r)	((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
+#define GITS_BASER_PAGE_SIZE_SHIFT	(8)
+#define GITS_BASER_PAGE_SIZE_4K		(0UL << GITS_BASER_PAGE_SIZE_SHIFT)
+#define GITS_BASER_PAGE_SIZE_16K	(1UL << GITS_BASER_PAGE_SIZE_SHIFT)
+#define GITS_BASER_PAGE_SIZE_64K	(2UL << GITS_BASER_PAGE_SIZE_SHIFT)
+#define GITS_BASER_PAGE_SIZE_MASK	(3UL << GITS_BASER_PAGE_SIZE_SHIFT)
+#define GITS_BASER_PAGES_MAX		256
+#define GITS_BASER_PAGES_SHIFT		(0)
+#define GITS_BASER_NR_PAGES(r)		(((r) & 0xff) + 1)
+#define GITS_BASER_PHYS_ADDR_MASK	0xFFFFFFFFF000
+#define GITS_BASER_TYPE_NONE		0
+#define GITS_BASER_TYPE_DEVICE		1
+#define GITS_BASER_TYPE_COLLECTION	4
+
+extern void its_parse_typer(void);
+extern void its_init(void);
+extern int its_parse_baser(int i, struct its_baser *baser);
+extern struct its_baser *its_lookup_baser(int type);
+
+#else /* __arm__ */
+
+static inline void its_init(void) {}
+
+#endif
+
+#endif /* !__ASSEMBLY__ */
+#endif /* _ASMARM_GIC_V3_ITS_H_ */

lib/arm/gic-v3-its.c new file +30 -0

new file mode 100644
index 0000000..2c0ce13
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2020, Red Hat Inc, Eric Auger <[email protected]>
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.
+ */
+#include <asm/gic.h>
+#include <alloc_page.h>
+#include <asm/gic-v3-its.h>
+
+void its_parse_typer(void)
+{
+	u64 typer = readq(gicv3_its_base() + GITS_TYPER);
+
+	its_data.typer.ite_size = ((typer & GITS_TYPER_ITT_ENTRY_SIZE) >>
+					GITS_TYPER_ITT_ENTRY_SIZE_SHIFT) + 1;
+	its_data.typer.pta = typer & GITS_TYPER_PTA;
+	its_data.typer.eventid_bits = ((typer & GITS_TYPER_IDBITS) >>
+						GITS_TYPER_IDBITS_SHIFT) + 1;
+	its_data.typer.deviceid_bits = ((typer & GITS_TYPER_DEVBITS) >>
+						GITS_TYPER_DEVBITS_SHIFT) + 1;
+
+	if (typer & GITS_TYPER_CIL)
+		its_data.typer.collid_bits = ((typer & GITS_TYPER_CIDBITS) >>
+						GITS_TYPER_CIDBITS_SHIFT) + 1;
+	else
+		its_data.typer.collid_bits = 16;
+
+	its_data.typer.virt_lpi = typer & GITS_TYPER_VLPIS;
+	its_data.typer.phys_lpi = typer & GITS_TYPER_PLPIS;
+}

lib/arm/gic-v3-its.c new file +48 -0

+
+	baser->valid = val & GITS_BASER_VALID;
+	baser->indirect = val & GITS_BASER_INDIRECT;
+	baser->type = GITS_BASER_TYPE(val);
+	baser->esz = GITS_BASER_ENTRY_SIZE(val);
+	baser->nr_pages = GITS_BASER_NR_PAGES(val);
+	baser->table_addr = val & GITS_BASER_PHYS_ADDR_MASK;
+	switch (val & GITS_BASER_PAGE_SIZE_MASK) {
+	case GITS_BASER_PAGE_SIZE_4K:
+		baser->psz = SZ_4K;
+		break;
+	case GITS_BASER_PAGE_SIZE_16K:
+		baser->psz = SZ_16K;
+		break;
+	case GITS_BASER_PAGE_SIZE_64K:
+		baser->psz = SZ_64K;
+		break;
+	default:
+		baser->psz = SZ_64K;
+	}
+	return 0;
+}
+
+struct its_baser *its_lookup_baser(int type)
+{
+	int i;
+
+	for (i = 0; i < GITS_BASER_NR_REGS; i++) {
+		struct its_baser *baser = &its_data.baser[i];
+
+		if (baser->type == type)
+			return baser;
+	}
+	return NULL;
+}
+
+void its_init(void)
+{
+	int i;
+
+	if (!its_data.base)
+		return;
+
+	its_parse_typer();
+	for (i = 0; i < GITS_BASER_NR_REGS; i++)
+		its_parse_baser(i, &its_data.baser[i]);
+}
+

lib/arm/gic.c +25 -5

index aa9cb86..6b70b05 100644
@@ -6,9 +6,11 @@
  #include <devicetree.h>
  #include <asm/gic.h>
  #include <asm/io.h>
+#include <asm/gic-v3-its.h>
 
  struct gicv2_data gicv2_data;
  struct gicv3_data gicv3_data;
+struct its_data its_data;
 
  struct gic_common_ops {
  	void (*enable_defaults)(void);

@@ -44,12 +46,13 @@ static const struct gic_common_ops gicv3_common_ops = {
   * Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
   */
  static bool
-gic_get_dt_bases(const char *compatible, void **base1, void **base2)
+gic_get_dt_bases(const char *compatible, void **base1, void **base2, void **base3)
  {
  	struct dt_pbus_reg reg;
-	struct dt_device gic;
+	struct dt_device gic, its;
  	struct dt_bus bus;
-	int node, ret, i;
+	int node, subnode, ret, i, len;
+	const void *fdt = dt_fdt();
 
  	dt_bus_init_defaults(&bus);
  	dt_device_init(&gic, &bus, NULL);

@@ -74,19 +77,35 @@ gic_get_dt_bases(const char *compatible, void **base1, void **base2)
  		base2[i] = ioremap(reg.addr, reg.size);
  	}
 
+	if (base3 && !strcmp(compatible, "arm,gic-v3")) {
+		dt_for_each_subnode(node, subnode) {
+			const struct fdt_property *prop;
+
+			prop = fdt_get_property(fdt, subnode, "compatible", &len);
+			if (!strcmp((char *)prop->data, "arm,gic-v3-its")) {
+				dt_device_bind_node(&its, subnode);
+				ret = dt_pbus_translate(&its, 0, &reg);
+				assert(ret == 0);
+				*base3 = ioremap(reg.addr, reg.size);
+				break;
+			}
+		}
+
+	}
+
  	return true;
  }
 
  int gicv2_init(void)
  {
  	return gic_get_dt_bases("arm,cortex-a15-gic",
-			&gicv2_data.dist_base, &gicv2_data.cpu_base);
+			&gicv2_data.dist_base, &gicv2_data.cpu_base, NULL);
  }
 
  int gicv3_init(void)
  {
  	return gic_get_dt_bases("arm,gic-v3", &gicv3_data.dist_base,
-			&gicv3_data.redist_bases[0]);
+			&gicv3_data.redist_bases[0], &its_data.base);
  }
 
  int gic_version(void)

@@ -104,6 +123,7 @@ int gic_init(void)
  		gic_common_ops = &gicv2_common_ops;
  	else if (gicv3_init())
  		gic_common_ops = &gicv3_common_ops;
+	its_init();
  	return gic_version();
  }
 

lib/arm64/asm/gic-v3-its.h new file +1 -0

new file mode 100644
index 0000000..083cba4
@@ -0,0 +1 @@
+#include "../../arm/asm/gic-v3-its.h"

Detect the presence of an ITS as part of the GICv3 init routine, initialize its base address and read few registers the IIDR, the TYPER to store its dimensioning parameters. Also parse the BASER registers.

This is our first ITS test, belonging to a new "its" group.

Signed-off-by Eric Auger <[email protected]>

---

v2 -> v3:
- updated dates and changed author
- squash "arm/arm64: ITS: Test BASER" into this patch but removes setup_baser which will be introduced later.
- only compile on aarch64
- restrict the new test to aarch64

v1 -> v2:
- clean GITS_TYPER macros and unused fields in typer struct
- remove memory attribute related macros
- remove everything related to memory attributes
- s/dev_baser/coll_baser/ in report_info
- add extra line
- removed index filed in its_baser

---
 arm/Makefile.arm64         |   1 +
 arm/gic.c                  |  49 ++++++++++++++++++
 arm/unittests.cfg          |   7 +++
 lib/arm/asm/gic-v3-its.h   | 103 +++++++++++++++++++++++++++++++++++++
 lib/arm/gic-v3-its.c       |  88 +++++++++++++++++++++++++++++++
 lib/arm/gic.c              |  30 +++++++++--
 lib/arm64/asm/gic-v3-its.h |   1 +
 7 files changed, 274 insertions(+), 5 deletions(-)
 create mode 100644 lib/arm/asm/gic-v3-its.h
 create mode 100644 lib/arm/gic-v3-its.c
 create mode 100644 lib/arm64/asm/gic-v3-its.h

arm/Makefile.arm64 +0 -0

index 6d3dc2c..2571ffb 100644

arm/gic.c +45 -0

+
+#else /* __arch64__ */
+
+static void test_its_introspection(void)
+{
+	struct its_baser *dev_baser, *coll_baser;
+	struct its_typer *typer = &its_data.typer;
+
+	if (!gicv3_its_base()) {
+		report_skip("No ITS, skip ...");
+		return;
+	}
+
+	/* IIDR */
+	report(test_readonly_32(gicv3_its_base() + GITS_IIDR, false),
+	       "GITS_IIDR is read-only"),
+
+	/* TYPER */
+	report(test_readonly_32(gicv3_its_base() + GITS_TYPER, false),
+	       "GITS_TYPER is read-only");
+
+	report(typer->phys_lpi, "ITS supports physical LPIs");
+	report_info("vLPI support: %s", typer->virt_lpi ? "yes" : "no");
+	report_info("ITT entry size = 0x%x", typer->ite_size);
+	report_info("Bit Count: EventID=%d DeviceId=%d CollId=%d",
+		    typer->eventid_bits, typer->deviceid_bits,
+		    typer->collid_bits);
+	report(typer->eventid_bits && typer->deviceid_bits &&
+	       typer->collid_bits, "ID spaces");
+	report_info("Target address format %s",
+			typer->pta ? "Redist basse address" : "PE #");
+
+	dev_baser = its_lookup_baser(GITS_BASER_TYPE_DEVICE);
+	coll_baser = its_lookup_baser(GITS_BASER_TYPE_COLLECTION);
+	report(dev_baser && coll_baser, "detect device and collection BASER");
+	report_info("device baser entry_size = 0x%x", dev_baser->esz);
+	report_info("collection baser entry_size = 0x%x", coll_baser->esz);
+}
+
+#endif
+
 int main(int argc, char **argv)
 {
 	if (!gic_init()) {

@@ -549,6 +594,10 @@ int main(int argc, char **argv)
 		report_prefix_push(argv[1]);
 		gic_test_mmio();
 		report_prefix_pop();
+	} else if (strcmp(argv[1], "its-introspection") == 0) {
+		report_prefix_push(argv[1]);
+		test_its_introspection();
+		report_prefix_pop();
 	} else {
 		report_abort("Unknown subtest '%s'", argv[1]);
 	}

arm/unittests.cfg +7 -0

index daeb5a0..ba2b31b 100644
@@ -122,6 +122,13 @@ smp = $MAX_SMP
 extra_params = -machine gic-version=3 -append 'active'
 groups = gic
 
+[its-introspection]
+file = gic.flat
+smp = $MAX_SMP
+extra_params = -machine gic-version=3 -append 'its-introspection'
+groups = its
+arch = arm64
+
 # Test PSCI emulation
 [psci]
 file = psci.flat

lib/arm/asm/gic-v3-its.h new file +1 -0

new file mode 100644
index 0000000..815c515
@@ -0,0 +1,103 @@
+/*

lib/arm/asm/gic-v3-its.h new file +77 -0

+
+struct its_typer {
+	unsigned int ite_size;
+	unsigned int eventid_bits;
+	unsigned int deviceid_bits;
+	unsigned int collid_bits;
+	bool pta;
+	bool phys_lpi;
+	bool virt_lpi;
+};
+
+struct its_baser {
+	int type;
+	size_t psz;
+	int nr_pages;
+	bool indirect;
+	phys_addr_t table_addr;
+	bool valid;
+	int esz;
+};
+
+#define GITS_BASER_NR_REGS              8
+
+struct its_data {
+	void *base;
+	struct its_typer typer;
+	struct its_baser baser[GITS_BASER_NR_REGS];
+};
+
+extern struct its_data its_data;
+
+#define gicv3_its_base()		(its_data.base)
+
+#if defined(__aarch64__)
+
+#define GITS_CTLR			0x0000
+#define GITS_IIDR			0x0004
+#define GITS_TYPER			0x0008
+#define GITS_CBASER			0x0080
+#define GITS_CWRITER			0x0088
+#define GITS_CREADR			0x0090
+#define GITS_BASER			0x0100
+
+#define GITS_TYPER_PLPIS                BIT(0)
+#define GITS_TYPER_VLPIS		BIT(1)
+#define GITS_TYPER_ITT_ENTRY_SIZE	GENMASK_ULL(7, 4)
+#define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT	4
+#define GITS_TYPER_IDBITS		GENMASK_ULL(8, 12)
+#define GITS_TYPER_IDBITS_SHIFT         8
+#define GITS_TYPER_DEVBITS		GENMASK_ULL(13, 17)
+#define GITS_TYPER_DEVBITS_SHIFT        13
+#define GITS_TYPER_PTA                  BIT(19)
+#define GITS_TYPER_CIDBITS		GENMASK_ULL(32, 35)
+#define GITS_TYPER_CIDBITS_SHIFT	32
+#define GITS_TYPER_CIL			BIT(36)
+
+#define GITS_CTLR_ENABLE		(1U << 0)
+
+#define GITS_CBASER_VALID		(1UL << 63)
+
+#define GITS_BASER_VALID		BIT(63)
+#define GITS_BASER_INDIRECT		BIT(62)
+#define GITS_BASER_TYPE_SHIFT		(56)
+#define GITS_BASER_TYPE(r)		(((r) >> GITS_BASER_TYPE_SHIFT) & 7)
+#define GITS_BASER_ENTRY_SIZE_SHIFT	(48)
+#define GITS_BASER_ENTRY_SIZE(r)	((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
+#define GITS_BASER_PAGE_SIZE_SHIFT	(8)
+#define GITS_BASER_PAGE_SIZE_4K		(0UL << GITS_BASER_PAGE_SIZE_SHIFT)
+#define GITS_BASER_PAGE_SIZE_16K	(1UL << GITS_BASER_PAGE_SIZE_SHIFT)
+#define GITS_BASER_PAGE_SIZE_64K	(2UL << GITS_BASER_PAGE_SIZE_SHIFT)
+#define GITS_BASER_PAGE_SIZE_MASK	(3UL << GITS_BASER_PAGE_SIZE_SHIFT)
+#define GITS_BASER_PAGES_MAX		256
+#define GITS_BASER_PAGES_SHIFT		(0)
+#define GITS_BASER_NR_PAGES(r)		(((r) & 0xff) + 1)
+#define GITS_BASER_PHYS_ADDR_MASK	0xFFFFFFFFF000
+#define GITS_BASER_TYPE_NONE		0
+#define GITS_BASER_TYPE_DEVICE		1

lib/arm/asm/gic-v3-its.h new file +5 -0

+
+#endif
+
+#endif /* !__ASSEMBLY__ */
+#endif /* _ASMARM_GIC_V3_ITS_H_ */

lib/arm/gic-v3-its.c new file +14 -0

new file mode 100644
index 0000000..2c0ce13
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2020, Red Hat Inc, Eric Auger <[email protected]>
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.
+ */
+#include <asm/gic.h>
+#include <alloc_page.h>
+#include <asm/gic-v3-its.h>
+
+void its_parse_typer(void)
+{
+	u64 typer = readq(gicv3_its_base() + GITS_TYPER);
+
+	its_data.typer.ite_size = ((typer & GITS_TYPER_ITT_ENTRY_SIZE) >>

lib/arm/gic-v3-its.c new file +64 -0

+	else
+		its_data.typer.collid_bits = 16;
+
+	its_data.typer.virt_lpi = typer & GITS_TYPER_VLPIS;
+	its_data.typer.phys_lpi = typer & GITS_TYPER_PLPIS;
+}
+
+int its_parse_baser(int i, struct its_baser *baser)
+{
+	void *reg_addr = gicv3_its_base() + GITS_BASER + i * 8;
+	u64 val = readq(reg_addr);
+
+	if (!val) {
+		memset(baser, 0, sizeof(*baser));
+		return -1;
+	}
+
+	baser->valid = val & GITS_BASER_VALID;
+	baser->indirect = val & GITS_BASER_INDIRECT;
+	baser->type = GITS_BASER_TYPE(val);
+	baser->esz = GITS_BASER_ENTRY_SIZE(val);
+	baser->nr_pages = GITS_BASER_NR_PAGES(val);
+	baser->table_addr = val & GITS_BASER_PHYS_ADDR_MASK;
+	switch (val & GITS_BASER_PAGE_SIZE_MASK) {
+	case GITS_BASER_PAGE_SIZE_4K:
+		baser->psz = SZ_4K;
+		break;
+	case GITS_BASER_PAGE_SIZE_16K:
+		baser->psz = SZ_16K;
+		break;
+	case GITS_BASER_PAGE_SIZE_64K:
+		baser->psz = SZ_64K;
+		break;
+	default:
+		baser->psz = SZ_64K;
+	}
+	return 0;
+}
+
+struct its_baser *its_lookup_baser(int type)
+{
+	int i;
+
+	for (i = 0; i < GITS_BASER_NR_REGS; i++) {
+		struct its_baser *baser = &its_data.baser[i];
+
+		if (baser->type == type)
+			return baser;
+	}
+	return NULL;
+}
+
+void its_init(void)
+{
+	int i;
+
+	if (!its_data.base)
+		return;
+
+	its_parse_typer();
+	for (i = 0; i < GITS_BASER_NR_REGS; i++)
+		its_parse_baser(i, &its_data.baser[i]);
+}
+

lib/arm/gic.c +6 -3

index aa9cb86..6b70b05 100644
@@ -6,9 +6,11 @@
 #include <devicetree.h>
 #include <asm/gic.h>
 #include <asm/io.h>
+#include <asm/gic-v3-its.h>
 
 struct gicv2_data gicv2_data;
 struct gicv3_data gicv3_data;
+struct its_data its_data;
 
 struct gic_common_ops {
 	void (*enable_defaults)(void);

@@ -44,12 +46,13 @@ static const struct gic_common_ops gicv3_common_ops = {
  * Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
  */
 static bool
-gic_get_dt_bases(const char *compatible, void **base1, void **base2)
+gic_get_dt_bases(const char *compatible, void **base1, void **base2, void **base3)
 {
 	struct dt_pbus_reg reg;
-	struct dt_device gic;
+	struct dt_device gic, its;
 	struct dt_bus bus;
-	int node, ret, i;
+	int node, subnode, ret, i, len;
+	const void *fdt = dt_fdt();
 
 	dt_bus_init_defaults(&bus);
 	dt_device_init(&gic, &bus, NULL);

lib/arm/gic.c +18 -2

+		dt_for_each_subnode(node, subnode) {
+			const struct fdt_property *prop;
+
+			prop = fdt_get_property(fdt, subnode, "compatible", &len);
+			if (!strcmp((char *)prop->data, "arm,gic-v3-its")) {
+				dt_device_bind_node(&its, subnode);
+				ret = dt_pbus_translate(&its, 0, &reg);
+				assert(ret == 0);
+				*base3 = ioremap(reg.addr, reg.size);
+				break;
+			}
+		}
+
+	}
+
 	return true;
 }
 
 int gicv2_init(void)
 {
 	return gic_get_dt_bases("arm,cortex-a15-gic",
-			&gicv2_data.dist_base, &gicv2_data.cpu_base);
+			&gicv2_data.dist_base, &gicv2_data.cpu_base, NULL);
 }
 
 int gicv3_init(void)
 {
 	return gic_get_dt_bases("arm,gic-v3", &gicv3_data.dist_base,
-			&gicv3_data.redist_bases[0]);
+			&gicv3_data.redist_bases[0], &its_data.base);
 }
 
 int gic_version(void)

@@ -104,6 +123,7 @@ int gic_init(void)
 		gic_common_ops = &gicv2_common_ops;
 	else if (gicv3_init())
 		gic_common_ops = &gicv3_common_ops;
+	its_init();
 	return gic_version();
 }
 

lib/arm64/asm/gic-v3-its.h new file +1 -0

new file mode 100644
index 0000000..083cba4
@@ -0,0 +1 @@
+#include "../../arm/asm/gic-v3-its.h"

Signature · 1 line

2.20.1

Quoted 43 lines · Eric Auger

Detect the presence of an ITS as part of the GICv3 init routine, initialize its base address and read few registers the IIDR, the TYPER to store its dimensioning parameters. Also parse the BASER registers.

This is our first ITS test, belonging to a new "its" group.

Signed-off-by Eric Auger <[email protected]>

---

v2 -> v3:
- updated dates and changed author
- squash "arm/arm64: ITS: Test BASER" into this patch but removes setup_baser which will be introduced later.
- only compile on aarch64
- restrict the new test to aarch64

v1 -> v2:
- clean GITS_TYPER macros and unused fields in typer struct
- remove memory attribute related macros
- remove everything related to memory attributes
- s/dev_baser/coll_baser/ in report_info
- add extra line
- removed index filed in its_baser

---
 arm/Makefile.arm64         |   1 +
 arm/gic.c                  |  49 ++++++++++++++++++
 arm/unittests.cfg          |   7 +++
 lib/arm/asm/gic-v3-its.h   | 103 +++++++++++++++++++++++++++++++++++++
 lib/arm/gic-v3-its.c       |  88 +++++++++++++++++++++++++++++++
 lib/arm/gic.c              |  30 +++++++++--
 lib/arm64/asm/gic-v3-its.h |   1 +
 7 files changed, 274 insertions(+), 5 deletions(-)
 create mode 100644 lib/arm/asm/gic-v3-its.h
 create mode 100644 lib/arm/gic-v3-its.c
 create mode 100644 lib/arm64/asm/gic-v3-its.h

arm/Makefile.arm64 +0 -0

index 6d3dc2c..2571ffb 100644

arm/Makefile.arm64 endef · line 22

Quoted 4 lines

arm/Makefile.arm64 +1 -0

@@ -19,6 +19,7 @@ endef
 cstart.o = $(TEST_DIR)/cstart64.o
 cflatobjs += lib/arm64/processor.o
 cflatobjs += lib/arm64/spinlock.o
+cflatobjs += lib/arm/gic-v3-its.o

If gic-v3-its.c will never be compiled for arm, then it should probably go lib/arm64, not lib/arm. Same comment for all other new source and header files. The only problem with that is...>

arm/gic.c line 19

Quoted 12 lines

arm/Makefile.arm64 +0 -0

 OBJDIRS += lib/arm64
 

arm/gic.c +1 -0

index abf08c7..4d7dd03 100644
@@ -16,6 +16,7 @@
 #include <asm/processor.h>
 #include <asm/delay.h>
 #include <asm/gic.h>
+#include <asm/gic-v3-its.h>

...here where we'd have to do

#if defined(__aarch64__)
#include <asm/gic-v3-its.h>
#endif

which is ugly. However that can be avoided by adding an empty lib/arm/asm/gic-v3-its.h file.

Quoted 9 lines

arm/gic.c +0 -0

 #include <asm/smp.h>
 #include <asm/barrier.h>
 #include <asm/io.h>

@@ -518,6 +519,50 @@ static void gic_test_mmio(void)
 		test_targets(nr_irqs);
 }
 

arm/gic.c static void gic_test_mmio(void) · line 524

Quoted 3 lines

arm/gic.c +3 -0

+#if defined(__arm__)
+
+static void test_its_introspection(void) {}

static void test_its_introspection(void)

 {
     report_abort(...);

}

Quoted 87 lines

arm/gic.c +45 -0

+
+#else /* __arch64__ */
+
+static void test_its_introspection(void)
+{
+	struct its_baser *dev_baser, *coll_baser;
+	struct its_typer *typer = &its_data.typer;
+
+	if (!gicv3_its_base()) {
+		report_skip("No ITS, skip ...");
+		return;
+	}
+
+	/* IIDR */
+	report(test_readonly_32(gicv3_its_base() + GITS_IIDR, false),
+	       "GITS_IIDR is read-only"),
+
+	/* TYPER */
+	report(test_readonly_32(gicv3_its_base() + GITS_TYPER, false),
+	       "GITS_TYPER is read-only");
+
+	report(typer->phys_lpi, "ITS supports physical LPIs");
+	report_info("vLPI support: %s", typer->virt_lpi ? "yes" : "no");
+	report_info("ITT entry size = 0x%x", typer->ite_size);
+	report_info("Bit Count: EventID=%d DeviceId=%d CollId=%d",
+		    typer->eventid_bits, typer->deviceid_bits,
+		    typer->collid_bits);
+	report(typer->eventid_bits && typer->deviceid_bits &&
+	       typer->collid_bits, "ID spaces");
+	report_info("Target address format %s",
+			typer->pta ? "Redist basse address" : "PE #");
+
+	dev_baser = its_lookup_baser(GITS_BASER_TYPE_DEVICE);
+	coll_baser = its_lookup_baser(GITS_BASER_TYPE_COLLECTION);
+	report(dev_baser && coll_baser, "detect device and collection BASER");
+	report_info("device baser entry_size = 0x%x", dev_baser->esz);
+	report_info("collection baser entry_size = 0x%x", coll_baser->esz);
+}
+
+#endif
+
 int main(int argc, char **argv)
 {
 	if (!gic_init()) {

@@ -549,6 +594,10 @@ int main(int argc, char **argv)
 		report_prefix_push(argv[1]);
 		gic_test_mmio();
 		report_prefix_pop();
+	} else if (strcmp(argv[1], "its-introspection") == 0) {
+		report_prefix_push(argv[1]);
+		test_its_introspection();
+		report_prefix_pop();
 	} else {
 		report_abort("Unknown subtest '%s'", argv[1]);
 	}

arm/unittests.cfg +7 -0

index daeb5a0..ba2b31b 100644
@@ -122,6 +122,13 @@ smp = $MAX_SMP
 extra_params = -machine gic-version=3 -append 'active'
 groups = gic
 
+[its-introspection]
+file = gic.flat
+smp = $MAX_SMP
+extra_params = -machine gic-version=3 -append 'its-introspection'
+groups = its
+arch = arm64
+
 # Test PSCI emulation
 [psci]
 file = psci.flat

lib/arm/asm/gic-v3-its.h new file +7 -0

new file mode 100644
index 0000000..815c515
@@ -0,0 +1,103 @@
+/*
+ * All ITS* defines are lifted from include/linux/irqchip/arm-gic-v3.h
+ *
+ * Copyright (C) 2020, Red Hat Inc, Eric Auger <[email protected]>
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.
+ */

lib/arm/asm/gic-v3-its.h line 11

Quoted 4 lines

lib/arm/asm/gic-v3-its.h new file +4 -0

+#ifndef _ASMARM_GIC_V3_ITS_H_
+#define _ASMARM_GIC_V3_ITS_H_
+
+#ifndef __ASSEMBLY__

Doesn't look like you use the #else /* __ASSEMBLY__ */ side of this. I'd leave out the #ifndef until we add defines we need to access from assembler.

Quoted 83 lines

lib/arm/asm/gic-v3-its.h new file +82 -0

+
+struct its_typer {
+	unsigned int ite_size;
+	unsigned int eventid_bits;
+	unsigned int deviceid_bits;
+	unsigned int collid_bits;
+	bool pta;
+	bool phys_lpi;
+	bool virt_lpi;
+};
+
+struct its_baser {
+	int type;
+	size_t psz;
+	int nr_pages;
+	bool indirect;
+	phys_addr_t table_addr;
+	bool valid;
+	int esz;
+};
+
+#define GITS_BASER_NR_REGS              8
+
+struct its_data {
+	void *base;
+	struct its_typer typer;
+	struct its_baser baser[GITS_BASER_NR_REGS];
+};
+
+extern struct its_data its_data;
+
+#define gicv3_its_base()		(its_data.base)
+
+#if defined(__aarch64__)
+
+#define GITS_CTLR			0x0000
+#define GITS_IIDR			0x0004
+#define GITS_TYPER			0x0008
+#define GITS_CBASER			0x0080
+#define GITS_CWRITER			0x0088
+#define GITS_CREADR			0x0090
+#define GITS_BASER			0x0100
+
+#define GITS_TYPER_PLPIS                BIT(0)
+#define GITS_TYPER_VLPIS		BIT(1)
+#define GITS_TYPER_ITT_ENTRY_SIZE	GENMASK_ULL(7, 4)
+#define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT	4
+#define GITS_TYPER_IDBITS		GENMASK_ULL(8, 12)
+#define GITS_TYPER_IDBITS_SHIFT         8
+#define GITS_TYPER_DEVBITS		GENMASK_ULL(13, 17)
+#define GITS_TYPER_DEVBITS_SHIFT        13
+#define GITS_TYPER_PTA                  BIT(19)
+#define GITS_TYPER_CIDBITS		GENMASK_ULL(32, 35)
+#define GITS_TYPER_CIDBITS_SHIFT	32
+#define GITS_TYPER_CIL			BIT(36)
+
+#define GITS_CTLR_ENABLE		(1U << 0)
+
+#define GITS_CBASER_VALID		(1UL << 63)
+
+#define GITS_BASER_VALID		BIT(63)
+#define GITS_BASER_INDIRECT		BIT(62)
+#define GITS_BASER_TYPE_SHIFT		(56)
+#define GITS_BASER_TYPE(r)		(((r) >> GITS_BASER_TYPE_SHIFT) & 7)
+#define GITS_BASER_ENTRY_SIZE_SHIFT	(48)
+#define GITS_BASER_ENTRY_SIZE(r)	((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
+#define GITS_BASER_PAGE_SIZE_SHIFT	(8)
+#define GITS_BASER_PAGE_SIZE_4K		(0UL << GITS_BASER_PAGE_SIZE_SHIFT)
+#define GITS_BASER_PAGE_SIZE_16K	(1UL << GITS_BASER_PAGE_SIZE_SHIFT)
+#define GITS_BASER_PAGE_SIZE_64K	(2UL << GITS_BASER_PAGE_SIZE_SHIFT)
+#define GITS_BASER_PAGE_SIZE_MASK	(3UL << GITS_BASER_PAGE_SIZE_SHIFT)
+#define GITS_BASER_PAGES_MAX		256
+#define GITS_BASER_PAGES_SHIFT		(0)
+#define GITS_BASER_NR_PAGES(r)		(((r) & 0xff) + 1)
+#define GITS_BASER_PHYS_ADDR_MASK	0xFFFFFFFFF000
+#define GITS_BASER_TYPE_NONE		0
+#define GITS_BASER_TYPE_DEVICE		1
+#define GITS_BASER_TYPE_COLLECTION	4
+
+extern void its_parse_typer(void);
+extern void its_init(void);
+extern int its_parse_baser(int i, struct its_baser *baser);

lib/arm/asm/gic-v3-its.h line 98

Quoted 5 lines

lib/arm/asm/gic-v3-its.h new file +5 -0

+extern struct its_baser *its_lookup_baser(int type);
+
+#else /* __arm__ */
+
+static inline void its_init(void) {}

Looks like the empty gic-v3-its.h I suggested creating above will actually be useful. We can add stubs like this in it.

Quoted 26 lines

lib/arm/asm/gic-v3-its.h new file +5 -0

+
+#endif
+
+#endif /* !__ASSEMBLY__ */
+#endif /* _ASMARM_GIC_V3_ITS_H_ */

lib/arm/gic-v3-its.c new file +14 -0

new file mode 100644
index 0000000..2c0ce13
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2020, Red Hat Inc, Eric Auger <[email protected]>
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.
+ */
+#include <asm/gic.h>
+#include <alloc_page.h>
+#include <asm/gic-v3-its.h>
+
+void its_parse_typer(void)
+{
+	u64 typer = readq(gicv3_its_base() + GITS_TYPER);
+
+	its_data.typer.ite_size = ((typer & GITS_TYPER_ITT_ENTRY_SIZE) >>

lib/arm/gic-v3-its.c line 24

Quoted 10 lines

lib/arm/gic-v3-its.c new file +10 -0

+					GITS_TYPER_ITT_ENTRY_SIZE_SHIFT) + 1;
+	its_data.typer.pta = typer & GITS_TYPER_PTA;
+	its_data.typer.eventid_bits = ((typer & GITS_TYPER_IDBITS) >>
+						GITS_TYPER_IDBITS_SHIFT) + 1;
+	its_data.typer.deviceid_bits = ((typer & GITS_TYPER_DEVBITS) >>
+						GITS_TYPER_DEVBITS_SHIFT) + 1;
+
+	if (typer & GITS_TYPER_CIL)
+		its_data.typer.collid_bits = ((typer & GITS_TYPER_CIDBITS) >>
+						GITS_TYPER_CIDBITS_SHIFT) + 1;

nit: please consider aligning like this

((typer & MASK) >>
SHIFT) + 1;

Or, maybe better to macro it

#define TYPER_FIELD(typer, mask, shift) (((type) & (mask) >> (shift)) + 1)

And, rather than have a bunch of 'its_data.typer's we could use an alias, helping us stay within 120 chars.

struct its_typer *t = &its_data.typer;

t->ite_size = TYPER_FIELD(typer, GITS_TYPER_ITT_ENTRY_SIZE,

                           GITS_TYPER_ITT_ENTRY_SIZE_SHIFT);

Quoted 101 lines

lib/arm/gic-v3-its.c new file +64 -0

+	else
+		its_data.typer.collid_bits = 16;
+
+	its_data.typer.virt_lpi = typer & GITS_TYPER_VLPIS;
+	its_data.typer.phys_lpi = typer & GITS_TYPER_PLPIS;
+}
+
+int its_parse_baser(int i, struct its_baser *baser)
+{
+	void *reg_addr = gicv3_its_base() + GITS_BASER + i * 8;
+	u64 val = readq(reg_addr);
+
+	if (!val) {
+		memset(baser, 0, sizeof(*baser));
+		return -1;
+	}
+
+	baser->valid = val & GITS_BASER_VALID;
+	baser->indirect = val & GITS_BASER_INDIRECT;
+	baser->type = GITS_BASER_TYPE(val);
+	baser->esz = GITS_BASER_ENTRY_SIZE(val);
+	baser->nr_pages = GITS_BASER_NR_PAGES(val);
+	baser->table_addr = val & GITS_BASER_PHYS_ADDR_MASK;
+	switch (val & GITS_BASER_PAGE_SIZE_MASK) {
+	case GITS_BASER_PAGE_SIZE_4K:
+		baser->psz = SZ_4K;
+		break;
+	case GITS_BASER_PAGE_SIZE_16K:
+		baser->psz = SZ_16K;
+		break;
+	case GITS_BASER_PAGE_SIZE_64K:
+		baser->psz = SZ_64K;
+		break;
+	default:
+		baser->psz = SZ_64K;
+	}
+	return 0;
+}
+
+struct its_baser *its_lookup_baser(int type)
+{
+	int i;
+
+	for (i = 0; i < GITS_BASER_NR_REGS; i++) {
+		struct its_baser *baser = &its_data.baser[i];
+
+		if (baser->type == type)
+			return baser;
+	}
+	return NULL;
+}
+
+void its_init(void)
+{
+	int i;
+
+	if (!its_data.base)
+		return;
+
+	its_parse_typer();
+	for (i = 0; i < GITS_BASER_NR_REGS; i++)
+		its_parse_baser(i, &its_data.baser[i]);
+}
+

lib/arm/gic.c +6 -3

index aa9cb86..6b70b05 100644
@@ -6,9 +6,11 @@
 #include <devicetree.h>
 #include <asm/gic.h>
 #include <asm/io.h>
+#include <asm/gic-v3-its.h>
 
 struct gicv2_data gicv2_data;
 struct gicv3_data gicv3_data;
+struct its_data its_data;
 
 struct gic_common_ops {
 	void (*enable_defaults)(void);

@@ -44,12 +46,13 @@ static const struct gic_common_ops gicv3_common_ops = {
  * Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
  */
 static bool
-gic_get_dt_bases(const char *compatible, void **base1, void **base2)
+gic_get_dt_bases(const char *compatible, void **base1, void **base2, void **base3)
 {
 	struct dt_pbus_reg reg;
-	struct dt_device gic;
+	struct dt_device gic, its;
 	struct dt_bus bus;
-	int node, ret, i;
+	int node, subnode, ret, i, len;
+	const void *fdt = dt_fdt();
 
 	dt_bus_init_defaults(&bus);
 	dt_device_init(&gic, &bus, NULL);

@@ -74,19 +77,35 @@ gic_get_dt_bases(const char *compatible, void **base1, void **base2)
 		base2[i] = ioremap(reg.addr, reg.size);
 	}
 

lib/arm/gic.c gic_get_dt_bases(const char *compatible, void **base1, void **base2) · line 80

Quoted 1 line

lib/arm/gic.c +1 -0

+	if (base3 && !strcmp(compatible, "arm,gic-v3")) {

If base != NULL, then we could assert(strcmp(compatible, "arm,cortex-a15-gic") != 0)

Quoted 52 lines

lib/arm/gic.c +18 -2

+		dt_for_each_subnode(node, subnode) {
+			const struct fdt_property *prop;
+
+			prop = fdt_get_property(fdt, subnode, "compatible", &len);
+			if (!strcmp((char *)prop->data, "arm,gic-v3-its")) {
+				dt_device_bind_node(&its, subnode);
+				ret = dt_pbus_translate(&its, 0, &reg);
+				assert(ret == 0);
+				*base3 = ioremap(reg.addr, reg.size);
+				break;
+			}
+		}
+
+	}
+
 	return true;
 }
 
 int gicv2_init(void)
 {
 	return gic_get_dt_bases("arm,cortex-a15-gic",
-			&gicv2_data.dist_base, &gicv2_data.cpu_base);
+			&gicv2_data.dist_base, &gicv2_data.cpu_base, NULL);
 }
 
 int gicv3_init(void)
 {
 	return gic_get_dt_bases("arm,gic-v3", &gicv3_data.dist_base,
-			&gicv3_data.redist_bases[0]);
+			&gicv3_data.redist_bases[0], &its_data.base);
 }
 
 int gic_version(void)

@@ -104,6 +123,7 @@ int gic_init(void)
 		gic_common_ops = &gicv2_common_ops;
 	else if (gicv3_init())
 		gic_common_ops = &gicv3_common_ops;
+	its_init();
 	return gic_version();
 }
 

lib/arm64/asm/gic-v3-its.h new file +1 -0

new file mode 100644
index 0000000..083cba4
@@ -0,0 +1 @@
+#include "../../arm/asm/gic-v3-its.h"

Signature · 1 line

2.20.1

Thanks,
drew

Allocate the LPI configuration and per re-distributor pending table. Set redistributor's PROPBASER and PENDBASER. The LPIs are enabled by default in the config table.

Also introduce a helper routine that allows to set the pending table bit for a given LPI.

Signed-off-by Eric Auger <[email protected]>

---

v2 -> v3:
- Move the helpers in lib/arm/gic-v3.c and prefix them with "gicv3_" and add _lpi prefix too

v1 -> v2:
- remove memory attributes

---
  lib/arm/asm/gic-v3.h | 16 +++++++++++
  lib/arm/gic-v3.c     | 64 ++++++++++++++++++++++++++++++++++++++++++++
  2 files changed, 80 insertions(+)

lib/arm/asm/gic-v3.h +0 -0

index ffb2e26..ec2a6f0 100644

lib/arm/asm/gic-v3.h +15 -0

+
+#define GICR_PENDBASER_PTZ                              BIT_ULL(62)
+
+#define LPI_PROP_GROUP1		(1 << 1)
+#define LPI_PROP_ENABLED	(1 << 0)
+#define LPI_PROP_DEFAULT_PRIO   0xa0
+#define LPI_PROP_DEFAULT	(LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1 | \
+				 LPI_PROP_ENABLED)
+
  #include <asm/arch_gicv3.h>
 
  #ifndef __ASSEMBLY__

@@ -64,6 +74,8 @@ struct gicv3_data {
  	void *dist_base;
  	void *redist_bases[GICV3_NR_REDISTS];
  	void *redist_base[NR_CPUS];
+	void *lpi_prop;
+	void *lpi_pend[NR_CPUS];
  	unsigned int irq_nr;
  };
  extern struct gicv3_data gicv3_data;

@@ -80,6 +92,10 @@ extern void gicv3_write_eoir(u32 irqstat);
  extern void gicv3_ipi_send_single(int irq, int cpu);
  extern void gicv3_ipi_send_mask(int irq, const cpumask_t *dest);
  extern void gicv3_set_redist_base(size_t stride);
+extern void gicv3_lpi_set_config(int n, u8 val);
+extern u8 gicv3_lpi_get_config(int n);
+extern void gicv3_lpi_set_pending_table_bit(int rdist, int n, bool set);
+extern void gicv3_lpi_alloc_tables(void);
 
  static inline void gicv3_do_wait_for_rwp(void *base)
  {

lib/arm/gic-v3.c +29 -0

index feecb5e..c33f883 100644
@@ -5,6 +5,7 @@
   */
  #include <asm/gic.h>
  #include <asm/io.h>
+#include <alloc_page.h>
 
  void gicv3_set_redist_base(size_t stride)
  {

@@ -147,3 +148,66 @@ void gicv3_ipi_send_single(int irq, int cpu)
  	cpumask_set_cpu(cpu, &dest);
  	gicv3_ipi_send_mask(irq, &dest);
  }
+
+#if defined(__aarch64__)
+/* alloc_lpi_tables: Allocate LPI config and pending tables */
+void gicv3_lpi_alloc_tables(void)
+{
+	unsigned long n = SZ_64K >> PAGE_SHIFT;
+	unsigned long order = fls(n);
+	u64 prop_val;
+	int cpu;
+
+	gicv3_data.lpi_prop = (void *)virt_to_phys(alloc_pages(order));
+
+	/* ID bits = 13, ie. up to 14b LPI INTID */
+	prop_val = (u64)gicv3_data.lpi_prop | 13;
+
+	/*
+	 * Allocate pending tables for each redistributor
+	 * and set PROPBASER and PENDBASER
+	 */
+	for_each_present_cpu(cpu) {
+		u64 pend_val;
+		void *ptr;
+
+		ptr = gicv3_data.redist_base[cpu];
+
+		writeq(prop_val, ptr + GICR_PROPBASER);
+
+		gicv3_data.lpi_pend[cpu] = (void *)virt_to_phys(alloc_pages(order));

lib/arm/gic-v3.c +18 -0

+
+	return *entry;
+}
+
+void gicv3_lpi_set_pending_table_bit(int rdist, int n, bool set)
+{
+	u8 *ptr = phys_to_virt((phys_addr_t)gicv3_data.lpi_pend[rdist]);
+	u8 mask = 1 << (n % 8), byte;
+
+	ptr += (n / 8);
+	byte = *ptr;
+	if (set)
+		byte |=  mask;
+	else
+		byte &= ~mask;
+	*ptr = byte;
+}
+#endif /* __aarch64__ */

Hi Eric,

Quoted 22 lines · Eric Auger

Allocate the LPI configuration and per re-distributor pending table. Set redistributor's PROPBASER and PENDBASER. The LPIs are enabled by default in the config table.

Also introduce a helper routine that allows to set the pending table bit for a given LPI.

Signed-off-by Eric Auger <[email protected]>

---

v2 -> v3:
- Move the helpers in lib/arm/gic-v3.c and prefix them with "gicv3_" and add _lpi prefix too

v1 -> v2:
- remove memory attributes
---
  lib/arm/asm/gic-v3.h | 16 +++++++++++
  lib/arm/gic-v3.c     | 64 ++++++++++++++++++++++++++++++++++++++++++++

  2 files changed, 80 insertions(+)

Quoted 9 lines

lib/arm/asm/gic-v3.h +0 -0

index ffb2e26..ec2a6f0 100644
@@ -48,6 +48,16 @@
   #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \

      (MPIDR_AFFINITY_LEVEL(cluster_id, level) << ICC_SGI1R_AFFINITY_## level ## _SHIFT)
  +#define GICR_PROPBASER_IDBITS_MASK                      (0x1f)

This is not being used.  You can use it when calculating prop_val or just drop it.

Quoted 82 lines

lib/arm/asm/gic-v3.h +9 -0

+
+#define GICR_PENDBASER_PTZ                              BIT_ULL(62)
+
+#define LPI_PROP_GROUP1        (1 << 1)
+#define LPI_PROP_ENABLED    (1 << 0)
+#define LPI_PROP_DEFAULT_PRIO   0xa0
+#define LPI_PROP_DEFAULT    (LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1 | \
+                 LPI_PROP_ENABLED)
+

  #include <asm/arch_gicv3.h>
    #ifndef __ASSEMBLY__

lib/arm/asm/gic-v3.h +6 -0

@@ -64,6 +74,8 @@ struct gicv3_data {
       void *dist_base;
       void *redist_bases[GICV3_NR_REDISTS];
       void *redist_base[NR_CPUS];
+    void *lpi_prop;
+    void *lpi_pend[NR_CPUS];
       unsigned int irq_nr;
   };
   extern struct gicv3_data gicv3_data;

@@ -80,6 +92,10 @@ extern void gicv3_write_eoir(u32 irqstat);
   extern void gicv3_ipi_send_single(int irq, int cpu);
   extern void gicv3_ipi_send_mask(int irq, const cpumask_t *dest);
   extern void gicv3_set_redist_base(size_t stride);
+extern void gicv3_lpi_set_config(int n, u8 val);
+extern u8 gicv3_lpi_get_config(int n);
+extern void gicv3_lpi_set_pending_table_bit(int rdist, int n, bool set);
+extern void gicv3_lpi_alloc_tables(void);
     static inline void gicv3_do_wait_for_rwp(void *base)
   {

lib/arm/gic-v3.c +29 -0

index feecb5e..c33f883 100644
@@ -5,6 +5,7 @@
    */
   #include <asm/gic.h>
   #include <asm/io.h>
+#include <alloc_page.h>
     void gicv3_set_redist_base(size_t stride)
   {

@@ -147,3 +148,66 @@ void gicv3_ipi_send_single(int irq, int cpu)
       cpumask_set_cpu(cpu, &dest);
       gicv3_ipi_send_mask(irq, &dest);
   }
+
+#if defined(__aarch64__)
+/* alloc_lpi_tables: Allocate LPI config and pending tables */
+void gicv3_lpi_alloc_tables(void)
+{
+    unsigned long n = SZ_64K >> PAGE_SHIFT;
+    unsigned long order = fls(n);
+    u64 prop_val;
+    int cpu;
+
+    gicv3_data.lpi_prop = (void *)virt_to_phys(alloc_pages(order));
+
+    /* ID bits = 13, ie. up to 14b LPI INTID */
+    prop_val = (u64)gicv3_data.lpi_prop | 13;
+
+    /*
+     * Allocate pending tables for each redistributor
+     * and set PROPBASER and PENDBASER
+     */
+    for_each_present_cpu(cpu) {
+        u64 pend_val;
+        void *ptr;
+
+        ptr = gicv3_data.redist_base[cpu];
+
+        writeq(prop_val, ptr + GICR_PROPBASER);
+
+        gicv3_data.lpi_pend[cpu] = (void

*)virt_to_phys(alloc_pages(order));

lib/arm/gic-v3.c +7 -0

+
+        pend_val = (u64)gicv3_data.lpi_pend[cpu];
+
+        writeq(pend_val, ptr + GICR_PENDBASER);
+    }
+}
+

lib/arm/gic-v3.c void gicv3_ipi_send_single(int irq, int cpu) · line 188

Quoted 3 lines

lib/arm/gic-v3.c +3 -0

+void gicv3_lpi_set_config(int n, u8 value)
+{
+    u8 *entry = (u8 *)(gicv3_data.lpi_prop + (n - 8192));

But this is actually the *physical* address, shouldn't it be converted by phys_to_virt() before reading/writing something? Like what you've done for the 'lpi_pend[rdist]' before writing pending bit.  Or I'm missing some points here?

lib/arm/gic-v3.c void gicv3_ipi_send_single(int irq, int cpu) · line 195

Quoted 8 lines

lib/arm/gic-v3.c +7 -0

+
+    *entry = value;
+}
+
+u8 gicv3_lpi_get_config(int n)
+{
+    u8 *entry = (u8 *)(gicv3_data.lpi_prop + (n - 8192));

The same as above.

Thanks,
Zenghui

Quoted 19 lines

lib/arm/gic-v3.c +18 -0

+
+    return *entry;
+}
+
+void gicv3_lpi_set_pending_table_bit(int rdist, int n, bool set)
+{
+    u8 *ptr = phys_to_virt((phys_addr_t)gicv3_data.lpi_pend[rdist]);
+    u8 mask = 1 << (n % 8), byte;
+
+    ptr += (n / 8);
+    byte = *ptr;
+    if (set)
+        byte |=  mask;
+    else
+        byte &= ~mask;
+    *ptr = byte;
+}
+#endif /* __aarch64__ */

Allocate the LPI configuration and per re-distributor pending table. Set redistributor's PROPBASER and PENDBASER. The LPIs are enabled by default in the config table.

Also introduce a helper routine that allows to set the pending table bit for a given LPI.

Signed-off-by Eric Auger <[email protected]>

---

v2 -> v3:
- Move the helpers in lib/arm/gic-v3.c and prefix them with "gicv3_" and add _lpi prefix too

v1 -> v2:
- remove memory attributes

---
 lib/arm/asm/gic-v3.h | 16 +++++++++++
 lib/arm/gic-v3.c     | 64 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 80 insertions(+)

lib/arm/asm/gic-v3.h +0 -0

index ffb2e26..ec2a6f0 100644

lib/arm/asm/gic-v3.h +13 -0

+
+#define LPI_PROP_GROUP1		(1 << 1)
+#define LPI_PROP_ENABLED	(1 << 0)
+#define LPI_PROP_DEFAULT_PRIO   0xa0
+#define LPI_PROP_DEFAULT	(LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1 | \
+				 LPI_PROP_ENABLED)
+
 #include <asm/arch_gicv3.h>
 
 #ifndef __ASSEMBLY__

@@ -64,6 +74,8 @@ struct gicv3_data {
 	void *dist_base;
 	void *redist_bases[GICV3_NR_REDISTS];
 	void *redist_base[NR_CPUS];
+	void *lpi_prop;
+	void *lpi_pend[NR_CPUS];
 	unsigned int irq_nr;
 };
 extern struct gicv3_data gicv3_data;

@@ -80,6 +92,10 @@ extern void gicv3_write_eoir(u32 irqstat);
 extern void gicv3_ipi_send_single(int irq, int cpu);
 extern void gicv3_ipi_send_mask(int irq, const cpumask_t *dest);
 extern void gicv3_set_redist_base(size_t stride);
+extern void gicv3_lpi_set_config(int n, u8 val);
+extern u8 gicv3_lpi_get_config(int n);
+extern void gicv3_lpi_set_pending_table_bit(int rdist, int n, bool set);
+extern void gicv3_lpi_alloc_tables(void);
 
 static inline void gicv3_do_wait_for_rwp(void *base)
 {

lib/arm/gic-v3.c +23 -0

index feecb5e..c33f883 100644
@@ -5,6 +5,7 @@
  */
 #include <asm/gic.h>
 #include <asm/io.h>
+#include <alloc_page.h>
 
 void gicv3_set_redist_base(size_t stride)
 {

@@ -147,3 +148,66 @@ void gicv3_ipi_send_single(int irq, int cpu)
 	cpumask_set_cpu(cpu, &dest);
 	gicv3_ipi_send_mask(irq, &dest);
 }
+
+#if defined(__aarch64__)
+/* alloc_lpi_tables: Allocate LPI config and pending tables */
+void gicv3_lpi_alloc_tables(void)
+{
+	unsigned long n = SZ_64K >> PAGE_SHIFT;
+	unsigned long order = fls(n);
+	u64 prop_val;
+	int cpu;
+
+	gicv3_data.lpi_prop = (void *)virt_to_phys(alloc_pages(order));
+
+	/* ID bits = 13, ie. up to 14b LPI INTID */
+	prop_val = (u64)gicv3_data.lpi_prop | 13;
+
+	/*
+	 * Allocate pending tables for each redistributor
+	 * and set PROPBASER and PENDBASER
+	 */
+	for_each_present_cpu(cpu) {
+		u64 pend_val;
+		void *ptr;

lib/arm/gic-v3.c +6 -0

+	}
+}
+
+void gicv3_lpi_set_config(int n, u8 value)
+{
+	u8 *entry = (u8 *)(gicv3_data.lpi_prop + (n - 8192));

lib/arm/gic-v3.c +7 -0

+	if (set)
+		byte |=  mask;
+	else
+		byte &= ~mask;
+	*ptr = byte;
+}
+#endif /* __aarch64__ */

Signature · 1 line

2.20.1

This helper function controls the signaling of LPIs at redistributor level.

Signed-off-by Eric Auger <[email protected]>

---

v2 -> v3:
- move the helper in lib/arm/gic-v3.c
- rename the function with gicv3_lpi_ prefix
- s/report_abort/assert

---
 lib/arm/asm/gic-v3.h |  1 +
 lib/arm/gic-v3.c     | 17 +++++++++++++++++
 2 files changed, 18 insertions(+)

lib/arm/asm/gic-v3.h +1 -0

index ec2a6f0..734c0c0 100644
@@ -96,6 +96,7 @@ extern void gicv3_lpi_set_config(int n, u8 val);
 extern u8 gicv3_lpi_get_config(int n);
 extern void gicv3_lpi_set_pending_table_bit(int rdist, int n, bool set);
 extern void gicv3_lpi_alloc_tables(void);
+extern void gicv3_lpi_rdist_ctrl(u32 redist, bool set);
 
 static inline void gicv3_do_wait_for_rwp(void *base)
 {

lib/arm/gic-v3.c +0 -0

index c33f883..7865d01 100644

lib/arm/gic-v3.c +6 -0

+{
+	void *ptr;
+	u64 val;
+
+	assert(redist < nr_cpus);
+

Signature · 1 line

2.20.1

Quoted 26 lines · Eric Auger

This helper function controls the signaling of LPIs at redistributor level.

Signed-off-by Eric Auger <[email protected]>

---

v2 -> v3:
- move the helper in lib/arm/gic-v3.c
- rename the function with gicv3_lpi_ prefix
- s/report_abort/assert

---
 lib/arm/asm/gic-v3.h |  1 +
 lib/arm/gic-v3.c     | 17 +++++++++++++++++
 2 files changed, 18 insertions(+)

lib/arm/asm/gic-v3.h +1 -0

index ec2a6f0..734c0c0 100644
@@ -96,6 +96,7 @@ extern void gicv3_lpi_set_config(int n, u8 val);
 extern u8 gicv3_lpi_get_config(int n);
 extern void gicv3_lpi_set_pending_table_bit(int rdist, int n, bool set);
 extern void gicv3_lpi_alloc_tables(void);
+extern void gicv3_lpi_rdist_ctrl(u32 redist, bool set);
 

lib/arm/gic-v3.c void gicv3_lpi_set_pending_table_bit(int rdist, int n, bool set) · line 214

Quoted 12 lines

lib/arm/asm/gic-v3.h +0 -0

 static inline void gicv3_do_wait_for_rwp(void *base)
 {

lib/arm/gic-v3.c +2 -0

index c33f883..7865d01 100644
@@ -210,4 +210,21 @@ void gicv3_lpi_set_pending_table_bit(int rdist, int n, bool set)
 		byte &= ~mask;
 	*ptr = byte;
 }
+
+void gicv3_lpi_rdist_ctrl(u32 redist, bool set)

_set_clr_ ?

Quoted 7 lines

lib/arm/gic-v3.c +6 -0

+{
+	void *ptr;
+	u64 val;
+
+	assert(redist < nr_cpus);
+

lib/arm/gic-v3.c void gicv3_lpi_set_pending_table_bit(int rdist, int n, bool set) · line 230

Quoted 10 lines

lib/arm/gic-v3.c +9 -0

+	ptr = gicv3_data.redist_base[redist];
+	val = readl(ptr + GICR_CTLR);
+	if (set)
+		val |= GICR_CTLR_ENABLE_LPIS;
+	else
+		val &= ~GICR_CTLR_ENABLE_LPIS;
+	writel(val,  ptr + GICR_CTLR);
+}
 #endif /* __aarch64__ */
+

stray blank line here

Quoted 3 lines

Signature · 1 line

2.20.1

I'm not sure why this needs its own patch. I could just be part of the next patch.

Thanks,
drew

its_enable_defaults() is the top init function that allocates the command queue and all the requested tables (device, collection, lpi config and pending tables), enable LPIs at distributor level and ITS level.

gicv3_enable_defaults must be called before.

Signed-off-by Eric Auger <[email protected]>

---

v2 -> v3:
- introduce its_setup_baser in this patch
- squash "arm/arm64: ITS: Init the command queue" in this patch.

---
  lib/arm/asm/gic-v3-its.h |  8 ++++
  lib/arm/gic-v3-its.c     | 89 ++++++++++++++++++++++++++++++++++++++++
  2 files changed, 97 insertions(+)

lib/arm/asm/gic-v3-its.h +8 -0

index 815c515..fe73c04 100644
@@ -36,6 +36,8 @@ struct its_data {
  	void *base;
  	struct its_typer typer;
  	struct its_baser baser[GITS_BASER_NR_REGS];
+	struct its_cmd_block *cmd_base;
+	struct its_cmd_block *cmd_write;
  };
 
  extern struct its_data its_data;

@@ -88,10 +90,16 @@ extern struct its_data its_data;
  #define GITS_BASER_TYPE_DEVICE		1
  #define GITS_BASER_TYPE_COLLECTION	4
 
+
+struct its_cmd_block {
+	u64 raw_cmd[4];
+};
+
  extern void its_parse_typer(void);
  extern void its_init(void);
  extern int its_parse_baser(int i, struct its_baser *baser);
  extern struct its_baser *its_lookup_baser(int type);
+extern void its_enable_defaults(void);
 
  #else /* __arm__ */
 

lib/arm/gic-v3-its.c +3 -0

index 2c0ce13..d1e7e52 100644
@@ -86,3 +86,92 @@ void its_init(void)
  		its_parse_baser(i, &its_data.baser[i]);
  }
 
+static void its_setup_baser(int i, struct its_baser *baser)
+{
+	unsigned long n = (baser->nr_pages * baser->psz) >> PAGE_SHIFT;

lib/arm/gic-v3-its.c +10 -0

+		(u64)baser->valid	<< 63);
+
+	switch (baser->psz) {
+	case SZ_4K:
+		val |= GITS_BASER_PAGE_SIZE_4K;
+		break;
+	case SZ_16K:
+		val |= GITS_BASER_PAGE_SIZE_16K;
+		break;
+	case SZ_64K:

Hi Eric,

Quoted 62 lines · Eric Auger

its_enable_defaults() is the top init function that allocates the command queue and all the requested tables (device, collection, lpi config and pending tables), enable LPIs at distributor level and ITS level.

gicv3_enable_defaults must be called before.

Signed-off-by Eric Auger <[email protected]>

---

v2 -> v3:
- introduce its_setup_baser in this patch
- squash "arm/arm64: ITS: Init the command queue" in this patch.
---
  lib/arm/asm/gic-v3-its.h |  8 ++++
  lib/arm/gic-v3-its.c     | 89 ++++++++++++++++++++++++++++++++++++++++

  2 files changed, 97 insertions(+)

lib/arm/asm/gic-v3-its.h +2 -0

index 815c515..fe73c04 100644
@@ -36,6 +36,8 @@ struct its_data {
       void *base;
       struct its_typer typer;
       struct its_baser baser[GITS_BASER_NR_REGS];
+    struct its_cmd_block *cmd_base;
+    struct its_cmd_block *cmd_write;
   };
     extern struct its_data its_data;

@@ -88,10 +90,16 @@ extern struct its_data its_data;
   #define GITS_BASER_TYPE_DEVICE        1
   #define GITS_BASER_TYPE_COLLECTION    4

  +

lib/arm/asm/gic-v3-its.h +4 -0

+struct its_cmd_block {
+    u64 raw_cmd[4];
+};
+

  extern void its_parse_typer(void);
  extern void its_init(void);
  extern int its_parse_baser(int i, struct its_baser *baser); extern struct its_baser *its_lookup_baser(int type); +extern void its_enable_defaults(void);
    #else /* __arm__ */
  diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c index 2c0ce13..d1e7e52 100644

lib/arm/gic-v3-its.c +9 -0

@@ -86,3 +86,92 @@ void its_init(void)
           its_parse_baser(i, &its_data.baser[i]);
   }
   +static void its_setup_baser(int i, struct its_baser *baser)
+{
+    unsigned long n = (baser->nr_pages * baser->psz) >> PAGE_SHIFT;
+    unsigned long order = is_power_of_2(n) ? fls(n) : fls(n) + 1;
+    u64 val;
+
+    baser->table_addr = (u64)virt_to_phys(alloc_pages(order));
+
+    val = ((u64)baser->table_addr                    |
+        ((u64)baser->type    << GITS_BASER_TYPE_SHIFT)    |

lib/arm/gic-v3-its.c void its_init(void) · line 101

Quoted 3 lines

lib/arm/gic-v3-its.c +3 -0

+        ((u64)(baser->esz - 1)    << GITS_BASER_ENTRY_SIZE_SHIFT)    |
+        ((baser->nr_pages - 1)    << GITS_BASER_PAGES_SHIFT)    |
+        (u64)baser->indirect    << 62                |

I haven't seen the 'nr_pages' and 'indirect' are programmed anywhere except in its_parse_baser(). It looks like they're treated as RO (but they shouldn't) and I now don't think it makes sense to parse them in its_parse_baser(), in patch#5.

Quoted 15 lines

lib/arm/gic-v3-its.c +14 -0

+        (u64)baser->valid    << 63);
+
+    switch (baser->psz) {
+    case SZ_4K:
+        val |= GITS_BASER_PAGE_SIZE_4K;
+        break;
+    case SZ_16K:
+        val |= GITS_BASER_PAGE_SIZE_16K;
+        break;
+    case SZ_64K:
+        val |= GITS_BASER_PAGE_SIZE_64K;
+        break;
+    }
+

lib/arm/gic-v3-its.c void its_init(void) · line 121

Quoted 6 lines

lib/arm/gic-v3-its.c +6 -0

+    writeq(val, gicv3_its_base() + GITS_BASER + i * 8);
+}
+
+/**
+ * init_cmd_queue: Allocate the command queue and initialize
+ * CBASER, CREADR, CWRITER

no 'CREADR'.

Thanks,
Zenghui

Hi Zenghui,

Quoted 65 lines · Zenghui Yu

Hi Eric,

Quoted 62 lines · Eric Auger

its_enable_defaults() is the top init function that allocates the command queue and all the requested tables (device, collection, lpi config and pending tables), enable LPIs at distributor level and ITS level.

gicv3_enable_defaults must be called before.

Signed-off-by Eric Auger <[email protected]>

---

v2 -> v3:
- introduce its_setup_baser in this patch
- squash "arm/arm64: ITS: Init the command queue" in this patch.

---
   lib/arm/asm/gic-v3-its.h |  8 ++++
   lib/arm/gic-v3-its.c     | 89 ++++++++++++++++++++++++++++++++++++++++
   2 files changed, 97 insertions(+)

lib/arm/asm/gic-v3-its.h +7 -0

index 815c515..fe73c04 100644
@@ -36,6 +36,8 @@ struct its_data {
       void *base;
       struct its_typer typer;
       struct its_baser baser[GITS_BASER_NR_REGS];
+    struct its_cmd_block *cmd_base;
+    struct its_cmd_block *cmd_write;
   };
     extern struct its_data its_data;

@@ -88,10 +90,16 @@ extern struct its_data its_data;
   #define GITS_BASER_TYPE_DEVICE        1
   #define GITS_BASER_TYPE_COLLECTION    4
   +
+struct its_cmd_block {
+    u64 raw_cmd[4];
+};
+
   extern void its_parse_typer(void);
   extern void its_init(void);
   extern int its_parse_baser(int i, struct its_baser *baser);
   extern struct its_baser *its_lookup_baser(int type);
+extern void its_enable_defaults(void);
     #else /* __arm__ */
   diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c

index 2c0ce13..d1e7e52 100644

lib/arm/gic-v3-its.c +9 -0

@@ -86,3 +86,92 @@ void its_init(void)
           its_parse_baser(i, &its_data.baser[i]);
   }
   +static void its_setup_baser(int i, struct its_baser *baser)
+{
+    unsigned long n = (baser->nr_pages * baser->psz) >> PAGE_SHIFT;
+    unsigned long order = is_power_of_2(n) ? fls(n) : fls(n) + 1;
+    u64 val;
+
+    baser->table_addr = (u64)virt_to_phys(alloc_pages(order));
+
+    val = ((u64)baser->table_addr                    |
+        ((u64)baser->type    << GITS_BASER_TYPE_SHIFT)    |

Quoted 8 lines

lib/arm/gic-v3-its.c void its_init(void) · line 101

Quoted 3 lines

lib/arm/gic-v3-its.c +3 -0

+        ((u64)(baser->esz - 1)    << GITS_BASER_ENTRY_SIZE_SHIFT)    |
+        ((baser->nr_pages - 1)    << GITS_BASER_PAGES_SHIFT)    |
+        (u64)baser->indirect    << 62                |

I haven't seen the 'nr_pages' and 'indirect' are programmed anywhere except in its_parse_baser(). It looks like they're treated as RO (but they shouldn't) and I now don't think it makes sense to parse them in its_parse_baser(), in patch#5.

First of all please forgive me for the delay.

I agree with you on nr_pages. However indirect also indicates the BASER capability to support or not 2 level tables. So I think it makes sense to read it on init.

its_enable_defaults() is the top init function that allocates the command queue and all the requested tables (device, collection, lpi config and pending tables), enable LPIs at distributor level and ITS level.

gicv3_enable_defaults must be called before.

Signed-off-by Eric Auger <[email protected]>

---

v2 -> v3:
- introduce its_setup_baser in this patch
- squash "arm/arm64: ITS: Init the command queue" in this patch.

---
 lib/arm/asm/gic-v3-its.h |  8 ++++
 lib/arm/gic-v3-its.c     | 89 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 97 insertions(+)

lib/arm/asm/gic-v3-its.h +8 -0

index 815c515..fe73c04 100644
@@ -36,6 +36,8 @@ struct its_data {
 	void *base;
 	struct its_typer typer;
 	struct its_baser baser[GITS_BASER_NR_REGS];
+	struct its_cmd_block *cmd_base;
+	struct its_cmd_block *cmd_write;
 };
 
 extern struct its_data its_data;

@@ -88,10 +90,16 @@ extern struct its_data its_data;
 #define GITS_BASER_TYPE_DEVICE		1
 #define GITS_BASER_TYPE_COLLECTION	4
 
+
+struct its_cmd_block {
+	u64 raw_cmd[4];
+};
+
 extern void its_parse_typer(void);
 extern void its_init(void);
 extern int its_parse_baser(int i, struct its_baser *baser);
 extern struct its_baser *its_lookup_baser(int type);
+extern void its_enable_defaults(void);
 
 #else /* __arm__ */
 

lib/arm/gic-v3-its.c +4 -0

index 2c0ce13..d1e7e52 100644
@@ -86,3 +86,92 @@ void its_init(void)
 		its_parse_baser(i, &its_data.baser[i]);
 }
 
+static void its_setup_baser(int i, struct its_baser *baser)
+{
+	unsigned long n = (baser->nr_pages * baser->psz) >> PAGE_SHIFT;
+	unsigned long order = is_power_of_2(n) ? fls(n) : fls(n) + 1;

lib/arm/gic-v3-its.c +40 -0

+
+	switch (baser->psz) {
+	case SZ_4K:
+		val |= GITS_BASER_PAGE_SIZE_4K;
+		break;
+	case SZ_16K:
+		val |= GITS_BASER_PAGE_SIZE_16K;
+		break;
+	case SZ_64K:
+		val |= GITS_BASER_PAGE_SIZE_64K;
+		break;
+	}
+
+	writeq(val, gicv3_its_base() + GITS_BASER + i * 8);
+}
+
+/**
+ * init_cmd_queue: Allocate the command queue and initialize
+ * CBASER, CREADR, CWRITER
+ */
+static void its_cmd_queue_init(void)
+{
+	unsigned long n = SZ_64K >> PAGE_SHIFT;
+	unsigned long order = fls(n);
+	u64 cbaser;
+
+	its_data.cmd_base = (void *)virt_to_phys(alloc_pages(order));
+
+	cbaser = ((u64)its_data.cmd_base | (SZ_64K / SZ_4K - 1)	| GITS_CBASER_VALID);
+
+	writeq(cbaser, its_data.base + GITS_CBASER);
+
+	its_data.cmd_write = its_data.cmd_base;
+	writeq(0, its_data.base + GITS_CWRITER);
+}
+
+void its_enable_defaults(void)
+{
+	unsigned int i;
+

lib/arm/gic-v3-its.c +13 -0

+		}
+	}
+
+	/* Allocate LPI config and pending tables */
+	gicv3_lpi_alloc_tables();
+
+	its_cmd_queue_init();
+
+	for (i = 0; i < nr_cpus; i++)
+		gicv3_lpi_rdist_ctrl(i, true);
+
+	writel(GITS_CTLR_ENABLE, its_data.base + GITS_CTLR);
+}

Signature · 1 line

2.20.1

Quoted 66 lines · Eric Auger

its_enable_defaults() is the top init function that allocates the command queue and all the requested tables (device, collection, lpi config and pending tables), enable LPIs at distributor level and ITS level.

gicv3_enable_defaults must be called before.

Signed-off-by Eric Auger <[email protected]>

---

v2 -> v3:
- introduce its_setup_baser in this patch
- squash "arm/arm64: ITS: Init the command queue" in this patch.

---
 lib/arm/asm/gic-v3-its.h |  8 ++++
 lib/arm/gic-v3-its.c     | 89 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 97 insertions(+)

lib/arm/asm/gic-v3-its.h +8 -0

index 815c515..fe73c04 100644
@@ -36,6 +36,8 @@ struct its_data {
 	void *base;
 	struct its_typer typer;
 	struct its_baser baser[GITS_BASER_NR_REGS];
+	struct its_cmd_block *cmd_base;
+	struct its_cmd_block *cmd_write;
 };
 
 extern struct its_data its_data;

@@ -88,10 +90,16 @@ extern struct its_data its_data;
 #define GITS_BASER_TYPE_DEVICE		1
 #define GITS_BASER_TYPE_COLLECTION	4
 
+
+struct its_cmd_block {
+	u64 raw_cmd[4];
+};
+
 extern void its_parse_typer(void);
 extern void its_init(void);
 extern int its_parse_baser(int i, struct its_baser *baser);
 extern struct its_baser *its_lookup_baser(int type);
+extern void its_enable_defaults(void);
 
 #else /* __arm__ */
 

lib/arm/gic-v3-its.c +9 -0

index 2c0ce13..d1e7e52 100644
@@ -86,3 +86,92 @@ void its_init(void)
 		its_parse_baser(i, &its_data.baser[i]);
 }
 
+static void its_setup_baser(int i, struct its_baser *baser)
+{
+	unsigned long n = (baser->nr_pages * baser->psz) >> PAGE_SHIFT;
+	unsigned long order = is_power_of_2(n) ? fls(n) : fls(n) + 1;
+	u64 val;
+
+	baser->table_addr = (u64)virt_to_phys(alloc_pages(order));
+
+	val = ((u64)baser->table_addr					|

lib/arm/gic-v3-its.c void its_init(void) · line 102

Quoted 5 lines

lib/arm/gic-v3-its.c +5 -0

+		((u64)baser->type	<< GITS_BASER_TYPE_SHIFT)	|
+		((u64)(baser->esz - 1)	<< GITS_BASER_ENTRY_SIZE_SHIFT)	|
+		((baser->nr_pages - 1)	<< GITS_BASER_PAGES_SHIFT)	|
+		(u64)baser->indirect	<< 62				|
+		(u64)baser->valid	<< 63);

<< GITS_BASER_INDIRECT
<< GITS_BASER_VALID

Quoted 46 lines

lib/arm/gic-v3-its.c +45 -0

+
+	switch (baser->psz) {
+	case SZ_4K:
+		val |= GITS_BASER_PAGE_SIZE_4K;
+		break;
+	case SZ_16K:
+		val |= GITS_BASER_PAGE_SIZE_16K;
+		break;
+	case SZ_64K:
+		val |= GITS_BASER_PAGE_SIZE_64K;
+		break;
+	}
+
+	writeq(val, gicv3_its_base() + GITS_BASER + i * 8);
+}
+
+/**
+ * init_cmd_queue: Allocate the command queue and initialize
+ * CBASER, CREADR, CWRITER
+ */
+static void its_cmd_queue_init(void)
+{
+	unsigned long n = SZ_64K >> PAGE_SHIFT;
+	unsigned long order = fls(n);
+	u64 cbaser;
+
+	its_data.cmd_base = (void *)virt_to_phys(alloc_pages(order));
+
+	cbaser = ((u64)its_data.cmd_base | (SZ_64K / SZ_4K - 1)	| GITS_CBASER_VALID);
+
+	writeq(cbaser, its_data.base + GITS_CBASER);
+
+	its_data.cmd_write = its_data.cmd_base;
+	writeq(0, its_data.base + GITS_CWRITER);
+}
+
+void its_enable_defaults(void)
+{
+	unsigned int i;
+
+	its_parse_typer();
+
+	/* Allocate BASER tables (device and collection tables) */
+	for (i = 0; i < GITS_BASER_NR_REGS; i++) {
+		struct its_baser *baser = &its_data.baser[i];

lib/arm/gic-v3-its.c void its_init(void) · line 152

Quoted 5 lines

lib/arm/gic-v3-its.c +5 -0

+		int ret;
+
+		ret = its_parse_baser(i, baser);
+		if (ret)
+			continue;

Didn't we already parse typer and baser at its_init time? How/why would its_parse_baser fail? Should we assert when it does?

lib/arm/gic-v3-its.c void its_init(void) · line 164

Quoted 13 lines

lib/arm/gic-v3-its.c +12 -0

+
+		switch (baser->type) {
+		case GITS_BASER_TYPE_DEVICE:
+			baser->valid = true;
+			its_setup_baser(i, baser);
+			break;
+		case GITS_BASER_TYPE_COLLECTION:
+			baser->valid = true;
+			its_setup_baser(i, baser);
+			break;
+		default:
+			break;

assert() ?

Quoted 16 lines

lib/arm/gic-v3-its.c +13 -0

+		}
+	}
+
+	/* Allocate LPI config and pending tables */
+	gicv3_lpi_alloc_tables();
+
+	its_cmd_queue_init();
+
+	for (i = 0; i < nr_cpus; i++)
+		gicv3_lpi_rdist_ctrl(i, true);
+
+	writel(GITS_CTLR_ENABLE, its_data.base + GITS_CTLR);
+}

Signature · 1 line

2.20.1

Quoted 1 line

It's looking like we don't have a clean separation between its_init and its_enable_defaults. I'd expect its_init to do all the allocating of memory and its_enable_defaults to do all the write's to the device. We should only do its_init once and its_enable should be something we can do again (after a disable, on reset, etc.). Is that not possible with the ITS device?

Thanks,
drew

Introduce an helper functions to register
- a new device, characterized by its device id and the max number of event IDs that dimension its ITT (Interrupt Translation Table). The function allocates the ITT.

- a new collection, characterized by its ID and the target processing engine (PE).

Signed-off-by Eric Auger <[email protected]>

---

v2 -> v3:
- s/report_abort/assert

v1 -> v2:
- s/nb_/nr_

---
  lib/arm/asm/gic-v3-its.h | 20 +++++++++++++++++-
  lib/arm/gic-v3-its.c     | 44 ++++++++++++++++++++++++++++++++++++++++
  2 files changed, 63 insertions(+), 1 deletion(-)

lib/arm/asm/gic-v3-its.h +19 -1

index fe73c04..acd97a9 100644
@@ -31,6 +31,19 @@ struct its_baser {
  };
 
  #define GITS_BASER_NR_REGS              8
+#define GITS_MAX_DEVICES		8
+#define GITS_MAX_COLLECTIONS		8
+
+struct its_device {
+	u32 device_id;	/* device ID */
+	u32 nr_ites;	/* Max Interrupt Translation Entries */
+	void *itt;	/* Interrupt Translation Table GPA */
+};
+
+struct its_collection {
+	u64 target_address;
+	u16 col_id;
+};
 
  struct its_data {
  	void *base;

@@ -38,6 +51,10 @@ struct its_data {
  	struct its_baser baser[GITS_BASER_NR_REGS];
  	struct its_cmd_block *cmd_base;
  	struct its_cmd_block *cmd_write;
+	struct its_device devices[GITS_MAX_DEVICES];
+	u32 nr_devices;		/* Allocated Devices */
+	struct its_collection collections[GITS_MAX_COLLECTIONS];
+	u32 nr_collections;	/* Allocated Collections */
  };
 
  extern struct its_data its_data;

@@ -90,7 +107,6 @@ extern struct its_data its_data;
  #define GITS_BASER_TYPE_DEVICE		1
  #define GITS_BASER_TYPE_COLLECTION	4
 
-
  struct its_cmd_block {
  	u64 raw_cmd[4];
  };

@@ -100,6 +116,8 @@ extern void its_init(void);
  extern int its_parse_baser(int i, struct its_baser *baser);
  extern struct its_baser *its_lookup_baser(int type);
  extern void its_enable_defaults(void);
+extern struct its_device *its_create_device(u32 dev_id, int nr_ites);
+extern struct its_collection *its_create_collection(u32 col_id, u32 target_pe);
 
  #else /* __arm__ */
 

lib/arm/gic-v3-its.c +4 -0

index d1e7e52..c2dcd01 100644
@@ -175,3 +175,47 @@ void its_enable_defaults(void)
 
  	writel(GITS_CTLR_ENABLE, its_data.base + GITS_CTLR);
  }
+
+struct its_device *its_create_device(u32 device_id, int nr_ites)
+{
+	struct its_baser *baser;