Add new series Micron SPI NAND devices
Subsystems (2)
v6 cover Add new series Micron SPI NAND devices
From: Shivamurthy Shastri <[email protected]>
This patchset is for the new series of Micron SPI NAND devices, and the following links are their datasheets.
M78A:
[1] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m78a_1gb_3v_nand_spi.pdf
[2] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m78a_1gb_1_8v_nand_spi.pdf
M79A:
[3] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m79a_2gb_1_8v_nand_spi.pdf
[4] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m79a_ddp_4gb_3v_nand_spi.pdf
M70A:
[5] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m70a_4gb_3v_nand_spi.pdf
[6] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m70a_4gb_1_8v_nand_spi.pdf
[7] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m70a_ddp_8gb_3v_nand_spi.pdf
[8] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m70a_ddp_8gb_1_8v_nand_spi.pdf
Changes since v5:
-----------------
1. Rebased series to v5.6-rc1.
Changes since v4:
-----------------
1. Patch 2 is separated into two as per the comment by Boris.
2. Renamed MICRON_CFG_CONTI_READ into MICRON_CFG_CR.
3. Reworked die selection function as per the comment by Boris.
Changes since v3:
-----------------
1. Patch 3 and 4 reworked as follows
- Patch 3 introducing the Continuous read feature
- Patch 4 adding devices with the feature
Changes since v2:
-----------------
1. Patch commit messages have been modified.
2. Handled devices with Continuous Read feature with vendor specific flag.
3. Reworked die selection function as per the comment.
Changes since v1:
-----------------
1. The patch split into multiple patches.
2. Added comments for selecting the die.
Shivamurthy Shastri (6):
mtd: spinand: micron: Generalize the OOB layout structure and function
names
mtd: spinand: micron: Describe the SPI NAND device MT29F2G01ABAGD
mtd: spinand: micron: Add new Micron SPI NAND devices
mtd: spinand: micron: identify SPI NAND device with Continuous Read
mode
mtd: spinand: micron: Add M70A series Micron SPI NAND devices
mtd: spinand: micron: Add new Micron SPI NAND devices with multiple
dies
drivers/mtd/nand/spi/micron.c | 150 ++++++++++++++++++++++++++++++---- include/linux/mtd/spinand.h | 1 + 2 files changed, 137 insertions(+), 14 deletions(-)
Signature · 1 line
2.17.1
PATCH v6 1/6 mtd: spinand: micron: Generalize the OOB layout structure and function names
From: Shivamurthy Shastri <[email protected]>
In order to add new Micron SPI NAND devices, we generalized the OOB layout structure and function names.
--- drivers/mtd/nand/spi/micron.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-)
drivers/mtd/nand/spi/micron.c +14 -14
@@ -34,38 +34,38 @@ static SPINAND_OP_VARIANTS(update_cache_variants,SPINAND_PROG_LOAD_X4 (false,0 ,NULL ,0 ), SPINAND_PROG_LOAD(false, 0, NULL, 0)); -static int mt29f2g01abagd_ooblayout_ecc (struct mtd_info *mtd,int section, -struct mtd_oob_region *region) +static int micron_8_ooblayout_ecc (struct mtd_info *mtd,int section, +struct mtd_oob_region *region) {if (section)return -ERANGE ; - region->offset =64 ; - region->length =64 ; + region->offset = mtd->oobsize /2 ; + region->length = mtd->oobsize /2 ;return 0 ; } -static int mt29f2g01abagd_ooblayout_free (struct mtd_info *mtd,int section, -struct mtd_oob_region *region) +static int micron_8_ooblayout_free (struct mtd_info *mtd,int section, +struct mtd_oob_region *region) {if (section)return -ERANGE ;/* Reserve 2 bytes for the BBM. */ region->offset =2 ; - region->length =62 ; + region->length = (mtd->oobsize /2 ) -2 ;return 0 ; } -static const struct mtd_ooblayout_ops mt29f2g01abagd_ooblayout = { - .ecc = mt29f2g01abagd_ooblayout_ecc, - .free = mt29f2g01abagd_ooblayout_free, +static const struct mtd_ooblayout_ops micron_8_ooblayout = { + .ecc = micron_8_ooblayout_ecc, + .free = micron_8_ooblayout_free, }; -static int mt29f2g01abagd_ecc_get_status (struct spinand_device *spinand, -u8 status) +static int micron_8_ecc_get_status (struct spinand_device *spinand, +u8 status) {switch (status &MICRON_STATUS_ECC_MASK ) {case STATUS_ECC_NO_BITFLIPS :
@@ -98,8 +98,8 @@ static const struct spinand_info micron_spinand_table[] = { &write_cache_variants, &update_cache_variants), 0, - SPINAND_ECCINFO(&mt29f2g01abagd_ooblayout, - mt29f2g01abagd_ecc_get_status)), + SPINAND_ECCINFO(µn_8_ooblayout, + micron_8_ecc_get_status)), };static int micron_spinand_detect (struct spinand_device *spinand)
Signature · 1 line
2.17.1
PATCH v6 2/6 mtd: spinand: micron: Describe the SPI NAND device MT29F2G01ABAGD
In reply to [email protected]From: Shivamurthy Shastri <[email protected]>
Add the SPI NAND device MT29F2G01ABAGD series number, size and voltage details as a comment.
--- drivers/mtd/nand/spi/micron.c | 1 + 1 file changed, 1 insertion(+)
drivers/mtd/nand/spi/micron.c +1 -0
@@ -91,6 +91,7 @@ static int micron_8_ecc_get_status(struct spinand_device *spinand, }static const struct spinand_info micron_spinand_table[] = { +/* M79A 2Gb 3.3V */ SPINAND_INFO("MT29F2G01ABAGD", 0x24, NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1), NAND_ECCREQ(8, 512),
Signature · 1 line
2.17.1
Re: [PATCH v6 2/6] mtd: spinand: micron: Describe the SPI NAND device MT29F2G01ABAGD
Quoted 6 lines · On Mon, 9 Mar 2020 12:52:26 +0100 [email protected] wrote:
From: Shivamurthy Shastri <[email protected]>
Add the SPI NAND device MT29F2G01ABAGD series number, size and voltage details as a comment.
Signed-off-by Shivamurthy Shastri <[email protected]>
Quoted 16 lines
--- drivers/mtd/nand/spi/micron.c | 1 + 1 file changed, 1 insertion(+)drivers/mtd/nand/spi/micron.c +1
-0@@ -91,6 +91,7 @@ static int micron_8_ecc_get_status(struct spinand_device *spinand, }static const struct spinand_info micron_spinand_table[] = { +/* M79A 2Gb 3.3V */ SPINAND_INFO("MT29F2G01ABAGD", 0x24, NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1), NAND_ECCREQ(8, 512),
PATCH v6 3/6 mtd: spinand: micron: Add new Micron SPI NAND devices
In reply to [email protected]From: Shivamurthy Shastri <[email protected]>
Add device table for M79A and M78A series Micron SPI NAND devices.
--- drivers/mtd/nand/spi/micron.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)
drivers/mtd/nand/spi/micron.c +30 -0
@@ -101,6 +101,36 @@ static const struct spinand_info micron_spinand_table[] = { 0, SPINAND_ECCINFO(µn_8_ooblayout, micron_8_ecc_get_status)), +/* M79A 2Gb 1.8V */ +SPINAND_INFO ("MT29F2G01ABBGD" ,0x25 , +NAND_MEMORG (1 ,2048 ,128 ,64 ,2048 ,40 ,2 ,1 ,1 ), +NAND_ECCREQ (8 ,512 ), +SPINAND_INFO_OP_VARIANTS (&read_cache_variants, + &write_cache_variants, + &update_cache_variants), +0 , +SPINAND_ECCINFO (µn_8_ooblayout, + micron_8_ecc_get_status)), +/* M78A 1Gb 3.3V */ +SPINAND_INFO ("MT29F1G01ABAFD" ,0x14 , +NAND_MEMORG (1 ,2048 ,128 ,64 ,1024 ,20 ,1 ,1 ,1 ), +NAND_ECCREQ (8 ,512 ), +SPINAND_INFO_OP_VARIANTS (&read_cache_variants, + &write_cache_variants, + &update_cache_variants), +0 , +SPINAND_ECCINFO (µn_8_ooblayout, + micron_8_ecc_get_status)), +/* M78A 1Gb 1.8V */ +SPINAND_INFO ("MT29F1G01ABAFD" ,0x15 , +NAND_MEMORG (1 ,2048 ,128 ,64 ,1024 ,20 ,1 ,1 ,1 ), +NAND_ECCREQ (8 ,512 ), +SPINAND_INFO_OP_VARIANTS (&read_cache_variants, + &write_cache_variants, + &update_cache_variants), +0 , +SPINAND_ECCINFO (µn_8_ooblayout, + micron_8_ecc_get_status)), };static int micron_spinand_detect (struct spinand_device *spinand)
Signature · 1 line
2.17.1
Re: [PATCH v6 3/6] mtd: spinand: micron: Add new Micron SPI NAND devices
Quoted 5 lines · On Mon, 9 Mar 2020 12:52:27 +0100 [email protected] wrote:
From: Shivamurthy Shastri <[email protected]>
Add device table for M79A and M78A series Micron SPI NAND devices.
Signed-off-by Shivamurthy Shastri <[email protected]>
Quoted 45 lines
--- drivers/mtd/nand/spi/micron.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)drivers/mtd/nand/spi/micron.c +30
-0@@ -101,6 +101,36 @@ static const struct spinand_info micron_spinand_table[] = { 0, SPINAND_ECCINFO(µn_8_ooblayout, micron_8_ecc_get_status)), +/* M79A 2Gb 1.8V */ +SPINAND_INFO ("MT29F2G01ABBGD" ,0x25 , +NAND_MEMORG (1 ,2048 ,128 ,64 ,2048 ,40 ,2 ,1 ,1 ), +NAND_ECCREQ (8 ,512 ), +SPINAND_INFO_OP_VARIANTS (&read_cache_variants, + &write_cache_variants, + &update_cache_variants), +0 , +SPINAND_ECCINFO (µn_8_ooblayout, + micron_8_ecc_get_status)), +/* M78A 1Gb 3.3V */ +SPINAND_INFO ("MT29F1G01ABAFD" ,0x14 , +NAND_MEMORG (1 ,2048 ,128 ,64 ,1024 ,20 ,1 ,1 ,1 ), +NAND_ECCREQ (8 ,512 ), +SPINAND_INFO_OP_VARIANTS (&read_cache_variants, + &write_cache_variants, + &update_cache_variants), +0 , +SPINAND_ECCINFO (µn_8_ooblayout, + micron_8_ecc_get_status)), +/* M78A 1Gb 1.8V */ +SPINAND_INFO ("MT29F1G01ABAFD" ,0x15 , +NAND_MEMORG (1 ,2048 ,128 ,64 ,1024 ,20 ,1 ,1 ,1 ), +NAND_ECCREQ (8 ,512 ), +SPINAND_INFO_OP_VARIANTS (&read_cache_variants, + &write_cache_variants, + &update_cache_variants), +0 , +SPINAND_ECCINFO (µn_8_ooblayout, + micron_8_ecc_get_status)), };static int micron_spinand_detect (struct spinand_device *spinand)
PATCH v6 4/6 mtd: spinand: micron: identify SPI NAND device with Continuous Read mode
In reply to [email protected]From: Shivamurthy Shastri <[email protected]>
Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with the Continuous Read mode.
Some of the Micron SPI NAND devices have the "Continuous Read" feature enabled by default, which does not fit the subsystem needs.
In this mode, the READ CACHE command doesn't require the starting column address. The device always output the data starting from the first column of the cache register, and once the end of the cache register reached, the data output continues through the next page. With the continuous read mode, it is possible to read out the entire block using a single READ command, and once the end of the block reached, the output pins become High-Z state. However, during this mode the read command doesn't output the OOB area.
Hence, we disable the feature at probe time.
--- drivers/mtd/nand/spi/micron.c | 16 ++++++++++++++++ include/linux/mtd/spinand.h | 1 + 2 files changed, 17 insertions(+)
drivers/mtd/nand/spi/micron.c +16 -0
@@ -18,6 +18,8 @@#define MICRON_STATUS_ECC_4TO6_BITFLIPS (3 << 4)#define MICRON_STATUS_ECC_7TO8_BITFLIPS (5 << 4) +#define MICRON_CFG_CR BIT(0) + static SPINAND_OP_VARIANTS(read_cache_variants, SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
@@ -153,8 +155,22 @@ static int micron_spinand_detect(struct spinand_device *spinand)return 1 ; } +static int micron_spinand_init (struct spinand_device *spinand) +{ +/* +* M70A device series enable Continuous Read feature at Power-up, +* which is not supported. Disable this bit to avoid any possible +* failure. +*/ +if (spinand->flags &SPINAND_HAS_CR_FEAT_BIT ) +return spinand_upd_cfg (spinand,MICRON_CFG_CR ,0 ); + +return 0 ; +} +static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = { .detect = micron_spinand_detect, + .init = micron_spinand_init, };const struct spinand_manufacturer micron_spinand_manufacturer = {
include/linux/mtd/spinand.h +1 -0
@@ -270,6 +270,7 @@ struct spinand_ecc_info { };#define SPINAND_HAS_QE_BIT BIT(0) +#define SPINAND_HAS_CR_FEAT_BIT BIT(1)/** * struct spinand_info - Structure used to describe SPI NAND chips
Signature · 1 line
2.17.1
Re: [PATCH v6 4/6] mtd: spinand: micron: identify SPI NAND device with Continuous Read mode
Quoted 17 lines · On Mon, 9 Mar 2020 12:52:28 +0100 [email protected] wrote:
From: Shivamurthy Shastri <[email protected]>
Add
SPINAND_HAS_CR_FEAT_BITflag to identify the SPI NAND device with the Continuous Read mode.Some of the Micron SPI NAND devices have the "Continuous Read" feature enabled by default, which does not fit the subsystem needs.
In this mode, the READ CACHE command doesn't require the starting column address. The device always output the data starting from the first column of the cache register, and once the end of the cache register reached, the data output continues through the next page. With the continuous read mode, it is possible to read out the entire block using a single READ command, and once the end of the block reached, the output pins become High-Z state. However, during this mode the read command doesn't output the OOB area.
Quoted 3 lines
Hence, we disable the feature at probe time.
Signed-off-by Shivamurthy Shastri <[email protected]>
Quoted 53 lines
--- drivers/mtd/nand/spi/micron.c | 16 ++++++++++++++++ include/linux/mtd/spinand.h | 1 + 2 files changed, 17 insertions(+)drivers/mtd/nand/spi/micron.c +16
-0@@ -18,6 +18,8 @@#define MICRON_STATUS_ECC_4TO6_BITFLIPS (3 << 4)#define MICRON_STATUS_ECC_7TO8_BITFLIPS (5 << 4) +#define MICRON_CFG_CR BIT(0) + static SPINAND_OP_VARIANTS(read_cache_variants, SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),@@ -153,8 +155,22 @@ static int micron_spinand_detect(struct spinand_device *spinand)return 1 ; } +static int micron_spinand_init (struct spinand_device *spinand) +{ +/* +* M70A device series enable Continuous Read feature at Power-up, +* which is not supported. Disable this bit to avoid any possible +* failure. +*/ +if (spinand->flags &SPINAND_HAS_CR_FEAT_BIT ) +return spinand_upd_cfg (spinand,MICRON_CFG_CR ,0 ); + +return 0 ; +} +static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = { .detect = micron_spinand_detect, + .init = micron_spinand_init, };const struct spinand_manufacturer micron_spinand_manufacturer = {include/linux/mtd/spinand.h +1
-0@@ -270,6 +270,7 @@ struct spinand_ecc_info { };#define SPINAND_HAS_QE_BIT BIT(0) +#define SPINAND_HAS_CR_FEAT_BIT BIT(1)/** * struct spinand_info - Structure used to describe SPI NAND chips
PATCH v6 5/6 mtd: spinand: micron: Add M70A series Micron SPI NAND devices
In reply to [email protected]From: Shivamurthy Shastri <[email protected]>
Add device table for M70A series Micron SPI NAND devices.
--- drivers/mtd/nand/spi/micron.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
drivers/mtd/nand/spi/micron.c +20 -0
@@ -133,6 +133,26 @@ static const struct spinand_info micron_spinand_table[] = { 0, SPINAND_ECCINFO(µn_8_ooblayout, micron_8_ecc_get_status)), +/* M70A 4Gb 3.3V */ +SPINAND_INFO ("MT29F4G01ABAFD" ,0x34 , +NAND_MEMORG (1 ,4096 ,256 ,64 ,2048 ,40 ,1 ,1 ,1 ), +NAND_ECCREQ (8 ,512 ), +SPINAND_INFO_OP_VARIANTS (&read_cache_variants, + &write_cache_variants, + &update_cache_variants), +SPINAND_HAS_CR_FEAT_BIT , +SPINAND_ECCINFO (µn_8_ooblayout, + micron_8_ecc_get_status)), +/* M70A 4Gb 1.8V */ +SPINAND_INFO ("MT29F4G01ABBFD" ,0x35 , +NAND_MEMORG (1 ,4096 ,256 ,64 ,2048 ,40 ,1 ,1 ,1 ), +NAND_ECCREQ (8 ,512 ), +SPINAND_INFO_OP_VARIANTS (&read_cache_variants, + &write_cache_variants, + &update_cache_variants), +SPINAND_HAS_CR_FEAT_BIT , +SPINAND_ECCINFO (µn_8_ooblayout, + micron_8_ecc_get_status)), };static int micron_spinand_detect (struct spinand_device *spinand)
Signature · 1 line
2.17.1
PATCH v6 6/6 mtd: spinand: micron: Add new Micron SPI NAND devices with multiple dies
In reply to [email protected]From: Shivamurthy Shastri <[email protected]>
Add device table for new Micron SPI NAND devices, which have multiple dies.
Also, enable support to select the dies.
--- drivers/mtd/nand/spi/micron.c | 55 +++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+)
drivers/mtd/nand/spi/micron.c +55 -0
@@ -20,6 +20,14 @@#define MICRON_CFG_CR BIT(0) +/* +* As per datasheet, die selection is done by the 6th bit of Die +* Select Register (Address 0xD0). +*/ +#define MICRON_DIE_SELECT_REG 0xD0 + +#define MICRON_SELECT_DIE (x) ((x) << 6) + static SPINAND_OP_VARIANTS(read_cache_variants, SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
@@ -66,6 +74,20 @@ static const struct mtd_ooblayout_ops micron_8_ooblayout = { .free = micron_8_ooblayout_free, }; +static int micron_select_target (struct spinand_device *spinand, +unsigned int target) +{ +struct spi_mem_op op =SPINAND_SET_FEATURE_OP (MICRON_DIE_SELECT_REG , + spinand->scratchbuf); + +if (target >1 ) +return -EINVAL ; + + *spinand->scratchbuf =MICRON_SELECT_DIE (target); + +return spi_mem_exec_op (spinand->spimem, &op); +} +static int micron_8_ecc_get_status (struct spinand_device *spinand,u8 status) {
@@ -133,6 +155,17 @@ static const struct spinand_info micron_spinand_table[] = { 0, SPINAND_ECCINFO(µn_8_ooblayout, micron_8_ecc_get_status)), +/* M79A 4Gb 3.3V */ +SPINAND_INFO ("MT29F4G01ADAGD" ,0x36 , +NAND_MEMORG (1 ,2048 ,128 ,64 ,2048 ,80 ,2 ,1 ,2 ), +NAND_ECCREQ (8 ,512 ), +SPINAND_INFO_OP_VARIANTS (&read_cache_variants, + &write_cache_variants, + &update_cache_variants), +0 , +SPINAND_ECCINFO (µn_8_ooblayout, + micron_8_ecc_get_status), +SPINAND_SELECT_TARGET (micron_select_target)),/* M70A 4Gb 3.3V */ SPINAND_INFO("MT29F4G01ABAFD", 0x34, NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
@@ -153,6 +186,28 @@ static const struct spinand_info micron_spinand_table[] = { SPINAND_HAS_CR_FEAT_BIT, SPINAND_ECCINFO(µn_8_ooblayout, micron_8_ecc_get_status)), +/* M70A 8Gb 3.3V */ +SPINAND_INFO ("MT29F8G01ADAFD" ,0x46 , +NAND_MEMORG (1 ,4096 ,256 ,64 ,2048 ,40 ,1 ,1 ,2 ), +NAND_ECCREQ (8 ,512 ), +SPINAND_INFO_OP_VARIANTS (&read_cache_variants, + &write_cache_variants, + &update_cache_variants), +SPINAND_HAS_CR_FEAT_BIT , +SPINAND_ECCINFO (µn_8_ooblayout, + micron_8_ecc_get_status), +SPINAND_SELECT_TARGET (micron_select_target)), +/* M70A 8Gb 1.8V */ +SPINAND_INFO ("MT29F8G01ADBFD" ,0x47 , +NAND_MEMORG (1 ,4096 ,256 ,64 ,2048 ,40 ,1 ,1 ,2 ), +NAND_ECCREQ (8 ,512 ), +SPINAND_INFO_OP_VARIANTS (&read_cache_variants, + &write_cache_variants, + &update_cache_variants), +SPINAND_HAS_CR_FEAT_BIT , +SPINAND_ECCINFO (µn_8_ooblayout, + micron_8_ecc_get_status), + SPINAND_SELECT_TARGET(micron_select_target)), };static int micron_spinand_detect (struct spinand_device *spinand)
Signature · 1 line
2.17.1
Re: [PATCH v6 6/6] mtd: spinand: micron: Add new Micron SPI NAND devices with multiple dies
Quoted 8 lines · On Mon, 9 Mar 2020 12:52:30 +0100 [email protected] wrote:
From: Shivamurthy Shastri <[email protected]>
Add device table for new Micron SPI NAND devices, which have multiple dies.
Also, enable support to select the dies.
Signed-off-by Shivamurthy Shastri <[email protected]>
Quoted 91 lines
--- drivers/mtd/nand/spi/micron.c | 55 +++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+)drivers/mtd/nand/spi/micron.c +55
-0@@ -20,6 +20,14 @@#define MICRON_CFG_CR BIT(0) +/* +* As per datasheet, die selection is done by the 6th bit of Die +* Select Register (Address 0xD0). +*/ +#define MICRON_DIE_SELECT_REG 0xD0 + +#define MICRON_SELECT_DIE (x) ((x) << 6) + static SPINAND_OP_VARIANTS(read_cache_variants, SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),@@ -66,6 +74,20 @@ static const struct mtd_ooblayout_ops micron_8_ooblayout = { .free = micron_8_ooblayout_free, }; +static int micron_select_target (struct spinand_device *spinand, +unsigned int target) +{ +struct spi_mem_op op =SPINAND_SET_FEATURE_OP (MICRON_DIE_SELECT_REG , + spinand->scratchbuf); + +if (target >1 ) +return -EINVAL ; + + *spinand->scratchbuf =MICRON_SELECT_DIE (target); + +return spi_mem_exec_op (spinand->spimem, &op); +} +static int micron_8_ecc_get_status (struct spinand_device *spinand,u8 status) {@@ -133,6 +155,17 @@ static const struct spinand_info micron_spinand_table[] = { 0, SPINAND_ECCINFO(µn_8_ooblayout, micron_8_ecc_get_status)), +/* M79A 4Gb 3.3V */ +SPINAND_INFO ("MT29F4G01ADAGD" ,0x36 , +NAND_MEMORG (1 ,2048 ,128 ,64 ,2048 ,80 ,2 ,1 ,2 ), +NAND_ECCREQ (8 ,512 ), +SPINAND_INFO_OP_VARIANTS (&read_cache_variants, + &write_cache_variants, + &update_cache_variants), +0 , +SPINAND_ECCINFO (µn_8_ooblayout, + micron_8_ecc_get_status), +SPINAND_SELECT_TARGET (micron_select_target)),/* M70A 4Gb 3.3V */ SPINAND_INFO("MT29F4G01ABAFD", 0x34, NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),@@ -153,6 +186,28 @@ static const struct spinand_info micron_spinand_table[] = { SPINAND_HAS_CR_FEAT_BIT, SPINAND_ECCINFO(µn_8_ooblayout, micron_8_ecc_get_status)), +/* M70A 8Gb 3.3V */ +SPINAND_INFO ("MT29F8G01ADAFD" ,0x46 , +NAND_MEMORG (1 ,4096 ,256 ,64 ,2048 ,40 ,1 ,1 ,2 ), +NAND_ECCREQ (8 ,512 ), +SPINAND_INFO_OP_VARIANTS (&read_cache_variants, + &write_cache_variants, + &update_cache_variants), +SPINAND_HAS_CR_FEAT_BIT , +SPINAND_ECCINFO (µn_8_ooblayout, + micron_8_ecc_get_status), +SPINAND_SELECT_TARGET (micron_select_target)), +/* M70A 8Gb 1.8V */ +SPINAND_INFO ("MT29F8G01ADBFD" ,0x47 , +NAND_MEMORG (1 ,4096 ,256 ,64 ,2048 ,40 ,1 ,1 ,2 ), +NAND_ECCREQ (8 ,512 ), +SPINAND_INFO_OP_VARIANTS (&read_cache_variants, + &write_cache_variants, + &update_cache_variants), +SPINAND_HAS_CR_FEAT_BIT , +SPINAND_ECCINFO (µn_8_ooblayout, + micron_8_ecc_get_status), + SPINAND_SELECT_TARGET(micron_select_target)), };static int micron_spinand_detect (struct spinand_device *spinand)
Hi Miquel,
I have rebased these patches to v5.6-rc1 as you suggested. Please let me know, if there is still a problem.
Thanks,
Shiva
Quoted 78 lines
From: Shivamurthy Shastri <[email protected]>
This patchset is for the new series of Micron SPI NAND devices, and the following links are their datasheets.
M78A:
[1] https://www.micron.com/~/media/documents/products/data-
sheet/nand-flash/70-series/m78a_1gb_3v_nand_spi.pdf
[2] https://www.micron.com/~/media/documents/products/data-
sheet/nand-flash/70-series/m78a_1gb_1_8v_nand_spi.pdfM79A:
[3] https://www.micron.com/~/media/documents/products/data-
sheet/nand-flash/70-series/m79a_2gb_1_8v_nand_spi.pdf
[4] https://www.micron.com/~/media/documents/products/data-
sheet/nand-flash/70-series/m79a_ddp_4gb_3v_nand_spi.pdfM70A:
[5] https://www.micron.com/~/media/documents/products/data-
sheet/nand-flash/70-series/m70a_4gb_3v_nand_spi.pdf
[6] https://www.micron.com/~/media/documents/products/data-
sheet/nand-flash/70-series/m70a_4gb_1_8v_nand_spi.pdf
[7] https://www.micron.com/~/media/documents/products/data-
sheet/nand-flash/70-series/m70a_ddp_8gb_3v_nand_spi.pdf
[8] https://www.micron.com/~/media/documents/products/data-
sheet/nand-flash/70-series/m70a_ddp_8gb_1_8v_nand_spi.pdfChanges since v5:
-----------------1. Rebased series to v5.6-rc1.
Changes since v4:
-----------------1. Patch 2 is separated into two as per the comment by Boris.
2. RenamedMICRON_CFG_CONTI_READintoMICRON_CFG_CR.
3. Reworked die selection function as per the comment by Boris.Changes since v3:
-----------------1. Patch 3 and 4 reworked as follows
- Patch 3 introducing the Continuous read feature
- Patch 4 adding devices with the featureChanges since v2:
-----------------1. Patch commit messages have been modified.
2. Handled devices with Continuous Read feature with vendor specific flag.
3. Reworked die selection function as per the comment.Changes since v1:
-----------------1. The patch split into multiple patches.
2. Added comments for selecting the die.Shivamurthy Shastri (6):
mtd: spinand: micron: Generalize the OOB layout structure and function
names
mtd: spinand: micron: Describe the SPI NAND device MT29F2G01ABAGD
mtd: spinand: micron: Add new Micron SPI NAND devices
mtd: spinand: micron: identify SPI NAND device with Continuous Read
mode
mtd: spinand: micron: Add M70A series Micron SPI NAND devices
mtd: spinand: micron: Add new Micron SPI NAND devices with multiple
diesdrivers/mtd/nand/spi/micron.c | 150 ++++++++++++++++++++++++++++++---- include/linux/mtd/spinand.h | 1 + 2 files changed, 137 insertions(+), 14 deletions(-)--
2.17.1
Miquel Raynal
maintainerHi Shiva,
[email protected] wrote on Mon, 9 Mar 2020 12:52:24 +0100:
Quoted 19 lines
From: Shivamurthy Shastri <[email protected]>
This patchset is for the new series of Micron SPI NAND devices, and the following links are their datasheets.
M78A:
[1] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m78a_1gb_3v_nand_spi.pdf
[2] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m78a_1gb_1_8v_nand_spi.pdfM79A:
[3] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m79a_2gb_1_8v_nand_spi.pdf
[4] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m79a_ddp_4gb_3v_nand_spi.pdfM70A:
[5] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m70a_4gb_3v_nand_spi.pdf
[6] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m70a_4gb_1_8v_nand_spi.pdf
[7] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m70a_ddp_8gb_3v_nand_spi.pdf
[8] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m70a_ddp_8gb_1_8v_nand_spi.pdf
Quoted 4 lines
Changes since v5:
-----------------1. Rebased series to v5.6-rc1.
I am very sorry but actually I had issues applying all your patches not because they were not based on v5.6-rc1, but because since then I applied a patch changing the detection that changed the content of a lot of structures (including in Micron's patches).
Can you please rebase again on top of the current nand/next? I am very sorry for this extra work, this is my mistake.
Head should be:
a5d53ad26a8b ("mtd: rawnand: brcmnand: Add support for flash-edu for dma transfers")
And the culprit commit is:
f1541773af49 ("mtd: spinand: rework detect procedure for different READ_ID operation")
Thanks,
Miquèl
Hi Miquel,
Quoted 47 lines
Hi Shiva,
[email protected] wrote on Mon, 9 Mar 2020 12:52:24 +0100:
Quoted 7 lines
From: Shivamurthy Shastri <[email protected]>
This patchset is for the new series of Micron SPI NAND devices, and the following links are their datasheets.
M78A:
[1] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m78a_1gb_3v_nand_spi.pdf
Quoted 1 line
sheet/nand-flash/70-series/m78a_1gb_1_8v_nand_spi.pdf
Quoted 3 lines
M79A:
[3] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m79a_2gb_1_8v_nand_spi.pdf
Quoted 1 line
sheet/nand-flash/70-series/m79a_ddp_4gb_3v_nand_spi.pdf
Quoted 3 lines
M70A:
[5] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m70a_4gb_3v_nand_spi.pdf
Quoted 1 line
sheet/nand-flash/70-series/m70a_4gb_1_8v_nand_spi.pdf
Quoted 1 line
sheet/nand-flash/70-series/m70a_ddp_8gb_3v_nand_spi.pdf
Quoted 1 line
sheet/nand-flash/70-series/m70a_ddp_8gb_1_8v_nand_spi.pdf
Quoted 5 lines
Changes since v5:
-----------------1. Rebased series to v5.6-rc1.
I am very sorry but actually I had issues applying all your patches not because they were not based on v5.6-rc1, but because since then I applied a patch changing the detection that changed the content of a lot of structures (including in Micron's patches).
Can you please rebase again on top of the current nand/next? I am very sorry for this extra work, this is my mistake.
Head should be:
Quoted 7 lines
a5d53ad26a8b("mtd: rawnand: brcmnand: Add support for flash-edu
for dma transfers")And the culprit commit is:
f1541773af49("mtd: spinand: rework detect procedure for differentREAD_IDoperation")
I will rebase and send the patches.
Meanwhile, there will be small code change because of the READ_ID patch.
Do I need to drop Reviewed-by from Boris?
Thanks,
Shiva
Quoted 54 lines · On Wed, 11 Mar 2020 17:33:41 +0000 "Shivamurthy Shastri (sshivamurthy)"…
Hi Miquel,
Quoted 52 lines
Hi Shiva,
[email protected] wrote on Mon, 9 Mar 2020 12:52:24 +0100:
Quoted 7 lines
From: Shivamurthy Shastri <[email protected]>
This patchset is for the new series of Micron SPI NAND devices, and the following links are their datasheets.
M78A:
[1] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m78a_1gb_3v_nand_spi.pdf
Quoted 1 line
sheet/nand-flash/70-series/m78a_1gb_1_8v_nand_spi.pdf
Quoted 3 lines
M79A:
[3] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m79a_2gb_1_8v_nand_spi.pdf
Quoted 1 line
sheet/nand-flash/70-series/m79a_ddp_4gb_3v_nand_spi.pdf
Quoted 3 lines
M70A:
[5] https://www.micron.com/~/media/documents/products/data-sheet/nand-flash/70-series/m70a_4gb_3v_nand_spi.pdf
Quoted 1 line
sheet/nand-flash/70-series/m70a_4gb_1_8v_nand_spi.pdf
Quoted 1 line
sheet/nand-flash/70-series/m70a_ddp_8gb_3v_nand_spi.pdf
Quoted 1 line
sheet/nand-flash/70-series/m70a_ddp_8gb_1_8v_nand_spi.pdf
Quoted 5 lines
Changes since v5:
-----------------1. Rebased series to v5.6-rc1.
I am very sorry but actually I had issues applying all your patches not because they were not based on v5.6-rc1, but because since then I applied a patch changing the detection that changed the content of a lot of structures (including in Micron's patches).
Can you please rebase again on top of the current nand/next? I am very sorry for this extra work, this is my mistake.
Head should be:
a5d53ad26a8b("mtd: rawnand: brcmnand: Add support for flash-edu
for dma transfers")And the culprit commit is:
Quoted 8 lines
Quoted 2 lines
f1541773af49("mtd: spinand: rework detect procedure for differentREAD_IDoperation")I will rebase and send the patches.
Meanwhile, there will be small code change because of theREAD_IDpatch.Do I need to drop Reviewed-by from Boris?
Nope, you can keep it.