clk: agilex: add clock driver
Dinh Nguyen
maintainerv3 cover clk: agilex: add clock driver
Hi,
This is version 3 of the patchset to add a clock driver to the Agilex platform.
This version adds 2 new patches that was a result from comments received in v2.
Patch 2/5: clk: socfpga: remove clk_ops enable/disable methods Patch 3/5: clk: socfpga: add const to _ops data structures
Thanks,
Dinh
Dinh Nguyen (5):
clk: socfpga: stratix10: use new parent data scheme
clk: socfpga: remove clk_ops enable/disable methods
clk: socfpga: add const to _ops data structures
dt-bindings: documentation: add clock bindings information for Agilex
clk: socfpga: agilex: add clock driver for the Agilex platform
.../bindings/clock/intel,agilex.yaml | 36 ++ drivers/clk/Makefile | 3 +- drivers/clk/socfpga/Makefile | 2 + drivers/clk/socfpga/clk-agilex.c | 454 ++++++++++++++++++ drivers/clk/socfpga/clk-gate-s10.c | 5 +- drivers/clk/socfpga/clk-periph-s10.c | 10 +- drivers/clk/socfpga/clk-pll-a10.c | 4 +- drivers/clk/socfpga/clk-pll-s10.c | 78 ++- drivers/clk/socfpga/clk-pll.c | 4 +- drivers/clk/socfpga/clk-s10.c | 160 ++++-- drivers/clk/socfpga/stratix10-clk.h | 10 +- include/dt-bindings/clock/agilex-clock.h | 70 +++ 12 files changed, 784 insertions(+), 52 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex.yaml create mode 100644 drivers/clk/socfpga/clk-agilex.c create mode 100644 include/dt-bindings/clock/agilex-clock.h
Signature · 1 line
2.25.1
Dinh Nguyen
maintainerPATCH v3 2/5 clk: socfpga: remove clk_ops enable/disable methods
From: Dinh Nguyen <[email protected]>
The enable/disable clock ops are already defined in the standard clock ops, so we don't need to assign them.
--- drivers/clk/socfpga/clk-pll-a10.c | 2 -- drivers/clk/socfpga/clk-pll-s10.c | 2 -- drivers/clk/socfpga/clk-pll.c | 2 -- 3 files changed, 6 deletions(-)
drivers/clk/socfpga/clk-pll-a10.c +0 -2
@@ -102,8 +102,6 @@ static struct clk * __init __socfpga_pll_init(struct device_node *node, pll_clk->hw.hw.init = &init; pll_clk->hw.bit_idx =SOCFPGA_PLL_EXT_ENA ; - clk_pll_ops.enable = clk_gate_ops.enable; - clk_pll_ops.disable = clk_gate_ops.disable; clk =clk_register (NULL , &pll_clk->hw.hw);if (WARN_ON (IS_ERR (clk))) {
drivers/clk/socfpga/clk-pll-s10.c +0 -2
@@ -138,8 +138,6 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks, pll_clk->hw.hw.init = &init; pll_clk->hw.bit_idx =SOCFPGA_PLL_POWER ; - clk_pll_ops.enable = clk_gate_ops.enable; - clk_pll_ops.disable = clk_gate_ops.disable; clk =clk_register (NULL , &pll_clk->hw.hw);if (WARN_ON (IS_ERR (clk))) {
drivers/clk/socfpga/clk-pll.c +0 -2
@@ -105,8 +105,6 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node, pll_clk->hw.hw.init = &init; pll_clk->hw.bit_idx =SOCFPGA_PLL_EXT_ENA ; - clk_pll_ops.enable = clk_gate_ops.enable; - clk_pll_ops.disable = clk_gate_ops.disable; clk =clk_register (NULL , &pll_clk->hw.hw);if (WARN_ON (IS_ERR (clk))) {
Signature · 1 line
2.25.1
Dinh Nguyen
maintainerPATCH v3 3/5 clk: socfpga: add const to _ops data structures
In reply to Dinh NguyenFrom: Dinh Nguyen <[email protected]>
All the static clk_ops data structure need a const.
--- drivers/clk/socfpga/clk-pll-a10.c | 2 +- drivers/clk/socfpga/clk-pll-s10.c | 4 ++-- drivers/clk/socfpga/clk-pll.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-)
drivers/clk/socfpga/clk-pll-a10.c +1 -1
@@ -58,7 +58,7 @@ static u8 clk_pll_get_parent(struct clk_hw *hwclk)CLK_MGR_PLL_CLK_SRC_MASK ; } -static struct clk_ops clk_pll_ops = { +static const struct clk_ops clk_pll_ops = { .recalc_rate = clk_pll_recalc_rate, .get_parent = clk_pll_get_parent, };
drivers/clk/socfpga/clk-pll-s10.c +2 -2
@@ -98,13 +98,13 @@ static int clk_pll_prepare(struct clk_hw *hwclk)return 0 ; } -static struct clk_ops clk_pll_ops = { +static const struct clk_ops clk_pll_ops = { .recalc_rate = clk_pll_recalc_rate, .get_parent = clk_pll_get_parent, .prepare = clk_pll_prepare, }; -static struct clk_ops clk_boot_ops = { +static const struct clk_ops clk_boot_ops = { .recalc_rate = clk_boot_clk_recalc_rate, .get_parent = clk_boot_get_parent, .prepare = clk_pll_prepare,
drivers/clk/socfpga/clk-pll.c +1 -1
@@ -65,7 +65,7 @@ static u8 clk_pll_get_parent(struct clk_hw *hwclk)CLK_MGR_PLL_CLK_SRC_MASK ; } -static struct clk_ops clk_pll_ops = { +static const struct clk_ops clk_pll_ops = { .recalc_rate = clk_pll_recalc_rate, .get_parent = clk_pll_get_parent, };
Signature · 1 line
2.25.1
Dinh Nguyen
maintainerPATCH v3 4/5 dt-bindings: documentation: add clock bindings information for Agilex
In reply to Dinh NguyenDocument the Agilex clock bindings, and add the clock header file. The clock header is an enumeration of all the different clocks on the Agilex platform.
---
v3: address comments from Stephen Boyd
fix build error(tab removed in line 37)
renamed to intel,agilex.yaml
v2: convert original document to YAML
--- .../bindings/clock/intel,agilex.yaml | 36 ++++++++++ include/dt-bindings/clock/agilex-clock.h | 70 +++++++++++++++++++ 2 files changed, 106 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex.yaml create mode 100644 include/dt-bindings/clock/agilex-clock.h
Documentation/devicetree/bindings/clock/intel,agilex.yaml new file +36 -0
@@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/intel,agilex.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA Agilex platform clock controller binding + +maintainers: + - Dinh Nguyen <[email protected]> + +description: + The Intel Agilex Clock controller is an integrated clock controller, which + generates and supplies to all modules. + +properties: + compatible: + const: intel,agilex-clkmgr + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +examples: + - | + # Clock controller node + clkmgr: clock-controller@ffd10000 { + compatible = "intel,agilex-clkmgr"; + reg = <0xffd10000 0x1000>; + #clock-cells = <1>; + }; +...
include/dt-bindings/clock/agilex-clock.h new file +70 -0
70 lines not on this page · raw message
Signature · 1 line
2.25.1
Rob Herring
maintainerRe: [PATCHv3 4/5] dt-bindings: documentation: add clock bindings information for Agilex
Quoted 10 lines · Dinh Nguyen
Document the Agilex clock bindings, and add the clock header file. The clock header is an enumeration of all the different clocks on the Agilex platform.
Signed-off-by Dinh Nguyen <[email protected]>---
v3: address comments from Stephen Boyd
fix build error(tab removed in line 37)
renamed to intel,agilex.yaml
v2: convert original document to YAML
Quoted 7 lines
--- .../bindings/clock/intel,agilex.yaml | 36 ++++++++++ include/dt-bindings/clock/agilex-clock.h | 70 +++++++++++++++++++ 2 files changed, 106 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex.yaml create mode 100644 include/dt-bindings/clock/agilex-clock.h
My bot found errors running 'make dt_binding_check' on your patch:
Error: Documentation/devicetree/bindings/clock/intel,agilex.example.dts:17.3-4 syntax error
FATAL ERROR: Unable to parse input treescripts/Makefile.lib:311: recipe for target 'Documentation/devicetree/bindings/clock/intel,agilex.example.dt.yaml' failed make[1]: *** [Documentation/devicetree/bindings/clock/intel,agilex.example.dt.yaml] Error 1 Makefile:1262: recipe for target 'dt_binding_check' failed
make: *** [dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1256630
Please check and re-submit.
Dinh Nguyen
maintainerRe: [PATCHv3 4/5] dt-bindings: documentation: add clock bindings information for Agilex
Hi Rob,
Quoted 28 lines · Rob Herring
Quoted 10 lines · Dinh Nguyen
Document the Agilex clock bindings, and add the clock header file. The clock header is an enumeration of all the different clocks on the Agilex platform.
Signed-off-by Dinh Nguyen <[email protected]>---
v3: address comments from Stephen Boyd
fix build error(tab removed in line 37)
renamed to intel,agilex.yaml
v2: convert original document to YAMLQuoted 7 lines
--- .../bindings/clock/intel,agilex.yaml | 36 ++++++++++ include/dt-bindings/clock/agilex-clock.h | 70 +++++++++++++++++++ 2 files changed, 106 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex.yaml create mode 100644 include/dt-bindings/clock/agilex-clock.hMy bot found errors running 'make
dt_binding_check' on your patch:Error: Documentation/devicetree/bindings/clock/intel,agilex.example.dts:17.3-4 syntax error
FATAL ERROR: Unable to parse input treescripts/Makefile.lib:311: recipe for target 'Documentation/devicetree/bindings/clock/intel,agilex.example.dt.yaml' failed make[1]: *** [Documentation/devicetree/bindings/clock/intel,agilex.example.dt.yaml] Error 1 Makefile:1262: recipe for target 'dt_binding_check' failed
make: *** [dt_binding_check] Error 2
Quoted 3 lines
See https://patchwork.ozlabs.org/patch/1256630
Please check and re-submit.
I want to be able check these errors locally before sending the next version. But I keep getting various errors when I try to "make dt_binding_check":
Traceback (most recent call last):
File "/bin/dt-doc-validate", line 15, in <module>
import ruamel.yaml
ImportError: No module named 'ruamel' Documentation/devicetree/bindings/Makefile:12: recipe for target 'Documentation/devicetree/bindings/arm/l2c2x0.example.dts' failed
Do you have a pointer on how to run the dt_binding_check?
Thanks,
Dinh
Rob Herring
maintainerRe: [PATCHv3 4/5] dt-bindings: documentation: add clock bindings information for Agilex
Quoted 48 lines · Dinh Nguyen
Hi Rob,
Quoted 28 lines · Rob Herring
Quoted 10 lines · Dinh Nguyen
Document the Agilex clock bindings, and add the clock header file. The clock header is an enumeration of all the different clocks on the Agilex platform.
Signed-off-by Dinh Nguyen <[email protected]>---
v3: address comments from Stephen Boyd
fix build error(tab removed in line 37)
renamed to intel,agilex.yaml
v2: convert original document to YAMLQuoted 7 lines
--- .../bindings/clock/intel,agilex.yaml | 36 ++++++++++ include/dt-bindings/clock/agilex-clock.h | 70 +++++++++++++++++++ 2 files changed, 106 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex.yaml create mode 100644 include/dt-bindings/clock/agilex-clock.hMy bot found errors running 'make
dt_binding_check' on your patch:Error: Documentation/devicetree/bindings/clock/intel,agilex.example.dts:17.3-4 syntax error
FATAL ERROR: Unable to parse input treescripts/Makefile.lib:311: recipe for target 'Documentation/devicetree/bindings/clock/intel,agilex.example.dt.yaml' failed make[1]: *** [Documentation/devicetree/bindings/clock/intel,agilex.example.dt.yaml] Error 1 Makefile:1262: recipe for target 'dt_binding_check' failed
make: *** [dt_binding_check] Error 2Quoted 3 lines
See https://patchwork.ozlabs.org/patch/1256630
Please check and re-submit.I want to be able check these errors locally before sending the next version. But I keep getting various errors when I try to "make
dt_binding_check":Traceback (most recent call last):
File "/bin/dt-doc-validate", line 15, in <module>
importruamel.yaml
ImportError: No module named 'ruamel'Documentation/devicetree/bindings/Makefile:12: recipe for target 'Documentation/devicetree/bindings/arm/l2c2x0.example.dts' failed
Quoted 1 line
Do you have a pointer on how to run the
dt_binding_check?
Documentation/devicetree/writing-schema.rst
ruamel should get installed automatically when you run pip3. If you just cloned dt-schema, then you still need to run pip on the project directory. That's documented in the project readme.
Rob
Dinh Nguyen
maintainerRe: [PATCHv3 4/5] dt-bindings: documentation: add clock bindings information for Agilex
Hi Rob,
Quoted 49 lines · Rob Herring
Quoted 48 lines · Dinh Nguyen
Hi Rob,
Quoted 28 lines · Rob Herring
Quoted 10 lines · Dinh Nguyen
Document the Agilex clock bindings, and add the clock header file. The clock header is an enumeration of all the different clocks on the Agilex platform.
Signed-off-by Dinh Nguyen <[email protected]>---
v3: address comments from Stephen Boyd
fix build error(tab removed in line 37)
renamed to intel,agilex.yaml
v2: convert original document to YAMLQuoted 7 lines
--- .../bindings/clock/intel,agilex.yaml | 36 ++++++++++ include/dt-bindings/clock/agilex-clock.h | 70 +++++++++++++++++++ 2 files changed, 106 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex.yaml create mode 100644 include/dt-bindings/clock/agilex-clock.hMy bot found errors running 'make
dt_binding_check' on your patch:Error: Documentation/devicetree/bindings/clock/intel,agilex.example.dts:17.3-4 syntax error
FATAL ERROR: Unable to parse input treescripts/Makefile.lib:311: recipe for target 'Documentation/devicetree/bindings/clock/intel,agilex.example.dt.yaml' failed make[1]: *** [Documentation/devicetree/bindings/clock/intel,agilex.example.dt.yaml] Error 1 Makefile:1262: recipe for target 'dt_binding_check' failed
make: *** [dt_binding_check] Error 2Quoted 3 lines
See https://patchwork.ozlabs.org/patch/1256630
Please check and re-submit.I want to be able check these errors locally before sending the next version. But I keep getting various errors when I try to "make
dt_binding_check":Traceback (most recent call last):
File "/bin/dt-doc-validate", line 15, in <module>
importruamel.yaml
ImportError: No module named 'ruamel'Documentation/devicetree/bindings/Makefile:12: recipe for target 'Documentation/devicetree/bindings/arm/l2c2x0.example.dts' failed
Quoted 8 lines
Quoted 1 line
Do you have a pointer on how to run the
dt_binding_check?
Documentation/devicetree/writing-schema.rstruamel should get installed automatically when you run pip3. If you just cloned dt-schema, then you still need to run pip on the project directory. That's documented in the project readme.
Thanks alot for the pointers. Fixed it.
Dinh
Dinh Nguyen
maintainerPATCH v3 5/5 clk: socfpga: agilex: add clock driver for the Agilex platform
In reply to Dinh NguyenFor the most part the Agilex clock structure is very similar to Stratix10, so we re-use most of the Stratix10 clock driver.
---
v3: Address Stephen Boyd's comments
v2: update to use clk_parent_data
--- drivers/clk/Makefile | 3 +- drivers/clk/socfpga/Makefile | 2 + drivers/clk/socfpga/clk-agilex.c | 454 ++++++++++++++++++++++++++++ drivers/clk/socfpga/clk-pll-s10.c | 68 +++++ drivers/clk/socfpga/stratix10-clk.h | 2 + 5 files changed, 528 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/socfpga/clk-agilex.c
drivers/clk/Makefile +2 -1
@@ -104,10 +104,11 @@ obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ obj-$(CONFIG_CLK_SIFIVE) += sifive/ obj-$(CONFIG_ARCH_SIRF) += sirf/ obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ +obj-$(CONFIG_ARCH_AGILEX) += socfpga/ +obj-$(CONFIG_ARCH_STRATIX10) += socfpga/ obj-$(CONFIG_PLAT_SPEAR) += spear/ obj-$(CONFIG_ARCH_SPRD) += sprd/ obj-$(CONFIG_ARCH_STI) += st/ -obj-$(CONFIG_ARCH_STRATIX10) += socfpga/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_SUNXI_CCU) += sunxi-ng/ obj-$(CONFIG_ARCH_TEGRA) += tegra/
drivers/clk/socfpga/Makefile +2 -0
@@ -3,3 +3,5 @@ obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o clk-periph.o obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o obj-$(CONFIG_ARCH_STRATIX10) += clk-s10.o obj-$(CONFIG_ARCH_STRATIX10) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o +obj-$(CONFIG_ARCH_AGILEX) += clk-agilex.o +obj-$(CONFIG_ARCH_AGILEX) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o
drivers/clk/socfpga/clk-agilex.c new file +454 -0
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drivers/clk/socfpga/clk-pll-s10.c +68 -0
91 lines not on this page · raw message
drivers/clk/socfpga/stratix10-clk.h +2 -0
@@ -62,6 +62,8 @@ struct stratix10_gate_clock {struct clk *s10_register_pll (const struct stratix10_pll_clock *,void __iomem *); +struct clk *agilex_register_pll (const struct stratix10_pll_clock *, +void __iomem *);struct clk *s10_register_periph (const struct stratix10_perip_c_clock *,void __iomem *); struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *,
Signature · 1 line
2.25.1
Dinh Nguyen
maintainerPATCH v2 1/5 clk: socfpga: stratix10: use new parent data scheme
In reply to Dinh NguyenConvert, where possible, the stratix10 clock driver to the new parent data scheme by specifying the parent data for clocks that have multiple parents.
---
v2: add fw_name
--- drivers/clk/socfpga/clk-gate-s10.c | 5 +- drivers/clk/socfpga/clk-periph-s10.c | 10 +- drivers/clk/socfpga/clk-pll-s10.c | 4 +- drivers/clk/socfpga/clk-s10.c | 160 ++++++++++++++++++++++----- drivers/clk/socfpga/stratix10-clk.h | 8 +- 5 files changed, 146 insertions(+), 41 deletions(-)
drivers/clk/socfpga/clk-gate-s10.c +3 -2
@@ -70,7 +70,6 @@ struct clk *s10_register_gate(const struct stratix10_gate_clock *clks, void __iostruct clk *clk;struct socfpga_gate_clk *socfpga_clk;struct clk_init_data init; -const char *const *parent_names = clks->parent_names;const char *parent_name = clks->parent_name; socfpga_clk =kzalloc (sizeof (*socfpga_clk),GFP_KERNEL );
@@ -108,7 +107,9 @@ struct clk *s10_register_gate(const struct stratix10_gate_clock *clks, void __io init.flags = clks->flags; init.num_parents = clks->num_parents; - init.parent_names = parent_names ? parent_names : &parent_name; + init.parent_names = parent_name ? &parent_name :NULL ; +if (init.parent_names ==NULL ) + init.parent_data = clks->parent_data; socfpga_clk->hw.hw.init = &init; clk =clk_register (NULL , &socfpga_clk->hw.hw);
drivers/clk/socfpga/clk-periph-s10.c +6 -4
@@ -81,7 +81,6 @@ struct clk *s10_register_periph(const struct stratix10_perip_c_clock *clks,struct clk_init_data init;const char *name = clks->name;const char *parent_name = clks->parent_name; -const char *const *parent_names = clks->parent_names; periph_clk =kzalloc (sizeof (*periph_clk),GFP_KERNEL );if (WARN_ON (!periph_clk))
@@ -94,7 +93,9 @@ struct clk *s10_register_periph(const struct stratix10_perip_c_clock *clks, init.flags = clks->flags; init.num_parents = clks->num_parents; - init.parent_names = parent_names ? parent_names : &parent_name; + init.parent_names = parent_name ? &parent_name :NULL ; +if (init.parent_names ==NULL ) + init.parent_data = clks->parent_data; periph_clk->hw.hw.init = &init;
@@ -114,7 +115,6 @@ struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clksstruct clk_init_data init;const char *name = clks->name;const char *parent_name = clks->parent_name; -const char *const *parent_names = clks->parent_names; periph_clk =kzalloc (sizeof (*periph_clk),GFP_KERNEL );if (WARN_ON (!periph_clk))
@@ -137,7 +137,9 @@ struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks init.flags = clks->flags; init.num_parents = clks->num_parents; - init.parent_names = parent_names ? parent_names : &parent_name; + init.parent_names = parent_name ? &parent_name :NULL ; +if (init.parent_names ==NULL ) + init.parent_data = clks->parent_data; periph_clk->hw.hw.init = &init;
drivers/clk/socfpga/clk-pll-s10.c +2 -2
@@ -117,7 +117,6 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks,struct socfpga_pll *pll_clk;struct clk_init_data init;const char *name = clks->name; -const char *const *parent_names = clks->parent_names; pll_clk =kzalloc (sizeof (*pll_clk),GFP_KERNEL );if (WARN_ON (!pll_clk))
@@ -134,7 +133,8 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks, init.flags = clks->flags; init.num_parents = clks->num_parents; - init.parent_names = parent_names; + init.parent_names =NULL ; + init.parent_data = clks->parent_data; pll_clk->hw.hw.init = &init; pll_clk->hw.bit_idx =SOCFPGA_PLL_POWER ;
drivers/clk/socfpga/clk-s10.c +131 -29
166 lines not on this page · raw message
drivers/clk/socfpga/stratix10-clk.h +4 -4
@@ -14,7 +14,7 @@ struct stratix10_clock_data {struct stratix10_pll_clock {unsigned int id;const char *name; -const char *const *parent_names; +const struct clk_parent_data *parent_data;u8 num_parents;unsigned long flags;unsigned long offset;
@@ -24,7 +24,7 @@ struct stratix10_perip_c_clock {unsigned int id;const char *name;const char *parent_name; -const char *const *parent_names; +const struct clk_parent_data *parent_data;u8 num_parents;unsigned long flags;unsigned long offset;
@@ -34,7 +34,7 @@ struct stratix10_perip_cnt_clock {unsigned int id;const char *name;const char *parent_name; -const char *const *parent_names; +const struct clk_parent_data *parent_data;u8 num_parents;unsigned long flags;unsigned long offset;
@@ -47,7 +47,7 @@ struct stratix10_gate_clock {unsigned int id;const char *name;const char *parent_name; -const char *const *parent_names; +const struct clk_parent_data *parent_data;u8 num_parents;unsigned long flags;unsigned long gate_reg;
Signature · 1 line
2.25.1