clk: socfpga: stratix10: use new parent data scheme

PATCH RESEND Applied Dinh Nguyen 2 participants 9 messages May 12, 2020 – May 27, 2020

Subsystems (3)

Device tree bindings Common clk Arm/socfpga clock framework support

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Dinh Nguyen

author maintainer

2020-05-12 18:17 UTC #0 lore raw

PATCH RESEND v7 1/5 clk: socfpga: stratix10: use new parent data scheme

Convert, where possible, the stratix10 clock driver to the new parent data scheme by specifying the parent data for clocks that have multiple parents.

Signed-off-by Dinh Nguyen <[email protected]>

---
v7: no change
v6: no change
v5: no change
v4: no change
v3: no change
v2: add fw_name

---
 drivers/clk/socfpga/clk-gate-s10.c   |   5 +-
 drivers/clk/socfpga/clk-periph-s10.c |  10 +-
 drivers/clk/socfpga/clk-pll-s10.c    |   4 +-
 drivers/clk/socfpga/clk-s10.c        | 160 ++++++++++++++++++++++-----
 drivers/clk/socfpga/stratix10-clk.h  |   8 +-
 5 files changed, 146 insertions(+), 41 deletions(-)

drivers/clk/socfpga/clk-gate-s10.c +3 -2

index 8be4722f6064..083b2ec21fdd 100644
@@ -70,7 +70,6 @@ struct clk *s10_register_gate(const struct stratix10_gate_clock *clks, void __io
 	struct clk *clk;
 	struct socfpga_gate_clk *socfpga_clk;
 	struct clk_init_data init;
-	const char * const *parent_names = clks->parent_names;
 	const char *parent_name = clks->parent_name;
 
 	socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);

@@ -108,7 +107,9 @@ struct clk *s10_register_gate(const struct stratix10_gate_clock *clks, void __io
 	init.flags = clks->flags;
 
 	init.num_parents = clks->num_parents;
-	init.parent_names = parent_names ? parent_names : &parent_name;
+	init.parent_names = parent_name ? &parent_name : NULL;
+	if (init.parent_names == NULL)
+		init.parent_data = clks->parent_data;
 	socfpga_clk->hw.hw.init = &init;
 
 	clk = clk_register(NULL, &socfpga_clk->hw.hw);

drivers/clk/socfpga/clk-periph-s10.c +6 -4

index dd6d4056e9de..397b77b89b16 100644
@@ -81,7 +81,6 @@ struct clk *s10_register_periph(const struct stratix10_perip_c_clock *clks,
 	struct clk_init_data init;
 	const char *name = clks->name;
 	const char *parent_name = clks->parent_name;
-	const char * const *parent_names = clks->parent_names;
 
 	periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
 	if (WARN_ON(!periph_clk))

@@ -94,7 +93,9 @@ struct clk *s10_register_periph(const struct stratix10_perip_c_clock *clks,
 	init.flags = clks->flags;
 
 	init.num_parents = clks->num_parents;
-	init.parent_names = parent_names ? parent_names : &parent_name;
+	init.parent_names = parent_name ? &parent_name : NULL;
+	if (init.parent_names == NULL)
+		init.parent_data = clks->parent_data;
 
 	periph_clk->hw.hw.init = &init;

@@ -114,7 +115,6 @@ struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks
 	struct clk_init_data init;
 	const char *name = clks->name;
 	const char *parent_name = clks->parent_name;
-	const char * const *parent_names = clks->parent_names;
 
 	periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
 	if (WARN_ON(!periph_clk))

@@ -137,7 +137,9 @@ struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks
 	init.flags = clks->flags;
 
 	init.num_parents = clks->num_parents;
-	init.parent_names = parent_names ? parent_names : &parent_name;
+	init.parent_names = parent_name ? &parent_name : NULL;
+	if (init.parent_names == NULL)
+		init.parent_data = clks->parent_data;
 
 	periph_clk->hw.hw.init = &init;

drivers/clk/socfpga/clk-pll-s10.c +2 -2

index a301bb22f36c..bcd3f14e9145 100644
@@ -117,7 +117,6 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks,
 	struct socfpga_pll *pll_clk;
 	struct clk_init_data init;
 	const char *name = clks->name;
-	const char * const *parent_names = clks->parent_names;
 
 	pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
 	if (WARN_ON(!pll_clk))

@@ -134,7 +133,8 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks,
 	init.flags = clks->flags;
 
 	init.num_parents = clks->num_parents;
-	init.parent_names = parent_names;
+	init.parent_names = NULL;
+	init.parent_data = clks->parent_data;
 	pll_clk->hw.hw.init = &init;
 
 	pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;

drivers/clk/socfpga/clk-s10.c +131 ~~-29~~

166 lines not on this page · raw message

drivers/clk/socfpga/stratix10-clk.h +4 -4

index fcabef42249c..ffbd1fb2c8ef 100644
@@ -14,7 +14,7 @@ struct stratix10_clock_data {
 struct stratix10_pll_clock {
 	unsigned int		id;
 	const char		*name;
-	const char		*const *parent_names;
+	const struct clk_parent_data	*parent_data;
 	u8			num_parents;
 	unsigned long		flags;
 	unsigned long		offset;

@@ -24,7 +24,7 @@ struct stratix10_perip_c_clock {
 	unsigned int		id;
 	const char		*name;
 	const char		*parent_name;
-	const char		*const *parent_names;
+	const struct clk_parent_data	*parent_data;
 	u8			num_parents;
 	unsigned long		flags;
 	unsigned long		offset;

@@ -34,7 +34,7 @@ struct stratix10_perip_cnt_clock {
 	unsigned int		id;
 	const char		*name;
 	const char		*parent_name;
-	const char		*const *parent_names;
+	const struct clk_parent_data	*parent_data;
 	u8			num_parents;
 	unsigned long		flags;
 	unsigned long		offset;

@@ -47,7 +47,7 @@ struct stratix10_gate_clock {
 	unsigned int		id;
 	const char		*name;
 	const char		*parent_name;
-	const char		*const *parent_names;
+	const struct clk_parent_data	*parent_data;
 	u8			num_parents;
 	unsigned long		flags;
 	unsigned long		gate_reg;

Signature · 1 line

2.17.1

Dinh Nguyen

author maintainer

2020-05-12 18:17 UTC #1 lore raw

PATCH RESEND v7 2/5 clk: socfpga: remove clk_ops enable/disable methods

The enable/disable clock ops are already defined in the standard clock ops, so we don't need to assign them.

Signed-off-by Dinh Nguyen <[email protected]>

---
v7: no changes
v6: no changes
v5: no changes
v4: no changes
v3: no changes
v2: created

---
 drivers/clk/socfpga/clk-pll-a10.c | 2 --
 drivers/clk/socfpga/clk-pll-s10.c | 2 --
 drivers/clk/socfpga/clk-pll.c     | 2 --
 3 files changed, 6 deletions(-)

drivers/clk/socfpga/clk-pll-a10.c +0 -2

index 3816fc04b274..6d9395106c0c 100644
@@ -102,8 +102,6 @@ static struct clk * __init __socfpga_pll_init(struct device_node *node,
 	pll_clk->hw.hw.init = &init;
 
 	pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
-	clk_pll_ops.enable = clk_gate_ops.enable;
-	clk_pll_ops.disable = clk_gate_ops.disable;
 
 	clk = clk_register(NULL, &pll_clk->hw.hw);
 	if (WARN_ON(IS_ERR(clk))) {

drivers/clk/socfpga/clk-pll-s10.c +0 -2

index bcd3f14e9145..9faa80ff3b53 100644
@@ -138,8 +138,6 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks,
 	pll_clk->hw.hw.init = &init;
 
 	pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
-	clk_pll_ops.enable = clk_gate_ops.enable;
-	clk_pll_ops.disable = clk_gate_ops.disable;
 
 	clk = clk_register(NULL, &pll_clk->hw.hw);
 	if (WARN_ON(IS_ERR(clk))) {

drivers/clk/socfpga/clk-pll.c +0 -2

index dc65cc0fd3bd..a001641b2f42 100644
@@ -105,8 +105,6 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node,
 	pll_clk->hw.hw.init = &init;
 
 	pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
-	clk_pll_ops.enable = clk_gate_ops.enable;
-	clk_pll_ops.disable = clk_gate_ops.disable;
 
 	clk = clk_register(NULL, &pll_clk->hw.hw);
 	if (WARN_ON(IS_ERR(clk))) {

Signature · 1 line

2.17.1

Stephen Boyd

maintainer Applied

2020-05-27 02:13 UTC #2 lore raw

Re: [RESEND PATCHv7 2/5] clk: socfpga: remove clk_ops enable/disable methods

Quoting Dinh Nguyen (2020-05-12 11:16:44)

Quoted 5 lines

The enable/disable clock ops are already defined in the standard clock ops, so we don't need to assign them.
Signed-off-by Dinh Nguyen <[email protected]>
---

Applied to clk-next

Dinh Nguyen

author maintainer

2020-05-12 18:17 UTC #3 lore raw

PATCH RESEND v7 3/5 clk: socfpga: add const to _ops data structures

In reply to Dinh Nguyen

All the static clk_ops data structure need a const.

Signed-off-by Dinh Nguyen <[email protected]>

---
v7: no changes
v6: no changes
v5: no changes
v4: no changes
v3: no changes
v2: created

---
 drivers/clk/socfpga/clk-pll-a10.c | 2 +-
 drivers/clk/socfpga/clk-pll-s10.c | 4 ++--
 drivers/clk/socfpga/clk-pll.c     | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

drivers/clk/socfpga/clk-pll-a10.c +1 -1

index 6d9395106c0c..db54f7d806a0 100644
@@ -58,7 +58,7 @@ static u8 clk_pll_get_parent(struct clk_hw *hwclk)
 		CLK_MGR_PLL_CLK_SRC_MASK;
 }
 
-static struct clk_ops clk_pll_ops = {
+static const struct clk_ops clk_pll_ops = {
 	.recalc_rate = clk_pll_recalc_rate,
 	.get_parent = clk_pll_get_parent,
 };

drivers/clk/socfpga/clk-pll-s10.c +2 -2

index 9faa80ff3b53..5c3e1ee44f6b 100644
@@ -98,13 +98,13 @@ static int clk_pll_prepare(struct clk_hw *hwclk)
 	return 0;
 }
 
-static struct clk_ops clk_pll_ops = {
+static const struct clk_ops clk_pll_ops = {
 	.recalc_rate = clk_pll_recalc_rate,
 	.get_parent = clk_pll_get_parent,
 	.prepare = clk_pll_prepare,
 };
 
-static struct clk_ops clk_boot_ops = {
+static const struct clk_ops clk_boot_ops = {
 	.recalc_rate = clk_boot_clk_recalc_rate,
 	.get_parent = clk_boot_get_parent,
 	.prepare = clk_pll_prepare,

drivers/clk/socfpga/clk-pll.c +1 -1

index a001641b2f42..e5fb786843f3 100644
@@ -65,7 +65,7 @@ static u8 clk_pll_get_parent(struct clk_hw *hwclk)
 			CLK_MGR_PLL_CLK_SRC_MASK;
 }
 
-static struct clk_ops clk_pll_ops = {
+static const struct clk_ops clk_pll_ops = {
 	.recalc_rate = clk_pll_recalc_rate,
 	.get_parent = clk_pll_get_parent,
 };

Signature · 1 line

2.17.1

Stephen Boyd

maintainer Applied

2020-05-27 02:13 UTC #4 lore raw

Re: [RESEND PATCHv7 3/5] clk: socfpga: add const to _ops data structures

Quoting Dinh Nguyen (2020-05-12 11:16:45)

Quoted 4 lines

All the static clk_ops data structure need a const.
Signed-off-by Dinh Nguyen <[email protected]>
---

Applied to clk-next

Dinh Nguyen

author maintainer

2020-05-12 18:17 UTC #5 lore raw

PATCH RESEND v7 4/5 dt-bindings: documentation: add clock bindings information for Agilex

In reply to Dinh Nguyen

Document the Agilex clock bindings, and add the clock header file. The clock header is an enumeration of all the different clocks on the Agilex platform.

Signed-off-by Dinh Nguyen <[email protected]>

Reviewed-by Rob Herring <[email protected]>

---
v7: Fix license to be "(GPL-2.0-only OR BSD-2-Clause)"
v6: fix build error by adding descriptions for clocks and reg in
properties
v5: update license to GPL-2.0-only
Add additionalProperties
Add clock input for clkmgr
v4: really fix build error(comment formatting was wrong)
v3: address comments from Stephen Boyd
fix build error(tab removed in line 37)
renamed to intel,agilex.yaml
v2: convert original document to YAML

---
 .../bindings/clock/intel,agilex.yaml          | 46 ++++++++++++
 include/dt-bindings/clock/agilex-clock.h      | 70 +++++++++++++++++++
 2 files changed, 116 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex.yaml
 create mode 100644 include/dt-bindings/clock/agilex-clock.h

Documentation/devicetree/bindings/clock/intel,agilex.yaml new file +46 -0

new file mode 100644
index 000000000000..cf5a9eb803e6
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/intel,agilex.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel SoCFPGA Agilex platform clock controller binding
+
+maintainers:
+  - Dinh Nguyen <[email protected]>
+
+description:
+  The Intel Agilex Clock controller is an integrated clock controller, which
+  generates and supplies to all modules.
+
+properties:
+  compatible:
+    const: intel,agilex-clkmgr
+
+  '#clock-cells':
+    const: 1
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  # Clock controller node:
+  - |
+    clkmgr: clock-controller@ffd10000 {
+      compatible = "intel,agilex-clkmgr";
+      reg = <0xffd10000 0x1000>;
+      clocks = <&osc1>;
+      #clock-cells = <1>;
+    };
+...

include/dt-bindings/clock/agilex-clock.h new file +70 -0

70 lines not on this page · raw message

Signature · 1 line

2.17.1

Stephen Boyd

maintainer Applied

2020-05-27 02:13 UTC #6 lore raw

Re: [RESEND PATCHv7 4/5] dt-bindings: documentation: add clock bindings information for Agilex

Quoting Dinh Nguyen (2020-05-12 11:16:46)

Quoted 7 lines

Document the Agilex clock bindings, and add the clock header file. The clock header is an enumeration of all the different clocks on the Agilex platform.
Signed-off-by Dinh Nguyen <[email protected]>
Reviewed-by Rob Herring <[email protected]>
---

Applied to clk-next

Dinh Nguyen

author maintainer

2020-05-12 18:17 UTC #7 lore raw

PATCH RESEND v7 5/5 clk: socfpga: agilex: add clock driver for the Agilex platform

In reply to Dinh Nguyen

For the most part the Agilex clock structure is very similar to Stratix10, so we re-use most of the Stratix10 clock driver.

Signed-off-by Dinh Nguyen <[email protected]>

---
v7: no changes
v6: no changes
v5: no changes
v4: no changes
v3: Address Stephen Boyd's comments
v2: update to use clk_parent_data

---
 drivers/clk/Makefile                |   3 +-
 drivers/clk/socfpga/Makefile        |   2 +
 drivers/clk/socfpga/clk-agilex.c    | 454 ++++++++++++++++++++++++++++
 drivers/clk/socfpga/clk-pll-s10.c   |  68 +++++
 drivers/clk/socfpga/stratix10-clk.h |   2 +
 5 files changed, 528 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/socfpga/clk-agilex.c

drivers/clk/Makefile +2 -1

index f4169cc2fd31..a178e4b6001f 100644
@@ -104,10 +104,11 @@ obj-$(CONFIG_COMMON_CLK_SAMSUNG)	+= samsung/
 obj-$(CONFIG_CLK_SIFIVE)		+= sifive/
 obj-$(CONFIG_ARCH_SIRF)			+= sirf/
 obj-$(CONFIG_ARCH_SOCFPGA)		+= socfpga/
+obj-$(CONFIG_ARCH_AGILEX)		+= socfpga/
+obj-$(CONFIG_ARCH_STRATIX10)		+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)		+= spear/
 obj-$(CONFIG_ARCH_SPRD)			+= sprd/
 obj-$(CONFIG_ARCH_STI)			+= st/
-obj-$(CONFIG_ARCH_STRATIX10)		+= socfpga/
 obj-$(CONFIG_ARCH_SUNXI)		+= sunxi/
 obj-$(CONFIG_SUNXI_CCU)			+= sunxi-ng/
 obj-$(CONFIG_ARCH_TEGRA)		+= tegra/

drivers/clk/socfpga/Makefile +2 -0

index ce5aa7802eb8..bf736f8d201a 100644
@@ -3,3 +3,5 @@ obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o clk-periph.o
 obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
 obj-$(CONFIG_ARCH_STRATIX10) += clk-s10.o
 obj-$(CONFIG_ARCH_STRATIX10) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o
+obj-$(CONFIG_ARCH_AGILEX) += clk-agilex.o
+obj-$(CONFIG_ARCH_AGILEX) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o

drivers/clk/socfpga/clk-agilex.c new file +454 -0

454 lines not on this page · raw message

drivers/clk/socfpga/clk-pll-s10.c +68 -0

91 lines not on this page · raw message

drivers/clk/socfpga/stratix10-clk.h +2 -0

index ffbd1fb2c8ef..f9d5d724c694 100644
@@ -62,6 +62,8 @@ struct stratix10_gate_clock {
 
 struct clk *s10_register_pll(const struct stratix10_pll_clock *,
 			     void __iomem *);
+struct clk *agilex_register_pll(const struct stratix10_pll_clock *,
+				void __iomem *);
 struct clk *s10_register_periph(const struct stratix10_perip_c_clock *,
 				void __iomem *);
 struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *,

Signature · 1 line

2.17.1

Stephen Boyd

maintainer Applied

2020-05-27 02:13 UTC #8 lore raw

Re: [RESEND PATCHv7 5/5] clk: socfpga: agilex: add clock driver for the Agilex platform

Quoting Dinh Nguyen (2020-05-12 11:16:47)

Quoted 5 lines

For the most part the Agilex clock structure is very similar to Stratix10, so we re-use most of the Stratix10 clock driver.
Signed-off-by Dinh Nguyen <[email protected]>
---

Applied to clk-next