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gpio: merrifield: Switch over to MSI interrupts

PATCH In review Andy Shevchenko 2 participants 7 messages Apr 8, 2020 – Apr 16, 2020

Subsystems (3)
GPIO Intel MID (Mobile Internet Device) platform Intel GPIO drivers
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Andy Shevchenko

author
#0 lore raw

PATCH v2 1/2 gpio: merrifield: Switch over to MSI interrupts

Some devices may support MSI interrupts. Let's at least try to use them in platforms that provide MSI capability.

Signed-off-by Andy Shevchenko <[email protected]>

---
v2: fix slipped compilation error

 drivers/gpio/gpio-merrifield.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)
drivers/gpio/gpio-merrifield.c +5 -1
index 48918a016cd8..11e6ea70568a 100644
@@ -473,6 +473,10 @@ static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id
 
 	raw_spin_lock_init(&priv->lock);
 
+	retval = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
+	if (retval < 0)
+		return retval;
+
 	girq = &priv->chip.irq;
 	girq->chip = &mrfld_irqchip;
 	girq->init_hw = mrfld_irq_init_hw;

@@ -482,7 +486,7 @@ static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id
 				     sizeof(*girq->parents), GFP_KERNEL);
 	if (!girq->parents)
 		return -ENOMEM;
-	girq->parents[0] = pdev->irq;
+	girq->parents[0] = pci_irq_vector(pdev, 0);
 	girq->first = irq_base;
 	girq->default_type = IRQ_TYPE_NONE;
 	girq->handler = handle_bad_irq;
Signature · 1 line
2.25.1
author
#1 lore raw

PATCH v2 2/2 gpio: merrifield: Better show how GPIO and IRQ bases are derived from hardware

It's a bit hard to realize what the BAR1 is for and what is the layout of the data in it. Be slightly more verbose to better show how GPIO and IRQ bases are derived from the hardware.

Signed-off-by Andy Shevchenko <[email protected]>

---
v2: no change

 drivers/gpio/gpio-merrifield.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/gpio/gpio-merrifield.c +2 -2
index 11e6ea70568a..706687fab634 100644
@@ -443,8 +443,8 @@ static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id
 
 	base = pcim_iomap_table(pdev)[1];
 
-	irq_base = readl(base);
-	gpio_base = readl(sizeof(u32) + base);
+	irq_base = readl(base + 0 * sizeof(u32));
+	gpio_base = readl(base + 1 * sizeof(u32));
 
 	/* Release the IO mapping, since we already get the info from BAR1 */
 	pcim_iounmap_regions(pdev, BIT(1));
Signature · 1 line
2.25.1
#2 lore raw

Re: [PATCH v2 2/2] gpio: merrifield: Better show how GPIO and IRQ bases are derived from hardware

Quoted 5 lines · Andy Shevchenko

It's a bit hard to realize what the BAR1 is for and what is the layout of the data in it. Be slightly more verbose to better show how GPIO and IRQ bases are derived from the hardware.

Signed-off-by Andy Shevchenko <[email protected]>

Patch applied.

Yours,
Linus Walleij

author
#4 lore raw
Quoted 9 lines · Linus Walleij
Quoted 4 lines · Andy Shevchenko

Some devices may support MSI interrupts. Let's at least try to use them in platforms that provide MSI capability.

Signed-off-by Andy Shevchenko <[email protected]>

Patch applied.

Can we return to established scheme when we send a PR to you? Or you think better not to do like that anymore?

Signature · 2 lines
With Best Regards,
Andy Shevchenko
#5 lore raw
Quoted 7 lines · Andy Shevchenko
Quoted 6 lines · Linus Walleij
Quoted 3 lines · Andy Shevchenko

Some devices may support MSI interrupts. Let's at least try to use them in platforms that provide MSI capability.

Quoted 6 lines
Quoted 3 lines
Quoted 1 line
Signed-off-by Andy Shevchenko <[email protected]>

Patch applied.

Can we return to established scheme when we send a PR to you? Or you think better not to do like that anymore?

No problem, I haven't pushed this out or anything, I will drop these.

Yours,
Linus Walleij

author
#6 lore raw
Quoted 9 lines · Linus Walleij
Quoted 7 lines · Andy Shevchenko
Quoted 6 lines · Linus Walleij
Quoted 3 lines · Andy Shevchenko

Some devices may support MSI interrupts. Let's at least try to use them in platforms that provide MSI capability.

Quoted 8 lines
Quoted 6 lines
Quoted 3 lines
Quoted 1 line
Signed-off-by Andy Shevchenko <[email protected]>

Patch applied.

Can we return to established scheme when we send a PR to you? Or you think better not to do like that anymore?

No problem, I haven't pushed this out or anything, I will drop these.

Thank you. Let's keep it the way we agreed before, i.e. PR for Intel GPIO drivers. For this cycle it seems PCH and Merrifield ones to the date.

Signature · 2 lines
With Best Regards,
Andy Shevchenko