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gpio: merrifield: Switch over to MSI interrupts

PATCH Superseded Andy Shevchenko 1 participant 3 messages Apr 8, 2020

Subsystems (3)
GPIO Intel MID (Mobile Internet Device) platform Intel GPIO drivers

v1 of 2 Superseded Latest is v2 →

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Andy Shevchenko

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#0 lore raw

PATCH 1/2 gpio: merrifield: Switch over to MSI interrupts

Some devices may support MSI interrupts. Let's at least try to use them in platforms that provide MSI capability.

Signed-off-by Andy Shevchenko <[email protected]>
---
 drivers/gpio/gpio-merrifield.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)
drivers/gpio/gpio-merrifield.c +5 -1
index 48918a016cd8..1f0cf909ea40 100644
@@ -473,6 +473,10 @@ static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id
 
 	raw_spin_lock_init(&priv->lock);
 
+	ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
+	if (ret < 0)
+		return ret;
+
 	girq = &priv->chip.irq;
 	girq->chip = &mrfld_irqchip;
 	girq->init_hw = mrfld_irq_init_hw;

@@ -482,7 +486,7 @@ static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id
 				     sizeof(*girq->parents), GFP_KERNEL);
 	if (!girq->parents)
 		return -ENOMEM;
-	girq->parents[0] = pdev->irq;
+	girq->parents[0] = pci_irq_vector(pdev, 0);
 	girq->first = irq_base;
 	girq->default_type = IRQ_TYPE_NONE;
 	girq->handler = handle_bad_irq;
Signature · 1 line
2.25.1
author
#1 lore raw

PATCH 2/2 gpio: merrifield: Better show how GPIO and IRQ bases are derived from hardware

It's a bit hard to realize what the BAR1 is for and what is the layout of the data in it. Be slightly more verbose to better show how GPIO and IRQ bases are derived from the hardware.

Signed-off-by Andy Shevchenko <[email protected]>
---
 drivers/gpio/gpio-merrifield.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/gpio/gpio-merrifield.c +2 -2
index 1f0cf909ea40..cdd782a186aa 100644
@@ -443,8 +443,8 @@ static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id
 
 	base = pcim_iomap_table(pdev)[1];
 
-	irq_base = readl(base);
-	gpio_base = readl(sizeof(u32) + base);
+	irq_base = readl(base + 0 * sizeof(u32));
+	gpio_base = readl(base + 1 * sizeof(u32));
 
 	/* Release the IO mapping, since we already get the info from BAR1 */
 	pcim_iounmap_regions(pdev, BIT(1));
Signature · 1 line
2.25.1
author
#2 lore raw
In reply to Andy Shevchenko
Quoted 2 lines · Andy Shevchenko

Some devices may support MSI interrupts. Let's at least try to use them in platforms that provide MSI capability.

This is wrong patch, please ignore.
I'll send v2 soon.

Signature · 2 lines
With Best Regards,
Andy Shevchenko