Add QMP V3 USB3 PHY support for SC7180
v5 cover Add QMP V3 USB3 PHY support for SC7180
Add QMP V3 USB3 PHY entries for SC7180 in phy driver and device tree bindings.
changes in v5:
*Addressed comments from Matthias in yaml file.
*Dropped PATCH 4/4 as it is landed in linux-next.
changes in v4:
*Addressed comments from Matthias and Rob in yaml file.
changes in v3:
*Addressed Rob's comments in yaml file.
*Sepearated the SC7180 support in yaml patch.
*corrected the phy reset entries in device tree.
changes in v2:
*Remove global phy reset in QMP PHY.
*Convert QMP PHY bindings to yaml.
Sandeep Maheswaram (3):
dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml
dt-bindings: phy: qcom,qmp: Add support for SC7180
phy: qcom-qmp: Add QMP V3 USB3 PHY support for SC7180
.../devicetree/bindings/phy/qcom,qmp-phy.yaml | 336 +++++++++++++++++++++ .../devicetree/bindings/phy/qcom-qmp-phy.txt | 242 --------------- drivers/phy/qualcomm/phy-qcom-qmp.c | 38 +++ 3 files changed, 374 insertions(+), 242 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml delete mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v5 1/3 dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml
Convert QMP PHY bindings to DT schema format using json-schema.
--- .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 332 +++++++++++++++++++++ .../devicetree/bindings/phy/qcom-qmp-phy.txt | 242 --------------- 2 files changed, 332 insertions(+), 242 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml delete mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml new file +332 -0
@@ -0,0 +1,332 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm QMP PHY controller + +maintainers: + - Manu Gautam <[email protected]> + +description: + QMP phy controller supports physical layer functionality for a number of + controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. + +properties: + compatible: + enum: + - qcom,ipq8074-qmp-pcie-phy + - qcom,msm8996-qmp-pcie-phy + - qcom,msm8996-qmp-ufs-phy + - qcom,msm8996-qmp-usb3-phy + - qcom,msm8998-qmp-pcie-phy + - qcom,msm8998-qmp-ufs-phy + - qcom,msm8998-qmp-usb3-phy + - qcom,sdm845-qhp-pcie-phy + - qcom,sdm845-qmp-pcie-phy + - qcom,sdm845-qmp-ufs-phy + - qcom,sdm845-qmp-usb3-phy + - qcom,sdm845-qmp-usb3-uni-phy + - qcom,sm8150-qmp-ufs-phy + + reg: + minItems: 1 + items: + - description: Address and length of PHY's common serdes block. + - description: Address and length of the DP_COM control block. + + reg-names: + items: + - const: reg-base + - const: dp_com + + "#clock-cells": + enum: [ 1, 2 ] + + "#address-cells": + enum: [ 1, 2 ] + + "#size-cells": + enum: [ 1, 2 ] + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + + resets: + minItems: 1 + maxItems: 3 + + reset-names: + minItems: 1 + maxItems: 3 + + vdda-phy-supply: + description: + Phandle to a regulator supply to PHY core block. + + vdda-pll-supply: + description: + Phandle to 1.8V regulator supply to PHY refclk pll block. + + vddp-ref-clk-supply: + description: + Phandle to a regulator supply to any specific refclk + pll block. + +#Required nodes: +patternProperties: + "^phy@[0-9a-f]+$": + type: object + description: + Each device node of QMP phy is required to have as many child nodes as + the number of lanes the PHY has. + +required: + - compatible + - reg + - "#clock-cells" + - "#address-cells" + - "#size-cells" + - clocks + - clock-names + - resets + - reset-names + - vdda-phy-supply + - vdda-pll-supply + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm845-qmp-usb3-phy + - qcom,sdm845-qmp-usb3-uni-phy + then: + properties: + clocks: + items: + - description: Phy aux clock. + - description: Phy config clock. + - description: 19.2 MHz ref clk. + - description: Phy common block aux clock. + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + - const: com_aux + resets: + items: + - description: reset of phy block. + - description: phy common block reset. + reset-names: + items: + - const: phy + - const: common + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8996-qmp-pcie-phy + then: + properties: + clocks: + items: + - description: Phy aux clock. + - description: Phy config clock. + - description: 19.2 MHz ref clk. + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + resets: + items: + - description: reset of phy block. + - description: phy common block reset. + - description: phy's ahb cfg block reset. + reset-names: + items: + - const: phy + - const: common + - const: cfg + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8996-qmp-usb3-phy + - qcom,msm8998-qmp-pcie-phy + - qcom,msm8998-qmp-usb3-phy + then: + properties: + clocks: + items: + - description: Phy aux clock. + - description: Phy config clock. + - description: 19.2 MHz ref clk. + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + resets: + items: + - description: reset of phy block. + - description: phy common block reset. + reset-names: + items: + - const: phy + - const: common + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8996-qmp-ufs-phy + then: + properties: + clocks: + items: + - description: 19.2 MHz ref clk. + clock-names: + items: + - const: ref + resets: + items: + - description: PHY reset in the UFS controller. + reset-names: + items: + - const: ufsphy + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8998-qmp-ufs-phy + - qcom,sdm845-qmp-ufs-phy + - qcom,sm8150-qmp-ufs-phy + then: + properties: + clocks: + items: + - description: 19.2 MHz ref clk. + - description: Phy reference aux clock. + clock-names: + items: + - const: ref + - const: ref_aux + resets: + items: + - description: PHY reset in the UFS controller. + reset-names: + items: + - const: ufsphy + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq8074-qmp-pcie-phy + then: + properties: + clocks: + items: + - description: pipe clk. + clock-names: + items: + - const: pipe_clk + resets: + items: + - description: reset of phy block. + - description: phy common block reset. + reset-names: + items: + - const: phy + - const: common + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm845-qhp-pcie-phy + - qcom,sdm845-qmp-pcie-phy + then: + properties: + clocks: + items: + - description: Phy aux clock. + - description: Phy config clock. + - description: 19.2 MHz ref clk. + - description: Phy refgen clk. + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + - const: refgen + resets: + items: + - description: reset of phy block. + reset-names: + items: + - const: phy + - if: + properties: + compatible: + contains: + const: qcom,sdm845-qmp-usb3-phy + then: + required: + - reg-names + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + usb_1_qmpphy: phy-wrapper@88e9000 { + compatible = "qcom,sdm845-qmp-usb3-phy"; + reg = <0 0x088e9000 0 0x18c>, + <0 0x088e8000 0 0x10>; + reg-names = "reg-base", "dp_com"; + #clock-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "com_aux"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + reset-names = "phy", "common"; + + vdda-phy-supply = <&vdda_usb2_ss_1p2>; + vdda-pll-supply = <&vdda_usb2_ss_core>; + + usb_1_ssphy: phy@88e9200 { + reg = <0 0x088e9200 0 0x128>, + <0 0x088e9400 0 0x200>, + <0 0x088e9c00 0 0x218>, + <0 0x088e9600 0 0x128>, + <0 0x088e9800 0 0x200>, + <0 0x088e9a00 0 0x100>; + #clock-cells = <0>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_phy_pipe_clk_src"; + }; + };
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt deleted +0 -242
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QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v5 1/3] dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml
Quoted 10 lines · Sandeep Maheswaram
Convert QMP PHY bindings to DT schema format using json-schema.
Signed-off-by Sandeep Maheswaram <[email protected]>--- .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 332 +++++++++++++++++++++ .../devicetree/bindings/phy/qcom-qmp-phy.txt | 242 --------------- 2 files changed, 332 insertions(+), 242 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml delete mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
Re: [PATCH v5 1/3] dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml
In reply to Sandeep MaheswaramQuoting Sandeep Maheswaram (2020-04-01 23:38:52)
Quoted 44 lines
Convert QMP PHY bindings to DT schema format using json-schema.
Signed-off-by Sandeep Maheswaram <[email protected]>--- .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 332 +++++++++++++++++++++ .../devicetree/bindings/phy/qcom-qmp-phy.txt | 242 --------------- 2 files changed, 332 insertions(+), 242 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml delete mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txtDocumentation/devicetree/bindings/phy/qcom,qmp-phy.yaml new file +28
-0@@ -0,0 +1,332 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm QMP PHY controller + +maintainers: + - Manu Gautam <[email protected]> + +description: + QMP phy controller supports physical layer functionality for a number of + controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. + +properties: + compatible: + enum: + - qcom,ipq8074-qmp-pcie-phy + - qcom,msm8996-qmp-pcie-phy + - qcom,msm8996-qmp-ufs-phy + - qcom,msm8996-qmp-usb3-phy + - qcom,msm8998-qmp-pcie-phy + - qcom,msm8998-qmp-ufs-phy + - qcom,msm8998-qmp-usb3-phy + - qcom,sdm845-qhp-pcie-phy + - qcom,sdm845-qmp-pcie-phy
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml line 38
Quoted 10 lines
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml new file +10
-0+ - qcom,sdm845-qmp-ufs-phy + - qcom,sdm845-qmp-usb3-phy + - qcom,sdm845-qmp-usb3-uni-phy + - qcom,sm8150-qmp-ufs-phy + + reg: + minItems: 1 + items: + - description: Address and length of PHY's common serdes block. + - description: Address and length of the DP_COM control block.
This DP_COM block is only for one compatible. Is it possible to split that compatible out of this binding so we can enforce the reg property being either one or two items?
In addition, I don't quite understand how this binding is supposed to work with the DP phy that sits inside qcom,sdm845-qmp-usb3-phy and then gets muxed out on the USB pins on sdm845 and sc7180 SoCs. Can you fill me in on how we plan to share the pins between the two phys so that all the combinations of DP and USB over the type-c pins will work here? My understanding is that the pins that are controlled by this hardware block are basically a full USB type-c connector pinout[1] (except that D+/D- isn't there and the VBUS and CC lines go to the PMIC). Either way, we get the TX1/2 and RX1/2 pins to use, so we can do 4x lanes of DP or 2x lanes DP and 2x lanes of USB. There's also a type-c orientation flipper bit that can flip the DP and USB phy lanes to the correct TX/RX pins on the SoC. And then the DP phy has a lane remapper to change the logical DP lane to the physical DP lane. It's a complex piece of hardware that isn't fully represented by this binding.
[1] https://en.wikipedia.org/wiki/USB-C#/media/File:USB_Type-C_Receptacle_Pinout.svg
Re: [PATCH v5 1/3] dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml
Hi Sandeep,
Quoted 75 lines · Stephen Boyd
Quoting Sandeep Maheswaram (2020-04-01 23:38:52)
Quoted 44 lines
Convert QMP PHY bindings to DT schema format using json-schema.
Signed-off-by Sandeep Maheswaram <[email protected]>--- .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 332 +++++++++++++++++++++ .../devicetree/bindings/phy/qcom-qmp-phy.txt | 242 --------------- 2 files changed, 332 insertions(+), 242 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml delete mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txtDocumentation/devicetree/bindings/phy/qcom,qmp-phy.yaml new file +28
-0@@ -0,0 +1,332 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm QMP PHY controller + +maintainers: + - Manu Gautam <[email protected]> + +description: + QMP phy controller supports physical layer functionality for a number of + controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. + +properties: + compatible: + enum: + - qcom,ipq8074-qmp-pcie-phy + - qcom,msm8996-qmp-pcie-phy + - qcom,msm8996-qmp-ufs-phy + - qcom,msm8996-qmp-usb3-phy + - qcom,msm8998-qmp-pcie-phy + - qcom,msm8998-qmp-ufs-phy + - qcom,msm8998-qmp-usb3-phy + - qcom,sdm845-qhp-pcie-phy + - qcom,sdm845-qmp-pcie-phyDocumentation/devicetree/bindings/phy/qcom,qmp-phy.yaml line 38
Quoted 10 lines
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml new file +10
-0+ - qcom,sdm845-qmp-ufs-phy + - qcom,sdm845-qmp-usb3-phy + - qcom,sdm845-qmp-usb3-uni-phy + - qcom,sm8150-qmp-ufs-phy + + reg: + minItems: 1 + items: + - description: Address and length of PHY's common serdes block. + - description: Address and length of the DP_COM control block.This
DP_COMblock is only for one compatible. Is it possible to split that compatible out of this binding so we can enforce the reg property being either one or two items?In addition, I don't quite understand how this binding is supposed to work with the DP phy that sits inside qcom,sdm845-qmp-usb3-phy and then gets muxed out on the USB pins on sdm845 and sc7180 SoCs. Can you fill me in on how we plan to share the pins between the two phys so that all the combinations of DP and USB over the type-c pins will work here? My understanding is that the pins that are controlled by this hardware block are basically a full USB type-c connector pinout[1] (except that D+/D- isn't there and the VBUS and CC lines go to the PMIC). Either way, we get the TX1/2 and RX1/2 pins to use, so we can do 4x lanes of DP or 2x lanes DP and 2x lanes of USB. There's also a type-c orientation flipper bit that can flip the DP and USB phy lanes to the correct TX/RX pins on the SoC. And then the DP phy has a lane remapper to change the logical DP lane to the physical DP lane. It's a complex piece of hardware that isn't fully represented by this binding.
Could you please answer Stephen's questions? It would be great to move forward and get support for SC7180 landed.
Re: [PATCH v5 1/3] dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml
Hi Sandeep,
Quoted 78 lines · Matthias Kaehlcke
Hi Sandeep,
Quoted 75 lines · Stephen Boyd
Quoting Sandeep Maheswaram (2020-04-01 23:38:52)
Quoted 44 lines
Convert QMP PHY bindings to DT schema format using json-schema.
Signed-off-by Sandeep Maheswaram <[email protected]>--- .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 332 +++++++++++++++++++++ .../devicetree/bindings/phy/qcom-qmp-phy.txt | 242 --------------- 2 files changed, 332 insertions(+), 242 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml delete mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txtDocumentation/devicetree/bindings/phy/qcom,qmp-phy.yaml new file +28
-0@@ -0,0 +1,332 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm QMP PHY controller + +maintainers: + - Manu Gautam <[email protected]> + +description: + QMP phy controller supports physical layer functionality for a number of + controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. + +properties: + compatible: + enum: + - qcom,ipq8074-qmp-pcie-phy + - qcom,msm8996-qmp-pcie-phy + - qcom,msm8996-qmp-ufs-phy + - qcom,msm8996-qmp-usb3-phy + - qcom,msm8998-qmp-pcie-phy + - qcom,msm8998-qmp-ufs-phy + - qcom,msm8998-qmp-usb3-phy + - qcom,sdm845-qhp-pcie-phy + - qcom,sdm845-qmp-pcie-phyDocumentation/devicetree/bindings/phy/qcom,qmp-phy.yaml line 38
Quoted 10 lines
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml new file +10
-0+ - qcom,sdm845-qmp-ufs-phy + - qcom,sdm845-qmp-usb3-phy + - qcom,sdm845-qmp-usb3-uni-phy + - qcom,sm8150-qmp-ufs-phy + + reg: + minItems: 1 + items: + - description: Address and length of PHY's common serdes block. + - description: Address and length of the DP_COM control block.This
DP_COMblock is only for one compatible. Is it possible to split that compatible out of this binding so we can enforce the reg property being either one or two items?In addition, I don't quite understand how this binding is supposed to work with the DP phy that sits inside qcom,sdm845-qmp-usb3-phy and then gets muxed out on the USB pins on sdm845 and sc7180 SoCs. Can you fill me in on how we plan to share the pins between the two phys so that all the combinations of DP and USB over the type-c pins will work here? My understanding is that the pins that are controlled by this hardware block are basically a full USB type-c connector pinout[1] (except that D+/D- isn't there and the VBUS and CC lines go to the PMIC). Either way, we get the TX1/2 and RX1/2 pins to use, so we can do 4x lanes of DP or 2x lanes DP and 2x lanes of USB. There's also a type-c orientation flipper bit that can flip the DP and USB phy lanes to the correct TX/RX pins on the SoC. And then the DP phy has a lane remapper to change the logical DP lane to the physical DP lane. It's a complex piece of hardware that isn't fully represented by this binding.
Quoted 4 lines
Could you please answer Stephen's questions? It would be great to move forward and get support for SC7180 landed.
You posted v6, which does the split Stephen asked for, but you didn't answer his question about the pin sharing. Since this is an existing binding there is probably no reason to block it from landing, but it would still be good to clarify this.
Thanks
Matthias
PATCH v5 2/3 dt-bindings: phy: qcom,qmp: Add support for SC7180
In reply to Sandeep MaheswaramAdd compatible for SC7180 in QMP PHY bindings.
--- Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +5 -1
@@ -24,6 +24,7 @@ properties: - qcom,msm8998-qmp-pcie-phy - qcom,msm8998-qmp-ufs-phy - qcom,msm8998-qmp-usb3-phy + - qcom,sc7180-qmp-usb3-phy - qcom,sdm845-qhp-pcie-phy - qcom,sdm845-qmp-pcie-phy - qcom,sdm845-qmp-ufs-phy
@@ -109,6 +110,7 @@ allOf: compatible: contains: enum: + - qcom,sc7180-qmp-usb3-phy - qcom,sdm845-qmp-usb3-phy - qcom,sdm845-qmp-usb3-uni-phy then:
@@ -286,7 +288,9 @@ allOf: properties: compatible: contains: - const: qcom,sdm845-qmp-usb3-phy + enum: + - qcom,sc7180-qmp-usb3-phy + - qcom,sdm845-qmp-usb3-phy then: required: - reg-names
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v5 2/3] dt-bindings: phy: qcom,qmp: Add support for SC7180
Quoting Sandeep Maheswaram (2020-04-01 23:38:53)
Quoted 6 lines
Add compatible for SC7180 in QMP PHY bindings.
Signed-off-by Sandeep Maheswaram <[email protected]>Reviewed-by Matthias Kaehlcke <[email protected]>Reviewed-by Rob Herring <[email protected]>---
PATCH v5 3/3 phy: qcom-qmp: Add QMP V3 USB3 PHY support for SC7180
In reply to Sandeep MaheswaramAdding QMP v3 USB3 PHY support for SC7180.
Adding only usb phy reset in the list to avoid
reset of DP block.
--- drivers/phy/qualcomm/phy-qcom-qmp.c | 38 +++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+)
drivers/phy/qualcomm/phy-qcom-qmp.c +38 -0
@@ -1458,6 +1458,10 @@ static const char * const msm8996_usb3phy_reset_l[] = { "phy", "common", }; +static const char *const sc7180_usb3phy_reset_l[] = { +"phy" , +}; +static const char *const sdm845_pciephy_reset_l[] = {"phy" , };
@@ -1671,6 +1675,37 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { .is_dual_lane_phy = true, }; +static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { + .type =PHY_TYPE_USB3 , + .nlanes =1 , + + .serdes_tbl = qmp_v3_usb3_serdes_tbl, + .serdes_tbl_num =ARRAY_SIZE (qmp_v3_usb3_serdes_tbl), + .tx_tbl = qmp_v3_usb3_tx_tbl, + .tx_tbl_num =ARRAY_SIZE (qmp_v3_usb3_tx_tbl), + .rx_tbl = qmp_v3_usb3_rx_tbl, + .rx_tbl_num =ARRAY_SIZE (qmp_v3_usb3_rx_tbl), + .pcs_tbl = qmp_v3_usb3_pcs_tbl, + .pcs_tbl_num =ARRAY_SIZE (qmp_v3_usb3_pcs_tbl), + .clk_list = qmp_v3_phy_clk_l, + .num_clks =ARRAY_SIZE (qmp_v3_phy_clk_l), + .reset_list = sc7180_usb3phy_reset_l, + .num_resets =ARRAY_SIZE (sc7180_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs =ARRAY_SIZE (qmp_phy_vreg_l), + .regs = qmp_v3_usb3phy_regs_layout, + + .start_ctrl =SERDES_START |PCS_START , + .pwrdn_ctrl =SW_PWRDN , + + .has_pwrdn_delay = true, + .pwrdn_delay_min =POWER_DOWN_DELAY_US_MIN , + .pwrdn_delay_max =POWER_DOWN_DELAY_US_MAX , + + .has_phy_dp_com_ctrl = true, + .is_dual_lane_phy = true, +}; +static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { .type =PHY_TYPE_USB3 , .nlanes =1 ,
@@ -2516,6 +2551,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { .compatible = "qcom,ipq8074-qmp-pcie-phy", .data = &ipq8074_pciephy_cfg, }, { + .compatible = "qcom,sc7180-qmp-usb3-phy", + .data = &sc7180_usb3phy_cfg, + }, { .compatible = "qcom,sdm845-qhp-pcie-phy", .data = &sdm845_qhp_pciephy_cfg, }, {
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v5 3/3] phy: qcom-qmp: Add QMP V3 USB3 PHY support for SC7180
Quoting Sandeep Maheswaram (2020-04-01 23:38:54)
Quoted 7 lines
Adding QMP v3 USB3 PHY support for SC7180. Adding only usb phy reset in the list to avoid reset of DP block.
Signed-off-by Sandeep Maheswaram <[email protected]>Reviewed-by Matthias Kaehlcke <[email protected]>---