Multiple fixes in PCIe qcom driver

Set some specific value for Tx De-Emphasis, Tx Swing and Rx equalization needed on some ipq8064 based device (Netgear R7800 for example). Without this the system locks on kernel load.

Fixes 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")

Signed-off-by Ansuel Smith <[email protected]>

Cc [email protected] # v4.5+

Reviewed-by Rob Herring <[email protected]>

---
 drivers/pci/controller/dwc/pcie-qcom.c | 27 ++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

drivers/pci/controller/dwc/pcie-qcom.c +0 -0

index f2ea1ab6f584..f5398b0d270c 100644

drivers/pci/controller/dwc/pcie-qcom.c +14 -0

+
 #define PCIE20_PARF_DBI_BASE_ADDR		0x168
 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE		0x16C
 #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL	0x174

@@ -77,6 +80,18 @@
 #define DBI_RO_WR_EN				1
 
 #define PERST_DELAY_US				1000
+/* PARF registers */
+#define PCIE20_PARF_PCS_DEEMPH			0x34
+#define PCS_DEEMPH_TX_DEEMPH_GEN1(x)		((x) << 16)
+#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x)	((x) << 8)
+#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x)	((x) << 0)
+
+#define PCIE20_PARF_PCS_SWING			0x38
+#define PCS_SWING_TX_SWING_FULL(x)		((x) << 8)
+#define PCS_SWING_TX_SWING_LOW(x)		((x) << 0)
+
+#define PCIE20_PARF_CONFIG_BITS		0x50
+#define PHY_RX0_EQ(x)				((x) << 24)
 
 #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE	0x358
 #define SLV_ADDR_SPACE_SZ			0x10000000

@@ -293,6 +308,7 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
 	struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
 	struct dw_pcie *pci = pcie->pci;
 	struct device *dev = pci->dev;
+	struct device_node *node = dev->of_node;
 	u32 val;
 	int ret;
 

@@ -347,6 +363,17 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
 	val &= ~BIT(0);

drivers/pci/controller/dwc/pcie-qcom.c +3 -0

+		writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
+	}
+
 	/* enable external reference clock */
 	val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
 	val |= BIT(16);

From: Sham Muthayyan <[email protected]>

Add Force GEN1 support needed in some ipq8064 board that needs to limit some PCIe line to gen1 for some hardware limitation. This is set by the max-link-speed binding and needed by some soc based on ipq8064. (for example Netgear R7800 router)

Signed-off-by Sham Muthayyan <[email protected]>

Signed-off-by Ansuel Smith <[email protected]>

Reviewed-by Rob Herring <[email protected]>

---
 drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

drivers/pci/controller/dwc/pcie-qcom.c +4 -0

index 259b627bf890..0ce15d53c46e 100644
@@ -27,6 +27,7 @@
 #include <linux/slab.h>
 #include <linux/types.h>
 
+#include "../../pci.h"
 #include "pcie-designware.h"
 
 #define PCIE20_PARF_SYS_CTRL			0x00

@@ -99,6 +100,8 @@
 #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE	0x358
 #define SLV_ADDR_SPACE_SZ			0x10000000
 
+#define PCIE20_LNK_CONTROL2_LINK_STATUS2	0xa0
+
 #define DEVICE_TYPE_RC				0x4
 
 #define QCOM_PCIE_2_1_0_MAX_SUPPLY	3

@@ -195,6 +198,7 @@ struct qcom_pcie {
 	struct phy *phy;
 	struct gpio_desc *reset;
 	const struct qcom_pcie_ops *ops;
+	int gen;
 };
 
 #define to_qcom_pcie(x)		dev_get_drvdata((x)->dev)

drivers/pci/controller/dwc/pcie-qcom.c +6 -0

+		writel(val, pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
+	}
 
 	/* Set the Max TLP size to 2K, instead of using default of 4K */
 	writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,

@@ -1397,6 +1406,10 @@ static int qcom_pcie_probe(struct platform_device *pdev)
 		goto err_pm_runtime_put;
 	}
 
+	pcie->gen = of_pci_get_max_link_speed(pdev->dev.of_node);
+	if (pcie->gen < 0)
+		pcie->gen = 2;
+
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
 	pcie->parf = devm_ioremap_resource(dev, res);
 	if (IS_ERR(pcie->parf)) {

Signature · 1 line

2.25.1

Quoted 3 lines

From: Sham Muthayyan <[email protected]>

Add Force GEN1 support needed in some ipq8064 board that needs to

limit

Quoted 4 lines

some PCIe line to gen1 for some hardware limitation. This is set by the max-link-speed binding and needed by some soc based on ipq8064. (for example Netgear R7800 router)

Review

Quoted 8 lines

Signed-off-by Sham Muthayyan <[email protected]>

Signed-off-by Ansuel Smith <[email protected]>

Reviewed-by Rob Herring <[email protected]>

---
 drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

(quoted diff) +0 -0

b/drivers/pci/controller/dwc/pcie-qcom.c

drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_init_2_1_0(struct

Quoted 29 lines

index 259b627bf890..0ce15d53c46e 100644

drivers/pci/controller/dwc/pcie-qcom.c +4 -0

@@ -27,6 +27,7 @@
 #include <linux/slab.h>
 #include <linux/types.h>
 
+#include "../../pci.h"
 #include "pcie-designware.h"
 
 #define PCIE20_PARF_SYS_CTRL			0x00

@@ -99,6 +100,8 @@
 #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE	0x358
 #define SLV_ADDR_SPACE_SZ			0x10000000
 
+#define PCIE20_LNK_CONTROL2_LINK_STATUS2	0xa0
+
 #define DEVICE_TYPE_RC				0x4
 
 #define QCOM_PCIE_2_1_0_MAX_SUPPLY	3

@@ -195,6 +198,7 @@ struct qcom_pcie {
 	struct phy *phy;
 	struct gpio_desc *reset;
 	const struct qcom_pcie_ops *ops;
+	int gen;
 };
 
 #define to_qcom_pcie(x)		dev_get_drvdata((x)->dev)

@@ -395,6 +399,11 @@ static int qcom_pcie_init_2_1_0(struct

qcom_pcie *pcie)

drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)

Quoted 5 lines

drivers/pci/controller/dwc/pcie-qcom.c +2 -0

 	/* wait for clock acquisition */
 	usleep_range(1000, 1500);
 
+	if (pcie->gen == 1) {
+		val = readl(pci->dbi_base +

PCIE20_LNK_CONTROL2_LINK_STATUS2);

drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) · line 404

Quoted 1 line

drivers/pci/controller/dwc/pcie-qcom.c +1 -0

+		val |= 1;

Is this the same bit that's visible in config space as PCI_EXP_LNKSTA_CLS_2_5GB? Why not use that #define?

There are a bunch of other #defines in this file that look like redefinitions of standard things:

  #define PCIE20_COMMAND_STATUS                   0x04
    Looks like PCI_COMMAND

  #define CMD_BME_VAL                             0x4
    Looks like PCI_COMMAND_MASTER

  #define PCIE20_DEVICE_CONTROL2_STATUS2          0x98
    Looks like (PCIE20_CAP + PCI_EXP_DEVCTL2)

  #define PCIE_CAP_CPL_TIMEOUT_DISABLE            0x10
    Looks like PCI_EXP_DEVCTL2_COMP_TMOUT_DIS

  #define PCIE20_CAP                              0x70
    This one is obviously device-specific

  #define PCIE20_CAP_LINK_CAPABILITIES            (PCIE20_CAP + 0xC)
    Looks like (PCIE20_CAP + PCI_EXP_LNKCAP)

#define PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT (BIT(10) |
BIT(11))
Looks like PCI_EXP_LNKCAP_ASPMS

#define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14)
#define PCIE_CAP_LINK1_VAL 0x2FD7F
This looks like PCIE20_CAP_LINK_1 should be (PCIE20_CAP + PCI_EXP_SLTCAP), but "CAP_LINK_1" doesn't sound like the Slot Capabilities register, and I don't know what PCIE_CAP_LINK1_VAL means.

drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_init_2_1_0(struct · line 405

Quoted 1 line

drivers/pci/controller/dwc/pcie-qcom.c +1 -0

+		writel(val, pci->dbi_base +

PCIE20_LNK_CONTROL2_LINK_STATUS2);

drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_probe(struct

Quoted 5 lines

drivers/pci/controller/dwc/pcie-qcom.c +1 -0

+	}
 
 	/* Set the Max TLP size to 2K, instead of using default of 4K */
 	writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,

@@ -1397,6 +1406,10 @@ static int qcom_pcie_probe(struct

platform_device *pdev)

drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_probe(struct platform_device *pdev)

Quoted 8 lines

drivers/pci/controller/dwc/pcie-qcom.c +4 -0

 		goto err_pm_runtime_put;
 	}
 
+	pcie->gen = of_pci_get_max_link_speed(pdev->dev.of_node);
+	if (pcie->gen < 0)
+		pcie->gen = 2;
+
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,

"parf");

Quoted 5 lines

drivers/pci/controller/dwc/pcie-qcom.c +0 -1

 	pcie->parf = devm_ioremap_resource(dev, res);
 	if (IS_ERR(pcie->parf)) {
--

2.25.1

Quoted 84 lines · Ansuel Smith

Quoted 3 lines

From: Sham Muthayyan <[email protected]>

Add Force GEN1 support needed in some ipq8064 board that needs to

limit

Quoted 4 lines

some PCIe line to gen1 for some hardware limitation. This is set by the max-link-speed binding and needed by some soc based on ipq8064. (for example Netgear R7800 router)

Review

Quoted 8 lines

Signed-off-by Sham Muthayyan <[email protected]>

Signed-off-by Ansuel Smith <[email protected]>

Reviewed-by Rob Herring <[email protected]>

---
 drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

(quoted diff) +0 -0

b/drivers/pci/controller/dwc/pcie-qcom.c

drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_init_2_1_0(struct

Quoted 29 lines

index 259b627bf890..0ce15d53c46e 100644

drivers/pci/controller/dwc/pcie-qcom.c +4 -0

@@ -27,6 +27,7 @@
 #include <linux/slab.h>
 #include <linux/types.h>
 
+#include "../../pci.h"
 #include "pcie-designware.h"
 
 #define PCIE20_PARF_SYS_CTRL			0x00

@@ -99,6 +100,8 @@
 #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE	0x358
 #define SLV_ADDR_SPACE_SZ			0x10000000
 
+#define PCIE20_LNK_CONTROL2_LINK_STATUS2	0xa0
+
 #define DEVICE_TYPE_RC				0x4
 
 #define QCOM_PCIE_2_1_0_MAX_SUPPLY	3

@@ -195,6 +198,7 @@ struct qcom_pcie {
 	struct phy *phy;
 	struct gpio_desc *reset;
 	const struct qcom_pcie_ops *ops;
+	int gen;
 };
 
 #define to_qcom_pcie(x)		dev_get_drvdata((x)->dev)

@@ -395,6 +399,11 @@ static int qcom_pcie_init_2_1_0(struct

qcom_pcie *pcie)

drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)

Quoted 5 lines

drivers/pci/controller/dwc/pcie-qcom.c +2 -0

 	/* wait for clock acquisition */
 	usleep_range(1000, 1500);
 
+	if (pcie->gen == 1) {
+		val = readl(pci->dbi_base +

PCIE20_LNK_CONTROL2_LINK_STATUS2);

drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) · line 404

Quoted 1 line

drivers/pci/controller/dwc/pcie-qcom.c +1 -0

+		val |= 1;

Is this the same bit that's visible in config space as PCI_EXP_LNKSTA_CLS_2_5GB? Why not use that #define?

There are a bunch of other #defines in this file that look like redefinitions of standard things:

  #define PCIE20_COMMAND_STATUS                   0x04
    Looks like PCI_COMMAND

  #define CMD_BME_VAL                             0x4
    Looks like PCI_COMMAND_MASTER

  #define PCIE20_DEVICE_CONTROL2_STATUS2          0x98
    Looks like (PCIE20_CAP + PCI_EXP_DEVCTL2)

  #define PCIE_CAP_CPL_TIMEOUT_DISABLE            0x10
    Looks like PCI_EXP_DEVCTL2_COMP_TMOUT_DIS

  #define PCIE20_CAP                              0x70
    This one is obviously device-specific

  #define PCIE20_CAP_LINK_CAPABILITIES            (PCIE20_CAP + 0xC)
    Looks like (PCIE20_CAP + PCI_EXP_LNKCAP)

#define PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT (BIT(10) |
BIT(11))
Looks like PCI_EXP_LNKCAP_ASPMS

Quoted 6 lines

#define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14)
#define PCIE_CAP_LINK1_VAL 0x2FD7F
This looks like PCIE20_CAP_LINK_1 should be (PCIE20_CAP + PCI_EXP_SLTCAP), but "CAP_LINK_1" doesn't sound like the Slot Capabilities register, and I don't know what PCIE_CAP_LINK1_VAL means.

The define are used by ipq8074 and I really can't test the changes. Anyway it shouldn't make a difference use the define instead of the custom value so a patch should not harm anything... Problem is the last 2 define that we really don't know what they are about... How should I proceed? Change only the value related to PCI_EXP_LNKSTA_CLS_2_5GB or change all the other except the last 2?

Quoted 22 lines

drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_init_2_1_0(struct · line 405

Quoted 1 line

drivers/pci/controller/dwc/pcie-qcom.c +1 -0

+		writel(val, pci->dbi_base +

PCIE20_LNK_CONTROL2_LINK_STATUS2);

drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_probe(struct

Quoted 5 lines

drivers/pci/controller/dwc/pcie-qcom.c +1 -0

+	}
 
 	/* Set the Max TLP size to 2K, instead of using default of 4K */
 	writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,

@@ -1397,6 +1406,10 @@ static int qcom_pcie_probe(struct

platform_device *pdev)

drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_probe(struct platform_device *pdev)

Quoted 8 lines

drivers/pci/controller/dwc/pcie-qcom.c +4 -0

 		goto err_pm_runtime_put;
 	}
 
+	pcie->gen = of_pci_get_max_link_speed(pdev->dev.of_node);
+	if (pcie->gen < 0)
+		pcie->gen = 2;
+
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,

"parf");

Quoted 5 lines

drivers/pci/controller/dwc/pcie-qcom.c +0 -1

 	pcie->parf = devm_ioremap_resource(dev, res);
 	if (IS_ERR(pcie->parf)) {
--

2.25.1

-----Messaggio originale-----
Da: Bjorn Helgaas <[email protected]>
Inviato: martedì 2 giugno 2020 19:28
A: [email protected]
Cc: 'Rob Herring' <[email protected]>; 'Sham Muthayyan' <[email protected]>; 'Rob Herring' <[email protected]>; 'Andy Gross' <[email protected]>; 'Bjorn Andersson' <[email protected]>; 'Bjorn Helgaas' <[email protected]>; 'Mark Rutland' <[email protected]>; 'Stanimir Varbanov' <[email protected]>; 'Lorenzo Pieralisi' <[email protected]>; 'Andrew Murray' <[email protected]>; 'Philipp Zabel' <[email protected]>; [email protected]; linux- [email protected]; [email protected]; linux- [email protected]; Varadarajan Narayanan <[email protected]>
Oggetto: Re: R: [PATCH v5 11/11] PCI: qcom: Add Force GEN1 support

[+cc Varada]

Quoted 6 lines · On Tue, Jun 02, 2020 at 07:07:27PM +0200, [email protected] wrote:

Quoted 6 lines · Ansuel Smith

Quoted 3 lines

From: Sham Muthayyan <[email protected]>

Add Force GEN1 support needed in some ipq8064 board that needs to

limit

Quoted 1 line

some PCIe line to gen1 for some hardware limitation. This is set by

Quoted 1 line

Quoted 1 line

Quoted 1 line

max-link-speed binding and needed by some soc based on ipq8064.

(for

Quoted 84 lines

Quoted 77 lines

Review

Quoted 10 lines

example Netgear R7800 router)

Signed-off-by Sham Muthayyan <[email protected]>

Signed-off-by Ansuel Smith <[email protected]>

Reviewed-by Rob Herring <[email protected]>

---
 drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

(quoted diff) +0 -0

b/drivers/pci/controller/dwc/pcie-qcom.c

drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_init_2_1_0(struct

Quoted 29 lines

index 259b627bf890..0ce15d53c46e 100644

drivers/pci/controller/dwc/pcie-qcom.c +4 -0

@@ -27,6 +27,7 @@
 #include <linux/slab.h>
 #include <linux/types.h>
 
+#include "../../pci.h"
 #include "pcie-designware.h"
 
 #define PCIE20_PARF_SYS_CTRL			0x00

@@ -99,6 +100,8 @@
 #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE	0x358
 #define SLV_ADDR_SPACE_SZ			0x10000000
 
+#define PCIE20_LNK_CONTROL2_LINK_STATUS2	0xa0
+
 #define DEVICE_TYPE_RC				0x4
 
 #define QCOM_PCIE_2_1_0_MAX_SUPPLY	3

@@ -195,6 +198,7 @@ struct qcom_pcie {
 	struct phy *phy;
 	struct gpio_desc *reset;
 	const struct qcom_pcie_ops *ops;
+	int gen;
 };
 
 #define to_qcom_pcie(x)		dev_get_drvdata((x)->dev)

@@ -395,6 +399,11 @@ static int qcom_pcie_init_2_1_0(struct

qcom_pcie *pcie)

drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)

Quoted 5 lines

drivers/pci/controller/dwc/pcie-qcom.c +2 -0

 	/* wait for clock acquisition */
 	usleep_range(1000, 1500);
 
+	if (pcie->gen == 1) {
+		val = readl(pci->dbi_base +

PCIE20_LNK_CONTROL2_LINK_STATUS2);

drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) · line 404

Quoted 1 line

drivers/pci/controller/dwc/pcie-qcom.c +1 -0

+		val |= 1;

Is this the same bit that's visible in config space as PCI_EXP_LNKSTA_CLS_2_5GB? Why not use that #define?

There are a bunch of other #defines in this file that look like redefinitions of standard things:

  #define PCIE20_COMMAND_STATUS                   0x04
    Looks like PCI_COMMAND

  #define CMD_BME_VAL                             0x4
    Looks like PCI_COMMAND_MASTER

  #define PCIE20_DEVICE_CONTROL2_STATUS2          0x98
    Looks like (PCIE20_CAP + PCI_EXP_DEVCTL2)

  #define PCIE_CAP_CPL_TIMEOUT_DISABLE            0x10
    Looks like PCI_EXP_DEVCTL2_COMP_TMOUT_DIS

  #define PCIE20_CAP                              0x70
    This one is obviously device-specific

  #define PCIE20_CAP_LINK_CAPABILITIES            (PCIE20_CAP + 0xC)
    Looks like (PCIE20_CAP + PCI_EXP_LNKCAP)

#define PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT (BIT(10) |
BIT(11))
Looks like PCI_EXP_LNKCAP_ASPMS

Quoted 6 lines

#define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14)
#define PCIE_CAP_LINK1_VAL 0x2FD7F
This looks like PCIE20_CAP_LINK_1 should be (PCIE20_CAP + PCI_EXP_SLTCAP), but "CAP_LINK_1" doesn't sound like the Slot Capabilities register, and I don't know what PCIE_CAP_LINK1_VAL means.

Quoted 6 lines

The define are used by ipq8074 and I really can't test the changes. Anyway it shouldn't make a difference use the define instead of the custom value so a patch should not harm anything... Problem is the last 2 define that we really don't know what they are about... How should I proceed? Change only the value related to PCI_EXP_LNKSTA_CLS_2_5GB or change all the other except the last 2?

I personally would change all the ones I mentioned above (in a separate patch from the one that adds "max-link-speed" support). Testing isn't a big deal because changing the #defines shouldn't change the generated code at all.

PCIE20_CAP_LINK_1 / PCIE_CAP_LINK1_VAL looks like a potential bug or at least a very misleading name. I wouldn't touch it unless we can figure out what's going on.

Looks like most of this was added by 5d76117f070d ("PCI: qcom: Add support for IPQ8074 PCIe controller"). Shame on me for not asking these questions at the time.

Sham, Varada, can you shed any light on PCIE20_CAP_LINK_1 and PCIE_CAP_LINK1_VAL?

Quoted 5 lines

Quoted 5 lines

drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_init_2_1_0(struct · line 405

Quoted 1 line

drivers/pci/controller/dwc/pcie-qcom.c +1 -0

+		writel(val, pci->dbi_base +

PCIE20_LNK_CONTROL2_LINK_STATUS2);

drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)

Quoted 3 lines

drivers/pci/controller/dwc/pcie-qcom.c +1 -0

+	}
 
 	/* Set the Max TLP size to 2K, instead of using default of

Quoted 18 lines

Quoted 17 lines

drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_probe(struct

Quoted 2 lines

drivers/pci/controller/dwc/pcie-qcom.c +0 -0

 	writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,

@@ -1397,6 +1406,10 @@ static int qcom_pcie_probe(struct

platform_device *pdev)

drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_probe(struct platform_device *pdev)

Quoted 8 lines

drivers/pci/controller/dwc/pcie-qcom.c +4 -0

 		goto err_pm_runtime_put;
 	}
 
+	pcie->gen = of_pci_get_max_link_speed(pdev->dev.of_node);
+	if (pcie->gen < 0)
+		pcie->gen = 2;
+
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,

"parf");

Quoted 5 lines

drivers/pci/controller/dwc/pcie-qcom.c +0 -1

 	pcie->parf = devm_ioremap_resource(dev, res);
 	if (IS_ERR(pcie->parf)) {
--

2.25.1

Quoted 17 lines

-----Messaggio originale-----
Da: Bjorn Helgaas <[email protected]>
Inviato: martedì 2 giugno 2020 19:28
A: [email protected]
Cc: 'Rob Herring' <[email protected]>; 'Sham Muthayyan' <[email protected]>; 'Rob Herring' <[email protected]>; 'Andy Gross' <[email protected]>; 'Bjorn Andersson' <[email protected]>; 'Bjorn Helgaas' <[email protected]>; 'Mark Rutland' <[email protected]>; 'Stanimir Varbanov' <[email protected]>; 'Lorenzo Pieralisi' <[email protected]>; 'Andrew Murray' <[email protected]>; 'Philipp Zabel' <[email protected]>; [email protected]; linux- [email protected]; [email protected]; linux- [email protected]; Varadarajan Narayanan <[email protected]>
Oggetto: Re: R: [PATCH v5 11/11] PCI: qcom: Add Force GEN1 support

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[+cc Varada]

Quoted 6 lines · On Tue, Jun 02, 2020 at 07:07:27PM +0200, [email protected] wrote:

Quoted 6 lines · Ansuel Smith

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From: Sham Muthayyan <[email protected]>

Add Force GEN1 support needed in some ipq8064 board that needs to

limit

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some PCIe line to gen1 for some hardware limitation. This is set by

the

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max-link-speed binding and needed by some soc based on ipq8064.

(for

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Review

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example Netgear R7800 router)

Signed-off-by Sham Muthayyan <[email protected]>

Signed-off-by Ansuel Smith <[email protected]>

Reviewed-by Rob Herring <[email protected]>

---
 drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

(quoted diff) +0 -0

b/drivers/pci/controller/dwc/pcie-qcom.c

drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_init_2_1_0(struct

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index 259b627bf890..0ce15d53c46e 100644

drivers/pci/controller/dwc/pcie-qcom.c +4 -0

@@ -27,6 +27,7 @@
 #include <linux/slab.h>
 #include <linux/types.h>
 
+#include "../../pci.h"
 #include "pcie-designware.h"
 
 #define PCIE20_PARF_SYS_CTRL			0x00

@@ -99,6 +100,8 @@
 #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE	0x358
 #define SLV_ADDR_SPACE_SZ			0x10000000
 
+#define PCIE20_LNK_CONTROL2_LINK_STATUS2	0xa0
+
 #define DEVICE_TYPE_RC				0x4
 
 #define QCOM_PCIE_2_1_0_MAX_SUPPLY	3

@@ -195,6 +198,7 @@ struct qcom_pcie {
 	struct phy *phy;
 	struct gpio_desc *reset;
 	const struct qcom_pcie_ops *ops;
+	int gen;
 };
 
 #define to_qcom_pcie(x)		dev_get_drvdata((x)->dev)

@@ -395,6 +399,11 @@ static int qcom_pcie_init_2_1_0(struct

qcom_pcie *pcie)

drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)

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drivers/pci/controller/dwc/pcie-qcom.c +2 -0

 	/* wait for clock acquisition */
 	usleep_range(1000, 1500);
 
+	if (pcie->gen == 1) {
+		val = readl(pci->dbi_base +

PCIE20_LNK_CONTROL2_LINK_STATUS2);

drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) · line 404

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drivers/pci/controller/dwc/pcie-qcom.c +1 -0

+		val |= 1;

Is this the same bit that's visible in config space as PCI_EXP_LNKSTA_CLS_2_5GB? Why not use that #define?

There are a bunch of other #defines in this file that look like redefinitions of standard things:

  #define PCIE20_COMMAND_STATUS                   0x04
    Looks like PCI_COMMAND

  #define CMD_BME_VAL                             0x4
    Looks like PCI_COMMAND_MASTER

  #define PCIE20_DEVICE_CONTROL2_STATUS2          0x98
    Looks like (PCIE20_CAP + PCI_EXP_DEVCTL2)

  #define PCIE_CAP_CPL_TIMEOUT_DISABLE            0x10
    Looks like PCI_EXP_DEVCTL2_COMP_TMOUT_DIS

  #define PCIE20_CAP                              0x70
    This one is obviously device-specific

  #define PCIE20_CAP_LINK_CAPABILITIES            (PCIE20_CAP + 0xC)
    Looks like (PCIE20_CAP + PCI_EXP_LNKCAP)

#define PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT (BIT(10) |
BIT(11))
Looks like PCI_EXP_LNKCAP_ASPMS

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#define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14)
#define PCIE_CAP_LINK1_VAL 0x2FD7F
This looks like PCIE20_CAP_LINK_1 should be (PCIE20_CAP + PCI_EXP_SLTCAP), but "CAP_LINK_1" doesn't sound like the Slot Capabilities register, and I don't know what PCIE_CAP_LINK1_VAL means.

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The define are used by ipq8074 and I really can't test the changes. Anyway it shouldn't make a difference use the define instead of the custom value so a patch should not harm anything... Problem is the last 2 define that we really don't know what they are about... How should I proceed? Change only the value related to PCI_EXP_LNKSTA_CLS_2_5GB or change all the other except the last 2?

I personally would change all the ones I mentioned above (in a separate patch from the one that adds "max-link-speed" support). Testing isn't a big deal because changing the #defines shouldn't change the generated code at all.

PCIE20_CAP_LINK_1 / PCIE_CAP_LINK1_VAL looks like a potential bug or at least a very misleading name. I wouldn't touch it unless we can figure out what's going on.

Looks like most of this was added by 5d76117f070d ("PCI: qcom: Add support for IPQ8074 PCIe controller"). Shame on me for not asking these questions at the time.

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Sham, Varada, can you shed any light on PCIE20_CAP_LINK_1 and PCIE_CAP_LINK1_VAL?

Still no response. Should I push a v6 with this fix and leave the unknown params as they are?