Add Actions Semi Owl family sirq support

This patch series adds support for the external interrupt controller (SIRQ) found in the Actions Semi Owl family of SoC's (S500, S700 and S900). The controller handles up to 3 external interrupt lines through dedicated SIRQ pins.

This is a rework of the patch series submitted some time ago by Parthiban Nallathambi:
https://lore.kernel.org/lkml/[email protected]/

Please note I have dropped, for the moment, the S700 related patches since I do not own a compatible hardware for testing. I'm using instead an S500 SoC based board for which I have already provided the initial support:
https://lore.kernel.org/lkml/[email protected]/

Additionally, I have taken the authorship for the driver patch, considering the original code has been already modified to a great extent and I'm firmly committed to maintaining it in the long run.

The SIRQ controller support is a prerequisite of the upcoming MFD driver for the Actions Semi ATC260x PMICs.

Thanks and regards,
Cristi

Changes in v7:
- Added Co-developed-by tags to the driver patch according to Marc's review

Changes in v6:
- Integrated binding doc related feedback from Rob and Marc
- Updated cover letter to handle the authorship issue indicated by Mani
- Rebased patch series on v5.9-rc4

Changes in v5:
- Integrated Marc's review (more details in the driver patch changelog)
- Rebased patch series on v5.9-rc1

Changes in v4:
- Simplified the DTS structure:
* dropped 'actions,sirq-shared-reg' node, now the differentiation between SoC variants is handled via the compatible property
* dropped 'actions,sirq-reg-offset', now controller base address in DTS points to SIRQ0 register, so no additional information is required for S500 and S700, while for S900 SoC the offsets of SIRQ1 and SIRQ2 regs are provided by the driver
* 'actions,ext-irq-range' was replaced with 'actions,ext-interrupts', an array of the GIC interrupts triggered by the controller
- Fixed wrong INTC_EXTCTL_TYPE_MASK definition
- Removed redundant irq_fwspec checks in owl_sirq_domain_alloc()
- Improved error handling in owl_sirq_of_init()
- Added yaml binding document
- Dropped S700 related DTS patches for lack of testing hardware:
* arm64: dts: actions: Add sirq node for Actions Semi S700
* arm64: dts: actions: s700-cubieboard7: Enable SIRQ
- Updated MAINTAINERS
- Rebased patchset on kernel v5.8
- Cosmetic changes
* Ordered include statements alphabetically
* Added comment to owl_sirq_set_type() describing conversion of falling edge or active low signals
* Replaced IRQF_TRIGGER_* with corresponding IRQ_TYPE_* variants
* Ensured data types and function naming are consistent regarding the 'owl_sirq' prefix

Changes in v3 (Parthiban Nallathambi):
- Set default operating frequency to 24MHz
- Falling edge and Low Level interrupts translated to rising edge and high level
- Introduced common function with lock handling for register read and write
- Used direct GIC interrupt number for interrupt local hwirq and finding offset using DT entry (range) when registers are shared
- Changed irq_ack to irq_eoi
- Added translation method for irq_domain_ops
- Clearing interrupt pending based on bitmask for edge triggered
- Added pinctrl definition for sirq for cubieboard7. This depends on,
https://lore.kernel.org/patchwork/patch/1012859/

Changes in v2 (Parthiban Nallathambi):
- Added SIRQ as hierarchical chip

        GIC <----> SIRQ <----> External interrupt controller/Child devices

- Device binding updates with vendor prefix
- Register sharing handled globally and common init sequence/data for all actions SoC family

Cristian Ciocaltea (3):
dt-bindings: interrupt-controller: Add Actions SIRQ controller binding
irqchip: Add Actions Semi Owl SIRQ controller
MAINTAINERS: Add entries for Actions Semi Owl SIRQ controller

 .../actions,owl-sirq.yaml                     |  65 ++++
 MAINTAINERS                                   |   2 +
 drivers/irqchip/Makefile                      |   1 +
 drivers/irqchip/irq-owl-sirq.c                | 359 ++++++++++++++++++
 4 files changed, 427 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml
 create mode 100644 drivers/irqchip/irq-owl-sirq.c

2.28.0

Actions Semi Owl SoCs SIRQ interrupt controller is found in S500, S700 and S900 SoCs and provides support for handling up to 3 external interrupt lines.

---
Changes in v7:
- None

Changes in v6:
- Got rid of the 'actions,owl-sirq' compatible, per Robs's feedback
- Replaced 'actions,ext-interrupts' with 'interrupts', as agreed with Rob and Marc

Changes in v5:
- Updated controller description statements both in the commit message and the binding doc

 .../actions,owl-sirq.yaml                     | 65 +++++++++++++++++++
 1 file changed, 65 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml

new file mode 100644
index 000000000000..5da333c644c9
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/actions,owl-sirq.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Actions Semi Owl SoCs SIRQ interrupt controller
+
+maintainers:
+  - Manivannan Sadhasivam <[email protected]>
+  - Cristian Ciocaltea <[email protected]>
+
+description: |
+  This interrupt controller is found in the Actions Semi Owl SoCs (S500, S700
+  and S900) and provides support for handling up to 3 external interrupt lines.
+
+properties:
+  compatible:
+    enum:
+      - actions,s500-sirq
+      - actions,s700-sirq
+      - actions,s900-sirq
+
+  reg:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    const: 2
+    description:
+      The first cell is the input IRQ number, between 0 and 2, while the second
+      cell is the trigger type as defined in interrupt.txt in this directory.
+
+  'interrupts':
+    description: |
+      Contains the GIC SPI IRQs mapped to the external interrupt lines.
+      They shall be specified sequentially from output 0 to 2.
+    minItems: 3
+    maxItems: 3
+
+required:
+  - compatible
+  - reg
+  - interrupt-controller
+  - '#interrupt-cells'
+  - 'interrupts'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    sirq: interrupt-controller@b01b0200 {
+      compatible = "actions,s500-sirq";
+      reg = <0xb01b0200 0x4>;
+      interrupt-controller;
+      #interrupt-cells = <2>;
+      interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ0 */
+                   <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ1 */
+                   <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; /* SIRQ2 */
+    };
+
+...

2.28.0

Thanks,
Cristi

This interrupt controller is found in the Actions Semi Owl SoCs (S500, S700 and S900) and provides support for handling up to 3 external interrupt lines.

Each line can be independently configured as interrupt and triggers on either of the edges or either of the levels. Additionally, each line can also be masked individually.

---
Changes in v7 - commit message update:
- Added the missing Co-developed-by tags, as indicated by Marc
- Removed the obsolete statements regarding the base work

Changes in v6:
- Got rid of the of_match table and used IRQCHIP_DECLARE for each of the 3 driver compatibles
- Transformed owl_sirq_of_init() into a helper function: renamed to owl_sirq_of_init(), dropped handling of the custom property 'actions,ext-interrupts' and used standard API for parsing the replacement 'interrupts'
- Used GIC_SPI constant instead of the related number
- Minor changes in the commit message

Changes in v5 - according to Marc's review:
- Updated commit message
- Aligned members in struct owl_sirq_chip_data
- Added naming for SIRQ0 control register offset
- Improved code readability by using FIELD_PREP and FIELD_GET
- Dropped redundant handling of the IRQ trigger information
- Added missing irq_set_affinity to owl_sirq_chip descriptor

 drivers/irqchip/Makefile       |   1 +
 drivers/irqchip/irq-owl-sirq.c | 359 +++++++++++++++++++++++++++++++++
 2 files changed, 360 insertions(+)
 create mode 100644 drivers/irqchip/irq-owl-sirq.c

index 133f9c45744a..b8eb5b8b766d 100644
@@ -7,6 +7,7 @@ obj-$(CONFIG_ATH79)			+= irq-ath79-cpu.o
 obj-$(CONFIG_ATH79)			+= irq-ath79-misc.o
 obj-$(CONFIG_ARCH_BCM2835)		+= irq-bcm2835.o
 obj-$(CONFIG_ARCH_BCM2835)		+= irq-bcm2836.o
+obj-$(CONFIG_ARCH_ACTIONS)		+= irq-owl-sirq.o
 obj-$(CONFIG_DAVINCI_AINTC)		+= irq-davinci-aintc.o
 obj-$(CONFIG_DAVINCI_CP_INTC)		+= irq-davinci-cp-intc.o
 obj-$(CONFIG_EXYNOS_IRQ_COMBINER)	+= exynos-combiner.o

2.28.0

Add entries for Actions Semi Owl SIRQ controller binding and driver.

---
 MAINTAINERS | 2 ++
 1 file changed, 2 insertions(+)

index 9544eec4eff2..04c75815fac6 100644
@@ -1525,6 +1525,7 @@ F:	Documentation/devicetree/bindings/arm/actions.yaml
 F:	Documentation/devicetree/bindings/clock/actions,owl-cmu.txt
 F:	Documentation/devicetree/bindings/dma/owl-dma.txt
 F:	Documentation/devicetree/bindings/i2c/i2c-owl.txt
+F:	Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml
 F:	Documentation/devicetree/bindings/mmc/owl-mmc.yaml
 F:	Documentation/devicetree/bindings/pinctrl/actions,*
 F:	Documentation/devicetree/bindings/power/actions,owl-sps.txt

@@ -1536,6 +1537,7 @@ F:	drivers/clk/actions/
 F:	drivers/clocksource/timer-owl*
 F:	drivers/dma/owl-dma.c
 F:	drivers/i2c/busses/i2c-owl.c
+F:	drivers/irqchip/irq-owl-sirq.c
 F:	drivers/mmc/host/owl-mmc.c
 F:	drivers/pinctrl/actions/*
 F:	drivers/soc/actions/

2.28.0

Applied to irq/irqchip-next, thanks!

[1/3] dt-bindings: interrupt-controller: Add Actions SIRQ controller binding

      commit: b2bd271c3961f35dd127c99c8f576d9fcc2cb0c4
[2/3] irqchip: Add Actions Semi Owl SIRQ controller
      commit: 27e9e554b01fea686929598556cb7f73a70fb964
[3/3] MAINTAINERS: Add entries for Actions Semi Owl SIRQ controller
      commit: aa524294ffb621cb51dbc0a0ccdb2929c0ca2bc1

Cheers,

	M.

Without deviation from the norm, progress is not possible.