arm64: dbm: Invalidate local TLB when setting TCR_EL1.HD
Will Deacon
maintainerPATCH 1/1 arm64: dbm: Invalidate local TLB when setting TCR_EL1.HD
TCR_EL1.HD is permitted to be cached in a TLB, so invalidate the local TLB after setting the bit when detected support for the feature. Although this isn't strictly necessary, since we can happily operate with the bit effectively clear, the current code uses an ISB in a half-hearted attempt to make the change effective, so let's just fix that up.
--- arch/arm64/kernel/cpufeature.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm64/kernel/cpufeature.c +1 -1
@@ -1442,7 +1442,7 @@ static inline void __cpu_enable_hw_dbm(void)u64 tcr =read_sysreg (tcr_el1) |TCR_HD ;write_sysreg (tcr, tcr_el1); -isb (); +local_flush_tlb_all (); }static bool cpu_has_broken_dbm (void )
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Catalin Marinas
maintainerQuoted 17 lines · Will Deacon
TCR_EL1.HD is permitted to be cached in a TLB, so invalidate the local TLB after setting the bit when detected support for the feature. Although this isn't strictly necessary, since we can happily operate with the bit effectively clear, the current code uses an ISB in a half-hearted attempt to make the change effective, so let's just fix that up.
Cc Catalin Marinas <[email protected]>Signed-off-by Will Deacon <[email protected]>--- arch/arm64/kernel/cpufeature.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)arch/arm64/kernel/cpufeature.c +0
-0
arch/arm64/kernel/cpufeature.c static inline void __cpu_enable_hw_dbm(void) · line 1445
Quoted 5 lines
arch/arm64/kernel/cpufeature.c +1
-1@@ -1442,7 +1442,7 @@ static inline void __cpu_enable_hw_dbm(void)u64 tcr =read_sysreg (tcr_el1) |TCR_HD ;write_sysreg (tcr, tcr_el1); -isb (); +local_flush_tlb_all ();
Is the TLBI ordered with the TCR_EL1 write or we need the ISB as well?
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Catalin _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Will Deacon
maintainerQuoted 20 lines · Catalin Marinas
Quoted 19 lines · Will Deacon
TCR_EL1.HD is permitted to be cached in a TLB, so invalidate the local TLB after setting the bit when detected support for the feature. Although this isn't strictly necessary, since we can happily operate with the bit effectively clear, the current code uses an ISB in a half-hearted attempt to make the change effective, so let's just fix that up.
Cc Catalin Marinas <[email protected]>Signed-off-by Will Deacon <[email protected]>--- arch/arm64/kernel/cpufeature.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)arch/arm64/kernel/cpufeature.c +0
-0@@ -1442,7 +1442,7 @@ static inline void __cpu_enable_hw_dbm(void)u64 tcr =read_sysreg (tcr_el1) |TCR_HD ;
Quoted 5 lines
arch/arm64/kernel/cpufeature.c static inline void __cpu_enable_hw_dbm(void) · line 1445
Quoted 3 lines
arch/arm64/kernel/cpufeature.c +1
-1write_sysreg (tcr, tcr_el1); -isb (); +local_flush_tlb_all ();Is the TLBI ordered with the
TCR_EL1write or we need the ISB as well?
Good catch! I think this is direct-write -> indirect-read ordering, which needs the ISB. so I'll keep it and add the flush immediately afterwards.
Will
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Mark Rutland
reviewerQuoted 20 lines · Catalin Marinas
Quoted 19 lines · Will Deacon
TCR_EL1.HD is permitted to be cached in a TLB, so invalidate the local TLB after setting the bit when detected support for the feature. Although this isn't strictly necessary, since we can happily operate with the bit effectively clear, the current code uses an ISB in a half-hearted attempt to make the change effective, so let's just fix that up.
Cc Catalin Marinas <[email protected]>Signed-off-by Will Deacon <[email protected]>--- arch/arm64/kernel/cpufeature.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)arch/arm64/kernel/cpufeature.c +0
-0@@ -1442,7 +1442,7 @@ static inline void __cpu_enable_hw_dbm(void)u64 tcr =read_sysreg (tcr_el1) |TCR_HD ;
Quoted 5 lines
arch/arm64/kernel/cpufeature.c static inline void __cpu_enable_hw_dbm(void) · line 1445
Quoted 3 lines
arch/arm64/kernel/cpufeature.c +1
-1write_sysreg (tcr, tcr_el1); -isb (); +local_flush_tlb_all ();Is the TLBI ordered with the
TCR_EL1write or we need the ISB as well?
I believe we still need the ISB prior to the TLBI since MSR and TLBI are not usually ordered w.r.t. one another, so after teh TLBI it might still be possible to allcote the stale value into TLBs.
Mark.
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