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mtd: rawnand: ifc: Move the ECC engine initialization to the right place

PATCH Superseded Fabio Estevam 1 participant 1 message Oct 16, 2020

Subsystems (2)
Memory technology devices (MTD) NAND flash

v1 of 3 Superseded Latest is v3 →

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Fabio Estevam

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PATCH 1/1 mtd: rawnand: ifc: Move the ECC engine initialization to the right place

No ECC initialization should happen during the host controller probe.

Indeed, we need the probe to call nand_scan() in order to:
- identify the device, its capabilities and constraints (nand_scan_ident())
- configure the ECC engine accordingly (->attach_chip())
- scan its content and prepare the core (nand_scan_tail())

Moving these lines to fsl_ifc_attach_chip() fixes a regression caused by a previous commit supposed to clarify these steps.

Based on a fix done at the mxc_nand driver by Miquel Raynal.

Reported-by Han Xu <[email protected]>
Signed-off-by Fabio Estevam <[email protected]>

---
Hi Han Xu,

Does this fix the ECC regression on Layerscape?

Hi Miquel,

If Han can confirm this fixes the problem, then I will audit the other drivers and submit the fixes too.

 drivers/mtd/nand/raw/fsl_ifc_nand.c | 44 ++++++++++++++++-------------
 1 file changed, 24 insertions(+), 20 deletions(-)
drivers/mtd/nand/raw/fsl_ifc_nand.c +24 -20
index 0e7a9b64301e..113048a1c423 100644
@@ -707,6 +707,30 @@ static int fsl_ifc_attach_chip(struct nand_chip *chip)
 {
 	struct mtd_info *mtd = nand_to_mtd(chip);
 	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
+	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
+	struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
+	u32 csor;
+
+	csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);
+
+	/* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
+	if (csor & CSOR_NAND_ECC_DEC_EN) {
+		chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
+		mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
+
+		/* Hardware generates ECC per 512 Bytes */
+		chip->ecc.size = 512;
+		if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) {
+			chip->ecc.bytes = 8;
+			chip->ecc.strength = 4;
+		} else {
+			chip->ecc.bytes = 16;
+			chip->ecc.strength = 8;
+		}
+	} else {
+		chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
+		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
+	}
 
 	dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
 		nanddev_ntargets(&chip->base));

@@ -742,7 +766,6 @@ static int fsl_ifc_attach_chip(struct nand_chip *chip)
 							mtd->writesize);
 	dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__,
 							mtd->oobsize);
-
 	return 0;
 }
 

@@ -910,25 +933,6 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
 		return -ENODEV;
 	}
 
-	/* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
-	if (csor & CSOR_NAND_ECC_DEC_EN) {
-		chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
-		mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
-
-		/* Hardware generates ECC per 512 Bytes */
-		chip->ecc.size = 512;
-		if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) {
-			chip->ecc.bytes = 8;
-			chip->ecc.strength = 4;
-		} else {
-			chip->ecc.bytes = 16;
-			chip->ecc.strength = 8;
-		}
-	} else {
-		chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
-		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
-	}
-
 	ret = fsl_ifc_sram_init(priv);
 	if (ret)
 		return ret;
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2.17.1


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