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mtd: rawnand: mxc: Move the ECC engine initialization to the right place

PATCH Superseded Fabio Estevam 1 participant 1 message Oct 16, 2020

Subsystems (3)
Arm i.MX and Layerscape Memory technology devices (MTD) NAND flash

v2 of 3 Superseded Latest is v3 →

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Fabio Estevam

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PATCH v2 1/1 mtd: rawnand: mxc: Move the ECC engine initialization to the right place

No ECC initialization should happen during the host controller probe.

In fact, we need the probe function to call nand_scan() in order to:
- identify the device, its capabilities and constraints (nand_scan_ident())
- configure the ECC engine accordingly (->attach_chip())
- scan its content and prepare the core (nand_scan_tail())

Moving these lines to mxcnd_attach_chip() fixes a regression caused by a previous commit supposed to clarify these steps.

When moving the ECC initialization from probe() to attach(), it is no longer possible to access pdata since it is not initialized.

Retrieve the "nand-ecc-mode" information from devicetree to decide the engine type.

Reported-by Fabio Estevam <[email protected]>
Co-developed-by Miquel Raynal <[email protected]>
Signed-off-by Miquel Raynal <[email protected]>
Signed-off-by Fabio Estevam <[email protected]>

---
Change since v1:

- Do not access pdata in attach(), since it is not initialized.

 drivers/mtd/nand/raw/mxc_nand.c | 27 +++++++++++++++------------
 1 file changed, 15 insertions(+), 12 deletions(-)
drivers/mtd/nand/raw/mxc_nand.c +15 -12
index d4200eb2ad32..b9e4de5ec8f8 100644
@@ -1680,6 +1680,21 @@ static int mxcnd_attach_chip(struct nand_chip *chip)
 	struct mtd_info *mtd = nand_to_mtd(chip);
 	struct mxc_nand_host *host = nand_get_controller_data(chip);
 	struct device *dev = mtd->dev.parent;
+	struct device_node *np = dev->of_node;
+	const char *ecc_mode;
+
+	chip->ecc.bytes = host->devtype_data->eccbytes;
+	host->eccsize = host->devtype_data->eccsize;
+	chip->ecc.size = 512;
+	mtd_set_ooblayout(mtd, host->devtype_data->ooblayout);
+
+	of_property_read_string(np, "nand-ecc-mode", &ecc_mode);
+	if (!strcasecmp(ecc_mode, "hw")) {
+		chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
+	} else {
+		chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
+		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
+	}
 
 	switch (chip->ecc.engine_type) {
 	case NAND_ECC_ENGINE_TYPE_ON_HOST:

@@ -1836,19 +1851,7 @@ static int mxcnd_probe(struct platform_device *pdev)
 	if (host->devtype_data->axi_offset)
 		host->regs_axi = host->base + host->devtype_data->axi_offset;
 
-	this->ecc.bytes = host->devtype_data->eccbytes;
-	host->eccsize = host->devtype_data->eccsize;
-
 	this->legacy.select_chip = host->devtype_data->select_chip;
-	this->ecc.size = 512;
-	mtd_set_ooblayout(mtd, host->devtype_data->ooblayout);
-
-	if (host->pdata.hw_ecc) {
-		this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
-	} else {
-		this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
-		this->ecc.algo = NAND_ECC_ALGO_HAMMING;
-	}
 
 	/* NAND bus width determines access functions used by upper layer */
 	if (host->pdata.width == 2)
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2.17.1


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