crypto: qat - rework firmware loader in preparation for qat_4xxx

PATCH In review Jack Xu 2 participants 34 messages Nov 6, 2020 – Nov 13, 2020 Crypto API

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Jack Xu

author

2020-11-06 11:28 UTC #0 lore raw

cover crypto: qat - rework firmware loader in preparation for qat_4xxx

Rework firmware loader in QAT driver in preparation for the support of the qat_4xxx driver.

Patch #1 add support for the mof format in the firmware loader
Patches from #2 to #7 introduce some general fixes
Patches from #8 to #30 rework and refactor the firmware loader to support the new features added by the next generation of QAT devices (QAT GEN4) Patch #31 introduces the firmware loader changes to support QAT GEN4 devices

Giovanni Cabiddu (1):
crypto: qat - support for mof format in fw loader

Jack Xu (31):
crypto: qat - loader: fix status check in qat_hal_put_rel_rd_xfer()
crypto: qat - loader: fix CSR access
crypto: qat - loader: fix error message
crypto: qat - loader: remove unnecessary parenthesis
crypto: qat - loader: introduce additional parenthesis
crypto: qat - loader: rename qat_uclo_del_uof_obj()
crypto: qat - loader: add support for relative FW ucode loading
crypto: qat - loader: change type for ctx_mask
crypto: qat - loader: change micro word data mask
crypto: qat - loader: refactor AE start
crypto: qat - loader: remove global CSRs helpers
crypto: qat - loader: move defines to header files
crypto: qat - loader: refactor qat_uclo_set_ae_mode()
crypto: qat - loader: refactor long expressions
crypto: qat - loader: introduce chip info structure
crypto: qat - loader: replace check based on DID
crypto: qat - loader: add next neighbor to chip_info
crypto: qat - loader: add support for lm2 and lm3
crypto: qat - loader: add local memory size to chip info
crypto: qat - loader: add reset CSR and mask to chip info
crypto: qat - loader: add clock enable CSR to chip info
crypto: qat - loader: add wake up event to chip info
crypto: qat - loader: add misc control CSR to chip info
crypto: qat - loader: add check for null pointer
crypto: qat - loader: use ae_mask
crypto: qat - loader: add CSS3K support
crypto: qat - loader: add FCU CSRs to chip info
crypto: qat - loader: allow to target specific AEs
crypto: qat - loader: add support for shared ustore
crypto: qat - loader: add support for broadcasting mode
crypto: qat - loader: add gen4 firmware loader

 .../crypto/qat/qat_common/adf_accel_devices.h |   2 +
 .../crypto/qat/qat_common/adf_accel_engine.c  |  13 +-
 .../crypto/qat/qat_common/adf_common_drv.h    |  19 +-
 .../qat/qat_common/icp_qat_fw_loader_handle.h |  26 +-
 drivers/crypto/qat/qat_common/icp_qat_hal.h   |  63 +-
 drivers/crypto/qat/qat_common/icp_qat_uclo.h  | 132 +++-
 drivers/crypto/qat/qat_common/qat_hal.c       | 400 +++++++---
 drivers/crypto/qat/qat_common/qat_uclo.c      | 737 ++++++++++++++----
 8 files changed, 1097 insertions(+), 295 deletions(-)

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:28 UTC #1 lore raw

PATCH 1/32 crypto: qat - support for mof format in fw loader

From: Giovanni Cabiddu <[email protected]>

Implement infrastructure for the Multiple Object File (MOF) format in the firmware loader. This will allow to load a specific firmware image contained inside an MOF file.

This patch is based on earlier work done by Pingchao Yang.

Signed-off-by Giovanni Cabiddu <[email protected]>

Reviewed-by Jack Xu <[email protected]>

---
 .../crypto/qat/qat_common/adf_accel_engine.c  |   2 +-
 .../crypto/qat/qat_common/adf_common_drv.h    |   2 +-
 .../qat/qat_common/icp_qat_fw_loader_handle.h |   1 +
 drivers/crypto/qat/qat_common/icp_qat_uclo.h  |  69 +++++
 drivers/crypto/qat/qat_common/qat_uclo.c      | 262 +++++++++++++++++-
 5 files changed, 331 insertions(+), 5 deletions(-)

drivers/crypto/qat/qat_common/adf_accel_engine.c +1 -1

index c8ad85b882be..1da4176356ab 100644
@@ -38,7 +38,7 @@ int adf_ae_fw_load(struct adf_accel_dev *accel_dev)
 		dev_err(&GET_DEV(accel_dev), "Failed to load MMP\n");
 		goto out_err;
 	}
-	if (qat_uclo_map_obj(loader_data->fw_loader, uof_addr, uof_size)) {
+	if (qat_uclo_map_obj(loader_data->fw_loader, uof_addr, uof_size, NULL)) {
 		dev_err(&GET_DEV(accel_dev), "Failed to map FW\n");
 		goto out_err;
 	}

drivers/crypto/qat/qat_common/adf_common_drv.h +1 -1

index f22342f612c1..8e6e346fd841 100644
@@ -184,7 +184,7 @@ void qat_uclo_del_uof_obj(struct icp_qat_fw_loader_handle *handle);
 int qat_uclo_wr_mimage(struct icp_qat_fw_loader_handle *handle, void *addr_ptr,
 		       int mem_size);
 int qat_uclo_map_obj(struct icp_qat_fw_loader_handle *handle,
-		     void *addr_ptr, int mem_size);
+		     void *addr_ptr, u32 mem_size, char *obj_name);
 #if defined(CONFIG_PCI_IOV)
 int adf_sriov_configure(struct pci_dev *pdev, int numvfs);
 void adf_disable_sriov(struct adf_accel_dev *accel_dev);

drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h +1 -0

index 3e8e291cd122..7d44786a223a 100644
@@ -27,6 +27,7 @@ struct icp_qat_fw_loader_handle {
 	struct pci_dev *pci_dev;
 	void *obj_handle;
 	void *sobj_handle;
+	void *mobj_handle;
 	bool fw_auth;
 	void __iomem *hal_sram_addr_v;
 	void __iomem *hal_cap_g_ctl_csr_addr_v;

drivers/crypto/qat/qat_common/icp_qat_uclo.h +69 -0

79 lines not on this page · raw message

drivers/crypto/qat/qat_common/qat_uclo.c +259 -3

283 lines not on this page · raw message

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:28 UTC #2 lore raw

PATCH 2/32 crypto: qat - loader: fix status check in qat_hal_put_rel_rd_xfer()

In reply to Jack Xu

The return value of qat_hal_rd_ae_csr() is always a CSR value and never a status and should not be stored in the status variable of qat_hal_put_rel_rd_xfer().

This removes the assignment as qat_hal_rd_ae_csr() is not expected to fail.
A more comprehensive handling of the theoretical corner case which could result in a fail will be submitted in a separate patch.

Fixes 8c9478a400b7 ("crypto: qat - reduce stack size with KASAN")

Signed-off-by Jack Xu <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

Reviewed-by Fiona Trahe <[email protected]>

---
 drivers/crypto/qat/qat_common/qat_hal.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/crypto/qat/qat_common/qat_hal.c +1 -1

index bc07199459e7..5da8475ed876 100644
@@ -1149,7 +1149,7 @@ static int qat_hal_put_rel_rd_xfer(struct icp_qat_fw_loader_handle *handle,
 	unsigned short mask;
 	unsigned short dr_offset = 0x10;
 
-	status = ctx_enables = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);
+	ctx_enables = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);
 	if (CE_INUSE_CONTEXTS & ctx_enables) {
 		if (ctx & 0x1) {
 			pr_err("QAT: bad 4-ctx mode,ctx=0x%x\n", ctx);

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:28 UTC #3 lore raw

PATCH 3/32 crypto: qat - loader: fix CSR access

In reply to Jack Xu

Do not mask the AE number with the AE mask when accessing the AE local CSRs. Bit 12 of the local CSR address is the start of AE number so just take out the AE mask here.

Signed-off-by Jack Xu <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 drivers/crypto/qat/qat_common/icp_qat_hal.h | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

drivers/crypto/qat/qat_common/icp_qat_hal.h +2 -4

index c0e9fc0c93dd..b48b313623fe 100644
@@ -94,15 +94,13 @@ enum fcu_sts {
 #define SET_GLB_CSR(handle, csr, val) SET_CAP_CSR(handle, csr + GLOBAL_CSR, val)
 #define GET_GLB_CSR(handle, csr) GET_CAP_CSR(handle, GLOBAL_CSR + csr)
 #define AE_CSR(handle, ae) \
-	((char __iomem *)handle->hal_cap_ae_local_csr_addr_v + \
-	((ae & handle->hal_handle->ae_mask) << 12))
+	((char __iomem *)handle->hal_cap_ae_local_csr_addr_v + (ae << 12))
 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & csr))
 #define SET_AE_CSR(handle, ae, csr, val) \
 	ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)
 #define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0)
 #define AE_XFER(handle, ae) \
-	((char __iomem *)handle->hal_cap_ae_xfer_csr_addr_v + \
-	((ae & handle->hal_handle->ae_mask) << 12))
+	((char __iomem *)handle->hal_cap_ae_xfer_csr_addr_v + (ae << 12))
 #define AE_XFER_ADDR(handle, ae, reg) (AE_XFER(handle, ae) + \
 	((reg & 0xff) << 2))
 #define SET_AE_XFER(handle, ae, reg, val) \

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:28 UTC #4 lore raw

PATCH 4/32 crypto: qat - loader: fix error message

In reply to Jack Xu

Change message in error path of qat_uclo_check_image_compat() to report an incompatible firmware image that contains a neighbor register table.

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 drivers/crypto/qat/qat_common/qat_uclo.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/crypto/qat/qat_common/qat_uclo.c +1 -1

index b475f6bfb90b..063af33c6ca6 100644
@@ -536,7 +536,7 @@ qat_uclo_check_image_compat(struct icp_qat_uof_encap_obj *encap_uof_obj,
 			(encap_uof_obj->beg_uof +
 			code_page->neigh_reg_tab_offset);
 	if (neigh_reg_tab->entry_num) {
-		pr_err("QAT: UOF can't contain shared control store feature\n");
+		pr_err("QAT: UOF can't contain neighbor register table\n");
 		return -EINVAL;
 	}
 	if (image->numpages > 1) {

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:28 UTC #5 lore raw

PATCH 5/32 crypto: qat - loader: remove unnecessary parenthesis

In reply to Jack Xu

Remove unnecessary parenthesis across the firmware loader.

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 drivers/crypto/qat/qat_common/qat_hal.c  |  6 +++---
 drivers/crypto/qat/qat_common/qat_uclo.c | 16 ++++++++--------
 2 files changed, 11 insertions(+), 11 deletions(-)

drivers/crypto/qat/qat_common/qat_hal.c +3 -3

index 5da8475ed876..bbfb2b1b6fee 100644
@@ -158,7 +158,7 @@ int qat_hal_set_ae_ctx_mode(struct icp_qat_fw_loader_handle *handle,
 {
 	unsigned int csr, new_csr;
 
-	if ((mode != 4) && (mode != 8)) {
+	if (mode != 4 && mode != 8) {
 		pr_err("QAT: bad ctx mode=%d\n", mode);
 		return -EINVAL;
 	}

@@ -430,7 +430,7 @@ static int qat_hal_init_esram(struct icp_qat_fw_loader_handle *handle)
 		qat_hal_wait_cycles(handle, 0, ESRAM_AUTO_INIT_USED_CYCLES, 0);
 		csr_val = ADF_CSR_RD(csr_addr, 0);
 	} while (!(csr_val & ESRAM_AUTO_TINIT_DONE) && times--);
-	if ((times < 0)) {
+	if (times < 0) {
 		pr_err("QAT: Fail to init eSram!\n");
 		return -EFAULT;
 	}

@@ -1128,7 +1128,7 @@ int qat_hal_batch_wr_lm(struct icp_qat_fw_loader_handle *handle,
 		plm_init = plm_init->next;
 	}
 	/* exec micro codes */
-	if (micro_inst_arry && (micro_inst_num > 0)) {
+	if (micro_inst_arry && micro_inst_num > 0) {
 		micro_inst_arry[micro_inst_num++] = 0x0E000010000ull;
 		stat = qat_hal_exec_micro_init_lm(handle, ae, 0, &first_exec,
 						  micro_inst_arry,

drivers/crypto/qat/qat_common/qat_uclo.c +8 -8

index 063af33c6ca6..4b2079353aa3 100644
@@ -74,7 +74,7 @@ static int qat_uclo_free_ae_data(struct icp_qat_uclo_aedata *ae_data)
 static char *qat_uclo_get_string(struct icp_qat_uof_strtable *str_table,
 				 unsigned int str_offset)
 {
-	if ((!str_table->table_len) || (str_offset > str_table->table_len))
+	if (!str_table->table_len || str_offset > str_table->table_len)
 		return NULL;
 	return (char *)(((uintptr_t)(str_table->strings)) + str_offset);
 }

@@ -736,8 +736,8 @@ static int qat_uclo_check_uof_compat(struct icp_qat_uclo_objhandle *obj_handle)
 		return -EINVAL;
 	}
 	maj_ver = obj_handle->prod_rev & 0xff;
-	if ((obj_handle->encap_uof_obj.obj_hdr->max_cpu_ver < maj_ver) ||
-	    (obj_handle->encap_uof_obj.obj_hdr->min_cpu_ver > maj_ver)) {
+	if (obj_handle->encap_uof_obj.obj_hdr->max_cpu_ver < maj_ver ||
+	    obj_handle->encap_uof_obj.obj_hdr->min_cpu_ver > maj_ver) {
 		pr_err("QAT: UOF majVer 0x%x out of range\n", maj_ver);
 		return -EINVAL;
 	}

@@ -1064,8 +1064,8 @@ static int qat_uclo_check_simg_compat(struct icp_qat_fw_loader_handle *handle,
 		return -EINVAL;
 	}
 	maj_ver = prod_rev & 0xff;
-	if ((maj_ver > img_ae_mode->devmax_ver) ||
-	    (maj_ver < img_ae_mode->devmin_ver)) {
+	if (maj_ver > img_ae_mode->devmax_ver ||
+	    maj_ver < img_ae_mode->devmin_ver) {
 		pr_err("QAT: incompatible device majver 0x%x\n", maj_ver);
 		return -EINVAL;
 	}

@@ -1108,7 +1108,7 @@ static int qat_uclo_map_suof(struct icp_qat_fw_loader_handle *handle,
 	unsigned int i = 0;
 	struct icp_qat_suof_img_hdr img_header;
 
-	if (!suof_ptr || (suof_size == 0)) {
+	if (!suof_ptr || suof_size == 0) {
 		pr_err("QAT: input parameter SUOF pointer/size is NULL\n");
 		return -EINVAL;
 	}

@@ -1199,7 +1199,7 @@ static void qat_uclo_simg_free(struct icp_qat_fw_loader_handle *handle,
 {
 	dma_free_coherent(&handle->pci_dev->dev,
 			  (size_t)(dram_desc->dram_size),
-			  (dram_desc->dram_base_addr_v),
+			  dram_desc->dram_base_addr_v,
 			  dram_desc->dram_bus_addr);
 	memset(dram_desc, 0, sizeof(*dram_desc));
 }

@@ -1851,7 +1851,7 @@ static int qat_uclo_wr_suof_img(struct icp_qat_fw_loader_handle *handle)
 		if (qat_uclo_map_auth_fw(handle,
 					 (char *)simg_hdr[i].simg_buf,
 					 (unsigned int)
-					 (simg_hdr[i].simg_len),
+					 simg_hdr[i].simg_len,
 					 &desc))
 			goto wr_err;
 		if (qat_uclo_auth_fw(handle, desc))

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:28 UTC #6 lore raw

PATCH 6/32 crypto: qat - loader: introduce additional parenthesis

In reply to Jack Xu

Introduce additional parenthesis to resolve a warninga reported by checkpatch.

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 drivers/crypto/qat/qat_common/icp_qat_hal.h | 14 +++++++-------
 drivers/crypto/qat/qat_common/qat_hal.c     |  6 +++---
 2 files changed, 10 insertions(+), 10 deletions(-)

drivers/crypto/qat/qat_common/icp_qat_hal.h +7 -7

index b48b313623fe..5640bb278bb1 100644
@@ -88,23 +88,23 @@ enum fcu_sts {
 #define FW_AUTH_MAX_RETRY   300
 
 #define SET_CAP_CSR(handle, csr, val) \
-	ADF_CSR_WR(handle->hal_cap_g_ctl_csr_addr_v, csr, val)
+	ADF_CSR_WR((handle)->hal_cap_g_ctl_csr_addr_v, csr, val)
 #define GET_CAP_CSR(handle, csr) \
-	ADF_CSR_RD(handle->hal_cap_g_ctl_csr_addr_v, csr)
+	ADF_CSR_RD((handle)->hal_cap_g_ctl_csr_addr_v, csr)
 #define SET_GLB_CSR(handle, csr, val) SET_CAP_CSR(handle, csr + GLOBAL_CSR, val)
 #define GET_GLB_CSR(handle, csr) GET_CAP_CSR(handle, GLOBAL_CSR + csr)
 #define AE_CSR(handle, ae) \
-	((char __iomem *)handle->hal_cap_ae_local_csr_addr_v + (ae << 12))
-#define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & csr))
+	((char __iomem *)(handle)->hal_cap_ae_local_csr_addr_v + ((ae) << 12))
+#define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & (csr)))
 #define SET_AE_CSR(handle, ae, csr, val) \
 	ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)
 #define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0)
 #define AE_XFER(handle, ae) \
-	((char __iomem *)handle->hal_cap_ae_xfer_csr_addr_v + (ae << 12))
+	((char __iomem *)(handle)->hal_cap_ae_xfer_csr_addr_v + ((ae) << 12))
 #define AE_XFER_ADDR(handle, ae, reg) (AE_XFER(handle, ae) + \
-	((reg & 0xff) << 2))
+	(((reg) & 0xff) << 2))
 #define SET_AE_XFER(handle, ae, reg, val) \
 	ADF_CSR_WR(AE_XFER_ADDR(handle, ae, reg), 0, val)
 #define SRAM_WRITE(handle, addr, val) \
-	ADF_CSR_WR(handle->hal_sram_addr_v, addr, val)
+	ADF_CSR_WR((handle)->hal_sram_addr_v, addr, val)
 #endif

drivers/crypto/qat/qat_common/qat_hal.c +3 -3

index bbfb2b1b6fee..c628ea30e3c2 100644
@@ -33,7 +33,7 @@
 		((((const_val) << 12) & 0x0FF00000ull) | \
 		(((const_val) <<  0) & 0x000000FFull))))
 
-#define AE(handle, ae) handle->hal_handle->aes[ae]
+#define AE(handle, ae) ((handle)->hal_handle->aes[ae])
 
 static const u64 inst_4b[] = {
 	0x0F0400C0000ull, 0x0F4400C0000ull, 0x0F040000300ull, 0x0F440000300ull,

@@ -150,8 +150,8 @@ static int qat_hal_wait_cycles(struct icp_qat_fw_loader_handle *handle,
 	return 0;
 }
 
-#define CLR_BIT(wrd, bit) (wrd & ~(1 << bit))
-#define SET_BIT(wrd, bit) (wrd | 1 << bit)
+#define CLR_BIT(wrd, bit) ((wrd) & ~(1 << (bit)))
+#define SET_BIT(wrd, bit) ((wrd) | 1 << (bit))
 
 int qat_hal_set_ae_ctx_mode(struct icp_qat_fw_loader_handle *handle,
 			    unsigned char ae, unsigned char mode)

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:28 UTC #7 lore raw

PATCH 7/32 crypto: qat - loader: rename qat_uclo_del_uof_obj()

In reply to Jack Xu

Rename the function qat_uclo_del_uof_obj() in qat_uclo_del_obj() since it frees the memory allocated for all firmware objects.

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 drivers/crypto/qat/qat_common/adf_accel_engine.c | 2 +-
 drivers/crypto/qat/qat_common/adf_common_drv.h   | 2 +-
 drivers/crypto/qat/qat_common/qat_uclo.c         | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

drivers/crypto/qat/qat_common/adf_accel_engine.c +1 -1

index 1da4176356ab..2c4a8c7c736e 100644
@@ -61,7 +61,7 @@ void adf_ae_fw_release(struct adf_accel_dev *accel_dev)
 	if (!hw_device->fw_name)
 		return;
 
-	qat_uclo_del_uof_obj(loader_data->fw_loader);
+	qat_uclo_del_obj(loader_data->fw_loader);
 	qat_hal_deinit(loader_data->fw_loader);
 	release_firmware(loader_data->uof_fw);
 	release_firmware(loader_data->mmp_fw);

drivers/crypto/qat/qat_common/adf_common_drv.h +1 -1

index 8e6e346fd841..22ac0517d15d 100644
@@ -180,7 +180,7 @@ int qat_hal_init_nn(struct icp_qat_fw_loader_handle *handle,
 int qat_hal_wr_lm(struct icp_qat_fw_loader_handle *handle,
 		  unsigned char ae, unsigned short lm_addr, unsigned int value);
 int qat_uclo_wr_all_uimage(struct icp_qat_fw_loader_handle *handle);
-void qat_uclo_del_uof_obj(struct icp_qat_fw_loader_handle *handle);
+void qat_uclo_del_obj(struct icp_qat_fw_loader_handle *handle);
 int qat_uclo_wr_mimage(struct icp_qat_fw_loader_handle *handle, void *addr_ptr,
 		       int mem_size);
 int qat_uclo_map_obj(struct icp_qat_fw_loader_handle *handle,

drivers/crypto/qat/qat_common/qat_uclo.c +1 -1

index 4b2079353aa3..dc2f2dcf21b8 100644
@@ -1705,7 +1705,7 @@ int qat_uclo_map_obj(struct icp_qat_fw_loader_handle *handle,
 			qat_uclo_map_uof_obj(handle, obj_addr, obj_size);
 }
 
-void qat_uclo_del_uof_obj(struct icp_qat_fw_loader_handle *handle)
+void qat_uclo_del_obj(struct icp_qat_fw_loader_handle *handle)
 {
 	struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
 	unsigned int a;

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:28 UTC #8 lore raw

PATCH 8/32 crypto: qat - loader: add support for relative FW ucode loading

In reply to Jack Xu

Improve the way micro instructions (FW code) are uploaded to Accelerator Engines (AEs). If code starts at PC zero (absolute addressing), read uwords with no relative address. Otherwise, use relative addressing to the page region.

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 drivers/crypto/qat/qat_common/qat_uclo.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

drivers/crypto/qat/qat_common/qat_uclo.c +7 -6

index dc2f2dcf21b8..1c03205c7166 100644
@@ -1735,21 +1735,22 @@ static void qat_uclo_fill_uwords(struct icp_qat_uclo_objhandle *obj_handle,
 				 u64 *uword, unsigned int addr_p,
 				 unsigned int raddr, u64 fill)
 {
+	unsigned int i, addr;
 	u64 uwrd = 0;
-	unsigned int i;
 
 	if (!encap_page) {
 		*uword = fill;
 		return;
 	}
+	addr = (encap_page->page_region) ? raddr : addr_p;
 	for (i = 0; i < encap_page->uwblock_num; i++) {
-		if (raddr >= encap_page->uwblock[i].start_addr &&
-		    raddr <= encap_page->uwblock[i].start_addr +
+		if (addr >= encap_page->uwblock[i].start_addr &&
+		    addr <= encap_page->uwblock[i].start_addr +
 		    encap_page->uwblock[i].words_num - 1) {
-			raddr -= encap_page->uwblock[i].start_addr;
-			raddr *= obj_handle->uword_in_bytes;
+			addr -= encap_page->uwblock[i].start_addr;
+			addr *= obj_handle->uword_in_bytes;
 			memcpy(&uwrd, (void *)(((uintptr_t)
-			       encap_page->uwblock[i].micro_words) + raddr),
+			       encap_page->uwblock[i].micro_words) + addr),
 			       obj_handle->uword_in_bytes);
 			uwrd = uwrd & 0xbffffffffffull;
 		}

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:28 UTC #9 lore raw

PATCH 9/32 crypto: qat - loader: change type for ctx_mask

In reply to Jack Xu

Change type for ctx_mask from unsigned char to unsigned long to avoid type casting.

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 drivers/crypto/qat/qat_common/adf_common_drv.h |  8 ++++----
 drivers/crypto/qat/qat_common/qat_hal.c        | 16 ++++++++--------
 2 files changed, 12 insertions(+), 12 deletions(-)

drivers/crypto/qat/qat_common/adf_common_drv.h +4 -4

index 22ac0517d15d..8109e2ab4257 100644
@@ -163,19 +163,19 @@ int qat_hal_batch_wr_lm(struct icp_qat_fw_loader_handle *handle,
 			unsigned char ae,
 			struct icp_qat_uof_batch_init *lm_init_header);
 int qat_hal_init_gpr(struct icp_qat_fw_loader_handle *handle,
-		     unsigned char ae, unsigned char ctx_mask,
+		     unsigned char ae, unsigned long ctx_mask,
 		     enum icp_qat_uof_regtype reg_type,
 		     unsigned short reg_num, unsigned int regdata);
 int qat_hal_init_wr_xfer(struct icp_qat_fw_loader_handle *handle,
-			 unsigned char ae, unsigned char ctx_mask,
+			 unsigned char ae, unsigned long ctx_mask,
 			 enum icp_qat_uof_regtype reg_type,
 			 unsigned short reg_num, unsigned int regdata);
 int qat_hal_init_rd_xfer(struct icp_qat_fw_loader_handle *handle,
-			 unsigned char ae, unsigned char ctx_mask,
+			 unsigned char ae, unsigned long ctx_mask,
 			 enum icp_qat_uof_regtype reg_type,
 			 unsigned short reg_num, unsigned int regdata);
 int qat_hal_init_nn(struct icp_qat_fw_loader_handle *handle,
-		    unsigned char ae, unsigned char ctx_mask,
+		    unsigned char ae, unsigned long ctx_mask,
 		    unsigned short reg_num, unsigned int regdata);
 int qat_hal_wr_lm(struct icp_qat_fw_loader_handle *handle,
 		  unsigned char ae, unsigned short lm_addr, unsigned int value);

drivers/crypto/qat/qat_common/qat_hal.c +8 -8

index c628ea30e3c2..a9243758a959 100644
@@ -1274,7 +1274,7 @@ static int qat_hal_convert_abs_to_rel(struct icp_qat_fw_loader_handle
 }
 
 int qat_hal_init_gpr(struct icp_qat_fw_loader_handle *handle,
-		     unsigned char ae, unsigned char ctx_mask,
+		     unsigned char ae, unsigned long ctx_mask,
 		     enum icp_qat_uof_regtype reg_type,
 		     unsigned short reg_num, unsigned int regdata)
 {

@@ -1294,7 +1294,7 @@ int qat_hal_init_gpr(struct icp_qat_fw_loader_handle *handle,
 		} else {
 			reg = reg_num;
 			type = reg_type;
-			if (!test_bit(ctx, (unsigned long *)&ctx_mask))
+			if (!test_bit(ctx, &ctx_mask))
 				continue;
 		}
 		stat = qat_hal_wr_rel_reg(handle, ae, ctx, type, reg, regdata);

@@ -1308,7 +1308,7 @@ int qat_hal_init_gpr(struct icp_qat_fw_loader_handle *handle,
 }
 
 int qat_hal_init_wr_xfer(struct icp_qat_fw_loader_handle *handle,
-			 unsigned char ae, unsigned char ctx_mask,
+			 unsigned char ae, unsigned long ctx_mask,
 			 enum icp_qat_uof_regtype reg_type,
 			 unsigned short reg_num, unsigned int regdata)
 {

@@ -1328,7 +1328,7 @@ int qat_hal_init_wr_xfer(struct icp_qat_fw_loader_handle *handle,
 		} else {
 			reg = reg_num;
 			type = reg_type;
-			if (!test_bit(ctx, (unsigned long *)&ctx_mask))
+			if (!test_bit(ctx, &ctx_mask))
 				continue;
 		}
 		stat = qat_hal_put_rel_wr_xfer(handle, ae, ctx, type, reg,

@@ -1343,7 +1343,7 @@ int qat_hal_init_wr_xfer(struct icp_qat_fw_loader_handle *handle,
 }
 
 int qat_hal_init_rd_xfer(struct icp_qat_fw_loader_handle *handle,
-			 unsigned char ae, unsigned char ctx_mask,
+			 unsigned char ae, unsigned long ctx_mask,
 			 enum icp_qat_uof_regtype reg_type,
 			 unsigned short reg_num, unsigned int regdata)
 {

@@ -1363,7 +1363,7 @@ int qat_hal_init_rd_xfer(struct icp_qat_fw_loader_handle *handle,
 		} else {
 			reg = reg_num;
 			type = reg_type;
-			if (!test_bit(ctx, (unsigned long *)&ctx_mask))
+			if (!test_bit(ctx, &ctx_mask))
 				continue;
 		}
 		stat = qat_hal_put_rel_rd_xfer(handle, ae, ctx, type, reg,

@@ -1378,7 +1378,7 @@ int qat_hal_init_rd_xfer(struct icp_qat_fw_loader_handle *handle,
 }
 
 int qat_hal_init_nn(struct icp_qat_fw_loader_handle *handle,
-		    unsigned char ae, unsigned char ctx_mask,
+		    unsigned char ae, unsigned long ctx_mask,
 		    unsigned short reg_num, unsigned int regdata)
 {
 	int stat = 0;

@@ -1388,7 +1388,7 @@ int qat_hal_init_nn(struct icp_qat_fw_loader_handle *handle,
 		return -EINVAL;
 
 	for (ctx = 0; ctx < ICP_QAT_UCLO_MAX_CTX; ctx++) {
-		if (!test_bit(ctx, (unsigned long *)&ctx_mask))
+		if (!test_bit(ctx, &ctx_mask))
 			continue;
 		stat = qat_hal_put_rel_nn(handle, ae, ctx, reg_num, regdata);
 		if (stat) {

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:28 UTC #10 lore raw

PATCH 10/32 crypto: qat - loader: change micro word data mask

In reply to Jack Xu

Change micro word data mask since the Acceleration Engine (AE) instruction codes have been changed in the new generation QAT devices.

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 drivers/crypto/qat/qat_common/qat_uclo.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/crypto/qat/qat_common/qat_uclo.c +1 -1

index 1c03205c7166..6423b1ea7021 100644
@@ -1752,7 +1752,7 @@ static void qat_uclo_fill_uwords(struct icp_qat_uclo_objhandle *obj_handle,
 			memcpy(&uwrd, (void *)(((uintptr_t)
 			       encap_page->uwblock[i].micro_words) + addr),
 			       obj_handle->uword_in_bytes);
-			uwrd = uwrd & 0xbffffffffffull;
+			uwrd = uwrd & GENMASK_ULL(43, 0);
 		}
 	}
 	*uword = uwrd;

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:28 UTC #11 lore raw

PATCH 11/32 crypto: qat - loader: refactor AE start

In reply to Jack Xu

Change the API and the behaviour of the qat_hal_start() function. With this change, the function starts under the hood all acceleration engines (AEs) and there is no longer need to call it for each engine.

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 .../crypto/qat/qat_common/adf_accel_engine.c  |  9 ++-----
 .../crypto/qat/qat_common/adf_common_drv.h    |  3 +--
 drivers/crypto/qat/qat_common/qat_hal.c       | 24 ++++++++++++-------
 3 files changed, 18 insertions(+), 18 deletions(-)

drivers/crypto/qat/qat_common/adf_accel_engine.c +2 -7

index 2c4a8c7c736e..08aaaf2b4659 100644
@@ -74,17 +74,12 @@ int adf_ae_start(struct adf_accel_dev *accel_dev)
 {
 	struct adf_fw_loader_data *loader_data = accel_dev->fw_loader;
 	struct adf_hw_device_data *hw_data = accel_dev->hw_device;
-	u32 ae_ctr, ae, max_aes = GET_MAX_ACCELENGINES(accel_dev);
+	u32 ae_ctr;
 
 	if (!hw_data->fw_name)
 		return 0;
 
-	for (ae = 0, ae_ctr = 0; ae < max_aes; ae++) {
-		if (hw_data->ae_mask & (1 << ae)) {
-			qat_hal_start(loader_data->fw_loader, ae, 0xFF);
-			ae_ctr++;
-		}
-	}
+	ae_ctr = qat_hal_start(loader_data->fw_loader);
 	dev_info(&GET_DEV(accel_dev),
 		 "qat_dev%d started %d acceleration engines\n",
 		 accel_dev->accel_id, ae_ctr);

drivers/crypto/qat/qat_common/adf_common_drv.h +1 -2

index 8109e2ab4257..945608b71937 100644
@@ -133,8 +133,7 @@ void adf_vf_isr_resource_free(struct adf_accel_dev *accel_dev);
 
 int qat_hal_init(struct adf_accel_dev *accel_dev);
 void qat_hal_deinit(struct icp_qat_fw_loader_handle *handle);
-void qat_hal_start(struct icp_qat_fw_loader_handle *handle, unsigned char ae,
-		   unsigned int ctx_mask);
+int qat_hal_start(struct icp_qat_fw_loader_handle *handle);
 void qat_hal_stop(struct icp_qat_fw_loader_handle *handle, unsigned char ae,
 		  unsigned int ctx_mask);
 void qat_hal_reset(struct icp_qat_fw_loader_handle *handle);

drivers/crypto/qat/qat_common/qat_hal.c +15 -9

index a9243758a959..f127233eec17 100644
@@ -742,26 +742,32 @@ void qat_hal_deinit(struct icp_qat_fw_loader_handle *handle)
 	kfree(handle);
 }
 
-void qat_hal_start(struct icp_qat_fw_loader_handle *handle, unsigned char ae,
-		   unsigned int ctx_mask)
+int qat_hal_start(struct icp_qat_fw_loader_handle *handle)
 {
+	unsigned long ae_mask = handle->hal_handle->ae_mask;
+	unsigned int fcu_sts;
+	unsigned char ae;
+	u32 ae_ctr = 0;
 	int retry = 0;
-	unsigned int fcu_sts = 0;
 
 	if (handle->fw_auth) {
+		ae_ctr = hweight32(ae_mask);
 		SET_CAP_CSR(handle, FCU_CONTROL, FCU_CTRL_CMD_START);
 		do {
 			msleep(FW_AUTH_WAIT_PERIOD);
 			fcu_sts = GET_CAP_CSR(handle, FCU_STATUS);
 			if (((fcu_sts >> FCU_STS_DONE_POS) & 0x1))
-				return;
+				return ae_ctr;
 		} while (retry++ < FW_AUTH_MAX_RETRY);
-		pr_err("QAT: start error (AE 0x%x FCU_STS = 0x%x)\n", ae,
-		       fcu_sts);
+		pr_err("QAT: start error (FCU_STS = 0x%x)\n", fcu_sts);
+		return 0;
 	} else {
-		qat_hal_put_wakeup_event(handle, ae, (~ctx_mask) &
-				 ICP_QAT_UCLO_AE_ALL_CTX, 0x10000);
-		qat_hal_enable_ctx(handle, ae, ctx_mask);
+		for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
+			qat_hal_put_wakeup_event(handle, ae, 0, 0x10000);
+			qat_hal_enable_ctx(handle, ae, ICP_QAT_UCLO_AE_ALL_CTX);
+			ae_ctr++;
+		}
+		return ae_ctr;
 	}
 }

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:29 UTC #12 lore raw

PATCH 12/32 crypto: qat - loader: remove global CSRs helpers

In reply to Jack Xu

Include the offset of GLOBAL_CSR directly into the enum hal_global_csr and remove the macros SET_GLB_CSR/GET_GLB_CSR to simplify the global CSR access.

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 drivers/crypto/qat/qat_common/icp_qat_hal.h |  9 +++------
 drivers/crypto/qat/qat_common/qat_hal.c     | 20 ++++++++++----------
 2 files changed, 13 insertions(+), 16 deletions(-)

drivers/crypto/qat/qat_common/icp_qat_hal.h +3 -6

index 5640bb278bb1..c2166dacdf5b 100644
@@ -5,9 +5,9 @@
 #include "icp_qat_fw_loader_handle.h"
 
 enum hal_global_csr {
-	MISC_CONTROL = 0x04,
-	ICP_RESET = 0x0c,
-	ICP_GLOBAL_CLK_ENABLE = 0x50
+	MISC_CONTROL = 0xA04,
+	ICP_RESET = 0xA0c,
+	ICP_GLOBAL_CLK_ENABLE = 0xA50
 };
 
 enum hal_ae_csr {

@@ -78,7 +78,6 @@ enum fcu_sts {
 #define XCWE_VOLUNTARY              (0x1)
 #define LCS_STATUS          (0x1)
 #define MMC_SHARE_CS_BITPOS         2
-#define GLOBAL_CSR                0xA00
 #define FCU_CTRL_AE_POS     0x8
 #define FCU_AUTH_STS_MASK   0x7
 #define FCU_STS_DONE_POS    0x9

@@ -91,8 +90,6 @@ enum fcu_sts {
 	ADF_CSR_WR((handle)->hal_cap_g_ctl_csr_addr_v, csr, val)
 #define GET_CAP_CSR(handle, csr) \
 	ADF_CSR_RD((handle)->hal_cap_g_ctl_csr_addr_v, csr)
-#define SET_GLB_CSR(handle, csr, val) SET_CAP_CSR(handle, csr + GLOBAL_CSR, val)
-#define GET_GLB_CSR(handle, csr) GET_CAP_CSR(handle, GLOBAL_CSR + csr)
 #define AE_CSR(handle, ae) \
 	((char __iomem *)(handle)->hal_cap_ae_local_csr_addr_v + ((ae) << 12))
 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & (csr)))

drivers/crypto/qat/qat_common/qat_hal.c +10 ~~-10~~

index f127233eec17..15ebb57ea14a 100644
@@ -273,10 +273,10 @@ void qat_hal_reset(struct icp_qat_fw_loader_handle *handle)
 {
 	unsigned int ae_reset_csr;
 
-	ae_reset_csr = GET_GLB_CSR(handle, ICP_RESET);
+	ae_reset_csr = GET_CAP_CSR(handle, ICP_RESET);
 	ae_reset_csr |= handle->hal_handle->ae_mask << RST_CSR_AE_LSB;
 	ae_reset_csr |= handle->hal_handle->slice_mask << RST_CSR_QAT_LSB;
-	SET_GLB_CSR(handle, ICP_RESET, ae_reset_csr);
+	SET_CAP_CSR(handle, ICP_RESET, ae_reset_csr);
 }
 
 static void qat_hal_wr_indr_csr(struct icp_qat_fw_loader_handle *handle,

@@ -390,9 +390,9 @@ static void qat_hal_reset_timestamp(struct icp_qat_fw_loader_handle *handle)
 	unsigned char ae;
 
 	/* stop the timestamp timers */
-	misc_ctl = GET_GLB_CSR(handle, MISC_CONTROL);
+	misc_ctl = GET_CAP_CSR(handle, MISC_CONTROL);
 	if (misc_ctl & MC_TIMESTAMP_ENABLE)
-		SET_GLB_CSR(handle, MISC_CONTROL, misc_ctl &
+		SET_CAP_CSR(handle, MISC_CONTROL, misc_ctl &
 			    (~MC_TIMESTAMP_ENABLE));
 
 	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {

@@ -400,7 +400,7 @@ static void qat_hal_reset_timestamp(struct icp_qat_fw_loader_handle *handle)
 		qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_HIGH, 0);
 	}
 	/* start timestamp timers */
-	SET_GLB_CSR(handle, MISC_CONTROL, misc_ctl | MC_TIMESTAMP_ENABLE);
+	SET_CAP_CSR(handle, MISC_CONTROL, misc_ctl | MC_TIMESTAMP_ENABLE);
 }
 
 #define ESRAM_AUTO_TINIT	BIT(2)

@@ -448,21 +448,21 @@ int qat_hal_clr_reset(struct icp_qat_fw_loader_handle *handle)
 	unsigned int csr;
 
 	/* write to the reset csr */
-	ae_reset_csr = GET_GLB_CSR(handle, ICP_RESET);
+	ae_reset_csr = GET_CAP_CSR(handle, ICP_RESET);
 	ae_reset_csr &= ~(handle->hal_handle->ae_mask << RST_CSR_AE_LSB);
 	ae_reset_csr &= ~(handle->hal_handle->slice_mask << RST_CSR_QAT_LSB);
 	do {
-		SET_GLB_CSR(handle, ICP_RESET, ae_reset_csr);
+		SET_CAP_CSR(handle, ICP_RESET, ae_reset_csr);
 		if (!(times--))
 			goto out_err;
-		csr = GET_GLB_CSR(handle, ICP_RESET);
+		csr = GET_CAP_CSR(handle, ICP_RESET);
 	} while ((handle->hal_handle->ae_mask |
 		 (handle->hal_handle->slice_mask << RST_CSR_QAT_LSB)) & csr);
 	/* enable clock */
-	clk_csr = GET_GLB_CSR(handle, ICP_GLOBAL_CLK_ENABLE);
+	clk_csr = GET_CAP_CSR(handle, ICP_GLOBAL_CLK_ENABLE);
 	clk_csr |= handle->hal_handle->ae_mask << 0;
 	clk_csr |= handle->hal_handle->slice_mask << 20;
-	SET_GLB_CSR(handle, ICP_GLOBAL_CLK_ENABLE, clk_csr);
+	SET_CAP_CSR(handle, ICP_GLOBAL_CLK_ENABLE, clk_csr);
 	if (qat_hal_check_ae_alive(handle))
 		goto out_err;

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:29 UTC #13 lore raw

PATCH 13/32 crypto: qat - loader: move defines to header files

In reply to Jack Xu

Move the definition of ICP_QAT_AE_OFFSET, ICP_QAT_CAP_OFFSET, LOCAL_TO_XFER_REG_OFFSET and ICP_QAT_EP_OFFSET from qat_hal.c to icp_qat_hal.h to avoid the definition of generation specific constants in qat_hal.c.

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 drivers/crypto/qat/qat_common/icp_qat_hal.h | 4 ++++
 drivers/crypto/qat/qat_common/qat_hal.c     | 4 ----
 2 files changed, 4 insertions(+), 4 deletions(-)

drivers/crypto/qat/qat_common/icp_qat_hal.h +4 -0

index c2166dacdf5b..eff9a3811435 100644
@@ -85,6 +85,10 @@ enum fcu_sts {
 #define FCU_LOADED_AE_POS   0x16
 #define FW_AUTH_WAIT_PERIOD 10
 #define FW_AUTH_MAX_RETRY   300
+#define ICP_QAT_AE_OFFSET 0x20000
+#define ICP_QAT_CAP_OFFSET (ICP_QAT_AE_OFFSET + 0x10000)
+#define LOCAL_TO_XFER_REG_OFFSET 0x800
+#define ICP_QAT_EP_OFFSET 0x3a000
 
 #define SET_CAP_CSR(handle, csr, val) \
 	ADF_CSR_WR((handle)->hal_cap_g_ctl_csr_addr_v, csr, val)

drivers/crypto/qat/qat_common/qat_hal.c +0 -4

index 15ebb57ea14a..5bf42f01a3de 100644
@@ -646,10 +646,6 @@ static int qat_hal_clear_gpr(struct icp_qat_fw_loader_handle *handle)
 	return 0;
 }
 
-#define ICP_QAT_AE_OFFSET	0x20000
-#define ICP_QAT_CAP_OFFSET       (ICP_QAT_AE_OFFSET + 0x10000)
-#define LOCAL_TO_XFER_REG_OFFSET    0x800
-#define ICP_QAT_EP_OFFSET	0x3a000
 int qat_hal_init(struct adf_accel_dev *accel_dev)
 {
 	unsigned char ae;

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:29 UTC #14 lore raw

PATCH 14/32 crypto: qat - loader: refactor qat_uclo_set_ae_mode()

In reply to Jack Xu

Refactor qat_uclo_set_ae_mode() by moving the logic that sets the AE modes to a separate function, qat_hal_set_modes().

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 drivers/crypto/qat/qat_common/qat_uclo.c | 69 +++++++++++++++---------
 1 file changed, 43 insertions(+), 26 deletions(-)

drivers/crypto/qat/qat_common/qat_uclo.c +43 ~~-26~~

index 6423b1ea7021..095e1b469412 100644
@@ -869,16 +869,52 @@ static int qat_uclo_init_globals(struct icp_qat_fw_loader_handle *handle)
 	return 0;
 }
 
+static int qat_hal_set_modes(struct icp_qat_fw_loader_handle *handle,
+			     struct icp_qat_uclo_objhandle *obj_handle,
+			     unsigned char ae,
+			     struct icp_qat_uof_image *uof_image)
+{
+	unsigned char mode;
+	int ret;
+
+	mode = ICP_QAT_CTX_MODE(uof_image->ae_mode);
+	ret = qat_hal_set_ae_ctx_mode(handle, ae, mode);
+	if (ret) {
+		pr_err("QAT: qat_hal_set_ae_ctx_mode error\n");
+		return ret;
+	}
+	mode = ICP_QAT_NN_MODE(uof_image->ae_mode);
+	ret = qat_hal_set_ae_nn_mode(handle, ae, mode);
+	if (ret) {
+		pr_err("QAT: qat_hal_set_ae_nn_mode error\n");
+		return ret;
+	}
+	mode = ICP_QAT_LOC_MEM0_MODE(uof_image->ae_mode);
+	ret = qat_hal_set_ae_lm_mode(handle, ae, ICP_LMEM0, mode);
+	if (ret) {
+		pr_err("QAT: qat_hal_set_ae_lm_mode LMEM0 error\n");
+		return ret;
+	}
+	mode = ICP_QAT_LOC_MEM1_MODE(uof_image->ae_mode);
+	ret = qat_hal_set_ae_lm_mode(handle, ae, ICP_LMEM1, mode);
+	if (ret) {
+		pr_err("QAT: qat_hal_set_ae_lm_mode LMEM1 error\n");
+		return ret;
+	}
+	return 0;
+}
+
 static int qat_uclo_set_ae_mode(struct icp_qat_fw_loader_handle *handle)
 {
-	unsigned char ae, nn_mode, s;
 	struct icp_qat_uof_image *uof_image;
 	struct icp_qat_uclo_aedata *ae_data;
 	struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
+	unsigned long ae_mask = handle->hal_handle->ae_mask;
+	unsigned char ae, s;
+	int error;
 
 	for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) {
-		if (!test_bit(ae,
-			      (unsigned long *)&handle->hal_handle->ae_mask))
+		if (!test_bit(ae, &ae_mask))
 			continue;
 		ae_data = &obj_handle->ae_data[ae];
 		for (s = 0; s < min_t(unsigned int, ae_data->slice_num,

@@ -886,29 +922,10 @@ static int qat_uclo_set_ae_mode(struct icp_qat_fw_loader_handle *handle)
 			if (!obj_handle->ae_data[ae].ae_slices[s].encap_image)
 				continue;
 			uof_image = ae_data->ae_slices[s].encap_image->img_ptr;
-			if (qat_hal_set_ae_ctx_mode(handle, ae,
-						    (char)ICP_QAT_CTX_MODE
-						    (uof_image->ae_mode))) {
-				pr_err("QAT: qat_hal_set_ae_ctx_mode error\n");
-				return -EFAULT;
-			}
-			nn_mode = ICP_QAT_NN_MODE(uof_image->ae_mode);
-			if (qat_hal_set_ae_nn_mode(handle, ae, nn_mode)) {
-				pr_err("QAT: qat_hal_set_ae_nn_mode error\n");
-				return -EFAULT;
-			}
-			if (qat_hal_set_ae_lm_mode(handle, ae, ICP_LMEM0,
-						   (char)ICP_QAT_LOC_MEM0_MODE
-						   (uof_image->ae_mode))) {
-				pr_err("QAT: qat_hal_set_ae_lm_mode LMEM0 error\n");
-				return -EFAULT;
-			}
-			if (qat_hal_set_ae_lm_mode(handle, ae, ICP_LMEM1,
-						   (char)ICP_QAT_LOC_MEM1_MODE
-						   (uof_image->ae_mode))) {
-				pr_err("QAT: qat_hal_set_ae_lm_mode LMEM1 error\n");
-				return -EFAULT;
-			}
+			error = qat_hal_set_modes(handle, obj_handle, ae,
+						  uof_image);
+			if (error)
+				return error;
 		}
 	}
 	return 0;

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:29 UTC #15 lore raw

PATCH 15/32 crypto: qat - loader: refactor long expressions

In reply to Jack Xu

Replace long expressions with local variables in the functions qat_uclo_wr_uimage_page(), qat_uclo_init_globals() and qat_uclo_init_umem_seg() to improve readability.

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 drivers/crypto/qat/qat_common/qat_uclo.c | 41 +++++++++++++-----------
 1 file changed, 23 insertions(+), 18 deletions(-)

drivers/crypto/qat/qat_common/qat_uclo.c +23 ~~-18~~

index 095e1b469412..8d08dac94ea9 100644
@@ -324,6 +324,7 @@ static int qat_uclo_init_umem_seg(struct icp_qat_fw_loader_handle *handle,
 {
 	struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
 	unsigned int ae, ustore_size, uaddr, i;
+	struct icp_qat_uclo_aedata *aed;
 
 	ustore_size = obj_handle->ustore_phy_size;
 	if (qat_uclo_fetch_initmem_ae(handle, init_mem, ustore_size, &ae))

@@ -333,11 +334,10 @@ static int qat_uclo_init_umem_seg(struct icp_qat_fw_loader_handle *handle,
 		return -EINVAL;
 	/* set the highest ustore address referenced */
 	uaddr = (init_mem->addr + init_mem->num_in_bytes) >> 0x2;
-	for (i = 0; i < obj_handle->ae_data[ae].slice_num; i++) {
-		if (obj_handle->ae_data[ae].ae_slices[i].
-		    encap_image->uwords_num < uaddr)
-			obj_handle->ae_data[ae].ae_slices[i].
-			encap_image->uwords_num = uaddr;
+	aed = &obj_handle->ae_data[ae];
+	for (i = 0; i < aed->slice_num; i++) {
+		if (aed->ae_slices[i].encap_image->uwords_num < uaddr)
+			aed->ae_slices[i].encap_image->uwords_num = uaddr;
 	}
 	return 0;
 }

@@ -845,6 +845,7 @@ static int qat_uclo_init_reg_sym(struct icp_qat_fw_loader_handle *handle,
 static int qat_uclo_init_globals(struct icp_qat_fw_loader_handle *handle)
 {
 	struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
+	struct icp_qat_uclo_aedata *aed;
 	unsigned int s, ae;
 
 	if (obj_handle->global_inited)

@@ -855,13 +856,13 @@ static int qat_uclo_init_globals(struct icp_qat_fw_loader_handle *handle)
 			return -EINVAL;
 		}
 	}
+
 	for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) {
-		for (s = 0; s < obj_handle->ae_data[ae].slice_num; s++) {
-			if (!obj_handle->ae_data[ae].ae_slices[s].encap_image)
+		aed = &obj_handle->ae_data[ae];
+		for (s = 0; s < aed->slice_num; s++) {
+			if (!aed->ae_slices[s].encap_image)
 				continue;
-			if (qat_uclo_init_reg_sym(handle, ae,
-						  obj_handle->ae_data[ae].
-						  ae_slices[s].encap_image))
+			if (qat_uclo_init_reg_sym(handle, ae, aed->ae_slices[s].encap_image))
 				return -EINVAL;
 		}
 	}

@@ -1820,6 +1821,8 @@ static void qat_uclo_wr_uimage_page(struct icp_qat_fw_loader_handle *handle,
 				    struct icp_qat_uof_image *image)
 {
 	struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
+	unsigned long ae_assigned = image->ae_assigned;
+	struct icp_qat_uclo_aedata *aed;
 	unsigned int ctx_mask, s;
 	struct icp_qat_uclo_page *page;
 	unsigned char ae;

@@ -1832,24 +1835,26 @@ static void qat_uclo_wr_uimage_page(struct icp_qat_fw_loader_handle *handle,
 	/* load the default page and set assigned CTX PC
 	 * to the entrypoint address */
 	for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) {
-		if (!test_bit(ae, (unsigned long *)&image->ae_assigned))
+		if (!test_bit(ae, &ae_assigned))
 			continue;
+
+		aed = &obj_handle->ae_data[ae];
 		/* find the slice to which this image is assigned */
-		for (s = 0; s < obj_handle->ae_data[ae].slice_num; s++) {
-			if (image->ctx_assigned & obj_handle->ae_data[ae].
-			    ae_slices[s].ctx_mask_assigned)
+		for (s = 0; s < aed->slice_num; s++) {
+			if (image->ctx_assigned &
+			    aed->ae_slices[s].ctx_mask_assigned)
 				break;
 		}
-		if (s >= obj_handle->ae_data[ae].slice_num)
+		if (s >= aed->slice_num)
 			continue;
-		page = obj_handle->ae_data[ae].ae_slices[s].page;
+		page = aed->ae_slices[s].page;
 		if (!page->encap_page->def_page)
 			continue;
 		qat_uclo_wr_uimage_raw_page(handle, page->encap_page, ae);
 
-		page = obj_handle->ae_data[ae].ae_slices[s].page;
+		page = aed->ae_slices[s].page;
 		for (ctx = 0; ctx < ICP_QAT_UCLO_MAX_CTX; ctx++)
-			obj_handle->ae_data[ae].ae_slices[s].cur_page[ctx] =
+			aed->ae_slices[s].cur_page[ctx] =
 					(ctx_mask & (1 << ctx)) ? page : NULL;
 		qat_hal_set_live_ctx(handle, (unsigned char)ae,
 				     image->ctx_assigned);

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:29 UTC #16 lore raw

PATCH 16/32 crypto: qat - loader: introduce chip info structure

In reply to Jack Xu

Introduce the chip info structure which contains device specific information. The initialization path has been split between common and hardware specific in order to facilitate the introduction of the next generation hardware.

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 .../qat/qat_common/icp_qat_fw_loader_handle.h |   7 +-
 drivers/crypto/qat/qat_common/qat_hal.c       | 110 +++++++++++++-----
 drivers/crypto/qat/qat_common/qat_uclo.c      |   6 +-
 3 files changed, 88 insertions(+), 35 deletions(-)

drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h +6 -1

index 7d44786a223a..6b1ad629357b 100644
@@ -22,13 +22,18 @@ struct icp_qat_fw_loader_hal_handle {
 	unsigned int max_ustore;
 };
 
+struct icp_qat_fw_loader_chip_info {
+	bool sram_visible;
+	bool fw_auth;
+};
+
 struct icp_qat_fw_loader_handle {
 	struct icp_qat_fw_loader_hal_handle *hal_handle;
+	struct icp_qat_fw_loader_chip_info *chip_info;
 	struct pci_dev *pci_dev;
 	void *obj_handle;
 	void *sobj_handle;
 	void *mobj_handle;
-	bool fw_auth;
 	void __iomem *hal_sram_addr_v;
 	void __iomem *hal_cap_g_ctl_csr_addr_v;
 	void __iomem *hal_cap_ae_xfer_csr_addr_v;

drivers/crypto/qat/qat_common/qat_hal.c +79 ~~-31~~

175 lines not on this page · raw message

drivers/crypto/qat/qat_common/qat_uclo.c +3 -3

index 8d08dac94ea9..1533981baf3a 100644
@@ -1405,7 +1405,7 @@ int qat_uclo_wr_mimage(struct icp_qat_fw_loader_handle *handle,
 	struct icp_qat_fw_auth_desc *desc = NULL;
 	int status = 0;
 
-	if (handle->fw_auth) {
+	if (handle->chip_info->fw_auth) {
 		if (!qat_uclo_map_auth_fw(handle, addr_ptr, mem_size, &desc))
 			status = qat_uclo_auth_fw(handle, desc);
 		qat_uclo_ummap_auth_fw(handle, &desc);

@@ -1718,7 +1718,7 @@ int qat_uclo_map_obj(struct icp_qat_fw_loader_handle *handle,
 		obj_size = mem_size;
 	}
 
-	return (handle->fw_auth) ?
+	return (handle->chip_info->fw_auth) ?
 			qat_uclo_map_suof_obj(handle, obj_addr, obj_size) :
 			qat_uclo_map_uof_obj(handle, obj_addr, obj_size);
 }

@@ -1909,6 +1909,6 @@ static int qat_uclo_wr_uof_img(struct icp_qat_fw_loader_handle *handle)
 
 int qat_uclo_wr_all_uimage(struct icp_qat_fw_loader_handle *handle)
 {
-	return (handle->fw_auth) ? qat_uclo_wr_suof_img(handle) :
+	return (handle->chip_info->fw_auth) ? qat_uclo_wr_suof_img(handle) :
 				   qat_uclo_wr_uof_img(handle);
 }

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:29 UTC #17 lore raw

PATCH 17/32 crypto: qat - loader: replace check based on DID

In reply to Jack Xu

Modify condition in qat_uclo_wr_mimage() to use a capability of the device (sram_visible), rather than the device ID, so the check is not specific to devices of the same type.

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 drivers/crypto/qat/qat_common/qat_uclo.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

drivers/crypto/qat/qat_common/qat_uclo.c +5 -3

index 1533981baf3a..5774916497bd 100644
@@ -1410,9 +1410,11 @@ int qat_uclo_wr_mimage(struct icp_qat_fw_loader_handle *handle,
 			status = qat_uclo_auth_fw(handle, desc);
 		qat_uclo_ummap_auth_fw(handle, &desc);
 	} else {
-		if (handle->pci_dev->device == PCI_DEVICE_ID_INTEL_QAT_C3XXX) {
-			pr_err("QAT: C3XXX doesn't support unsigned MMP\n");
-			return -EINVAL;
+		if (!handle->chip_info->sram_visible) {
+			dev_dbg(&handle->pci_dev->dev,
+				"QAT MMP fw not loaded for device 0x%x",
+				handle->pci_dev->device);
+			return status;
 		}
 		qat_uclo_wr_sram_by_words(handle, 0, addr_ptr, mem_size);
 	}

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:29 UTC #18 lore raw

PATCH 18/32 crypto: qat - loader: add next neighbor to chip_info

In reply to Jack Xu

Introduce the next neighbor (NN) capability in chip_info as NN registers are not supported in certain SKUs of QAT.

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 .../crypto/qat/qat_common/icp_qat_fw_loader_handle.h |  1 +
 drivers/crypto/qat/qat_common/qat_hal.c              | 11 ++++++++++-
 drivers/crypto/qat/qat_common/qat_uclo.c             | 12 +++++++-----
 3 files changed, 18 insertions(+), 6 deletions(-)

drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h +1 -0

index 6b1ad629357b..8025be597d18 100644
@@ -24,6 +24,7 @@ struct icp_qat_fw_loader_hal_handle {
 
 struct icp_qat_fw_loader_chip_info {
 	bool sram_visible;
+	bool nn;
 	bool fw_auth;
 };

drivers/crypto/qat/qat_common/qat_hal.c +10 -1

index 2faf8638526c..e0d0ab43fd12 100644
@@ -603,7 +603,9 @@ static int qat_hal_clear_gpr(struct icp_qat_fw_loader_handle *handle)
 		qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, csr_val);
 		csr_val = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);
 		csr_val &= IGNORE_W1C_MASK;
-		csr_val |= CE_NN_MODE;
+		if (handle->chip_info->nn)
+			csr_val |= CE_NN_MODE;
+
 		qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, csr_val);
 		qat_hal_wr_uwords(handle, ae, 0, ARRAY_SIZE(inst),
 				  (u64 *)inst);

@@ -665,10 +667,12 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
 	case PCI_DEVICE_ID_INTEL_QAT_C62X:
 	case PCI_DEVICE_ID_INTEL_QAT_C3XXX:
 		handle->chip_info->sram_visible = false;
+		handle->chip_info->nn = true;
 		handle->chip_info->fw_auth = true;
 		break;
 	case PCI_DEVICE_ID_INTEL_QAT_DH895XCC:
 		handle->chip_info->sram_visible = true;
+		handle->chip_info->nn = true;
 		handle->chip_info->fw_auth = false;
 		break;
 	default:

@@ -1433,6 +1437,11 @@ int qat_hal_init_nn(struct icp_qat_fw_loader_handle *handle,
 {
 	int stat = 0;
 	unsigned char ctx;
+	if (!handle->chip_info->nn) {
+		dev_err(&handle->pci_dev->dev, "QAT: No next neigh in 0x%x\n",
+			handle->pci_dev->device);
+		return -EINVAL;
+	}
 
 	if (ctx_mask == 0)
 		return -EINVAL;

drivers/crypto/qat/qat_common/qat_uclo.c +7 -5

index 5774916497bd..fce075874962 100644
@@ -884,11 +884,13 @@ static int qat_hal_set_modes(struct icp_qat_fw_loader_handle *handle,
 		pr_err("QAT: qat_hal_set_ae_ctx_mode error\n");
 		return ret;
 	}
-	mode = ICP_QAT_NN_MODE(uof_image->ae_mode);
-	ret = qat_hal_set_ae_nn_mode(handle, ae, mode);
-	if (ret) {
-		pr_err("QAT: qat_hal_set_ae_nn_mode error\n");
-		return ret;
+	if (handle->chip_info->nn) {
+		mode = ICP_QAT_NN_MODE(uof_image->ae_mode);
+		ret = qat_hal_set_ae_nn_mode(handle, ae, mode);
+		if (ret) {
+			pr_err("QAT: qat_hal_set_ae_nn_mode error\n");
+			return ret;
+		}
 	}
 	mode = ICP_QAT_LOC_MEM0_MODE(uof_image->ae_mode);
 	ret = qat_hal_set_ae_lm_mode(handle, ae, ICP_LMEM0, mode);

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:29 UTC #19 lore raw

PATCH 19/32 crypto: qat - loader: add support for lm2 and lm3

In reply to Jack Xu

Add support for local memory lm2 and lm3 which is introduced in the next generation of QAT devices.

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 .../crypto/qat/qat_common/adf_common_drv.h    |  2 +
 .../qat/qat_common/icp_qat_fw_loader_handle.h |  1 +
 drivers/crypto/qat/qat_common/icp_qat_hal.h   |  9 +++
 drivers/crypto/qat/qat_common/icp_qat_uclo.h  |  5 ++
 drivers/crypto/qat/qat_common/qat_hal.c       | 70 ++++++++++++++++++-
 drivers/crypto/qat/qat_common/qat_uclo.c      | 16 +++++
 6 files changed, 101 insertions(+), 2 deletions(-)

drivers/crypto/qat/qat_common/adf_common_drv.h +2 -0

index 945608b71937..f4c90c701670 100644
@@ -178,6 +178,8 @@ int qat_hal_init_nn(struct icp_qat_fw_loader_handle *handle,
 		    unsigned short reg_num, unsigned int regdata);
 int qat_hal_wr_lm(struct icp_qat_fw_loader_handle *handle,
 		  unsigned char ae, unsigned short lm_addr, unsigned int value);
+void qat_hal_set_ae_tindex_mode(struct icp_qat_fw_loader_handle *handle,
+				unsigned char ae, unsigned char mode);
 int qat_uclo_wr_all_uimage(struct icp_qat_fw_loader_handle *handle);
 void qat_uclo_del_obj(struct icp_qat_fw_loader_handle *handle);
 int qat_uclo_wr_mimage(struct icp_qat_fw_loader_handle *handle, void *addr_ptr,

drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h +1 -0

index 8025be597d18..3c587105d09d 100644
@@ -25,6 +25,7 @@ struct icp_qat_fw_loader_hal_handle {
 struct icp_qat_fw_loader_chip_info {
 	bool sram_visible;
 	bool nn;
+	bool lm2lm3;
 	bool fw_auth;
 };

drivers/crypto/qat/qat_common/icp_qat_hal.h +9 -0

index eff9a3811435..82ac33a4500f 100644
@@ -26,8 +26,14 @@ enum hal_ae_csr {
 	CTX_WAKEUP_EVENTS_INDIRECT = 0x050,
 	LM_ADDR_0_INDIRECT = 0x060,
 	LM_ADDR_1_INDIRECT = 0x068,
+	LM_ADDR_2_INDIRECT = 0x0cc,
+	LM_ADDR_3_INDIRECT = 0x0d4,
 	INDIRECT_LM_ADDR_0_BYTE_INDEX = 0x0e0,
 	INDIRECT_LM_ADDR_1_BYTE_INDEX = 0x0e8,
+	INDIRECT_LM_ADDR_2_BYTE_INDEX = 0x10c,
+	INDIRECT_LM_ADDR_3_BYTE_INDEX = 0x114,
+	INDIRECT_T_INDEX = 0x0f8,
+	INDIRECT_T_INDEX_BYTE_INDEX = 0x0fc,
 	FUTURE_COUNT_SIGNAL_INDIRECT = 0x078,
 	TIMESTAMP_LOW = 0x0c0,
 	TIMESTAMP_HIGH = 0x0c4,

@@ -68,6 +74,9 @@ enum fcu_sts {
 #define CE_ENABLE_BITPOS            0x8
 #define CE_LMADDR_0_GLOBAL_BITPOS   16
 #define CE_LMADDR_1_GLOBAL_BITPOS   17
+#define CE_LMADDR_2_GLOBAL_BITPOS   22
+#define CE_LMADDR_3_GLOBAL_BITPOS   23
+#define CE_T_INDEX_GLOBAL_BITPOS    21
 #define CE_NN_MODE_BITPOS           20
 #define CE_REG_PAR_ERR_BITPOS       25
 #define CE_BREAKPOINT_BITPOS        27

drivers/crypto/qat/qat_common/icp_qat_uclo.h +5 -0

index 101de1430896..5728a81d9dea 100644
@@ -69,6 +69,9 @@
 
 #define ICP_QAT_LOC_MEM0_MODE(ae_mode) (((ae_mode) >> 0x8) & 0x1)
 #define ICP_QAT_LOC_MEM1_MODE(ae_mode) (((ae_mode) >> 0x9) & 0x1)
+#define ICP_QAT_LOC_MEM2_MODE(ae_mode) (((ae_mode) >> 0x6) & 0x1)
+#define ICP_QAT_LOC_MEM3_MODE(ae_mode) (((ae_mode) >> 0x7) & 0x1)
+#define ICP_QAT_LOC_TINDEX_MODE(ae_mode) (((ae_mode) >> 0xe) & 0x1)
 
 enum icp_qat_uof_mem_region {
 	ICP_QAT_UOF_SRAM_REGION = 0x0,

@@ -98,6 +101,8 @@ enum icp_qat_uof_regtype {
 	ICP_LMEM0	= 27,
 	ICP_LMEM1	= 28,
 	ICP_NEIGH_REL	= 31,
+	ICP_LMEM2	= 61,
+	ICP_LMEM3	= 62,
 };
 
 enum icp_qat_css_fwtype {

drivers/crypto/qat/qat_common/qat_hal.c +68 -2

118 lines not on this page · raw message

drivers/crypto/qat/qat_common/qat_uclo.c +16 -0

index fce075874962..4a90b150199c 100644
@@ -904,6 +904,22 @@ static int qat_hal_set_modes(struct icp_qat_fw_loader_handle *handle,
 		pr_err("QAT: qat_hal_set_ae_lm_mode LMEM1 error\n");
 		return ret;
 	}
+	if (handle->chip_info->lm2lm3) {
+		mode = ICP_QAT_LOC_MEM2_MODE(uof_image->ae_mode);
+		ret = qat_hal_set_ae_lm_mode(handle, ae, ICP_LMEM2, mode);
+		if (ret) {
+			pr_err("QAT: qat_hal_set_ae_lm_mode LMEM2 error\n");
+			return ret;
+		}
+		mode = ICP_QAT_LOC_MEM3_MODE(uof_image->ae_mode);
+		ret = qat_hal_set_ae_lm_mode(handle, ae, ICP_LMEM3, mode);
+		if (ret) {
+			pr_err("QAT: qat_hal_set_ae_lm_mode LMEM3 error\n");
+			return ret;
+		}
+		mode = ICP_QAT_LOC_TINDEX_MODE(uof_image->ae_mode);
+		qat_hal_set_ae_tindex_mode(handle, ae, mode);
+	}
 	return 0;
 }

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:29 UTC #20 lore raw

PATCH 20/32 crypto: qat - loader: add local memory size to chip info

In reply to Jack Xu

Add the local memory size to the chip info since the size of this memory will be different in the next generation of QAT devices.

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h | 1 +
 drivers/crypto/qat/qat_common/qat_hal.c                  | 2 ++
 drivers/crypto/qat/qat_common/qat_uclo.c                 | 2 +-
 3 files changed, 4 insertions(+), 1 deletion(-)

drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h +1 -0

index 3c587105d09d..0fa5c22fd9c0 100644
@@ -26,6 +26,7 @@ struct icp_qat_fw_loader_chip_info {
 	bool sram_visible;
 	bool nn;
 	bool lm2lm3;
+	u32 lm_size;
 	bool fw_auth;
 };

drivers/crypto/qat/qat_common/qat_hal.c +2 -0

index 70fc93f31e79..44cf797ace71 100644
@@ -699,12 +699,14 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
 		handle->chip_info->sram_visible = false;
 		handle->chip_info->nn = true;
 		handle->chip_info->lm2lm3 = false;
+		handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG;
 		handle->chip_info->fw_auth = true;
 		break;
 	case PCI_DEVICE_ID_INTEL_QAT_DH895XCC:
 		handle->chip_info->sram_visible = true;
 		handle->chip_info->nn = true;
 		handle->chip_info->lm2lm3 = false;
+		handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG;
 		handle->chip_info->fw_auth = false;
 		break;
 	default:

drivers/crypto/qat/qat_common/qat_uclo.c +1 -1

index 4a90b150199c..32c64a48926f 100644
@@ -311,7 +311,7 @@ static int qat_uclo_init_lmem_seg(struct icp_qat_fw_loader_handle *handle,
 	unsigned int ae;
 
 	if (qat_uclo_fetch_initmem_ae(handle, init_mem,
-				      ICP_QAT_UCLO_MAX_LMEM_REG, &ae))
+				      handle->chip_info->lm_size, &ae))
 		return -EINVAL;
 	if (qat_uclo_create_batch_init_list(handle, init_mem, ae,
 					    &obj_handle->lm_init_tab[ae]))

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:29 UTC #21 lore raw

PATCH 21/32 crypto: qat - loader: add reset CSR and mask to chip info

In reply to Jack Xu

Add reset CSR offset and mask to chip info since they are different in new QAT devices. This also simplifies the reset/clrReset functions by using the reset mask.

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 .../qat/qat_common/icp_qat_fw_loader_handle.h |  2 +
 drivers/crypto/qat/qat_common/qat_hal.c       | 39 +++++++++++--------
 2 files changed, 24 insertions(+), 17 deletions(-)

drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h +2 -0

index 0fa5c22fd9c0..5e2c0ef6d26c 100644
@@ -27,6 +27,8 @@ struct icp_qat_fw_loader_chip_info {
 	bool nn;
 	bool lm2lm3;
 	u32 lm_size;
+	u32 icp_rst_csr;
+	u32 icp_rst_mask;
 	bool fw_auth;
 };

drivers/crypto/qat/qat_common/qat_hal.c +22 ~~-17~~

index 44cf797ace71..0d64e074fb44 100644
@@ -301,12 +301,13 @@ static unsigned short qat_hal_get_reg_addr(unsigned int type,
 
 void qat_hal_reset(struct icp_qat_fw_loader_handle *handle)
 {
-	unsigned int ae_reset_csr;
+	unsigned int reset_mask = handle->chip_info->icp_rst_mask;
+	unsigned int reset_csr = handle->chip_info->icp_rst_csr;
+	unsigned int csr_val;
 
-	ae_reset_csr = GET_CAP_CSR(handle, ICP_RESET);
-	ae_reset_csr |= handle->hal_handle->ae_mask << RST_CSR_AE_LSB;
-	ae_reset_csr |= handle->hal_handle->slice_mask << RST_CSR_QAT_LSB;
-	SET_CAP_CSR(handle, ICP_RESET, ae_reset_csr);
+	csr_val = GET_CAP_CSR(handle, reset_csr);
+	csr_val |= reset_mask;
+	SET_CAP_CSR(handle, reset_csr, csr_val);
 }
 
 static void qat_hal_wr_indr_csr(struct icp_qat_fw_loader_handle *handle,

@@ -470,28 +471,27 @@ static int qat_hal_init_esram(struct icp_qat_fw_loader_handle *handle)
 #define SHRAM_INIT_CYCLES 2060
 int qat_hal_clr_reset(struct icp_qat_fw_loader_handle *handle)
 {
+	unsigned int reset_mask = handle->chip_info->icp_rst_mask;
+	unsigned int reset_csr = handle->chip_info->icp_rst_csr;
 	unsigned long ae_mask = handle->hal_handle->ae_mask;
-	unsigned int ae_reset_csr;
-	unsigned char ae;
+	unsigned char ae = 0;
 	unsigned int clk_csr;
 	unsigned int times = 100;
-	unsigned int csr;
+	unsigned int csr_val;
 
 	/* write to the reset csr */
-	ae_reset_csr = GET_CAP_CSR(handle, ICP_RESET);
-	ae_reset_csr &= ~(handle->hal_handle->ae_mask << RST_CSR_AE_LSB);
-	ae_reset_csr &= ~(handle->hal_handle->slice_mask << RST_CSR_QAT_LSB);
+	csr_val = GET_CAP_CSR(handle, reset_csr);
+	csr_val &= ~reset_mask;
 	do {
-		SET_CAP_CSR(handle, ICP_RESET, ae_reset_csr);
+		SET_CAP_CSR(handle, reset_csr, csr_val);
 		if (!(times--))
 			goto out_err;
-		csr = GET_CAP_CSR(handle, ICP_RESET);
-	} while ((handle->hal_handle->ae_mask |
-		 (handle->hal_handle->slice_mask << RST_CSR_QAT_LSB)) & csr);
+		csr_val = GET_CAP_CSR(handle, reset_csr);
+		csr_val &= reset_mask;
+	} while (csr_val);
 	/* enable clock */
 	clk_csr = GET_CAP_CSR(handle, ICP_GLOBAL_CLK_ENABLE);
-	clk_csr |= handle->hal_handle->ae_mask << 0;
-	clk_csr |= handle->hal_handle->slice_mask << 20;
+	clk_csr |= reset_mask;
 	SET_CAP_CSR(handle, ICP_GLOBAL_CLK_ENABLE, clk_csr);
 	if (qat_hal_check_ae_alive(handle))
 		goto out_err;

@@ -700,6 +700,7 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
 		handle->chip_info->nn = true;
 		handle->chip_info->lm2lm3 = false;
 		handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG;
+		handle->chip_info->icp_rst_csr = ICP_RESET;
 		handle->chip_info->fw_auth = true;
 		break;
 	case PCI_DEVICE_ID_INTEL_QAT_DH895XCC:

@@ -707,6 +708,7 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
 		handle->chip_info->nn = true;
 		handle->chip_info->lm2lm3 = false;
 		handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG;
+		handle->chip_info->icp_rst_csr = ICP_RESET;
 		handle->chip_info->fw_auth = false;
 		break;
 	default:

@@ -719,6 +721,9 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
 			&pci_info->pci_bars[hw_data->get_sram_bar_id(hw_data)];
 		handle->hal_sram_addr_v = sram_bar->virt_addr;
 	}
+
+	handle->chip_info->icp_rst_mask = (hw_data->ae_mask << RST_CSR_AE_LSB) |
+					  (hw_data->accel_mask << RST_CSR_QAT_LSB);
 	handle->hal_cap_g_ctl_csr_addr_v =
 		(void __iomem *)((uintptr_t)misc_bar->virt_addr +
 				 ICP_QAT_CAP_OFFSET);

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:29 UTC #22 lore raw

PATCH 22/32 crypto: qat - loader: add clock enable CSR to chip info

In reply to Jack Xu

Add global clock enable CSR to the chip info since the CSR offset will be different in the next generation of QAT devices.

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 .../crypto/qat/qat_common/icp_qat_fw_loader_handle.h   |  1 +
 drivers/crypto/qat/qat_common/qat_hal.c                | 10 ++++++----
 2 files changed, 7 insertions(+), 4 deletions(-)

drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h +1 -0

index 5e2c0ef6d26c..1d6ab3407dc9 100644
@@ -29,6 +29,7 @@ struct icp_qat_fw_loader_chip_info {
 	u32 lm_size;
 	u32 icp_rst_csr;
 	u32 icp_rst_mask;
+	u32 glb_clk_enable_csr;
 	bool fw_auth;
 };

drivers/crypto/qat/qat_common/qat_hal.c +6 -4

index 0d64e074fb44..6e6bca281ab7 100644
@@ -471,11 +471,11 @@ static int qat_hal_init_esram(struct icp_qat_fw_loader_handle *handle)
 #define SHRAM_INIT_CYCLES 2060
 int qat_hal_clr_reset(struct icp_qat_fw_loader_handle *handle)
 {
+	unsigned int clk_csr = handle->chip_info->glb_clk_enable_csr;
 	unsigned int reset_mask = handle->chip_info->icp_rst_mask;
 	unsigned int reset_csr = handle->chip_info->icp_rst_csr;
 	unsigned long ae_mask = handle->hal_handle->ae_mask;
 	unsigned char ae = 0;
-	unsigned int clk_csr;
 	unsigned int times = 100;
 	unsigned int csr_val;

@@ -490,9 +490,9 @@ int qat_hal_clr_reset(struct icp_qat_fw_loader_handle *handle)
 		csr_val &= reset_mask;
 	} while (csr_val);
 	/* enable clock */
-	clk_csr = GET_CAP_CSR(handle, ICP_GLOBAL_CLK_ENABLE);
-	clk_csr |= reset_mask;
-	SET_CAP_CSR(handle, ICP_GLOBAL_CLK_ENABLE, clk_csr);
+	csr_val = GET_CAP_CSR(handle, clk_csr);
+	csr_val |= reset_mask;
+	SET_CAP_CSR(handle, clk_csr, csr_val);
 	if (qat_hal_check_ae_alive(handle))
 		goto out_err;

@@ -701,6 +701,7 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
 		handle->chip_info->lm2lm3 = false;
 		handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG;
 		handle->chip_info->icp_rst_csr = ICP_RESET;
+		handle->chip_info->glb_clk_enable_csr = ICP_GLOBAL_CLK_ENABLE;
 		handle->chip_info->fw_auth = true;
 		break;
 	case PCI_DEVICE_ID_INTEL_QAT_DH895XCC:

@@ -709,6 +710,7 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
 		handle->chip_info->lm2lm3 = false;
 		handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG;
 		handle->chip_info->icp_rst_csr = ICP_RESET;
+		handle->chip_info->glb_clk_enable_csr = ICP_GLOBAL_CLK_ENABLE;
 		handle->chip_info->fw_auth = false;
 		break;
 	default:

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:29 UTC #23 lore raw

PATCH 23/32 crypto: qat - loader: add wake up event to chip info

In reply to Jack Xu

Add the wake up event to chip info since this value will be different in the next generation of QAT devices.

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h | 1 +
 drivers/crypto/qat/qat_common/icp_qat_hal.h              | 1 +
 drivers/crypto/qat/qat_common/qat_hal.c                  | 5 ++++-
 3 files changed, 6 insertions(+), 1 deletion(-)

drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h +1 -0

index 1d6ab3407dc9..090c3e73938c 100644
@@ -30,6 +30,7 @@ struct icp_qat_fw_loader_chip_info {
 	u32 icp_rst_csr;
 	u32 icp_rst_mask;
 	u32 glb_clk_enable_csr;
+	u32 wakeup_event_val;
 	bool fw_auth;
 };

drivers/crypto/qat/qat_common/icp_qat_hal.h +1 -0

index 82ac33a4500f..b3aa4c8a3ba8 100644
@@ -87,6 +87,7 @@ enum fcu_sts {
 #define XCWE_VOLUNTARY              (0x1)
 #define LCS_STATUS          (0x1)
 #define MMC_SHARE_CS_BITPOS         2
+#define WAKEUP_EVENT 0x10000
 #define FCU_CTRL_AE_POS     0x8
 #define FCU_AUTH_STS_MASK   0x7
 #define FCU_STS_DONE_POS    0x9

drivers/crypto/qat/qat_common/qat_hal.c +4 -1

index 6e6bca281ab7..c073e4e3e3ae 100644
@@ -702,6 +702,7 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
 		handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG;
 		handle->chip_info->icp_rst_csr = ICP_RESET;
 		handle->chip_info->glb_clk_enable_csr = ICP_GLOBAL_CLK_ENABLE;
+		handle->chip_info->wakeup_event_val = WAKEUP_EVENT;
 		handle->chip_info->fw_auth = true;
 		break;
 	case PCI_DEVICE_ID_INTEL_QAT_DH895XCC:

@@ -711,6 +712,7 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
 		handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG;
 		handle->chip_info->icp_rst_csr = ICP_RESET;
 		handle->chip_info->glb_clk_enable_csr = ICP_GLOBAL_CLK_ENABLE;
+		handle->chip_info->wakeup_event_val = WAKEUP_EVENT;
 		handle->chip_info->fw_auth = false;
 		break;
 	default:

@@ -834,6 +836,7 @@ void qat_hal_deinit(struct icp_qat_fw_loader_handle *handle)
 int qat_hal_start(struct icp_qat_fw_loader_handle *handle)
 {
 	unsigned long ae_mask = handle->hal_handle->ae_mask;
+	u32 wakeup_val = handle->chip_info->wakeup_event_val;
 	unsigned int fcu_sts;
 	unsigned char ae;
 	u32 ae_ctr = 0;

@@ -852,7 +855,7 @@ int qat_hal_start(struct icp_qat_fw_loader_handle *handle)
 		return 0;
 	} else {
 		for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
-			qat_hal_put_wakeup_event(handle, ae, 0, 0x10000);
+			qat_hal_put_wakeup_event(handle, ae, 0, wakeup_val);
 			qat_hal_enable_ctx(handle, ae, ICP_QAT_UCLO_AE_ALL_CTX);
 			ae_ctr++;
 		}

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:29 UTC #24 lore raw

PATCH 24/32 crypto: qat - loader: add misc control CSR to chip info

In reply to Jack Xu

Add misc control CSR to chip info since the CSR offset will be different in the next generation of QAT devices.

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 .../crypto/qat/qat_common/icp_qat_fw_loader_handle.h  |  1 +
 drivers/crypto/qat/qat_common/qat_hal.c               | 11 +++++++----
 2 files changed, 8 insertions(+), 4 deletions(-)

drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h +1 -0

index 090c3e73938c..81dba42248bf 100644
@@ -30,6 +30,7 @@ struct icp_qat_fw_loader_chip_info {
 	u32 icp_rst_csr;
 	u32 icp_rst_mask;
 	u32 glb_clk_enable_csr;
+	u32 misc_ctl_csr;
 	u32 wakeup_event_val;
 	bool fw_auth;
 };

drivers/crypto/qat/qat_common/qat_hal.c +7 -4

index c073e4e3e3ae..eae1a5e0efeb 100644
@@ -417,13 +417,14 @@ int qat_hal_check_ae_active(struct icp_qat_fw_loader_handle *handle,
 static void qat_hal_reset_timestamp(struct icp_qat_fw_loader_handle *handle)
 {
 	unsigned long ae_mask = handle->hal_handle->ae_mask;
-	unsigned int misc_ctl;
+	unsigned int misc_ctl_csr, misc_ctl;
 	unsigned char ae;
 
+	misc_ctl_csr = handle->chip_info->misc_ctl_csr;
 	/* stop the timestamp timers */
-	misc_ctl = GET_CAP_CSR(handle, MISC_CONTROL);
+	misc_ctl = GET_CAP_CSR(handle, misc_ctl_csr);
 	if (misc_ctl & MC_TIMESTAMP_ENABLE)
-		SET_CAP_CSR(handle, MISC_CONTROL, misc_ctl &
+		SET_CAP_CSR(handle, misc_ctl_csr, misc_ctl &
 			    (~MC_TIMESTAMP_ENABLE));
 
 	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {

@@ -431,7 +432,7 @@ static void qat_hal_reset_timestamp(struct icp_qat_fw_loader_handle *handle)
 		qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_HIGH, 0);
 	}
 	/* start timestamp timers */
-	SET_CAP_CSR(handle, MISC_CONTROL, misc_ctl | MC_TIMESTAMP_ENABLE);
+	SET_CAP_CSR(handle, misc_ctl_csr, misc_ctl | MC_TIMESTAMP_ENABLE);
 }
 
 #define ESRAM_AUTO_TINIT	BIT(2)

@@ -702,6 +703,7 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
 		handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG;
 		handle->chip_info->icp_rst_csr = ICP_RESET;
 		handle->chip_info->glb_clk_enable_csr = ICP_GLOBAL_CLK_ENABLE;
+		handle->chip_info->misc_ctl_csr = MISC_CONTROL;
 		handle->chip_info->wakeup_event_val = WAKEUP_EVENT;
 		handle->chip_info->fw_auth = true;
 		break;

@@ -712,6 +714,7 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
 		handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG;
 		handle->chip_info->icp_rst_csr = ICP_RESET;
 		handle->chip_info->glb_clk_enable_csr = ICP_GLOBAL_CLK_ENABLE;
+		handle->chip_info->misc_ctl_csr = MISC_CONTROL;
 		handle->chip_info->wakeup_event_val = WAKEUP_EVENT;
 		handle->chip_info->fw_auth = false;
 		break;

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:29 UTC #25 lore raw

PATCH 25/32 crypto: qat - loader: add check for null pointer

In reply to Jack Xu

Add null pointer check when freeing the memory for firmware.

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

---
 drivers/crypto/qat/qat_common/qat_uclo.c | 28 ++++++++++++++----------
 1 file changed, 17 insertions(+), 11 deletions(-)

drivers/crypto/qat/qat_common/qat_uclo.c +17 ~~-11~~

index 32c64a48926f..7b02c4e165c6 100644
@@ -1233,11 +1233,15 @@ static int qat_uclo_simg_alloc(struct icp_qat_fw_loader_handle *handle,
 static void qat_uclo_simg_free(struct icp_qat_fw_loader_handle *handle,
 			       struct icp_firml_dram_desc *dram_desc)
 {
-	dma_free_coherent(&handle->pci_dev->dev,
-			  (size_t)(dram_desc->dram_size),
-			  dram_desc->dram_base_addr_v,
-			  dram_desc->dram_bus_addr);
-	memset(dram_desc, 0, sizeof(*dram_desc));
+	if (handle && dram_desc && dram_desc->dram_base_addr_v) {
+		dma_free_coherent(&handle->pci_dev->dev,
+				  (size_t)(dram_desc->dram_size),
+				  dram_desc->dram_base_addr_v,
+				  dram_desc->dram_bus_addr);
+	}
+
+	if (dram_desc)
+		memset(dram_desc, 0, sizeof(*dram_desc));
 }
 
 static void qat_uclo_ummap_auth_fw(struct icp_qat_fw_loader_handle *handle,

@@ -1245,12 +1249,14 @@ static void qat_uclo_ummap_auth_fw(struct icp_qat_fw_loader_handle *handle,
 {
 	struct icp_firml_dram_desc dram_desc;
 
-	dram_desc.dram_base_addr_v = *desc;
-	dram_desc.dram_bus_addr = ((struct icp_qat_auth_chunk *)
-				   (*desc))->chunk_bus_addr;
-	dram_desc.dram_size = ((struct icp_qat_auth_chunk *)
-			       (*desc))->chunk_size;
-	qat_uclo_simg_free(handle, &dram_desc);
+	if (*desc) {
+		dram_desc.dram_base_addr_v = *desc;
+		dram_desc.dram_bus_addr = ((struct icp_qat_auth_chunk *)
+					   (*desc))->chunk_bus_addr;
+		dram_desc.dram_size = ((struct icp_qat_auth_chunk *)
+				       (*desc))->chunk_size;
+		qat_uclo_simg_free(handle, &dram_desc);
+	}
 }
 
 static int qat_uclo_map_auth_fw(struct icp_qat_fw_loader_handle *handle,

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:29 UTC #26 lore raw

PATCH 26/32 crypto: qat - loader: use ae_mask

In reply to Jack Xu

Use ae_mask to decide which Accelerator Engine (AE) to target in AE related operations, instead of a sequential loop, to skip AEs that are fused out.

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 drivers/crypto/qat/qat_common/qat_uclo.c | 26 +++++++++++++-----------
 1 file changed, 14 insertions(+), 12 deletions(-)

drivers/crypto/qat/qat_common/qat_uclo.c +14 ~~-12~~

index 7b02c4e165c6..0b1cf0708e2e 100644
@@ -373,6 +373,7 @@ static int qat_uclo_init_ustore(struct icp_qat_fw_loader_handle *handle,
 	unsigned int ustore_size;
 	unsigned int patt_pos;
 	struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
+	unsigned long ae_mask = handle->hal_handle->ae_mask;
 	u64 *fill_data;
 
 	uof_image = image->img_ptr;

@@ -385,7 +386,7 @@ static int qat_uclo_init_ustore(struct icp_qat_fw_loader_handle *handle,
 		       sizeof(u64));
 	page = image->page;
 
-	for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) {
+	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
 		if (!test_bit(ae, (unsigned long *)&uof_image->ae_assigned))
 			continue;
 		ustore_size = obj_handle->ae_data[ae].eff_ustore_size;

@@ -406,6 +407,7 @@ static int qat_uclo_init_memory(struct icp_qat_fw_loader_handle *handle)
 	int i, ae;
 	struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
 	struct icp_qat_uof_initmem *initmem = obj_handle->init_mem_tab.init_mem;
+	unsigned long ae_mask = handle->hal_handle->ae_mask;
 
 	for (i = 0; i < obj_handle->init_mem_tab.entry_num; i++) {
 		if (initmem->num_in_bytes) {

@@ -418,7 +420,8 @@ static int qat_uclo_init_memory(struct icp_qat_fw_loader_handle *handle)
 			(sizeof(struct icp_qat_uof_memvar_attr) *
 			initmem->val_attr_num));
 	}
-	for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) {
+
+	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
 		if (qat_hal_batch_wr_lm(handle, ae,
 					obj_handle->lm_init_tab[ae])) {
 			pr_err("QAT: fail to batch init lmem for AE %d\n", ae);

@@ -649,11 +652,9 @@ static int qat_uclo_map_ae(struct icp_qat_fw_loader_handle *handle, int max_ae)
 	int i, ae;
 	int mflag = 0;
 	struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
+	unsigned long ae_mask = handle->hal_handle->ae_mask;
 
-	for (ae = 0; ae < max_ae; ae++) {
-		if (!test_bit(ae,
-			      (unsigned long *)&handle->hal_handle->ae_mask))
-			continue;
+	for_each_set_bit(ae, &ae_mask, max_ae) {
 		for (i = 0; i < obj_handle->uimage_num; i++) {
 			if (!test_bit(ae, (unsigned long *)
 			&obj_handle->ae_uimage[i].img_ptr->ae_assigned))

@@ -845,6 +846,7 @@ static int qat_uclo_init_reg_sym(struct icp_qat_fw_loader_handle *handle,
 static int qat_uclo_init_globals(struct icp_qat_fw_loader_handle *handle)
 {
 	struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
+	unsigned long ae_mask = handle->hal_handle->ae_mask;
 	struct icp_qat_uclo_aedata *aed;
 	unsigned int s, ae;

@@ -857,7 +859,7 @@ static int qat_uclo_init_globals(struct icp_qat_fw_loader_handle *handle)
 		}
 	}
 
-	for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) {
+	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
 		aed = &obj_handle->ae_data[ae];
 		for (s = 0; s < aed->slice_num; s++) {
 			if (!aed->ae_slices[s].encap_image)

@@ -932,9 +934,7 @@ static int qat_uclo_set_ae_mode(struct icp_qat_fw_loader_handle *handle)
 	unsigned char ae, s;
 	int error;
 
-	for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) {
-		if (!test_bit(ae, &ae_mask))
-			continue;
+	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
 		ae_data = &obj_handle->ae_data[ae];
 		for (s = 0; s < min_t(unsigned int, ae_data->slice_num,
 				      ICP_QAT_UCLO_MAX_CTX); s++) {

@@ -1372,13 +1372,14 @@ static int qat_uclo_load_fw(struct icp_qat_fw_loader_handle *handle,
 	unsigned int fcu_sts;
 	struct icp_qat_simg_ae_mode *virt_addr;
 	unsigned int fcu_loaded_ae_pos = FCU_LOADED_AE_POS;
+	unsigned long ae_mask = handle->hal_handle->ae_mask;
 
 	virt_addr = (void *)((uintptr_t)desc +
 		     sizeof(struct icp_qat_auth_chunk) +
 		     sizeof(struct icp_qat_css_hdr) +
 		     ICP_QAT_CSS_FWSK_PUB_LEN +
 		     ICP_QAT_CSS_SIGNATURE_LEN);
-	for (i = 0; i < handle->hal_handle->ae_max_num; i++) {
+	for_each_set_bit(i, &ae_mask, handle->hal_handle->ae_max_num) {
 		int retry = 0;
 
 		if (!((virt_addr->ae_mask >> i) & 0x1))

@@ -1847,6 +1848,7 @@ static void qat_uclo_wr_uimage_page(struct icp_qat_fw_loader_handle *handle,
 				    struct icp_qat_uof_image *image)
 {
 	struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
+	unsigned long ae_mask = handle->hal_handle->ae_mask;
 	unsigned long ae_assigned = image->ae_assigned;
 	struct icp_qat_uclo_aedata *aed;
 	unsigned int ctx_mask, s;

@@ -1860,7 +1862,7 @@ static void qat_uclo_wr_uimage_page(struct icp_qat_fw_loader_handle *handle,
 		ctx_mask = 0x55;
 	/* load the default page and set assigned CTX PC
 	 * to the entrypoint address */
-	for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) {
+	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
 		if (!test_bit(ae, &ae_assigned))
 			continue;

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:29 UTC #27 lore raw

PATCH 27/32 crypto: qat - loader: add CSS3K support

In reply to Jack Xu

Add support for CSS3K, which uses RSA3K as image signature algorithm, to support the next generation of QAT devices.

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 .../qat/qat_common/icp_qat_fw_loader_handle.h |  1 +
 drivers/crypto/qat/qat_common/icp_qat_uclo.h  | 54 +++++++++++++------
 drivers/crypto/qat/qat_common/qat_hal.c       |  2 +
 drivers/crypto/qat/qat_common/qat_uclo.c      | 51 +++++++++---------
 4 files changed, 68 insertions(+), 40 deletions(-)

drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h +1 -0

index 81dba42248bf..29710e88e8b8 100644
@@ -33,6 +33,7 @@ struct icp_qat_fw_loader_chip_info {
 	u32 misc_ctl_csr;
 	u32 wakeup_event_val;
 	bool fw_auth;
+	bool css_3k;
 };
 
 struct icp_qat_fw_loader_handle {

drivers/crypto/qat/qat_common/icp_qat_uclo.h +39 ~~-15~~

63 lines not on this page · raw message

drivers/crypto/qat/qat_common/qat_hal.c +2 -0

index eae1a5e0efeb..8470139bcfe8 100644
@@ -706,6 +706,7 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
 		handle->chip_info->misc_ctl_csr = MISC_CONTROL;
 		handle->chip_info->wakeup_event_val = WAKEUP_EVENT;
 		handle->chip_info->fw_auth = true;
+		handle->chip_info->css_3k = false;
 		break;
 	case PCI_DEVICE_ID_INTEL_QAT_DH895XCC:
 		handle->chip_info->sram_visible = true;

@@ -717,6 +718,7 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
 		handle->chip_info->misc_ctl_csr = MISC_CONTROL;
 		handle->chip_info->wakeup_event_val = WAKEUP_EVENT;
 		handle->chip_info->fw_auth = false;
+		handle->chip_info->css_3k = false;
 		break;
 	default:
 		ret = -EINVAL;

drivers/crypto/qat/qat_common/qat_uclo.c +26 ~~-25~~

116 lines not on this page · raw message

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:29 UTC #28 lore raw

PATCH 28/32 crypto: qat - loader: add FCU CSRs to chip info

In reply to Jack Xu

Add firmware control unit (FCU) CSRs to chip info so the firmware authentication code is common between all devices.

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 .../qat/qat_common/icp_qat_fw_loader_handle.h |  6 +++
 drivers/crypto/qat/qat_common/qat_hal.c       | 19 +++++++-
 drivers/crypto/qat/qat_common/qat_uclo.c      | 44 +++++++++++++------
 3 files changed, 53 insertions(+), 16 deletions(-)

drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h +6 -0

index 29710e88e8b8..e280a077303f 100644
@@ -34,6 +34,12 @@ struct icp_qat_fw_loader_chip_info {
 	u32 wakeup_event_val;
 	bool fw_auth;
 	bool css_3k;
+	u32 fcu_ctl_csr;
+	u32 fcu_sts_csr;
+	u32 fcu_dram_addr_hi;
+	u32 fcu_dram_addr_lo;
+	u32 fcu_loaded_ae_csr;
+	u8 fcu_loaded_ae_pos;
 };
 
 struct icp_qat_fw_loader_handle {

drivers/crypto/qat/qat_common/qat_hal.c +17 -2

index 8470139bcfe8..da138fb11a63 100644
@@ -707,6 +707,12 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
 		handle->chip_info->wakeup_event_val = WAKEUP_EVENT;
 		handle->chip_info->fw_auth = true;
 		handle->chip_info->css_3k = false;
+		handle->chip_info->fcu_ctl_csr = FCU_CONTROL;
+		handle->chip_info->fcu_sts_csr = FCU_STATUS;
+		handle->chip_info->fcu_dram_addr_hi = FCU_DRAM_ADDR_HI;
+		handle->chip_info->fcu_dram_addr_lo = FCU_DRAM_ADDR_LO;
+		handle->chip_info->fcu_loaded_ae_csr = FCU_STATUS;
+		handle->chip_info->fcu_loaded_ae_pos = FCU_LOADED_AE_POS;
 		break;
 	case PCI_DEVICE_ID_INTEL_QAT_DH895XCC:
 		handle->chip_info->sram_visible = true;

@@ -719,6 +725,12 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
 		handle->chip_info->wakeup_event_val = WAKEUP_EVENT;
 		handle->chip_info->fw_auth = false;
 		handle->chip_info->css_3k = false;
+		handle->chip_info->fcu_ctl_csr = 0;
+		handle->chip_info->fcu_sts_csr = 0;
+		handle->chip_info->fcu_dram_addr_hi = 0;
+		handle->chip_info->fcu_dram_addr_lo = 0;
+		handle->chip_info->fcu_loaded_ae_csr = 0;
+		handle->chip_info->fcu_loaded_ae_pos = 0;
 		break;
 	default:
 		ret = -EINVAL;

@@ -842,17 +854,20 @@ int qat_hal_start(struct icp_qat_fw_loader_handle *handle)
 {
 	unsigned long ae_mask = handle->hal_handle->ae_mask;
 	u32 wakeup_val = handle->chip_info->wakeup_event_val;
+	u32 fcu_ctl_csr, fcu_sts_csr;
 	unsigned int fcu_sts;
 	unsigned char ae;
 	u32 ae_ctr = 0;
 	int retry = 0;
 
 	if (handle->chip_info->fw_auth) {
+		fcu_ctl_csr = handle->chip_info->fcu_ctl_csr;
+		fcu_sts_csr = handle->chip_info->fcu_sts_csr;
 		ae_ctr = hweight32(ae_mask);
-		SET_CAP_CSR(handle, FCU_CONTROL, FCU_CTRL_CMD_START);
+		SET_CAP_CSR(handle, fcu_ctl_csr, FCU_CTRL_CMD_START);
 		do {
 			msleep(FW_AUTH_WAIT_PERIOD);
-			fcu_sts = GET_CAP_CSR(handle, FCU_STATUS);
+			fcu_sts = GET_CAP_CSR(handle, fcu_sts_csr);
 			if (((fcu_sts >> FCU_STS_DONE_POS) & 0x1))
 				return ae_ctr;
 		} while (retry++ < FW_AUTH_MAX_RETRY);

drivers/crypto/qat/qat_common/qat_uclo.c +30 ~~-14~~

75 lines not on this page · raw message

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:29 UTC #29 lore raw

PATCH 29/32 crypto: qat - loader: allow to target specific AEs

In reply to Jack Xu

Introduce new API, qat_uclo_set_cfg_ae_mask(), to allow the load of the firmware image to a subset of Acceleration Engines (AEs). This is required by the next generation of QAT devices to be able to load different firmware images to the device.

Signed-off-by Jack Xu <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 .../crypto/qat/qat_common/adf_common_drv.h    |  2 +
 .../qat/qat_common/icp_qat_fw_loader_handle.h |  1 +
 drivers/crypto/qat/qat_common/icp_qat_hal.h   |  2 +
 drivers/crypto/qat/qat_common/icp_qat_uclo.h  |  2 +-
 drivers/crypto/qat/qat_common/qat_hal.c       |  1 +
 drivers/crypto/qat/qat_common/qat_uclo.c      | 42 +++++++++++++++----
 6 files changed, 42 insertions(+), 8 deletions(-)

drivers/crypto/qat/qat_common/adf_common_drv.h +2 -0

index f4c90c701670..c61476553728 100644
@@ -186,6 +186,8 @@ int qat_uclo_wr_mimage(struct icp_qat_fw_loader_handle *handle, void *addr_ptr,
 		       int mem_size);
 int qat_uclo_map_obj(struct icp_qat_fw_loader_handle *handle,
 		     void *addr_ptr, u32 mem_size, char *obj_name);
+int qat_uclo_set_cfg_ae_mask(struct icp_qat_fw_loader_handle *handle,
+			     unsigned int cfg_ae_mask);
 #if defined(CONFIG_PCI_IOV)
 int adf_sriov_configure(struct pci_dev *pdev, int numvfs);
 void adf_disable_sriov(struct adf_accel_dev *accel_dev);

drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h +1 -0

index e280a077303f..cc9b83d965af 100644
@@ -49,6 +49,7 @@ struct icp_qat_fw_loader_handle {
 	void *obj_handle;
 	void *sobj_handle;
 	void *mobj_handle;
+	unsigned int cfg_ae_mask;
 	void __iomem *hal_sram_addr_v;
 	void __iomem *hal_cap_g_ctl_csr_addr_v;
 	void __iomem *hal_cap_ae_xfer_csr_addr_v;

drivers/crypto/qat/qat_common/icp_qat_hal.h +2 -0

index b3aa4c8a3ba8..02476b2ceee1 100644
@@ -68,6 +68,8 @@ enum fcu_sts {
 	FCU_STS_LOAD_FAIL = 4,
 	FCU_STS_BUSY      = 5
 };
+
+#define ALL_AE_MASK                 0xFFFFFFFF
 #define UA_ECS                      (0x1 << 31)
 #define ACS_ABO_BITPOS              31
 #define ACS_ACNO                    0x7

drivers/crypto/qat/qat_common/icp_qat_uclo.h +1 -1

index 4315b4504c26..0ec8a5ab51b5 100644
@@ -432,7 +432,7 @@ struct icp_qat_suof_handle {
 
 struct icp_qat_fw_auth_desc {
 	unsigned int   img_len;
-	unsigned int   reserved;
+	unsigned int   ae_mask;
 	unsigned int   css_hdr_high;
 	unsigned int   css_hdr_low;
 	unsigned int   img_high;

drivers/crypto/qat/qat_common/qat_hal.c +1 -0

index da138fb11a63..94c0b04088b5 100644
@@ -761,6 +761,7 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
 	handle->hal_handle->revision_id = accel_dev->accel_pci_dev.revid;
 	handle->hal_handle->ae_mask = hw_data->ae_mask;
 	handle->hal_handle->slice_mask = hw_data->accel_mask;
+	handle->cfg_ae_mask = ALL_AE_MASK;
 	/* create AE objects */
 	handle->hal_handle->upc_mask = 0x1ffff;
 	handle->hal_handle->max_ustore = 0x4000;

drivers/crypto/qat/qat_common/qat_uclo.c +35 -7

120 lines not on this page · raw message

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:29 UTC #30 lore raw

PATCH 30/32 crypto: qat - loader: add support for shared ustore

In reply to Jack Xu

Add support for shared ustore mode support. This is required by the next generation of QAT devices to share the same fw image across engines.

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 .../qat/qat_common/icp_qat_fw_loader_handle.h |  1 +
 drivers/crypto/qat/qat_common/qat_hal.c       |  2 ++
 drivers/crypto/qat/qat_common/qat_uclo.c      | 29 ++++++++++---------
 3 files changed, 19 insertions(+), 13 deletions(-)

drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h +1 -0

index cc9b83d965af..5b9f2e8c9451 100644
@@ -34,6 +34,7 @@ struct icp_qat_fw_loader_chip_info {
 	u32 wakeup_event_val;
 	bool fw_auth;
 	bool css_3k;
+	bool tgroup_share_ustore;
 	u32 fcu_ctl_csr;
 	u32 fcu_sts_csr;
 	u32 fcu_dram_addr_hi;

drivers/crypto/qat/qat_common/qat_hal.c +2 -0

index 94c0b04088b5..6ccfb8cf3a07 100644
@@ -707,6 +707,7 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
 		handle->chip_info->wakeup_event_val = WAKEUP_EVENT;
 		handle->chip_info->fw_auth = true;
 		handle->chip_info->css_3k = false;
+		handle->chip_info->tgroup_share_ustore = false;
 		handle->chip_info->fcu_ctl_csr = FCU_CONTROL;
 		handle->chip_info->fcu_sts_csr = FCU_STATUS;
 		handle->chip_info->fcu_dram_addr_hi = FCU_DRAM_ADDR_HI;

@@ -725,6 +726,7 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
 		handle->chip_info->wakeup_event_val = WAKEUP_EVENT;
 		handle->chip_info->fw_auth = false;
 		handle->chip_info->css_3k = false;
+		handle->chip_info->tgroup_share_ustore = false;
 		handle->chip_info->fcu_ctl_csr = 0;
 		handle->chip_info->fcu_sts_csr = 0;
 		handle->chip_info->fcu_dram_addr_hi = 0;

drivers/crypto/qat/qat_common/qat_uclo.c +16 ~~-13~~

index c6b309d107f3..b280fb0722c5 100644
@@ -1180,21 +1180,24 @@ static int qat_uclo_map_suof(struct icp_qat_fw_loader_handle *handle,
 		if (!suof_img_hdr)
 			return -ENOMEM;
 		suof_handle->img_table.simg_hdr = suof_img_hdr;
-	}
 
-	for (i = 0; i < suof_handle->img_table.num_simgs; i++) {
-		qat_uclo_map_simg(handle, &suof_img_hdr[i],
-				  &suof_chunk_hdr[1 + i]);
-		ret = qat_uclo_check_simg_compat(handle,
-						 &suof_img_hdr[i]);
-		if (ret)
-			return ret;
-		suof_img_hdr[i].ae_mask &= handle->cfg_ae_mask;
-		if ((suof_img_hdr[i].ae_mask & 0x1) != 0)
-			ae0_img = i;
+		for (i = 0; i < suof_handle->img_table.num_simgs; i++) {
+			qat_uclo_map_simg(handle, &suof_img_hdr[i],
+					  &suof_chunk_hdr[1 + i]);
+			ret = qat_uclo_check_simg_compat(handle,
+							 &suof_img_hdr[i]);
+			if (ret)
+				return ret;
+			suof_img_hdr[i].ae_mask &= handle->cfg_ae_mask;
+			if ((suof_img_hdr[i].ae_mask & 0x1) != 0)
+				ae0_img = i;
+		}
+
+		if (!handle->chip_info->tgroup_share_ustore) {
+			qat_uclo_tail_img(suof_img_hdr, ae0_img,
+					  suof_handle->img_table.num_simgs);
+		}
 	}
-	qat_uclo_tail_img(suof_img_hdr, ae0_img,
-			  suof_handle->img_table.num_simgs);
 	return 0;
 }

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:29 UTC #31 lore raw

PATCH 31/32 crypto: qat - loader: add support for broadcasting mode

In reply to Jack Xu

Add support for broadcasting mode in firmware loader to enable the next generation of QAT devices.

Signed-off-by Jack Xu <[email protected]>

Co-developed-by Wojciech Ziemba <[email protected]>

Signed-off-by Wojciech Ziemba <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 .../qat/qat_common/icp_qat_fw_loader_handle.h |  1 +
 drivers/crypto/qat/qat_common/icp_qat_hal.h   | 10 +++
 drivers/crypto/qat/qat_common/qat_hal.c       |  1 +
 drivers/crypto/qat/qat_common/qat_uclo.c      | 90 ++++++++++++++++++-
 4 files changed, 99 insertions(+), 3 deletions(-)

drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h +1 -0

index 5b9f2e8c9451..b8f3463be6ef 100644
@@ -15,6 +15,7 @@ struct icp_qat_fw_loader_ae_data {
 struct icp_qat_fw_loader_hal_handle {
 	struct icp_qat_fw_loader_ae_data aes[ICP_QAT_UCLO_MAX_AE];
 	unsigned int ae_mask;
+	unsigned int admin_ae_mask;
 	unsigned int slice_mask;
 	unsigned int revision_id;
 	unsigned int ae_max_num;

drivers/crypto/qat/qat_common/icp_qat_hal.h +10 -0

index 02476b2ceee1..8372f18ebc80 100644
@@ -53,6 +53,15 @@ enum fcu_csr {
 	FCU_RAMBASE_ADDR_LO   = 0x8d8
 };
 
+enum fcu_csr_4xxx {
+	FCU_CONTROL_4XXX           = 0x1000,
+	FCU_STATUS_4XXX            = 0x1004,
+	FCU_ME_BROADCAST_MASK_TYPE = 0x1008,
+	FCU_AE_LOADED_4XXX         = 0x1010,
+	FCU_DRAM_ADDR_LO_4XXX      = 0x1014,
+	FCU_DRAM_ADDR_HI_4XXX      = 0x1018,
+};
+
 enum fcu_cmd {
 	FCU_CTRL_CMD_NOOP  = 0,
 	FCU_CTRL_CMD_AUTH  = 1,

@@ -90,6 +99,7 @@ enum fcu_sts {
 #define LCS_STATUS          (0x1)
 #define MMC_SHARE_CS_BITPOS         2
 #define WAKEUP_EVENT 0x10000
+#define FCU_CTRL_BROADCAST_POS   0x4
 #define FCU_CTRL_AE_POS     0x8
 #define FCU_AUTH_STS_MASK   0x7
 #define FCU_STS_DONE_POS    0x9

drivers/crypto/qat/qat_common/qat_hal.c +1 -0

index 6ccfb8cf3a07..a3c1f2163910 100644
@@ -762,6 +762,7 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
 	handle->pci_dev = pci_info->pci_dev;
 	handle->hal_handle->revision_id = accel_dev->accel_pci_dev.revid;
 	handle->hal_handle->ae_mask = hw_data->ae_mask;
+	handle->hal_handle->admin_ae_mask = hw_data->admin_ae_mask;
 	handle->hal_handle->slice_mask = hw_data->accel_mask;
 	handle->cfg_ae_mask = ALL_AE_MASK;
 	/* create AE objects */

drivers/crypto/qat/qat_common/qat_uclo.c +87 -3

108 lines not on this page · raw message

Signature · 1 line

2.25.4

Jack Xu

author

2020-11-06 11:29 UTC #32 lore raw

PATCH 32/32 crypto: qat - loader: add gen4 firmware loader

In reply to Jack Xu

Add support for the QAT gen4 devices in the firmware loader.

Signed-off-by Jack Xu <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

---
 .../crypto/qat/qat_common/adf_accel_devices.h |  2 +
 drivers/crypto/qat/qat_common/icp_qat_hal.h   | 12 ++-
 drivers/crypto/qat/qat_common/icp_qat_uclo.h  |  2 +
 drivers/crypto/qat/qat_common/qat_hal.c       | 77 +++++++++++++++----
 drivers/crypto/qat/qat_common/qat_uclo.c      |  2 +
 5 files changed, 78 insertions(+), 17 deletions(-)

drivers/crypto/qat/qat_common/adf_accel_devices.h +2 -0

index 996d25565b11..5694422ec66c 100644
@@ -15,6 +15,8 @@
 #define ADF_C62XVF_DEVICE_NAME "c6xxvf"
 #define ADF_C3XXX_DEVICE_NAME "c3xxx"
 #define ADF_C3XXXVF_DEVICE_NAME "c3xxxvf"
+#define ADF_4XXX_PCI_DEVICE_ID 0x4940
+#define ADF_4XXXIOV_PCI_DEVICE_ID 0x4941
 #define ADF_ERRSOU3 (0x3A000 + 0x0C)
 #define ADF_ERRSOU5 (0x3A000 + 0xD8)
 #define ADF_DEVICE_FUSECTL_OFFSET 0x40

drivers/crypto/qat/qat_common/icp_qat_hal.h +11 -1

index 8372f18ebc80..20b2ee1fc65a 100644
@@ -10,6 +10,14 @@ enum hal_global_csr {
 	ICP_GLOBAL_CLK_ENABLE = 0xA50
 };
 
+enum {
+	MISC_CONTROL_C4XXX = 0xAA0,
+	ICP_RESET_CPP0 = 0x938,
+	ICP_RESET_CPP1 = 0x93c,
+	ICP_GLOBAL_CLK_ENABLE_CPP0 = 0x964,
+	ICP_GLOBAL_CLK_ENABLE_CPP1 = 0x968
+};
+
 enum hal_ae_csr {
 	USTORE_ADDRESS = 0x000,
 	USTORE_DATA_LOWER = 0x004,

@@ -111,7 +119,9 @@ enum fcu_sts {
 #define ICP_QAT_CAP_OFFSET (ICP_QAT_AE_OFFSET + 0x10000)
 #define LOCAL_TO_XFER_REG_OFFSET 0x800
 #define ICP_QAT_EP_OFFSET 0x3a000
-
+#define ICP_QAT_EP_OFFSET_4XXX   0x200000 /* HI MMIO CSRs */
+#define ICP_QAT_AE_OFFSET_4XXX   0x600000
+#define ICP_QAT_CAP_OFFSET_4XXX  0x640000
 #define SET_CAP_CSR(handle, csr, val) \
 	ADF_CSR_WR((handle)->hal_cap_g_ctl_csr_addr_v, csr, val)
 #define GET_CAP_CSR(handle, csr) \

drivers/crypto/qat/qat_common/icp_qat_uclo.h +2 -0

index 0ec8a5ab51b5..4b36869bf460 100644
@@ -6,6 +6,7 @@
 #define ICP_QAT_AC_895XCC_DEV_TYPE 0x00400000
 #define ICP_QAT_AC_C62X_DEV_TYPE   0x01000000
 #define ICP_QAT_AC_C3XXX_DEV_TYPE  0x02000000
+#define ICP_QAT_AC_4XXX_A_DEV_TYPE 0x08000000
 #define ICP_QAT_UCLO_MAX_AE       12
 #define ICP_QAT_UCLO_MAX_CTX      8
 #define ICP_QAT_UCLO_MAX_UIMAGE   (ICP_QAT_UCLO_MAX_AE * ICP_QAT_UCLO_MAX_CTX)

@@ -13,6 +14,7 @@
 #define ICP_QAT_UCLO_MAX_XFER_REG 128
 #define ICP_QAT_UCLO_MAX_GPR_REG  128
 #define ICP_QAT_UCLO_MAX_LMEM_REG 1024
+#define ICP_QAT_UCLO_MAX_LMEM_REG_2X 1280
 #define ICP_QAT_UCLO_AE_ALL_CTX   0xff
 #define ICP_QAT_UOF_OBJID_LEN     8
 #define ICP_QAT_UOF_FID 0xc6c2

drivers/crypto/qat/qat_common/qat_hal.c +61 ~~-16~~

113 lines not on this page · raw message

drivers/crypto/qat/qat_common/qat_uclo.c +2 -0

index c089c2709376..1fb5fc852f6b 100644
@@ -728,6 +728,8 @@ qat_uclo_get_dev_type(struct icp_qat_fw_loader_handle *handle)
 		return ICP_QAT_AC_C62X_DEV_TYPE;
 	case PCI_DEVICE_ID_INTEL_QAT_C3XXX:
 		return ICP_QAT_AC_C3XXX_DEV_TYPE;
+	case ADF_4XXX_PCI_DEVICE_ID:
+		return ICP_QAT_AC_4XXX_A_DEV_TYPE;
 	default:
 		pr_err("QAT: unsupported device 0x%x\n",
 		       handle->pci_dev->device);

Signature · 1 line

2.25.4

Herbert Xu

maintainer

2020-11-13 05:10 UTC #33 lore raw

In reply to Jack Xu

Quoted 43 lines · Jack Xu

Rework firmware loader in QAT driver in preparation for the support of the qat_4xxx driver.
Patch #1 add support for the mof format in the firmware loader
Patches from #2 to #7 introduce some general fixes
Patches from #8 to #30 rework and refactor the firmware loader to support the new features added by the next generation of QAT devices (QAT GEN4) Patch #31 introduces the firmware loader changes to support QAT GEN4 devices
Giovanni Cabiddu (1):
crypto: qat - support for mof format in fw loader
Jack Xu (31):
crypto: qat - loader: fix status check in qat_hal_put_rel_rd_xfer()
crypto: qat - loader: fix CSR access
crypto: qat - loader: fix error message
crypto: qat - loader: remove unnecessary parenthesis
crypto: qat - loader: introduce additional parenthesis
crypto: qat - loader: rename qat_uclo_del_uof_obj()
crypto: qat - loader: add support for relative FW ucode loading
crypto: qat - loader: change type for ctx_mask
crypto: qat - loader: change micro word data mask
crypto: qat - loader: refactor AE start
crypto: qat - loader: remove global CSRs helpers
crypto: qat - loader: move defines to header files
crypto: qat - loader: refactor qat_uclo_set_ae_mode()
crypto: qat - loader: refactor long expressions
crypto: qat - loader: introduce chip info structure
crypto: qat - loader: replace check based on DID
crypto: qat - loader: add next neighbor to chip_info
crypto: qat - loader: add support for lm2 and lm3
crypto: qat - loader: add local memory size to chip info
crypto: qat - loader: add reset CSR and mask to chip info
crypto: qat - loader: add clock enable CSR to chip info
crypto: qat - loader: add wake up event to chip info
crypto: qat - loader: add misc control CSR to chip info
crypto: qat - loader: add check for null pointer
crypto: qat - loader: use ae_mask
crypto: qat - loader: add CSS3K support
crypto: qat - loader: add FCU CSRs to chip info
crypto: qat - loader: allow to target specific AEs
crypto: qat - loader: add support for shared ustore
crypto: qat - loader: add support for broadcasting mode
crypto: qat - loader: add gen4 firmware loader

Quoted 9 lines

 .../crypto/qat/qat_common/adf_accel_devices.h |   2 +
 .../crypto/qat/qat_common/adf_accel_engine.c  |  13 +-
 .../crypto/qat/qat_common/adf_common_drv.h    |  19 +-
 .../qat/qat_common/icp_qat_fw_loader_handle.h |  26 +-
 drivers/crypto/qat/qat_common/icp_qat_hal.h   |  63 +-
 drivers/crypto/qat/qat_common/icp_qat_uclo.h  | 132 +++-
 drivers/crypto/qat/qat_common/qat_hal.c       | 400 +++++++---
 drivers/crypto/qat/qat_common/qat_uclo.c      | 737 ++++++++++++++----
 8 files changed, 1097 insertions(+), 295 deletions(-)

All applied. Thanks.

Signature · 3 lines

Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt