Add clock drivers for SM8350

Add bindings and update documentation for clock rpmh driver on SM8350.

Reviewed-by Bjorn Andersson <[email protected]>

Signed-off-by Vinod Koul <[email protected]>

---
 Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 +
 1 file changed, 1 insertion(+)

Add bindings and update documentation for clock rpmh driver on SM8350.

Reviewed-by Bjorn Andersson <[email protected]>

Signed-off-by Vinod Koul <[email protected]>

---

This adds the RPMH clocks present in SM8350 SoC

Reviewed-by Bjorn Andersson <[email protected]>

Signed-off-by Vinod Koul <[email protected]>

---

Add device tree bindings for global clock controller on SM8350 SoCs.

Signed-off-by Vinod Koul <[email protected]>

---
 .../bindings/clock/qcom,gcc-sm8350.yaml       |  68 +++++
 include/dt-bindings/clock/qcom,gcc-sm8350.h   | 261 ++++++++++++++++++
 2 files changed, 329 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
 create mode 100644 include/dt-bindings/clock/qcom,gcc-sm8350.h

Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml new file +41 -0

new file mode 100644
index 000000000000..2b0939f81162
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8350.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller Binding for SM8350
+
+maintainers:
+  - Vinod Koul <[email protected]>
+
+description: |
+  Qualcomm global clock control module which supports the clocks, resets and
+  power domains on SM8350.
+
+  See also:
+  - dt-bindings/clock/qcom,gcc-sm8350.h
+
+properties:
+  compatible:
+    const: qcom,gcc-sm8350
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: Sleep clock source
+
+  clock-names:
+    items:
+      - const: bi_tcxo
+      - const: sleep_clk
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 1
+
+  '#power-domain-cells':
+    const: 1
+

Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml new file +17 -0

+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    clock-controller@100000 {
+      compatible = "qcom,gcc-sm8350";
+      reg = <0x00100000 0x1f0000>;
+      clocks = <&rpmhcc RPMH_CXO_CLK>,
+               <&sleep_clk>;
+      clock-names = "bi_tcxo", "sleep_clk";
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+    };
+
+...

include/dt-bindings/clock/qcom,gcc-sm8350.h new file +261 -0

new file mode 100644
index 000000000000..2462f64f6e75
@@ -0,0 +1,261 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020, Linaro Limited
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8350_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_SM8350_H
+
+/* GCC HW clocks */
+#define CORE_BI_PLL_TEST_SE					0
+#define PCIE_0_PIPE_CLK						1
+#define PCIE_1_PIPE_CLK						2
+#define UFS_CARD_RX_SYMBOL_0_CLK				3
+#define UFS_CARD_RX_SYMBOL_1_CLK				4
+#define UFS_CARD_TX_SYMBOL_0_CLK				5
+#define UFS_PHY_RX_SYMBOL_0_CLK					6
+#define UFS_PHY_RX_SYMBOL_1_CLK					7
+#define UFS_PHY_TX_SYMBOL_0_CLK					8
+#define USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK			9
+#define USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK			10
+
+/* GCC clocks */
+#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK				11
+#define GCC_AGGRE_NOC_PCIE_1_AXI_CLK				12
+#define GCC_AGGRE_NOC_PCIE_TBU_CLK				13
+#define GCC_AGGRE_UFS_CARD_AXI_CLK				14
+#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK			15
+#define GCC_AGGRE_UFS_PHY_AXI_CLK				16
+#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK			17
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK				18
+#define GCC_AGGRE_USB3_SEC_AXI_CLK				19
+#define GCC_BOOT_ROM_AHB_CLK					20
+#define GCC_CAMERA_AHB_CLK					21
+#define GCC_CAMERA_HF_AXI_CLK					22
+#define GCC_CAMERA_SF_AXI_CLK					23
+#define GCC_CAMERA_XO_CLK					24
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				25
+#define GCC_CFG_NOC_USB3_SEC_AXI_CLK				26
+#define GCC_DDRSS_GPU_AXI_CLK					27
+#define GCC_DDRSS_PCIE_SF_TBU_CLK				28
+#define GCC_DISP_AHB_CLK					29
+#define GCC_DISP_HF_AXI_CLK					30
+#define GCC_DISP_SF_AXI_CLK					31
+#define GCC_DISP_XO_CLK						32
+#define GCC_GP1_CLK						33
+#define GCC_GP1_CLK_SRC						34
+#define GCC_GP2_CLK						35
+#define GCC_GP2_CLK_SRC						36
+#define GCC_GP3_CLK						37
+#define GCC_GP3_CLK_SRC						38
+#define GCC_GPLL0						39
+#define GCC_GPLL0_OUT_EVEN					40
+#define GCC_GPLL4						41
+#define GCC_GPLL9						42
+#define GCC_GPU_CFG_AHB_CLK					43
+#define GCC_GPU_GPLL0_CLK_SRC					44
+#define GCC_GPU_GPLL0_DIV_CLK_SRC				45
+#define GCC_GPU_IREF_EN						46
+#define GCC_GPU_MEMNOC_GFX_CLK					47
+#define GCC_GPU_SNOC_DVM_GFX_CLK				48
+#define GCC_PCIE0_PHY_RCHNG_CLK					49
+#define GCC_PCIE1_PHY_RCHNG_CLK					50
+#define GCC_PCIE_0_AUX_CLK					51
+#define GCC_PCIE_0_AUX_CLK_SRC					52
+#define GCC_PCIE_0_CFG_AHB_CLK					53
+#define GCC_PCIE_0_CLKREF_EN					54
+#define GCC_PCIE_0_MSTR_AXI_CLK					55
+#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC				56
+#define GCC_PCIE_0_PIPE_CLK					57
+#define GCC_PCIE_0_PIPE_CLK_SRC					58
+#define GCC_PCIE_0_SLV_AXI_CLK					59
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				60
+#define GCC_PCIE_1_AUX_CLK					61
+#define GCC_PCIE_1_AUX_CLK_SRC					62
+#define GCC_PCIE_1_CFG_AHB_CLK					63
+#define GCC_PCIE_1_CLKREF_EN					64
+#define GCC_PCIE_1_MSTR_AXI_CLK					65
+#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC				66
+#define GCC_PCIE_1_PIPE_CLK					67
+#define GCC_PCIE_1_PIPE_CLK_SRC					68
+#define GCC_PCIE_1_SLV_AXI_CLK					69
+#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				70
+#define GCC_PDM2_CLK						71
+#define GCC_PDM2_CLK_SRC					72
+#define GCC_PDM_AHB_CLK						73
+#define GCC_PDM_XO4_CLK						74
+#define GCC_QMIP_CAMERA_NRT_AHB_CLK				75
+#define GCC_QMIP_CAMERA_RT_AHB_CLK				76
+#define GCC_QMIP_DISP_AHB_CLK					77
+#define GCC_QMIP_VIDEO_CVP_AHB_CLK				78
+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				79
+#define GCC_QUPV3_WRAP0_CORE_2X_CLK				80
+#define GCC_QUPV3_WRAP0_CORE_CLK				81
+#define GCC_QUPV3_WRAP0_S0_CLK					82
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC				83
+#define GCC_QUPV3_WRAP0_S1_CLK					84
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC				85
+#define GCC_QUPV3_WRAP0_S2_CLK					86
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC				87
+#define GCC_QUPV3_WRAP0_S3_CLK					88
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC				89
+#define GCC_QUPV3_WRAP0_S4_CLK					90
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC				91
+#define GCC_QUPV3_WRAP0_S5_CLK					92
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC				93
+#define GCC_QUPV3_WRAP0_S6_CLK					94
+#define GCC_QUPV3_WRAP0_S6_CLK_SRC				95
+#define GCC_QUPV3_WRAP0_S7_CLK					96
+#define GCC_QUPV3_WRAP0_S7_CLK_SRC				97
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK				98
+#define GCC_QUPV3_WRAP1_CORE_CLK				99
+#define GCC_QUPV3_WRAP1_S0_CLK					100
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC				101
+#define GCC_QUPV3_WRAP1_S1_CLK					102
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC				103
+#define GCC_QUPV3_WRAP1_S2_CLK					104
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC				105
+#define GCC_QUPV3_WRAP1_S3_CLK					106
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC				107
+#define GCC_QUPV3_WRAP1_S4_CLK					108
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC				109
+#define GCC_QUPV3_WRAP1_S5_CLK					110
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC				111
+#define GCC_QUPV3_WRAP2_CORE_2X_CLK				112
+#define GCC_QUPV3_WRAP2_CORE_CLK				113
+#define GCC_QUPV3_WRAP2_S0_CLK					114
+#define GCC_QUPV3_WRAP2_S0_CLK_SRC				115
+#define GCC_QUPV3_WRAP2_S1_CLK					116
+#define GCC_QUPV3_WRAP2_S1_CLK_SRC				117
+#define GCC_QUPV3_WRAP2_S2_CLK					118
+#define GCC_QUPV3_WRAP2_S2_CLK_SRC				119
+#define GCC_QUPV3_WRAP2_S3_CLK					120
+#define GCC_QUPV3_WRAP2_S3_CLK_SRC				121
+#define GCC_QUPV3_WRAP2_S4_CLK					122
+#define GCC_QUPV3_WRAP2_S4_CLK_SRC				123
+#define GCC_QUPV3_WRAP2_S5_CLK					124
+#define GCC_QUPV3_WRAP2_S5_CLK_SRC				125
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK				126
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK				127
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK				128
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK				129
+#define GCC_QUPV3_WRAP_2_M_AHB_CLK				130
+#define GCC_QUPV3_WRAP_2_S_AHB_CLK				131
+#define GCC_SDCC2_AHB_CLK					132
+#define GCC_SDCC2_APPS_CLK					133
+#define GCC_SDCC2_APPS_CLK_SRC					134
+#define GCC_SDCC4_AHB_CLK					135
+#define GCC_SDCC4_APPS_CLK					136
+#define GCC_SDCC4_APPS_CLK_SRC					137
+#define GCC_THROTTLE_PCIE_AHB_CLK				138
+#define GCC_UFS_1_CLKREF_EN					139
+#define GCC_UFS_CARD_AHB_CLK					140
+#define GCC_UFS_CARD_AXI_CLK					141
+#define GCC_UFS_CARD_AXI_CLK_SRC				142
+#define GCC_UFS_CARD_AXI_HW_CTL_CLK				143
+#define GCC_UFS_CARD_ICE_CORE_CLK				144
+#define GCC_UFS_CARD_ICE_CORE_CLK_SRC				145
+#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK			146
+#define GCC_UFS_CARD_PHY_AUX_CLK				147
+#define GCC_UFS_CARD_PHY_AUX_CLK_SRC				148
+#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK				149
+#define GCC_UFS_CARD_RX_SYMBOL_0_CLK				150
+#define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC			151
+#define GCC_UFS_CARD_RX_SYMBOL_1_CLK				152
+#define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC			153
+#define GCC_UFS_CARD_TX_SYMBOL_0_CLK				154
+#define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC			155
+#define GCC_UFS_CARD_UNIPRO_CORE_CLK				156
+#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC			157
+#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK			158
+#define GCC_UFS_PHY_AHB_CLK					159
+#define GCC_UFS_PHY_AXI_CLK					160
+#define GCC_UFS_PHY_AXI_CLK_SRC					161
+#define GCC_UFS_PHY_AXI_HW_CTL_CLK				162
+#define GCC_UFS_PHY_ICE_CORE_CLK				163
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				164
+#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK				165
+#define GCC_UFS_PHY_PHY_AUX_CLK					166
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				167
+#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK				168
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				169
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC				170
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				171
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC				172
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				173
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC				174
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK				175
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				176
+#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK			177
+#define GCC_USB30_PRIM_MASTER_CLK				178
+#define GCC_USB30_PRIM_MASTER_CLK__FORCE_MEM_CORE_ON		179
+#define GCC_USB30_PRIM_MASTER_CLK_SRC				180
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK				181
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			182
+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC		183
+#define GCC_USB30_PRIM_SLEEP_CLK				184
+#define GCC_USB30_SEC_MASTER_CLK				185
+#define GCC_USB30_SEC_MASTER_CLK__FORCE_MEM_CORE_ON		186
+#define GCC_USB30_SEC_MASTER_CLK_SRC				187
+#define GCC_USB30_SEC_MOCK_UTMI_CLK				188
+#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				189
+#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC			190
+#define GCC_USB30_SEC_SLEEP_CLK					191
+#define GCC_USB3_PRIM_PHY_AUX_CLK				192
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				193
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				194
+#define GCC_USB3_PRIM_PHY_PIPE_CLK				195
+#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC				196
+#define GCC_USB3_SEC_CLKREF_EN					197
+#define GCC_USB3_SEC_PHY_AUX_CLK				198
+#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				199
+#define GCC_USB3_SEC_PHY_COM_AUX_CLK				200
+#define GCC_USB3_SEC_PHY_PIPE_CLK				201
+#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC				202
+#define GCC_VIDEO_AHB_CLK					203
+#define GCC_VIDEO_AXI0_CLK					204
+#define GCC_VIDEO_AXI1_CLK					205
+#define GCC_VIDEO_XO_CLK					206
+
+/* GCC resets */
+#define GCC_CAMERA_BCR						0
+#define GCC_DISPLAY_BCR						1
+#define GCC_GPU_BCR						2
+#define GCC_MMSS_BCR						3
+#define GCC_PCIE_0_BCR						4
+#define GCC_PCIE_0_LINK_DOWN_BCR				5
+#define GCC_PCIE_0_NOCSR_COM_PHY_BCR				6
+#define GCC_PCIE_0_PHY_BCR					7
+#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR			8
+#define GCC_PCIE_1_BCR						9
+#define GCC_PCIE_1_LINK_DOWN_BCR				10
+#define GCC_PCIE_1_NOCSR_COM_PHY_BCR				11
+#define GCC_PCIE_1_PHY_BCR					12
+#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR			13
+#define GCC_PCIE_PHY_CFG_AHB_BCR				14
+#define GCC_PCIE_PHY_COM_BCR					15
+#define GCC_PDM_BCR						16
+#define GCC_QUPV3_WRAPPER_0_BCR					17
+#define GCC_QUPV3_WRAPPER_1_BCR					18
+#define GCC_QUPV3_WRAPPER_2_BCR					19
+#define GCC_QUSB2PHY_PRIM_BCR					20
+#define GCC_QUSB2PHY_SEC_BCR					21
+#define GCC_SDCC2_BCR						22
+#define GCC_SDCC4_BCR						23
+#define GCC_UFS_CARD_BCR					24
+#define GCC_UFS_PHY_BCR						25
+#define GCC_USB30_PRIM_BCR					26
+#define GCC_USB30_SEC_BCR					27
+#define GCC_USB3_DP_PHY_PRIM_BCR				28
+#define GCC_USB3_DP_PHY_SEC_BCR					29
+#define GCC_USB3_PHY_PRIM_BCR					30
+#define GCC_USB3_PHY_SEC_BCR					31
+#define GCC_USB3PHY_PHY_PRIM_BCR				32
+#define GCC_USB3PHY_PHY_SEC_BCR					33
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR				34
+#define GCC_VIDEO_AXI0_CLK_ARES					35
+#define GCC_VIDEO_AXI1_CLK_ARES					36
+#define GCC_VIDEO_BCR						37
+
+#endif

Signature · 1 line

2.26.2

Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml line 51

Quoted 7 lines · Vinod Koul

Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml new file +7 -0

+required:
+  - compatible
+  - clocks
+  - clock-names
+  - reg
+  - '#clock-cells'
+  - '#reset-cells'

You may or may not have power domains?

Quoted 10 lines · Vinod Koul

Quoted 8 lines

Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml new file +7 -0

+required:
+  - compatible
+  - clocks
+  - clock-names
+  - reg
+  - '#clock-cells'
+  - '#reset-cells'

Quoted 1 line

You may or may not have power domains?

I have not added them in the driver yet, so I dont think it made sense to add them when they are not present. For basic stuff it is not required but eventually yes, so I plan to update binding and driver at that time

Quoting Vinod Koul (2020-12-09 22:11:59)

Quoted 11 lines · Rob Herring

Quoted 10 lines · Vinod Koul

Quoted 8 lines

Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml new file +7 -0

+required:
+  - compatible
+  - clocks
+  - clock-names
+  - reg
+  - '#clock-cells'
+  - '#reset-cells'

Quoted 7 lines

Quoted 1 line

You may or may not have power domains?

I have not added them in the driver yet, so I dont think it made sense to add them when they are not present. For basic stuff it is not required but eventually yes, so I plan to update binding and driver at that time

They should still be required in the binding though if the hardware has power domains. It's not like the hardware doesn't have power domains already or can gain that ability after the fact. The driver should deal with it when it is ready.

drivers/clk/qcom/clk-alpha-pll.c +11 -0

+
 #define pll_alpha_width(p)                                     \
                ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
                                 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)

@@ -1561,3 +1567,220 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
        .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);
+
+static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw)
+{
+       struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+       u32 val;
+       int ret;
+
+       ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
+       if (ret)
+               return ret;

drivers/clk/qcom/clk-alpha-pll.c +8 -0

+       regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN);
+
+       ret = wait_for_pll_enable_lock(pll);
+       if (ret)
+               return ret;
+
+       /* Enable the PLL outputs */
+       ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);

drivers/clk/qcom/clk-alpha-pll.c +32 -0

+       return ret;
+}
+
+static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw)
+{
+       struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+       u32 val;
+       int ret;
+
+       ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
+       if (ret)
+               return;
+
+       /* If in FSM mode, just unvote it */
+       if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
+               clk_disable_regmap(hw);
+               return;
+       }
+
+       /* Disable the global PLL output */
+       ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
+       if (ret)
+               return;
+
+       /* Disable the PLL outputs */
+       ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
+       if (ret)
+               return;
+
+       /* Place the PLL mode in STANDBY */
+       regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY);
+}

drivers/clk/qcom/clk-alpha-pll.c +29 -0

+       int ret;
+
+       /* Return early if calibration is not needed. */
+       regmap_read(pll->clkr.regmap, PLL_MODE(pll), &regval);
+       if (regval & LUCID_5LPE_PCAL_DONE)
+               return 0;
+
+       p = clk_hw_get_parent(hw);
+       if (!p)
+               return -EINVAL;
+
+       ret = alpha_pll_lucid_5lpe_enable(hw);
+       if (ret)
+               return ret;
+
+       alpha_pll_lucid_5lpe_disable(hw);
+
+       return 0;
+}
+
+static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate,
+                                        unsigned long prate)
+{
+       struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+       unsigned long rrate;
+       u32 regval, l;
+       u64 a;
+       int ret;
+

drivers/clk/qcom/clk-alpha-pll.c +43 -0

+
+       regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
+       regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
+
+       /* Latch the PLL input */
+       ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
+                                LUCID_5LPE_PLL_LATCH_INPUT, LUCID_5LPE_PLL_LATCH_INPUT);
+       if (ret)
+               return ret;
+
+       /* Wait for 2 reference cycles before checking the ACK bit. */
+       udelay(1);
+       regmap_read(pll->clkr.regmap, PLL_MODE(pll), &regval);
+       if (!(regval & LUCID_5LPE_ALPHA_PLL_ACK_LATCH)) {
+               pr_err("Lucid 5LPE PLL latch failed. Output may be unstable!\n");
+               return -EINVAL;
+       }
+
+       /* Return the latch input to 0 */
+       ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), LUCID_5LPE_PLL_LATCH_INPUT, 0);
+       if (ret)
+               return ret;
+
+       if (clk_hw_is_enabled(hw)) {
+               ret = wait_for_pll_enable_lock(pll);
+               if (ret)
+                       return ret;
+       }
+
+       /* Wait for PLL output to stabilize */
+       udelay(100);
+       return 0;
+}
+
+static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
+                                              unsigned long parent_rate)
+{
+       struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
+       int i, val = 0, div, ret;
+
+       /*
+        * If the PLL is in FSM mode, then treat set_rate callback as a
+        * no-operation.

drivers/clk/qcom/clk-alpha-pll.c +3 -0

+                               val << pll->post_div_shift);
+}
+

Quoting Vinod Koul (2020-12-07 22:47:01)

Quoted 8 lines

drivers/clk/qcom/clk-alpha-pll.c +0 -0

index 564431130a76..6a399663d564 100644
@@ -146,6 +146,12 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
 /* LUCID PLL specific settings and offsets */
 #define LUCID_PCAL_DONE                BIT(27)
 

drivers/clk/qcom/clk-alpha-pll.c EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); · line 153

Quoted 5 lines

drivers/clk/qcom/clk-alpha-pll.c +5 -0

+/* LUCID 5LPE PLL specific settings and offsets */
+#define LUCID_5LPE_PCAL_DONE           BIT(11)
+#define LUCID_5LPE_ENABLE_VOTE_RUN     BIT(21)
+#define LUCID_5LPE_PLL_LATCH_INPUT     BIT(14)
+#define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13)

Sort these by bit or define name?

Quoted 23 lines

drivers/clk/qcom/clk-alpha-pll.c +15 -0

+
 #define pll_alpha_width(p)                                     \
                ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
                                 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)

@@ -1561,3 +1567,220 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
        .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);
+
+static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw)
+{
+       struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+       u32 val;
+       int ret;
+
+       ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
+       if (ret)
+               return ret;
+
+       /* If in FSM mode, just vote for it */
+       if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
+               ret = clk_enable_regmap(hw);

drivers/clk/qcom/clk-alpha-pll.c const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { · line 1589

Quoted 6 lines

drivers/clk/qcom/clk-alpha-pll.c +6 -0

+               if (ret)
+                       return ret;
+               return wait_for_pll_enable_lock(pll);
+       }
+
+       /* Check if PLL is already enabled */

Yeah that's obvious, but then what?

drivers/clk/qcom/clk-alpha-pll.c const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { · line 1598

Quoted 9 lines

drivers/clk/qcom/clk-alpha-pll.c +9 -0

+       ret = trion_pll_is_enabled(pll, pll->clkr.regmap);
+       if (ret < 0)
+               return ret;
+
+       ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
+       if (ret)
+               return ret;
+
+       /* Set operation mode to RUN */

This comment is worthless.

Quoted 13 lines

drivers/clk/qcom/clk-alpha-pll.c +12 -0

+       regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN);
+
+       ret = wait_for_pll_enable_lock(pll);
+       if (ret)
+               return ret;
+
+       /* Enable the PLL outputs */
+       ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
+       if (ret)
+               return ret;
+
+       /* Enable the global PLL outputs */

drivers/clk/qcom/clk-alpha-pll.c const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { · line 1616

Quoted 6 lines

drivers/clk/qcom/clk-alpha-pll.c +6 -0

+       ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
+       if (ret)
+               return ret;
+
+       /* Ensure that the write above goes through before returning. */
+       mb();

Regmap has a memory barrier in writel. Drop this.

Quoted 39 lines

drivers/clk/qcom/clk-alpha-pll.c +38 -0

+       return ret;
+}
+
+static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw)
+{
+       struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+       u32 val;
+       int ret;
+
+       ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
+       if (ret)
+               return;
+
+       /* If in FSM mode, just unvote it */
+       if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
+               clk_disable_regmap(hw);
+               return;
+       }
+
+       /* Disable the global PLL output */
+       ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
+       if (ret)
+               return;
+
+       /* Disable the PLL outputs */
+       ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
+       if (ret)
+               return;
+
+       /* Place the PLL mode in STANDBY */
+       regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY);
+}
+
+/*
+ * The Lucid 5LPE PLL requires a power-on self-calibration which happens
+ * when the PLL comes out of reset. Calibrate in case it is not completed.
+ */
+static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw)

drivers/clk/qcom/clk-alpha-pll.c const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { · line 1658

Quoted 4 lines

drivers/clk/qcom/clk-alpha-pll.c +4 -0

+{
+       struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+       struct clk_hw *p;
+       u32 regval;

Can you use u32 val? And also include a patch to replace the couple times where there is 'regval' in this file. The former is shorter and used far more in qcom clk code.

Quoted 34 lines

drivers/clk/qcom/clk-alpha-pll.c +33 -0

+       int ret;
+
+       /* Return early if calibration is not needed. */
+       regmap_read(pll->clkr.regmap, PLL_MODE(pll), &regval);
+       if (regval & LUCID_5LPE_PCAL_DONE)
+               return 0;
+
+       p = clk_hw_get_parent(hw);
+       if (!p)
+               return -EINVAL;
+
+       ret = alpha_pll_lucid_5lpe_enable(hw);
+       if (ret)
+               return ret;
+
+       alpha_pll_lucid_5lpe_disable(hw);
+
+       return 0;
+}
+
+static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate,
+                                        unsigned long prate)
+{
+       struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+       unsigned long rrate;
+       u32 regval, l;
+       u64 a;
+       int ret;
+
+       rrate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_16BIT_WIDTH);
+
+       /*
+        * Due to a limited number of bits for fractional rate programming, the

drivers/clk/qcom/clk-alpha-pll.c const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { · line 1697

Quoted 6 lines

drivers/clk/qcom/clk-alpha-pll.c +6 -0

+        * rounded up rate could be marginally higher than the requested rate.
+        */
+       if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) {
+               pr_err("Call set rate on the PLL with rounded rates!\n");
+               return -EINVAL;
+       }

Can we use alpha_pll_check_rate_margin()?

Quoted 48 lines

drivers/clk/qcom/clk-alpha-pll.c +47 -0

+
+       regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
+       regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
+
+       /* Latch the PLL input */
+       ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
+                                LUCID_5LPE_PLL_LATCH_INPUT, LUCID_5LPE_PLL_LATCH_INPUT);
+       if (ret)
+               return ret;
+
+       /* Wait for 2 reference cycles before checking the ACK bit. */
+       udelay(1);
+       regmap_read(pll->clkr.regmap, PLL_MODE(pll), &regval);
+       if (!(regval & LUCID_5LPE_ALPHA_PLL_ACK_LATCH)) {
+               pr_err("Lucid 5LPE PLL latch failed. Output may be unstable!\n");
+               return -EINVAL;
+       }
+
+       /* Return the latch input to 0 */
+       ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), LUCID_5LPE_PLL_LATCH_INPUT, 0);
+       if (ret)
+               return ret;
+
+       if (clk_hw_is_enabled(hw)) {
+               ret = wait_for_pll_enable_lock(pll);
+               if (ret)
+                       return ret;
+       }
+
+       /* Wait for PLL output to stabilize */
+       udelay(100);
+       return 0;
+}
+
+static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
+                                              unsigned long parent_rate)
+{
+       struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
+       int i, val = 0, div, ret;
+
+       /*
+        * If the PLL is in FSM mode, then treat set_rate callback as a
+        * no-operation.
+        */
+       ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
+       if (ret)
+               return ret;

drivers/clk/qcom/clk-alpha-pll.c const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { · line 1750

Quoted 6 lines

drivers/clk/qcom/clk-alpha-pll.c +6 -0

+
+       if (val & LUCID_5LPE_ENABLE_VOTE_RUN)
+               return 0;
+
+       if (!pll->post_div_table) {
+               pr_err("Missing the post_div_table for the PLL\n");

Can this be rolled into the loop below?

drivers/clk/qcom/clk-alpha-pll.c const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { · line 1755

Quoted 5 lines

drivers/clk/qcom/clk-alpha-pll.c +5 -0

+               return -EINVAL;
+       }
+
+       div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+       for (i = 0; i < pll->num_post_div; i++) {

So that this finds nothing.

drivers/clk/qcom/clk-alpha-pll.c const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { · line 1760

Quoted 5 lines

drivers/clk/qcom/clk-alpha-pll.c +5 -0

+               if (pll->post_div_table[i].div == div) {
+                       val = pll->post_div_table[i].val;
+                       break;
+               }
+       }

and then if val == -1 we return -EINVAL?

drivers/clk/qcom/clk-alpha-pll.c const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { · line 1763

Quoted 3 lines

drivers/clk/qcom/clk-alpha-pll.c +3 -0

+
+       return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
+                               (BIT(pll->width) - 1) << pll->post_div_shift,

Use GENMASK?

Quoted 5 lines

drivers/clk/qcom/clk-alpha-pll.c const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { · line 1763

Quoted 3 lines

drivers/clk/qcom/clk-alpha-pll.c +3 -0

+
+       return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
+                               (BIT(pll->width) - 1) << pll->post_div_shift,

Use GENMASK?

Looks like this can be:

                GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift)

Not sure which one you like :)

drivers/clk/qcom/Kconfig +0 -0

index 3a965bd326d5..5015dd9332cd 100644
@@ -437,6 +437,15 @@ config SM_GCC_8250
          Say Y if you want to use peripheral devices such as UART,
          SPI, I2C, USB, SD/UFS, PCIe etc.

drivers/clk/qcom/Kconfig +0 -0

 config SM_GPUCC_8150
        tristate "SM8150 Graphics Clock Controller"
        select SM_GCC_8150

drivers/clk/qcom/Makefile +1 -0

index 11ae86febe87..915794872e38 100644
@@ -67,6 +67,7 @@ obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
 obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
 obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
 obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
+obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o
 obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
 obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
 obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o

drivers/clk/qcom/gcc-sm8350.c new file +0 -0

new file mode 100644
index 000000000000..94ee9ef563af

drivers/clk/qcom/gcc-sm8350.c new file +107 -0

+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "common.h"
+#include "reset.h"
+
+enum {
+       P_BI_TCXO,
+       P_CORE_BI_PLL_TEST_SE,
+       P_GCC_GPLL0_OUT_EVEN,
+       P_GCC_GPLL0_OUT_MAIN,
+       P_GCC_GPLL4_OUT_MAIN,
+       P_GCC_GPLL9_OUT_MAIN,
+       P_PCIE_0_PIPE_CLK,
+       P_PCIE_1_PIPE_CLK,
+       P_SLEEP_CLK,
+       P_UFS_CARD_RX_SYMBOL_0_CLK,
+       P_UFS_CARD_RX_SYMBOL_1_CLK,
+       P_UFS_CARD_TX_SYMBOL_0_CLK,
+       P_UFS_PHY_RX_SYMBOL_0_CLK,
+       P_UFS_PHY_RX_SYMBOL_1_CLK,
+       P_UFS_PHY_TX_SYMBOL_0_CLK,
+       P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
+       P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK,
+};
+
+static struct clk_alpha_pll gcc_gpll0 = {
+       .offset = 0x0,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+       .clkr = {
+               .enable_reg = 0x52018,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_gpll0",
+                       .parent_data = &(const struct clk_parent_data){
+                               .fw_name = "bi_tcxo",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
+               },
+       },
+};
+
+static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
+       { 0x1, 2 },
+       { }
+};
+
+static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
+       .offset = 0x0,
+       .post_div_shift = 8,
+       .post_div_table = post_div_table_gcc_gpll0_out_even,
+       .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
+       .width = 4,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gcc_gpll0_out_even",
+               .parent_data = &(const struct clk_parent_data){
+                       .hw = &gcc_gpll0.clkr.hw,
+               },
+               .num_parents = 1,
+               .ops = &clk_alpha_pll_postdiv_lucid_5lpe_ops,
+       },
+};
+
+static struct clk_alpha_pll gcc_gpll4 = {
+       .offset = 0x76000,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+       .clkr = {
+               .enable_reg = 0x52018,
+               .enable_mask = BIT(4),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_gpll4",
+                       .parent_data = &(const struct clk_parent_data){
+                               .fw_name = "bi_tcxo",
+                               .name = "bi_tcxo",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
+               },
+       },
+};
+
+static struct clk_alpha_pll gcc_gpll9 = {
+       .offset = 0x1c000,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+       .clkr = {
+               .enable_reg = 0x52018,
+               .enable_mask = BIT(9),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_gpll9",
+                       .parent_data = &(const struct clk_parent_data){
+                               .fw_name = "bi_tcxo",
+                               .name = "bi_tcxo",
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
+               },
+       },
+};
+
+static const struct parent_map gcc_parent_map_0[] = {
+       { P_BI_TCXO, 0 },

drivers/clk/qcom/gcc-sm8350.c new file +97 -0

+};
+
+static const struct parent_map gcc_parent_map_1[] = {
+       { P_BI_TCXO, 0 },
+       { P_GCC_GPLL0_OUT_MAIN, 1 },
+       { P_SLEEP_CLK, 5 },
+       { P_GCC_GPLL0_OUT_EVEN, 6 },
+       { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const struct clk_parent_data gcc_parent_data_1[] = {
+       { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+       { .hw = &gcc_gpll0.clkr.hw },
+       { .fw_name = "sleep_clk", .name = "sleep_clk" },
+       { .hw = &gcc_gpll0_out_even.clkr.hw },
+       { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+};
+
+static const struct parent_map gcc_parent_map_2[] = {
+       { P_BI_TCXO, 0 },
+       { P_SLEEP_CLK, 5 },
+       { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const struct clk_parent_data gcc_parent_data_2[] = {
+       { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+       { .fw_name = "sleep_clk", .name = "sleep_clk" },
+       { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+};
+
+static const struct parent_map gcc_parent_map_3[] = {
+       { P_BI_TCXO, 0 },
+       { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const struct clk_parent_data gcc_parent_data_3[] = {
+       { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+       { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+};
+
+static const struct parent_map gcc_parent_map_4[] = {
+       { P_PCIE_0_PIPE_CLK, 0 },
+       { P_BI_TCXO, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_4[] = {
+       { .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk" },
+       { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+};
+
+static const struct parent_map gcc_parent_map_5[] = {
+       { P_PCIE_1_PIPE_CLK, 0 },
+       { P_BI_TCXO, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_5[] = {
+       { .fw_name = "pcie_1_pipe_clk", .name = "pcie_1_pipe_clk" },
+       { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+};
+
+static const struct parent_map gcc_parent_map_6[] = {
+       { P_BI_TCXO, 0 },
+       { P_GCC_GPLL0_OUT_MAIN, 1 },
+       { P_GCC_GPLL9_OUT_MAIN, 2 },
+       { P_GCC_GPLL4_OUT_MAIN, 5 },
+       { P_GCC_GPLL0_OUT_EVEN, 6 },
+       { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const struct clk_parent_data gcc_parent_data_6[] = {
+       { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+       { .hw = &gcc_gpll0.clkr.hw },
+       { .hw = &gcc_gpll9.clkr.hw },
+       { .hw = &gcc_gpll4.clkr.hw },
+       { .hw = &gcc_gpll0_out_even.clkr.hw },
+       { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+};
+
+static const struct parent_map gcc_parent_map_7[] = {
+       { P_UFS_CARD_RX_SYMBOL_0_CLK, 0 },
+       { P_BI_TCXO, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_7[] = {
+       { .fw_name = "ufs_card_rx_symbol_0_clk", .name =
+               "ufs_card_rx_symbol_0_clk" },
+       { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+};
+
+static const struct parent_map gcc_parent_map_8[] = {
+       { P_UFS_CARD_RX_SYMBOL_1_CLK, 0 },
+       { P_BI_TCXO, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_8[] = {
+       { .fw_name = "ufs_card_rx_symbol_1_clk", .name =
+               "ufs_card_rx_symbol_1_clk" },

drivers/clk/qcom/gcc-sm8350.c new file +35 -0

+               "ufs_card_tx_symbol_0_clk" },
+       { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+};
+
+static const struct parent_map gcc_parent_map_10[] = {
+       { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
+       { P_BI_TCXO, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_10[] = {
+       { .fw_name = "ufs_phy_rx_symbol_0_clk", .name =
+               "ufs_phy_rx_symbol_0_clk" },
+       { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+};
+
+static const struct parent_map gcc_parent_map_11[] = {
+       { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
+       { P_BI_TCXO, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_11[] = {
+       { .fw_name = "ufs_phy_rx_symbol_1_clk", .name =
+               "ufs_phy_rx_symbol_1_clk" },
+       { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+};
+
+static const struct parent_map gcc_parent_map_12[] = {
+       { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
+       { P_BI_TCXO, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_12[] = {
+       { .fw_name = "ufs_phy_tx_symbol_0_clk", .name =
+               "ufs_phy_tx_symbol_0_clk" },
+       { .fw_name = "bi_tcxo", .name = "bi_tcxo" },

drivers/clk/qcom/gcc-sm8350.c new file +761 -0

+               "usb3_uni_phy_sec_gcc_usb30_pipe_clk" },
+       { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+       { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+};
+
+static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
+       .reg = 0x6b054,
+       .shift = 0,
+       .width = 2,
+       .parent_map = gcc_parent_map_4,
+       .clkr = {
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_pcie_0_pipe_clk_src",
+                       .parent_data = gcc_parent_data_4,
+                       .num_parents = 2,
+                       .ops = &clk_regmap_mux_closest_ops,
+               },
+       },
+};
+
+static struct clk_fixed_factor pcie_0_pipe_clk = {
+       .hw.init = &(struct clk_init_data){
+               .name = "pcie_0_pipe_clk",
+               .ops = &clk_fixed_factor_ops,
+       },
+};
+
+static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = {
+       .reg = 0x8d054,
+       .shift = 0,
+       .width = 2,
+       .parent_map = gcc_parent_map_5,
+       .clkr = {
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_pcie_1_pipe_clk_src",
+                       .parent_data = gcc_parent_data_5,
+                       .num_parents = 2,
+                       .ops = &clk_regmap_mux_closest_ops,
+               },
+       },
+};
+
+static struct clk_fixed_factor pcie_1_pipe_clk = {
+       .hw.init = &(struct clk_init_data){
+               .name = "pcie_1_pipe_clk",
+               .ops = &clk_fixed_factor_ops,
+       },
+};
+
+static struct clk_regmap_mux gcc_ufs_card_rx_symbol_0_clk_src = {
+       .reg = 0x75058,
+       .shift = 0,
+       .width = 2,
+       .parent_map = gcc_parent_map_7,
+       .clkr = {
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_ufs_card_rx_symbol_0_clk_src",
+                       .parent_data = gcc_parent_data_7,
+                       .num_parents = 2,
+                       .ops = &clk_regmap_mux_closest_ops,
+               },
+       },
+};
+
+static struct clk_fixed_factor ufs_card_rx_symbol_0_clk = {
+       .hw.init = &(struct clk_init_data){
+               .name = "ufs_card_rx_symbol_0_clk",
+               .ops = &clk_fixed_factor_ops,
+       },
+};
+
+static struct clk_regmap_mux gcc_ufs_card_rx_symbol_1_clk_src = {
+       .reg = 0x750c8,
+       .shift = 0,
+       .width = 2,
+       .parent_map = gcc_parent_map_8,
+       .clkr = {
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_ufs_card_rx_symbol_1_clk_src",
+                       .parent_data = gcc_parent_data_8,
+                       .num_parents = 2,
+                       .ops = &clk_regmap_mux_closest_ops,
+               },
+       },
+};
+
+static struct clk_fixed_factor ufs_card_rx_symbol_1_clk = {
+       .hw.init = &(struct clk_init_data){
+               .name = "ufs_card_rx_symbol_1_clk",
+               .ops = &clk_fixed_factor_ops,
+       },
+};
+
+static struct clk_regmap_mux gcc_ufs_card_tx_symbol_0_clk_src = {
+       .reg = 0x75048,
+       .shift = 0,
+       .width = 2,
+       .parent_map = gcc_parent_map_9,
+       .clkr = {
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_ufs_card_tx_symbol_0_clk_src",
+                       .parent_data = gcc_parent_data_9,
+                       .num_parents = 2,
+                       .ops = &clk_regmap_mux_closest_ops,
+               },
+       },
+};
+
+static struct clk_fixed_factor ufs_card_tx_symbol_0_clk = {
+       .hw.init = &(struct clk_init_data){
+               .name = "ufs_card_tx_symbol_0_clk",
+               .ops = &clk_fixed_factor_ops,
+       },
+};
+
+static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
+       .reg = 0x77058,
+       .shift = 0,
+       .width = 2,
+       .parent_map = gcc_parent_map_10,
+       .clkr = {
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_ufs_phy_rx_symbol_0_clk_src",
+                       .parent_data = gcc_parent_data_10,
+                       .num_parents = 2,
+                       .ops = &clk_regmap_mux_closest_ops,
+               },
+       },
+};
+
+static struct clk_fixed_factor ufs_phy_rx_symbol_0_clk = {
+       .hw.init = &(struct clk_init_data){
+               .name = "ufs_phy_rx_symbol_0_clk",
+               .ops = &clk_fixed_factor_ops,
+       },
+};
+
+static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
+       .reg = 0x770c8,
+       .shift = 0,
+       .width = 2,
+       .parent_map = gcc_parent_map_11,
+       .clkr = {
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_ufs_phy_rx_symbol_1_clk_src",
+                       .parent_data = gcc_parent_data_11,
+                       .num_parents = 2,
+                       .ops = &clk_regmap_mux_closest_ops,
+               },
+       },
+};
+
+static struct clk_fixed_factor ufs_phy_rx_symbol_1_clk = {
+       .hw.init = &(struct clk_init_data){
+               .name = "ufs_phy_rx_symbol_1_clk",
+               .ops = &clk_fixed_factor_ops,
+       },
+};
+
+static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
+       .reg = 0x77048,
+       .shift = 0,
+       .width = 2,
+       .parent_map = gcc_parent_map_12,
+       .clkr = {
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_ufs_phy_tx_symbol_0_clk_src",
+                       .parent_data = gcc_parent_data_12,
+                       .num_parents = 2,
+                       .ops = &clk_regmap_mux_closest_ops,
+               },
+       },
+};
+
+static struct clk_fixed_factor ufs_phy_tx_symbol_0_clk = {
+       .hw.init = &(struct clk_init_data){
+               .name = "ufs_phy_tx_symbol_0_clk",
+               .ops = &clk_fixed_factor_ops,
+       },
+};
+
+static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
+       .reg = 0xf060,
+       .shift = 0,
+       .width = 2,
+       .parent_map = gcc_parent_map_13,
+       .clkr = {
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_usb3_prim_phy_pipe_clk_src",
+                       .parent_data = gcc_parent_data_13,
+                       .num_parents = 3,
+                       .ops = &clk_regmap_mux_closest_ops,
+               },
+       },
+};
+
+static struct clk_fixed_factor usb3_phy_wrapper_gcc_usb30_pipe_clk = {
+       .hw.init = &(struct clk_init_data){
+               .name = "usb3_phy_wrapper_gcc_usb30_pipe_clk",
+               .ops = &clk_fixed_factor_ops,
+       },
+};
+
+static struct clk_fixed_factor core_bi_pll_test_se = {
+       .hw.init = &(struct clk_init_data){
+               .name = "core_bi_pll_test_se",
+               .ops = &clk_fixed_factor_ops,
+       },
+};
+
+static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
+       .reg = 0x10060,
+       .shift = 0,
+       .width = 2,
+       .parent_map = gcc_parent_map_14,
+       .clkr = {
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_usb3_sec_phy_pipe_clk_src",
+                       .parent_data = gcc_parent_data_14,
+                       .num_parents = 3,
+                       .ops = &clk_regmap_mux_closest_ops,
+               },
+       },
+};
+
+static struct clk_fixed_factor usb3_uni_phy_sec_gcc_usb30_pipe_clk = {
+       .hw.init = &(struct clk_init_data){
+               .name = "usb3_uni_phy_sec_gcc_usb30_pipe_clk",
+               .ops = &clk_fixed_factor_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
+       F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
+       F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
+       F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 gcc_gp1_clk_src = {
+       .cmd_rcgr = 0x64004,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_1,
+       .freq_tbl = ftbl_gcc_gp1_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gcc_gp1_clk_src",
+               .parent_data = gcc_parent_data_1,
+               .num_parents = 5,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 gcc_gp2_clk_src = {
+       .cmd_rcgr = 0x65004,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_1,
+       .freq_tbl = ftbl_gcc_gp1_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gcc_gp2_clk_src",
+               .parent_data = gcc_parent_data_1,
+               .num_parents = 5,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 gcc_gp3_clk_src = {
+       .cmd_rcgr = 0x66004,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_1,
+       .freq_tbl = ftbl_gcc_gp1_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gcc_gp3_clk_src",
+               .parent_data = gcc_parent_data_1,
+               .num_parents = 5,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
+       F(9600000, P_BI_TCXO, 2, 0, 0),
+       F(19200000, P_BI_TCXO, 1, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
+       .cmd_rcgr = 0x6b058,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_2,
+       .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gcc_pcie_0_aux_clk_src",
+               .parent_data = gcc_parent_data_2,
+               .num_parents = 3,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
+       F(19200000, P_BI_TCXO, 1, 0, 0),
+       F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
+       .cmd_rcgr = 0x6b03c,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gcc_pcie_0_phy_rchng_clk_src",
+               .parent_data = gcc_parent_data_0,
+               .num_parents = 4,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
+       .cmd_rcgr = 0x8d058,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_2,
+       .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gcc_pcie_1_aux_clk_src",
+               .parent_data = gcc_parent_data_2,
+               .num_parents = 3,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
+       .cmd_rcgr = 0x8d03c,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gcc_pcie_1_phy_rchng_clk_src",
+               .parent_data = gcc_parent_data_0,
+               .num_parents = 4,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
+       F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 gcc_pdm2_clk_src = {
+       .cmd_rcgr = 0x33010,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_pdm2_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gcc_pdm2_clk_src",
+               .parent_data = gcc_parent_data_0,
+               .num_parents = 4,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
+       F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
+       F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
+       F(19200000, P_BI_TCXO, 1, 0, 0),
+       F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
+       F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
+       F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
+       F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
+       F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
+       F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
+       F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
+       F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
+       { }
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
+       .name = "gcc_qupv3_wrap0_s0_clk_src",
+       .parent_data = gcc_parent_data_0,
+       .num_parents = 4,
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
+       .cmd_rcgr = 0x17010,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+       .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
+       .name = "gcc_qupv3_wrap0_s1_clk_src",
+       .parent_data = gcc_parent_data_0,
+       .num_parents = 4,
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
+       .cmd_rcgr = 0x17140,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+       .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
+       .name = "gcc_qupv3_wrap0_s2_clk_src",
+       .parent_data = gcc_parent_data_0,
+       .num_parents = 4,
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
+       .cmd_rcgr = 0x17270,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+       .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
+       .name = "gcc_qupv3_wrap0_s3_clk_src",
+       .parent_data = gcc_parent_data_0,
+       .num_parents = 4,
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
+       .cmd_rcgr = 0x173a0,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+       .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
+       .name = "gcc_qupv3_wrap0_s4_clk_src",
+       .parent_data = gcc_parent_data_0,
+       .num_parents = 4,
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
+       .cmd_rcgr = 0x174d0,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+       .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
+       .name = "gcc_qupv3_wrap0_s5_clk_src",
+       .parent_data = gcc_parent_data_0,
+       .num_parents = 4,
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
+       .cmd_rcgr = 0x17600,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+       .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
+       .name = "gcc_qupv3_wrap0_s6_clk_src",
+       .parent_data = gcc_parent_data_0,
+       .num_parents = 4,
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
+       .cmd_rcgr = 0x17730,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+       .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
+       .name = "gcc_qupv3_wrap0_s7_clk_src",
+       .parent_data = gcc_parent_data_0,
+       .num_parents = 4,
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
+       .cmd_rcgr = 0x17860,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+       .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
+};
+
+static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = {
+       F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
+       F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
+       F(19200000, P_BI_TCXO, 1, 0, 0),
+       F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
+       F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
+       F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
+       F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
+       F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
+       F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
+       F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
+       F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
+       F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
+       F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
+       F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
+       F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
+       { }
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
+       .name = "gcc_qupv3_wrap1_s0_clk_src",
+       .parent_data = gcc_parent_data_0,
+       .num_parents = 4,
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
+       .cmd_rcgr = 0x18010,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
+       .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
+       .name = "gcc_qupv3_wrap1_s1_clk_src",
+       .parent_data = gcc_parent_data_0,
+       .num_parents = 4,
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
+       .cmd_rcgr = 0x18140,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+       .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
+       .name = "gcc_qupv3_wrap1_s2_clk_src",
+       .parent_data = gcc_parent_data_0,
+       .num_parents = 4,
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
+       .cmd_rcgr = 0x18270,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+       .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
+       .name = "gcc_qupv3_wrap1_s3_clk_src",
+       .parent_data = gcc_parent_data_0,
+       .num_parents = 4,
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
+       .cmd_rcgr = 0x183a0,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+       .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
+       .name = "gcc_qupv3_wrap1_s4_clk_src",
+       .parent_data = gcc_parent_data_0,
+       .num_parents = 4,
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
+       .cmd_rcgr = 0x184d0,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+       .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
+       .name = "gcc_qupv3_wrap1_s5_clk_src",
+       .parent_data = gcc_parent_data_0,
+       .num_parents = 4,
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
+       .cmd_rcgr = 0x18600,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+       .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
+       .name = "gcc_qupv3_wrap2_s0_clk_src",
+       .parent_data = gcc_parent_data_0,
+       .num_parents = 4,
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
+       .cmd_rcgr = 0x1e010,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
+       .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
+       .name = "gcc_qupv3_wrap2_s1_clk_src",
+       .parent_data = gcc_parent_data_0,
+       .num_parents = 4,
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
+       .cmd_rcgr = 0x1e140,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
+       .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
+       .name = "gcc_qupv3_wrap2_s2_clk_src",
+       .parent_data = gcc_parent_data_0,
+       .num_parents = 4,
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
+       .cmd_rcgr = 0x1e270,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+       .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
+       .name = "gcc_qupv3_wrap2_s3_clk_src",
+       .parent_data = gcc_parent_data_0,
+       .num_parents = 4,
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
+       .cmd_rcgr = 0x1e3a0,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+       .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
+       .name = "gcc_qupv3_wrap2_s4_clk_src",
+       .parent_data = gcc_parent_data_0,
+       .num_parents = 4,
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
+       .cmd_rcgr = 0x1e4d0,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+       .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
+       .name = "gcc_qupv3_wrap2_s5_clk_src",
+       .parent_data = gcc_parent_data_0,
+       .num_parents = 4,
+       .flags = CLK_SET_RATE_PARENT,
+       .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
+       .cmd_rcgr = 0x1e600,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+       .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
+       F(400000, P_BI_TCXO, 12, 1, 4),
+       F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
+       F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
+       F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
+       F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
+       .cmd_rcgr = 0x1400c,

drivers/clk/qcom/gcc-sm8350.c new file +12 -0

+       },
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
+       F(400000, P_BI_TCXO, 12, 1, 4),
+       F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
+       F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
+       .cmd_rcgr = 0x1600c,

drivers/clk/qcom/gcc-sm8350.c new file +448 -0

+       },
+};
+
+static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
+       F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
+       F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
+       F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
+       F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
+       .cmd_rcgr = 0x75024,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gcc_ufs_card_axi_clk_src",
+               .parent_data = gcc_parent_data_0,
+               .num_parents = 4,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
+       F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
+       F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
+       F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
+       .cmd_rcgr = 0x7506c,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gcc_ufs_card_ice_core_clk_src",
+               .parent_data = gcc_parent_data_0,
+               .num_parents = 4,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = {
+       F(19200000, P_BI_TCXO, 1, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
+       .cmd_rcgr = 0x750a0,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_3,
+       .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gcc_ufs_card_phy_aux_clk_src",
+               .parent_data = gcc_parent_data_3,
+               .num_parents = 2,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
+       .cmd_rcgr = 0x75084,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gcc_ufs_card_unipro_core_clk_src",
+               .parent_data = gcc_parent_data_0,
+               .num_parents = 4,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
+       .cmd_rcgr = 0x77024,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gcc_ufs_phy_axi_clk_src",
+               .parent_data = gcc_parent_data_0,
+               .num_parents = 4,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
+       .cmd_rcgr = 0x7706c,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gcc_ufs_phy_ice_core_clk_src",
+               .parent_data = gcc_parent_data_0,
+               .num_parents = 4,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
+       .cmd_rcgr = 0x770a0,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_3,
+       .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gcc_ufs_phy_phy_aux_clk_src",
+               .parent_data = gcc_parent_data_3,
+               .num_parents = 2,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
+       .cmd_rcgr = 0x77084,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gcc_ufs_phy_unipro_core_clk_src",
+               .parent_data = gcc_parent_data_0,
+               .num_parents = 4,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
+       F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
+       F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
+       F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
+       F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
+       .cmd_rcgr = 0xf020,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gcc_usb30_prim_master_clk_src",
+               .parent_data = gcc_parent_data_0,
+               .num_parents = 4,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
+       .cmd_rcgr = 0xf038,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gcc_usb30_prim_mock_utmi_clk_src",
+               .parent_data = gcc_parent_data_0,
+               .num_parents = 4,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
+       .cmd_rcgr = 0x10020,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gcc_usb30_sec_master_clk_src",
+               .parent_data = gcc_parent_data_0,
+               .num_parents = 4,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
+       .cmd_rcgr = 0x10038,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_0,
+       .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gcc_usb30_sec_mock_utmi_clk_src",
+               .parent_data = gcc_parent_data_0,
+               .num_parents = 4,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
+       .cmd_rcgr = 0xf064,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_2,
+       .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gcc_usb3_prim_phy_aux_clk_src",
+               .parent_data = gcc_parent_data_2,
+               .num_parents = 3,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
+       .cmd_rcgr = 0x10064,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_2,
+       .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gcc_usb3_sec_phy_aux_clk_src",
+               .parent_data = gcc_parent_data_2,
+               .num_parents = 3,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
+       .reg = 0xf050,
+       .shift = 0,
+       .width = 4,
+       .clkr.hw.init = &(struct clk_init_data) {
+               .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
+               .parent_data = &(const struct clk_parent_data){
+                       .hw = &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
+               },
+               .num_parents = 1,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_regmap_div_ro_ops,
+       },
+};
+
+static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
+       .reg = 0x10050,
+       .shift = 0,
+       .width = 4,
+       .clkr.hw.init = &(struct clk_init_data) {
+               .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
+               .parent_data = &(const struct clk_parent_data){
+                       .hw = &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
+               },
+               .num_parents = 1,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_regmap_div_ro_ops,
+       },
+};
+
+static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = {
+       .halt_reg = 0x6b080,
+       .halt_check = BRANCH_HALT_SKIP,
+       .clkr = {
+               .enable_reg = 0x52000,
+               .enable_mask = BIT(12),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_aggre_noc_pcie_0_axi_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_aggre_noc_pcie_1_axi_clk = {
+       .halt_reg = 0x8d084,
+       .halt_check = BRANCH_HALT_SKIP,
+       .clkr = {
+               .enable_reg = 0x52000,
+               .enable_mask = BIT(11),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_aggre_noc_pcie_1_axi_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
+       .halt_reg = 0x9000c,
+       .halt_check = BRANCH_HALT_VOTED,
+       .hwcg_reg = 0x9000c,
+       .hwcg_bit = 1,
+       .clkr = {
+               .enable_reg = 0x52000,
+               .enable_mask = BIT(18),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_aggre_noc_pcie_tbu_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
+       .halt_reg = 0x750cc,
+       .halt_check = BRANCH_HALT_VOTED,
+       .hwcg_reg = 0x750cc,
+       .hwcg_bit = 1,
+       .clkr = {
+               .enable_reg = 0x750cc,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_aggre_ufs_card_axi_clk",
+                       .parent_data = &(const struct clk_parent_data){
+                               .hw = &gcc_ufs_card_axi_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {
+       .halt_reg = 0x750cc,
+       .halt_check = BRANCH_HALT_VOTED,
+       .hwcg_reg = 0x750cc,
+       .hwcg_bit = 1,
+       .clkr = {
+               .enable_reg = 0x750cc,
+               .enable_mask = BIT(1),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",
+                       .parent_data = &(const struct clk_parent_data){
+                               .hw = &gcc_ufs_card_axi_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
+       .halt_reg = 0x770cc,
+       .halt_check = BRANCH_HALT_VOTED,
+       .hwcg_reg = 0x770cc,
+       .hwcg_bit = 1,
+       .clkr = {
+               .enable_reg = 0x770cc,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_aggre_ufs_phy_axi_clk",
+                       .parent_data = &(const struct clk_parent_data){
+                               .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
+       .halt_reg = 0x770cc,
+       .halt_check = BRANCH_HALT_VOTED,
+       .hwcg_reg = 0x770cc,
+       .hwcg_bit = 1,
+       .clkr = {
+               .enable_reg = 0x770cc,
+               .enable_mask = BIT(1),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
+                       .parent_data = &(const struct clk_parent_data){
+                               .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
+       .halt_reg = 0xf080,
+       .halt_check = BRANCH_HALT_VOTED,
+       .hwcg_reg = 0xf080,
+       .hwcg_bit = 1,
+       .clkr = {
+               .enable_reg = 0xf080,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_aggre_usb3_prim_axi_clk",
+                       .parent_data = &(const struct clk_parent_data){
+                               .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
+       .halt_reg = 0x10080,
+       .halt_check = BRANCH_HALT_VOTED,
+       .hwcg_reg = 0x10080,
+       .hwcg_bit = 1,
+       .clkr = {
+               .enable_reg = 0x10080,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_aggre_usb3_sec_axi_clk",
+                       .parent_data = &(const struct clk_parent_data){
+                               .hw = &gcc_usb30_sec_master_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_boot_rom_ahb_clk = {
+       .halt_reg = 0x38004,
+       .halt_check = BRANCH_HALT_VOTED,
+       .hwcg_reg = 0x38004,
+       .hwcg_bit = 1,
+       .clkr = {
+               .enable_reg = 0x52000,
+               .enable_mask = BIT(10),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_boot_rom_ahb_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_camera_ahb_clk = {

drivers/clk/qcom/gcc-sm8350.c new file +34 -0

+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_camera_hf_axi_clk = {
+       .halt_reg = 0x26010,
+       .halt_check = BRANCH_HALT_SKIP,
+       .hwcg_reg = 0x26010,
+       .hwcg_bit = 1,
+       .clkr = {
+               .enable_reg = 0x26010,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_camera_hf_axi_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_camera_sf_axi_clk = {
+       .halt_reg = 0x26014,
+       .halt_check = BRANCH_HALT_SKIP,
+       .hwcg_reg = 0x26014,
+       .hwcg_bit = 1,
+       .clkr = {
+               .enable_reg = 0x26014,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_camera_sf_axi_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};

drivers/clk/qcom/gcc-sm8350.c new file +76 -0

+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
+       .halt_reg = 0xf07c,
+       .halt_check = BRANCH_HALT_VOTED,
+       .hwcg_reg = 0xf07c,
+       .hwcg_bit = 1,
+       .clkr = {
+               .enable_reg = 0xf07c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_cfg_noc_usb3_prim_axi_clk",
+                       .parent_data = &(const struct clk_parent_data){
+                               .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
+       .halt_reg = 0x1007c,
+       .halt_check = BRANCH_HALT_VOTED,
+       .hwcg_reg = 0x1007c,
+       .hwcg_bit = 1,
+       .clkr = {
+               .enable_reg = 0x1007c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_cfg_noc_usb3_sec_axi_clk",
+                       .parent_data = &(const struct clk_parent_data){
+                               .hw = &gcc_usb30_sec_master_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_ddrss_gpu_axi_clk = {
+       .halt_reg = 0x71154,
+       .halt_check = BRANCH_HALT_SKIP,
+       .hwcg_reg = 0x71154,
+       .hwcg_bit = 1,
+       .clkr = {
+               .enable_reg = 0x71154,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_ddrss_gpu_axi_clk",
+                       .ops = &clk_branch2_aon_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = {
+       .halt_reg = 0x8d080,
+       .halt_check = BRANCH_HALT_SKIP,
+       .hwcg_reg = 0x8d080,
+       .hwcg_bit = 1,
+       .clkr = {
+               .enable_reg = 0x52000,
+               .enable_mask = BIT(19),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_ddrss_pcie_sf_tbu_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_disp_ahb_clk = {

drivers/clk/qcom/gcc-sm8350.c new file +34 -0

+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_disp_hf_axi_clk = {
+       .halt_reg = 0x2700c,
+       .halt_check = BRANCH_HALT_SKIP,
+       .hwcg_reg = 0x2700c,
+       .hwcg_bit = 1,
+       .clkr = {
+               .enable_reg = 0x2700c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_disp_hf_axi_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_disp_sf_axi_clk = {
+       .halt_reg = 0x27014,
+       .halt_check = BRANCH_HALT_SKIP,
+       .hwcg_reg = 0x27014,
+       .hwcg_bit = 1,
+       .clkr = {
+               .enable_reg = 0x27014,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_disp_sf_axi_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};

drivers/clk/qcom/gcc-sm8350.c new file +23 -0

+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_gp1_clk = {
+       .halt_reg = 0x64000,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x64000,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_gp1_clk",
+                       .parent_data = &(const struct clk_parent_data){
+                               .hw = &gcc_gp1_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+

drivers/clk/qcom/gcc-sm8350.c new file +8 -0

+       .clkr = {
+               .enable_reg = 0x1005c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_usb3_sec_phy_pipe_clk",
+                       .parent_data = &(const struct clk_parent_data){
+                               .hw = &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
+                       },

drivers/clk/qcom/gcc-sm8350.c new file +6 -0

+       .hwcg_reg = 0x28004,
+       .hwcg_bit = 1,
+       .clkr = {
+               .enable_reg = 0x28004,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){

drivers/clk/qcom/gcc-sm8350.c new file +41 -0

+       .hwcg_reg = 0x28010,
+       .hwcg_bit = 1,
+       .clkr = {
+               .enable_reg = 0x28010,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_video_axi0_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_video_axi1_clk = {
+       .halt_reg = 0x28018,
+       .halt_check = BRANCH_HALT_SKIP,
+       .hwcg_reg = 0x28018,
+       .hwcg_bit = 1,
+       .clkr = {
+               .enable_reg = 0x28018,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_video_axi1_clk",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_video_xo_clk = {
+       .halt_reg = 0x28020,
+       .halt_check = BRANCH_HALT_DELAY,
+       .clkr = {
+               .enable_reg = 0x28020,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_video_xo_clk",
+                       .flags = CLK_IS_CRITICAL,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+

drivers/clk/qcom/gcc-sm8350.c new file +7 -0

+
+static int gcc_sm8350_probe(struct platform_device *pdev)
+{
+       struct regmap *regmap;
+       int ret;
+
+       regmap = qcom_cc_map(pdev, &gcc_sm8350_desc);

drivers/clk/qcom/gcc-sm8350.c new file +5 -0

+       regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
+
+       return qcom_cc_really_probe(pdev, &gcc_sm8350_desc, regmap);
+}
+

Quoting Vinod Koul (2020-12-07 22:47:02)

drivers/clk/qcom/Kconfig config SM_GCC_8250 · line 448

Quoted 9 lines

drivers/clk/qcom/Kconfig +9 -0

+config SM_GCC_8350
+       tristate "SM8350 Global Clock Controller"
+       select QCOM_GDSC
+       help
+         Support for the global clock controller on SM8350 devices.
+         Say Y if you want to use peripheral devices such as UART,
+         SPI, I2C, USB, SD/UFS, PCIe etc.
+
+

Why double newline?

drivers/clk/qcom/gcc-sm8350.c line 8

Quoted 2 lines

drivers/clk/qcom/gcc-sm8350.c new file +2 -0

+#include <linux/bitops.h>
+#include <linux/clk.h>

Is this include used?

drivers/clk/qcom/gcc-sm8350.c line 17

Quoted 10 lines

drivers/clk/qcom/gcc-sm8350.c new file +9 -0

+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>

Please add newline here

Quoted 1 line

+#include <dt-bindings/clock/qcom,gcc-sm8350.h>

Please add newline here

drivers/clk/qcom/gcc-sm8350.c line 135

Quoted 5 lines

drivers/clk/qcom/gcc-sm8350.c new file +5 -0

+static const struct clk_parent_data gcc_parent_data_0[] = {
+       { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+       { .hw = &gcc_gpll0.clkr.hw },
+       { .hw = &gcc_gpll0_out_even.clkr.hw },
+       { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },

Is this .fw_name in the binding? Please remove .name everywhere in this driver as it shouldn't be necessary.

drivers/clk/qcom/gcc-sm8350.c line 287

Quoted 2 lines

drivers/clk/qcom/gcc-sm8350.c new file +2 -0

+static const struct clk_parent_data gcc_parent_data_13[] = {
+       { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk", .name =

Is this documented in the binding?

drivers/clk/qcom/gcc-sm8350.c line 1071

Quoted 12 lines

drivers/clk/qcom/gcc-sm8350.c new file +12 -0

+static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
+       .cmd_rcgr = 0x1400c,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = gcc_parent_map_6,
+       .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "gcc_sdcc2_apps_clk_src",
+               .parent_data = gcc_parent_data_6,
+               .num_parents = 6,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,